Three-dimensional memory and preparation method thereof

Abstract

The invention provides a three-dimensional memory and a preparation method, relates to the field of memories, and aims to solve the problem that a current memory structure with a transistor is difficult to adapt to a bit cost scalable layer stacking technology. The device comprises a plurality of stacked structures which are stacked in the first direction, and each stacked structure comprises an isolation layer, a first electrode layer, a storage layer, a structural layer and a second electrode layer which are sequentially stacked in the first direction; the plurality of contact holes penetrate through the plurality of stacked structures along the first direction; compared with the side wall of the contact hole, the structural layer shrinks inwards to form a cavity; and the channel layer, the gate insulating layer and the gate layer sequentially cover the surface of the cavity, and the contact hole is filled with the gate layer. The present application enables a memory structure with transistors to be adapted to bit cost scalable layer stacking techniques.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a three-dimensional memory and its fabrication method. Background Technology

[0002] Early resistive random access memories (RRAMs) had planar structures, specifically single-resistor structures or structures with one transistor and one resistor. The presence of transistors effectively avoids problems such as parasitic current, interference, and crosstalk, significantly improving device performance. However, transistor-based structures have an inherent Z-axis scaling bottleneck during device size scaling. On the other hand, while bit-cost scalable layer stacking technology can achieve flash memory and ultra-low bit cost, for newer memory types such as ferroelectric memories and memristors, which require transistor-based structures to avoid parasitic current or crosstalk issues, transistor-based memory structures are difficult to adapt to bit-cost scalable layer stacking technology. This application proposes a memory that incorporates transistors and is compatible with bit-cost scalable layer stacking technology. Summary of the Invention

[0003] This application proposes a three-dimensional memory designed to incorporate transistors and be compatible with bit-cost scalable layer stacking technology.

[0004] To achieve the above objectives, embodiments of this application provide a three-dimensional memory, comprising: a plurality of stacked structures stacked along a first direction, the stacked structures including an isolation layer, a first electrode layer, a storage layer, a structural layer, and a second electrode layer stacked sequentially along the first direction; a plurality of contact holes penetrating the plurality of stacked structures along the first direction; the structural layer being recessed to form a cavity relative to the sidewalls of the contact holes; a channel layer, a gate insulating layer, and a gate layer sequentially covering the surface of the cavity, and the gate layer filling the contact holes.

[0005] The three-dimensional memory provided in the above embodiments of this application includes an isolation layer, a first electrode layer, a memory layer, a structural layer, and a second electrode layer in a stacked structure. Contact holes are then formed on the stacked structure. A cavity is formed on the structural layer relative to the sidewall of the contact holes. A channel layer, a gate insulating layer, and a gate layer are sequentially disposed on the cavity. This structure avoids the problem in BICS (Bit Cost Scaling) structures where two horizontally adjacent memories are connected in parallel. Furthermore, it increases density while maintaining performance, significantly reducing the manufacturing cost per bit and lowering the overall cost. This three-dimensional memory makes it possible to fabricate three-dimensional stacked 1T1x (one transistor per memory cell) devices using BiCS technology. BiCS itself has a significant advantage in manufacturing cost due to the fewer photolithography steps required. Compared to existing three-dimensional structures without transistor sidewall stacking techniques, it significantly improves performance. It increases density while maintaining performance, greatly reducing bit cost and lowering overall cost.

[0006] In some embodiments, along a second direction parallel to the plane where the isolation layer is located, multiple stacked structures form multiple steps, and the multiple steps expose the first electrode layer and the second electrode layer in the multiple stacked structures; The three-dimensional memory also includes a plurality of first contact structures and a plurality of second contact structures. The first contact structures extend along a first direction and are in electrical contact with a first electrode layer; the second contact structures extend along the first direction and are in electrical contact with a second electrode layer.

[0007] In some embodiments, a plurality of contact holes are arranged in an array, including multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane where the isolation layer is located, and each column of contact holes is arranged along a third direction parallel to the plane where the isolation layer is located. The second direction and the third direction intersect. The three-dimensional memory also includes a plurality of third contact structures and a plurality of word lines. The gate layer in each column of contact holes is electrically connected to a word line through a plurality of third contact structures.

[0008] In some embodiments, a plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the insulating layer, and each column of contact holes is arranged along a third direction parallel to the plane of the insulating layer. The second direction intersects with the third direction.

[0009] The three-dimensional memory also includes multiple cutting structures that penetrate multiple stacked structures along a first direction; and the cutting structures are located between two adjacent rows of contact holes.

[0010] In some embodiments, the storage layer includes a plurality of stacks that sequentially cover the surface of the cavity.

[0011] In some embodiments, the storage layer includes one of a resistive switching layer and a ferroelectric layer.

[0012] A second aspect of this application provides a method for fabricating a three-dimensional memory. The method includes: forming a plurality of stacked structures, wherein the plurality of stacked structures are stacked along a first direction, and the stacked structures include an isolation layer, a first electrode layer, a storage layer, a structural layer, and a second electrode layer sequentially stacked along the first direction; forming a plurality of contact holes, wherein the contact holes penetrate the plurality of stacked structures along the first direction; etching the structural layer in the plurality of stacked structures through the contact holes, wherein the structural layer is recessed relative to the sidewall of the contact hole to form a cavity; and sequentially forming a channel layer, a gate insulating layer, and a gate layer on the surface of the cavity, wherein the gate layer fills the contact holes.

[0013] In some embodiments, after forming multiple stacked structures, the fabrication method further includes: etching multiple stacked structures to form multiple steps, and exposing a first electrode layer and a second electrode layer in the multiple stacked structures along a second direction parallel to the plane where the isolation layer is located; forming multiple first contact structures and multiple second contact structures, wherein the first contact structures extend along a first direction and are in electrical contact with the first electrode layer; and the second contact structures extend along the first direction and are in electrical contact with the second electrode layer.

[0014] In some embodiments, a plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the isolation layer, and each column of contact holes is arranged along a third direction parallel to the plane of the isolation layer, wherein the second direction and the third direction intersect. After a channel layer, a gate insulating layer and a gate layer are sequentially formed on the surface of the cavity, the fabrication method further includes: forming a plurality of third contact structures, wherein one third contact structure is electrically connected to the gate layer in one contact hole; and forming a plurality of word lines, wherein one word line is electrically connected to the gate layer in one column of contact holes through the plurality of third contact structures.

[0015] In some embodiments, a plurality of contact holes are arranged in an array, the plurality of contact holes including multiple rows and multiple columns, each row of contact holes is arranged along a second direction parallel to the plane where the isolation layer is located, and each column of contact holes is arranged along a third direction parallel to the plane where the isolation layer is located, the second direction intersecting the third direction; after forming a plurality of stacked structures, the fabrication method further includes: etching the plurality of stacked structures to form a plurality of cutting trenches, the cutting trenches penetrating the plurality of stacked structures along a first direction, and the cutting trenches being located between two adjacent rows of contact holes; forming a cutting structure within the cutting trenches.

[0016] The method for fabricating a three-dimensional memory provided in the above embodiments of this application first stacks multiple stacked structures, each including an isolation layer, a first electrode layer, a memory layer, a structural layer, and a second electrode layer. Then, contact holes are formed on the stacked structures. A cavity is formed on the structural layer relative to the sidewall of the contact holes. A channel layer, a gate insulating layer, and a gate layer are sequentially disposed on the cavity. This structure avoids the problem in BICS (Bit Cost Scaling) structures where two horizontally adjacent memories are connected in parallel, and increases density while maintaining performance, significantly reducing the manufacturing cost per bit and lowering the overall cost. This three-dimensional memory makes it possible to fabricate three-dimensional stacked 1T1x (one transistor, one memory cell) devices using BiCS technology. BiCS itself has a significant advantage in manufacturing cost due to the fewer photolithography steps required. Compared to existing three-dimensional structures without transistor sidewall stacking techniques, it significantly improves performance. It increases density while maintaining performance, greatly reducing bit cost and lowering overall cost. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0018] Figure 1 A schematic diagram of a three-dimensional memory provided in an embodiment of this application; Figure 2 A partial cross-sectional view of a three-dimensional memory provided in an embodiment of this application; Figure 3 A schematic diagram illustrating a method for fabricating a stack in a three-dimensional memory according to an embodiment of this application; Figure 4 A cross-sectional view of a memory in a three-dimensional memory provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0021] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0022] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part. It can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0023] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0024] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0025] The earliest RRAM (Resistive Random Access Memory) was a planar structure (single R or 1T1R). The presence of the T (Transistor) could avoid many problems (parasitic current / interference / crosstalk, etc.), thus improving performance. However, during the scaling process, the crossbar structure could not be scaled in the Z direction because there were many connections in the x direction and also many connections in the Y direction.

[0026] On the other hand, ultra-low bit cost FLASH (flash memory) can be achieved through BiCS layer stacking technology, although most of them are NAND (NAND-type Flash Memory) or NOR (NOR-type Flash Memory) structures, but they are all based on FLASH devices. New types of memory include various types such as ferroelectric and memristors. Any memory requiring a 1T1x stack (where T is a transistor and x can be a resistive switching memory, ferroelectric memory, a pass transistor, or other material layers with storage properties) is prone to parasitic currents or crosstalk, making stacking difficult. This is because BiCS requires a regular initial stack for Z-axis scaling. Returning to the limitations of the crossbar structure mentioned earlier, incorporating a 1T1x stack into this BiCS stack is extremely difficult. For example, in existing 1TnR stacking methods, each layer requires individual exposure. VRRAM (Vertical Resistive Random Access Memory) utilizes sidewall growth, but the performance of VRRAM produced using this method is not as good as that of VRRAM grown using the initial stacking method.

[0027] Based on the above, this application provides a three-dimensional memory, such as... Figure 1 and Figure 2 As shown, where Figure 2 for Figure 1 A cross-sectional view taken along the upper left corner. The three-dimensional memory 1 includes: a plurality of stacked structures 10 stacked along a first direction Z, each stacked structure 10 including an isolation layer 101, a first electrode layer 102, a memory layer 103, a structural layer 104, and a second electrode layer 105 stacked sequentially along the first direction Z; a plurality of contact holes 106 penetrating the plurality of stacked structures 10 along the first direction Z; the structural layer 104 is recessed relative to the sidewall of the contact holes 106 to form a cavity 107; a channel layer 108, a gate insulating layer 109, and a gate layer 110 sequentially cover the surface of the cavity 107, and the gate layer 110 fills the contact holes. Along the first direction, the gate insulating layer covers the channel layer, the isolation layer, the first electrode layer, the memory layer, the structural layer, and the second electrode layer; the gate layer covers the gate insulating layer.

[0028] The three-dimensional memory provided in the above embodiments of this application first stacks multiple stacked structures 10. Each stacked structure 10 includes an isolation layer 101, a first electrode layer 102, a memory layer 103, a structural layer 104, and a second electrode layer 105. Then, contact holes 106 are formed on the stacked structures 10. A cavity 107 is formed on the structural layer 104 relative to the sidewall of the contact hole 106. A channel layer 108, a gate insulating layer 109, and a gate layer 110 are sequentially disposed on the cavity 107. This structure avoids the problem in BICS (Bit Cost Scaling) structures where two horizontally adjacent memories are connected in parallel, and increases density while maintaining performance, significantly reducing the manufacturing cost per bit and lowering the overall cost. This three-dimensional memory makes it possible to fabricate three-dimensional stacked 1T1x (one transistor, one memory cell) devices using BiCS technology. BiCS itself has a significant advantage in manufacturing cost due to the fewer photolithography steps required. Compared to existing three-dimensional structures without transistor sidewall stacking techniques, it significantly improves performance. Increasing density while maintaining performance greatly reduces bit cost and overall cost.

[0029] In some embodiments, along a second direction X parallel to the plane where the isolation layer 101 is located, a plurality of stacked structures 10 form a plurality of steps 201, and the plurality of steps 201 expose the first electrode layer and the second electrode layer in the plurality of stacked structures 10. The three-dimensional memory 1 also includes a plurality of first contact structures 30 and a plurality of second contact structures 31. The first contact structures 30 extend along the first direction Z and are in electrical contact with the first electrode layer; the second contact structures 31 extend along the first direction Z and are in electrical contact with the second electrode layer.

[0030] In some embodiments, a plurality of contact holes 106 are arranged in an array, including multiple rows and multiple columns. Each row of contact holes is arranged along a second direction X parallel to the plane where the isolation layer 101 is located, and each column of contact holes is arranged along a third direction Y parallel to the plane where the isolation layer is located. The second direction and the third direction intersect. The three-dimensional memory also includes a plurality of third contact structures 32 and a plurality of word lines 202. The gate layer 110 in each column of contact holes is electrically connected to a word line 202 through the plurality of third contact structures 32.

[0031] In some embodiments, a plurality of contact holes 106 are arranged in an array, the plurality of contact holes 106 including multiple rows and multiple columns, each row of contact holes is arranged along a second direction X parallel to the plane where the isolation layer is located, and each column of contact holes is arranged along a third direction Y parallel to the plane where the isolation layer 101 is located, the second direction X and the third direction Y intersect. The three-dimensional memory 1 also includes a plurality of cutting structures 203, which penetrate the plurality of stacked structures 10 along the first direction Y; and the cutting structures 203 are located between two adjacent rows of contact holes 106.

[0032] In some embodiments, the storage layer 103 includes a plurality of stacks that sequentially cover the surface of the cavity.

[0033] In some embodiments, the storage layer 103 includes one of a resistive switching layer and a ferroelectric layer.

[0034] Another embodiment of this application provides a method for fabricating a three-dimensional memory, such as... Figure 3 As shown, the preparation method includes: Multiple stacked structures 10 are formed, and the multiple stacked structures 10 are stacked along the first direction Y. The stacked structure 10 includes, in sequence along the first direction Z, an isolation layer 101, a first electrode layer 102, a storage layer 103, a structural layer 104, and a second electrode layer 105. Multiple contact holes 106 are formed, and the multiple contact holes 106 penetrate the multiple stacked structures 10 along the first direction Z. Through the contact holes 106, the structural layer 104 in the multiple stacked structures 10 is etched, and the structural layer 104 is reduced inward relative to the sidewall of the contact hole 106. A cavity 107 is formed; on the surface of the cavity 107, a channel layer 108, a gate insulating layer 109, and a gate layer 110 are sequentially formed, and the gate layer 110 fills the contact hole 106; wherein, the channel layer 108 covers the surface of the structural layer 104 inside the cavity 107; along the first direction, the gate insulating layer 109 covers the channel layer 108, the isolation layer 101, the first electrode layer 102, the storage layer 103, the structural layer 104, and the second electrode layer 105; the gate layer 110 covers the gate insulating layer 109.

[0035] Specifically, the stacked structure 10 is deposited regularly on the substrate using sputtering or other methods. This cyclical deposition initially ensures contact between the films, improving device quality. Each layer includes at least an isolation layer 101, a first electrode layer 102, a storage layer 103, a structural layer 104, and a second electrode layer 105. The entire thin film stack is etched to define regions, and then the structural layer 104 is etched using a recess etching process (usually wet etching). If the structural layer 104 is silicon nitride, it can be etched using hot phosphoric acid, but any combination (e.g., growing alumina followed by weak alkali etching) is acceptable as long as the exposed storage functional layer is not damaged. Dry etching is also possible for this step, but requires specialized equipment. The process involves depositing a channel film (or other materials capable of full-coverage growth, primarily using ALD (Atomic Layer Deposition) and CVD (Chemical Vapor Deposition). Many semiconductors can be used for the channel, including all oxide semiconductors such as IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), and IWO (Indium Tungsten Oxide). Then, vertical etching is performed to remove the outer areas of the channel film. This step is dry etching and requires extremely high verticality. Next, the gate insulating layer 109 and gate layer 110 are deposited (similarly requiring full coverage growth via ALD or CVD, covering the vertical sidewalls and recesses) along with other subsequent connections.

[0036] In some embodiments, a plurality of stacked structures 10 are etched to form a plurality of steps 201. Along a second direction X parallel to the plane where the isolation layer 101 is located, the plurality of steps 201 expose the first electrode layer and the second electrode layer in the plurality of stacked structures 10. A plurality of first contact structures 30 and a plurality of second contact structures 31 are formed. The first contact structures 30 extend along a first direction Z and are in electrical contact with the first electrode layer. The second contact structures 31 extend along the first direction Z and are in electrical contact with the second electrode layer.

[0037] In some embodiments, a plurality of contact holes 106 are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes 106 is arranged along a second direction X parallel to the plane of the isolation layer, and each column of contact holes is arranged along a third direction Y parallel to the plane of the isolation layer. The second direction X and the third direction Y intersect. After a channel layer 108, a gate insulating layer 109, and a gate layer 110 are sequentially formed on the surface of the cavity 107, the fabrication method further includes: forming a plurality of third contact structures 32, wherein one third contact structure 32 is electrically connected to the gate layer 110 in one contact hole 106; and forming a plurality of word lines 202, wherein the gate layer in each column of contact holes is electrically connected to one word line 202 through the plurality of third contact structures 32.

[0038] In some embodiments, after forming a plurality of stacked structures 10, the fabrication method further includes: etching the plurality of stacked structures 10 to form a plurality of cutting trenches, the cutting trenches penetrating the plurality of stacked structures 10 along a first direction Z, and the cutting trenches being located between two adjacent rows of contact holes; forming a cutting structure 203 in the cutting trenches, and the cutting structure 203 being located between two adjacent rows of contact holes 106.

[0039] This process is basically back-end of line (BEOL) compatible, and can be used with conventional RRAM, selector, and ferroelectric materials. However, it may not be compatible with other processes that require high-temperature annealing, such as STT magnetic storage.

[0040] The fabrication method of the three-dimensional memory 1 provided in the above embodiments of this application first stacks multiple stacked structures 10. Each stacked structure 10 includes an isolation layer 101, a first electrode layer 102, a memory layer 103, a structural layer 104, and a second electrode layer 105. Then, contact holes 106 are formed on the stacked structures 10. A cavity 107 is formed on the structural layer 104 relative to the sidewall of the contact hole 106. A channel layer 108, a gate insulating layer 109, and a gate layer 110 are sequentially disposed on the cavity 107. This structure avoids the problem in BICS (Bit Cost Scaling) structures where two horizontally adjacent memories are connected in parallel, and increases density while maintaining performance, greatly reducing the manufacturing cost per bit and lowering the overall cost. This three-dimensional memory makes it possible to fabricate three-dimensional stacked 1T1x (one transistor, one memory cell) devices using BiCS technology. BiCS itself has a significant advantage in manufacturing cost due to the fewer photolithography steps required. Compared to existing three-dimensional structures with sidewall stacking but no transistors, this approach significantly improves performance. It increases density while maintaining performance, greatly reducing bit cost and overall cost.

[0041] In some examples, such as Figure 4 As shown, the first electrode layer 102 is the drain, the storage layer 103 is a stacked layer, the gate insulating layer 109 is the gate oxide layer, and the gate layer 110 is a metal gate layer.

[0042] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, include: Multiple stacked structures are stacked along a first direction, the stacked structure including an isolation layer, a first electrode layer, a storage layer, a structural layer and a second electrode layer stacked sequentially along the first direction; Multiple contact holes are provided along the first direction, and the contact holes penetrate multiple stacked structures; the structural layers are recessed to form cavities relative to the sidewalls of the contact holes; A channel layer, a gate insulating layer, and a gate layer are sequentially covered on the surface of the cavity, and the gate layer fills the contact hole.

2. The three-dimensional memory according to claim 1, characterized in that, Along a second direction parallel to the plane where the isolation layer is located, the plurality of stacked structures form a plurality of steps, the plurality of steps exposing the first electrode layer and the second electrode layer in the plurality of stacked structures; The three-dimensional memory further includes a plurality of first contact structures and a plurality of second contact structures, wherein the first contact structures extend along the first direction and are in electrical contact with the first electrode layer; and the second contact structures extend along the first direction and are in electrical contact with the second electrode layer.

3. The three-dimensional memory according to claim 1, characterized in that, The plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the insulating layer, and each column of contact holes is arranged along a third direction parallel to the plane of the insulating layer. The second direction intersects the third direction. The three-dimensional memory also includes multiple third contact structures and multiple word lines, with the gate layer in each column of contact holes electrically connected to a word line through multiple third contact structures.

4. The three-dimensional memory according to claim 1, characterized in that, The plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the insulating layer, and each column of contact holes is arranged along a third direction parallel to the plane of the insulating layer. The second direction intersects the third direction. The three-dimensional memory also includes a plurality of cutting structures that penetrate the plurality of stacked structures along the first direction; and the cutting structures are located between two adjacent rows of contact holes.

5. The memory according to claim 1, characterized in that, The storage layer comprises multiple stacks, which sequentially cover the surface of the cavity.

6. The memory according to claim 1, characterized in that, The storage layer includes one of a resistive switching layer and a ferroelectric layer.

7. A method for fabricating a three-dimensional memory, characterized in that, include: Multiple stacked structures are formed, and the multiple stacked structures are stacked along a first direction. The stacked structure includes an isolation layer, a first electrode layer, a storage layer, a structural layer and a second electrode layer stacked sequentially along the first direction. Multiple contact holes are formed, and along the first direction, the contact holes penetrate multiple stacked structures; Through the contact hole, the structural layers in the plurality of stacked structures are etched, and the structural layers are recessed to form cavities relative to the sidewalls of the contact hole; A channel layer, a gate insulating layer, and a gate layer are sequentially formed on the surface of the cavity, and the gate layer fills the contact hole.

8. The method for fabricating a three-dimensional memory according to claim 7, characterized in that, After forming multiple stacked structures, the fabrication method further includes: The plurality of stacked structures are etched to form a plurality of steps, and along a second direction parallel to the plane where the isolation layer is located, the plurality of steps expose the first electrode layer and the second electrode layer in the plurality of stacked structures; Multiple first contact structures and multiple second contact structures are formed. The first contact structures extend along the first direction and are in electrical contact with the first electrode layer. The second contact structures extend along the first direction and are in electrical contact with the second electrode layer.

9. The method for fabricating a three-dimensional memory according to claim 7, characterized in that, The plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the insulating layer, and each column of contact holes is arranged along a third direction parallel to the plane of the insulating layer. The second direction intersects the third direction. After sequentially forming a channel layer, a gate insulating layer, and a gate layer on the surface of the cavity, the fabrication method further includes: Multiple third contact structures are formed, and one third contact structure is electrically connected to the gate layer in a contact hole; Multiple word lines are formed, and each word line is electrically connected to the gate layer in a row of contact holes through multiple third contact structures.

10. The method for fabricating a three-dimensional memory according to claim 7, characterized in that, The plurality of contact holes are arranged in an array, comprising multiple rows and multiple columns. Each row of contact holes is arranged along a second direction parallel to the plane of the insulating layer, and each column of contact holes is arranged along a third direction parallel to the plane of the insulating layer. The second direction intersects the third direction. After forming multiple stacked structures, the fabrication method further includes: The plurality of stacked structures are etched to form a plurality of cutting trenches. Along the first direction, the cutting trenches penetrate the plurality of stacked structures and are located between two adjacent rows of contact holes. A cutting structure is formed within the cutting groove.

Images