Chip-on-package package

Abstract

The invention relates to a chip package on package. A chip stack package includes a first semiconductor chip having a first test bump on a first surface and a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite the first surface. The chip stack package also includes a second test bump bonded to the first test bump. The chip package on package further includes a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump. The chip package on package further includes a test pad disposed on the molding member and connected to the second test bump.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a chip stack-up package. Background Technology

[0002] Chip stack-up packages, or chip stacked packages, are semiconductor packages that extend functionality and increase capacity and integration by stacking multiple semiconductor chips. Through-silicon via (TSV) stack-up packages are chip stack-up packages in which through-silicon vias (TSVs) are formed on the semiconductor chips. The semiconductor chips are electrically interconnected using TSVs.

[0003] In TSV stacked packages, bumps or hybrid bonding can be used for connections between chips.

[0004] TSV stacked packages may include a substrate chip, multiple core chips stacked on the substrate chip, and a molded component that seals the substrate chip and the core chips. Summary of the Invention

[0005] According to embodiments of this disclosure, a chip stack-up package includes: a first semiconductor chip having a first test bump on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a second test bump engaged with the first test bump; a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump; and a test pad disposed on the molding member and connected to the second test bump.

[0006] According to an embodiment of the present disclosure, a chip stack package includes: a first semiconductor chip having test bumps on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a molding member surrounding the first semiconductor chip and the second semiconductor chip; and test pads disposed below the molding member and connected to the test bumps.

[0007] According to embodiments of this disclosure, a chip stack-up package includes: a first semiconductor chip having a first test bump on a first surface; a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite to the first surface; a second test bump engaged with the first test bump; a molding member surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump; a redistribution layer disposed on the molding member and the second test bump; and test pads disposed on the redistribution layer.

[0008] According to an embodiment of the present disclosure, a chip stack package includes: a redistribution substrate; a first semiconductor chip having test bumps bonded to a first surface of the redistribution substrate; a second semiconductor chip stacked on the first semiconductor chip; a molding member surrounding the first semiconductor chip and the second semiconductor chip; and test pads disposed on a second surface of the redistribution substrate opposite to the first surface. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0010] Figure 2 yes Figure 1 A magnified view of part A.

[0011] Figure 3 and Figure 4 This is a cross-sectional view showing a first front bump, a carrier bump, an external connection bump, and a passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0012] Figure 5 This is a plan view illustrating a chip stacked package according to an embodiment of the present disclosure.

[0013] Figure 6A and Figure 6B This is a diagram illustrating the second alignment bump according to an embodiment of the present disclosure.

[0014] Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure, shown in process order.

[0015] Figure 10 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0016] Figure 11 yes Figure 10 A magnified view of part B.

[0017] Figure 12 and Figure 13 This is a cross-sectional view showing a first front bump, a carrier bump, an external connection bump, and a passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0018] Figure 14 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0019] Figure 15 yes Figure 14 A magnified view of part C.

[0020] Figure 16 This is a cross-sectional view showing a first front bump, an external connection bump, and a passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0021] Figure 17 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0022] Figure 18 yes Figure 17 A magnified view of part D.

[0023] Figure 19 It is shown Figure 18 A plan view of the first chip pad, the second chip pad, the first front bump, the first test bump, the external connection bump, and the test pad.

[0024] Figure 20 and Figure 21 A first front bump, a carrier bump, a first test bump, and a second test bump of a chip stacked package according to an embodiment of the present disclosure are shown.

[0025] Figure 22 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0026] Figure 23 yes Figure 22 A magnified view of part E.

[0027] Figure 24 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0028] Figure 25 yes Figure 23 A magnified view of part F.

[0029] Figure 26 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure.

[0030] Figure 27 yes Figure 26 A magnified view of part G.

[0031] Figure 28 This is a plan view showing the external connection bumps and test pads of a chip stacked package according to an embodiment of the present disclosure. Detailed Implementation

[0032] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0033] Cross shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material associated with those areas.

[0034] When one element is marked "connected" or "attached" to another element, these elements can be directly connected or directly coupled, or connected through an intermediate element between the elements. When two elements are marked "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0035] When one element is identified as being "above", "over", or "below" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0036] The use of terms such as “vertical,” “top,” “bottom,” “above,” “below,” “under,” “upper,” “side,” “upper part,” “lower part,” “front,” and “horizontal,” as well as other terms that suggest relative spatial relationships or orientations, is for the purpose of description or reference to the accompanying drawings only, and is not intended to be limiting in any other way. Other spatial relationships or orientations not shown in the drawings or described in the specification are also possible within the scope of this disclosure.

[0037] Use terms such as "first" and "second" to distinguish various components without implying the size, order, priority, number, or importance of the components. For example, in one example, the first component might be named the second component, and in another example, the second component might be named the first component.

[0038] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0039] Figure 1This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure, and Figure 2 yes Figure 1 A magnified view of part A.

[0040] Reference Figure 1 The chip stacked package 100 according to embodiments of the present disclosure includes a first semiconductor chip 10, a second semiconductor chip 20, a third semiconductor chip 30, a molding member 40, a carrier bump 51, and an external connection bump 61. The chip stacked package 100 according to embodiments of the present disclosure also includes a second dummy bump 52, a second test bump 53, a test pad 62, and a passivation layer 80.

[0041] A second semiconductor chip 20 is stacked on top of a first semiconductor chip 10. A third semiconductor chip 30 is stacked on top of a second semiconductor chip 20. Figure 1 An example is shown where the number of semiconductor chips to be stacked is three, but in this disclosure the number of semiconductor chips to be stacked can be two or four or more.

[0042] In one embodiment, the first semiconductor chip 10 may be a substrate die, the second semiconductor chip 20 may be a mid-core die, and the third semiconductor chip 30 may be a top-core die. Although Figure 1 It includes a core intermediate die, but two or more core intermediate dies may be stacked between the base die and the core top die.

[0043] The first semiconductor chip 10 includes a first substrate 11, a first wiring structure 12, a first front bump 13A, a first rear bump 14, and a first through-hole 15. Furthermore, the first semiconductor chip 10 also includes a first dummy bump 13B and a first test bump 13C.

[0044] The first substrate 11 includes a first substrate body and a first integrated circuit disposed on the first substrate body. The first substrate body may include silicon. The first integrated circuit may be implemented in various ways depending on the type of the first semiconductor chip 10. In one embodiment, the second semiconductor chip 20 and the third semiconductor chip 30 may be memory dies, and the first semiconductor chip 10 may be a logic die for controlling the memory die. The first integrated circuit may include logic transistors for controlling the memory die.

[0045] A first wiring structure 12 is disposed on the lower surface of the first substrate 11. Although not shown, the first wiring structure 12 includes wiring and an insulating layer. The lower surface of the first wiring structure 12 may constitute the lower surface of the first semiconductor chip 10. In one embodiment, the lower surface of the first semiconductor chip 10 may face the passivation layer 80 and be away from the second semiconductor chip 20. A first front bump 13A, a first dummy bump 13B, and a first test bump 13C are disposed on the lower surface of the first semiconductor chip 10.

[0046] The first front bump 13A is connected to one of the wirings in the first wiring structure 12. The first front bump 13A is connected to the first integrated circuit through the wiring of the first wiring structure 12. The first front bump 13A can be used to input and / or output electrical signals such as data signals, power supply voltages, and ground voltages.

[0047] The first test bump 13C is connected to a trace in the wiring of the first wiring structure 12. The first test bump 13C is connected to the first integrated circuit via the trace in the first wiring structure 12. The first test bump 13C is used to test the chip stack-up package 100. During the test, an electrical signal may be applied to the first test bump 13C. After the test is completed, no electrical signal may be applied to the first test bump 13C. After the test is completed, the first test bump 13C may be electrically floated.

[0048] The first dummy bump 13B, together with the first front bump 13A and the first test bump 13C, can support the first semiconductor chip 10, thereby helping to alleviate the stress applied to the first front bump 13A and the first test bump 13C. In one embodiment, during the manufacturing process of the chip stack package 100, the first dummy bump 13B can fix the first semiconductor chip 10 to the carrier substrate, as will be described later. Thus, in one embodiment, warpage in the first semiconductor chip 10 can be suppressed, and solder non-wetting problems caused by warpage can be suppressed. In one embodiment, the first dummy bump 13B can prevent the first semiconductor chip 10 from being pushed down or up due to the pressure of the injected sealant during the formation of the molding member 40, thereby forming a molding member 40 with a uniform thickness on the lower surface of the first semiconductor chip 10. The first dummy bump 13B may not be used to transmit electrical signals. Electrical signals may not be applied to the first dummy bump 13B. The first dummy bump 13B can be electrically floated.

[0049] The first front bump 13A includes a conductive post 13Aa located below the first wiring structure 12 and a solder layer 13Ab located below the conductive post 13Aa. In one embodiment, the conductive post 13Aa of the first front bump 13A may include nickel (Ni). The conductive post 13Aa of the first front bump 13A may be formed of a nickel (Ni) layer. In one embodiment, the conductive post 13Aa of the first front bump 13A may be formed of a copper (Cu) layer and a nickel layer below the copper layer. The solder layer 13Ab of the first front bump 13A may include a tin-silver (Sn-Ag) alloy.

[0050] A bottom bump metallization (UBM) pattern (not shown) can be formed between the first wiring structure 12 and the first front bump 13A. The UBM pattern may include a barrier metal layer beneath the first wiring structure 12 and a seed layer beneath the barrier metal layer. The barrier metal layer may include titanium (Ti). The seed layer may include copper. The conductive post 13Aa of the first front bump 13A may be formed using the seed layer via an electroplating process.

[0051] The first dummy bump 13B includes a conductive post 13Ba located below the first wiring structure 12 and a solder layer 13Bb located below the conductive post 13Ba. The first test bump 13C includes a conductive post 13Ca located below the first wiring structure 12 and a solder layer 13Cb located below the conductive post 13Ca.

[0052] The conductive post 13Ba of the first dummy bump 13B and the conductive post 13Ca of the first test bump 13C can be formed together with the conductive post 13Aa of the first front bump 13A during the formation of the conductive post 13Aa of the first front bump 13A. The conductive post 13Ba of the first dummy bump 13B and the conductive post 13Ca of the first test bump 13C can be made of the same material as the conductive post 13Aa of the first front bump 13A. In one embodiment, each of the conductive post 13Ba of the first dummy bump 13B and the conductive post 13Ca of the first test bump 13C can be formed of a nickel layer. In one embodiment, each of the conductive post 13Ba of the first dummy bump 13B and the conductive post 13Ca of the first test bump 13C can be formed of a copper layer and a nickel layer beneath the copper layer.

[0053] The solder layer 13Bb of the first dummy bump 13B and the solder layer 13Cb of the first test bump 13C can be formed together with the solder layer 13Ab of the first front bump 13A during the formation of the solder layer 13Ab of the first front bump 13A. The solder layer 13Bb of the first dummy bump 13B and the solder layer 13Cb of the first test bump 13C can be made of the same material as the solder layer 13Ab of the first front bump 13A. The solder layer 13Bb of the first dummy bump 13B and the solder layer 13Cb of the first test bump 13C can include a Sn-Ag alloy.

[0054] A first insulating layer 16 is disposed on the upper surface of the first substrate 11. The first insulating layer 16 may include inorganic insulating materials and / or organic insulating materials. Inorganic insulating materials may include silicon nitrides, silicon oxides, and silicon nitrides. Organic insulating materials may include polyimide.

[0055] A first rear bump 14 is disposed above a first through-hole 15 and a first insulating layer 16 surrounding the first through-hole 15. The first rear bump 14 is disposed on the upper surface of the first semiconductor chip 10. In one embodiment, the first rear bump 14 may consist of a copper layer and a nickel layer on the copper layer. In another embodiment, the first rear bump 14 may be constructed of a nickel layer.

[0056] A UBM pattern (not shown) may be disposed between the first rear bump 14 and the first through hole 15, and between the first rear bump 14 and the first insulating layer 16. The UBM pattern may include a barrier metal layer and a seed layer. The barrier metal layer may be disposed on the first through hole 15 and the first insulating layer 16. The seed layer may be disposed on the barrier metal layer. The first rear bump 14 may be formed on the seed layer by an electroplating process.

[0057] A first through-hole 15 vertically penetrates the first substrate 11. The first through-hole 15 includes a protrusion extending from the upper surface of the first substrate 11. A first insulating layer 16 surrounds the side surface of the protrusion of the first through-hole 15. The upper end of the first through-hole 15 is connected to a first rear bump 14. The lower end of the first through-hole 15 is connected to a first wiring structure 12. The first through-hole 15 can be connected to wiring in the first wiring structure 12. The first through-hole 15 can be connected to a first front bump 13A through wiring in the first wiring structure 12.

[0058] The second semiconductor chip 20 includes a second substrate 21, a second wiring structure 22, a second front bump 23, a second rear bump 24, and a second through hole 25.

[0059] The second substrate 21 includes a second substrate body and a second integrated circuit disposed on the second substrate body. The second substrate body may include silicon. The second integrated circuit may be implemented in various ways depending on the type of the second semiconductor chip 20. In one embodiment, the second semiconductor chip 20 may be a memory die, and the second integrated circuit may include memory cells. The memory may include volatile memory or non-volatile memory. Volatile memory may include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Non-volatile memory may include NAND, NOR, PRAM (Phase Change Random Access Memory), and MRAM (Magnetoresistive Random Access Memory).

[0060] A second wiring structure 22 is disposed on the lower surface of the second substrate 21. Although not shown, the second wiring structure 22 may include wiring and an insulating layer. The lower surface of the second wiring structure 22 may constitute the lower surface of the second semiconductor chip 20.

[0061] The second front bump 23 is disposed on the lower surface of the second wiring structure 22. The second front bump 23 is connected to one of the wirings in the second wiring structure 22. The second front bump 23 is connected to the second integrated circuit through the wiring of the second wiring structure 22.

[0062] The second front bump 23 includes a conductive post 23a located below the second wiring structure 22 and a solder layer 23b located below the conductive post 23a. In one embodiment, the conductive post 23a of the second front bump 23 may be formed of a nickel layer. In another embodiment, the conductive post 23a of the second front bump 23 may be formed of a copper layer and a nickel layer below the copper layer. The solder layer 23b of the second front bump 23 may include a tin-silver alloy.

[0063] A UBM pattern (not shown) may be provided between the second wiring structure 22 and the second front bump 23. The UBM pattern may include a barrier metal layer located below the second wiring structure 22 and a seed layer located below the barrier metal layer. The conductive pillars 23a of the second front bump 23 may be formed using the seed layer through an electroplating process.

[0064] A second insulating layer 26 is disposed on the upper surface of the second substrate 21. The second insulating layer 26 may include inorganic insulating materials and organic insulating materials. Inorganic insulating materials may include silicon nitrides, silicon oxides, and silicon oxide nitrides. Organic insulating materials may include polyimide. The upper surface of the second insulating layer 26 may constitute the upper surface of the second semiconductor chip 20.

[0065] The second rear bump 24 is disposed above the second insulating layer 26 surrounding the second through hole 25. The second rear bump 24 is disposed on the upper surface of the second semiconductor chip 20.

[0066] A UBM pattern (not shown) may be disposed between the second rear bump 24 and the second through hole 25, and between the second rear bump 24 and the second insulating layer 26. The UBM pattern may include a barrier metal layer and a seed layer. The barrier metal layer may be disposed on the second through hole 25 and the second insulating layer 26. The seed layer may be disposed on the barrier metal layer. The second rear bump 24 may be formed using the seed layer through an electroplating process.

[0067] In one embodiment, the second rear bump 24 may consist of a copper layer and a nickel layer on the copper layer. In another embodiment, the second rear bump 24 may be composed of a nickel layer.

[0068] The second through-hole 25 penetrates the second substrate 21 vertically. The second through-hole 25 includes a protrusion that extends beyond the upper surface of the second substrate 21. A second insulating layer 26 surrounds the side surface of the protrusion of the second through-hole 25. The upper end of the second through-hole 25 is connected to the second rear bump 24. The lower end of the second through-hole 25 is connected to the second wiring structure 22. The second through-hole 25 can be connected to the wiring of the second wiring structure 22 and can be connected to the second front bump 23 through the wiring of the second wiring structure 22.

[0069] The second semiconductor chip 20 is connected to the first semiconductor chip 10 via a second front bump 23. The second front bump 23 of the second semiconductor chip 20 is disposed above the first rear bump 14 of the first semiconductor chip 10. The second front bump 23 overlaps perpendicularly with the first rear bump 14. The solder layer 23b of the second front bump 23 is bonded to the first rear bump 14.

[0070] The third semiconductor chip 30 includes a third substrate 31, a third wiring structure 32, and a third front bump 33.

[0071] The third substrate 31 includes a third substrate body and a third integrated circuit disposed on the third substrate body. The third substrate body may include silicon. The thickness of the third substrate 31 may be different from the thickness of the second substrate 21. The third substrate 31 may be thicker than the second substrate 21.

[0072] The third integrated circuit can be implemented in various ways depending on the type of the third semiconductor chip 30. In one embodiment, the third semiconductor chip 30 may be a memory die, and the third integrated circuit may include memory cells.

[0073] The third wiring structure 32 may be disposed on the lower surface of the third substrate 31. Although not shown, the third wiring structure 32 may include wiring and an insulating layer. The lower surface of the third wiring structure 32 constitutes the lower surface of the third semiconductor chip 30.

[0074] The third front bump 33 is disposed on the lower surface of the third wiring structure 32. The third front bump 33 is disposed on the lower surface of the third semiconductor chip 30. The third front bump 33 is connected to one of the wirings in the third wiring structure 32. The third front bump 33 is connected to the third integrated circuit through the wirings in the third wiring structure 32.

[0075] The third front bump 33 includes a conductive post 33a located below the third wiring structure 32 and a solder layer 33b located below the conductive post 33a.

[0076] In one embodiment, the conductive post 33a of the third front bump 33 may be formed of a nickel layer. In another embodiment, the conductive post 33a of the third front bump 33 may be formed of a copper layer and a nickel layer beneath the copper layer. The solder layer 33b of the third front bump 33 may include a tin-silver alloy.

[0077] A UBM pattern (not shown) may be provided between the third wiring structure 32 and the third front bump 33. The UBM pattern may include a barrier metal layer located below the third wiring structure 32 and a seed layer located below the barrier metal layer. The conductive pillars 33a of the third front bump 33 may be formed using the seed layer through an electroplating process.

[0078] The third semiconductor chip 30 is connected to the second semiconductor chip 20 via a third front bump 33. The third front bump 33 of the third semiconductor chip 30 is disposed above the second rear bump 24. The third front bump 33 overlaps perpendicularly with the second rear bump 24. The solder layer 33b of the third front bump 33 is bonded to the second rear bump 24.

[0079] The first front bump 13A of the first semiconductor chip 10 is bonded to the carrier bump 51. The first front bump 13A of the first semiconductor chip 10 is disposed above the carrier bump 51. The first front bump 13A overlaps perpendicularly with the carrier bump 51. The solder layer 13Ab of the first front bump 13A is bonded to the carrier bump 51.

[0080] The carrier bump 51 comprises at least one metal. In one embodiment, the carrier bump 51 may consist of a copper layer and a nickel layer on the copper layer. In another embodiment, the carrier bump 51 may be composed of a nickel layer.

[0081] A first dummy bump 13B of a first semiconductor chip 10 is bonded to a second dummy bump 52. The first dummy bump 13B of the first semiconductor chip 10 is disposed above the second dummy bump 52. The first dummy bump 13B and the second dummy bump 52 overlap perpendicularly. The solder layer 13Bb of the first dummy bump 13B is bonded to the second dummy bump 52.

[0082] A first test bump 13C of a first semiconductor chip 10 is bonded to a second test bump 53. The first test bump 13C of the first semiconductor chip 10 is disposed above the second test bump 53. The first test bump 13C and the second test bump 53 overlap perpendicularly. The solder layer 13Cb of the first test bump 13C is bonded to the second test bump 53.

[0083] The second dummy bump 52 and the second test bump 53 can be formed together with the carrier bump 51 during the formation of the carrier bump 51. The second dummy bump 52 and the second test bump 53 can be made of the same material as the carrier bump 51. In one embodiment, the second dummy bump 52 and the second test bump 53 can be formed of a copper layer and a nickel layer below the copper layer. In another embodiment, the second dummy bump 52 and the second test bump 53 can be formed of a nickel layer.

[0084] The molding component 40 covers and surrounds the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the carrier bump 51, the second dummy bump 52, and the second test bump 53. The molding component 40 protects the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the carrier bump 51, the second dummy bump 52, and the second test bump 53 from the influence of the external environment.

[0085] The molding member 40 covers the side surfaces of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30, as well as the lower surface of the first semiconductor chip 10. The molding member 40 exposes the upper surface of the third semiconductor chip 30. The upper surface of the molding member 40 and the upper surface of the third semiconductor chip 30 may be on the same plane. In one embodiment, because the upper surface of the third semiconductor chip 30 is exposed, the heat generated when the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 are operated can be released to the outside of the chip stack package 100 through the upper surface of the third semiconductor chip 30.

[0086] The molding member 40 can extend to fill the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. The molding member 40 can have a molded underfill (MUF) shape for filling the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. As another example, the space between the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip 30 can be filled with an underfill material different from that of the molding member 40. As another example, an adhesive layer can be provided between the first semiconductor chip and the second semiconductor chip, and between the second semiconductor chip and the third semiconductor chip, thereby attaching the semiconductor chips to each other.

[0087] The molded component 40 can be formed using a liquid sealant through a molding process. The sealant may include an epoxy molding compound (EMC). The epoxy molding compound may include a resin and fillers.

[0088] The lower surfaces of the carrier bump 51, the second dummy bump 52, and the second test bump 53 are exposed to the lower surface of the molding member 40. These surfaces may be coplanar with the lower surface of the molding member 40. A passivation layer 80 is disposed on the lower surface of the molding member 40. A first opening OP1 is formed in the passivation layer 80, through which the lower surface of the carrier bump 51 is exposed. A second opening OP2 is formed in the passivation layer 80, through which the lower surface of the second test bump 53 is exposed. The passivation layer 80 covers the lower surface of the second dummy bump 52. The passivation layer 80 includes an insulating material. The insulating material may include a polymer-based photosensitive material.

[0089] An external connecting bump 61 is disposed below the carrier bump 51 exposed through the first opening OP1. The upper part of the external connecting bump 61 is disposed inside the first opening OP1.

[0090] The first opening OP1 has a larger planar area than the carrier bump 51. The external connecting bump 61 may have a larger planar area than the carrier bump 51. The external connecting bump 61 is disposed below the carrier bump 51 and the molding member 40 surrounding the carrier bump 51. The external connecting bump 61 overlaps perpendicularly with the carrier bump 51 and the molding member 40 surrounding the carrier bump 51.

[0091] The external connection bump 61 includes a first copper layer 61a, a first nickel layer 61b below the first copper layer 61a, a second copper layer 61c below the first nickel layer 61b, and a solder layer 61d below the second copper layer 61c.

[0092] The thickness of the first copper layer 61a can be greater than the thickness of the first nickel layer 61b. The first copper layer 61a, made of copper which has a lower resistivity than nickel, can be formed thicker than the first nickel layer 61b to ensure the conductivity of the external connection bump 61. In one embodiment, the thickness of the layers can be measured, for example, in the vertical direction or stacking direction of the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30.

[0093] A first nickel layer 61b is interposed between a first copper layer 61a and a second copper layer 61c. A copper-solder intermetallic compound (not shown) may be formed between the second copper layer 61c and the solder layer 61d. The first nickel layer 61b can suppress the diffusion of copper contained in the first copper layer 61a toward the interface between the second copper layer 61c and the solder layer 61d, thereby preventing the formation of a thick copper-solder intermetallic compound. The side surface of the first nickel layer 61b may protrude beyond the side surfaces of the first copper layer 61a and the second copper layer 61c. The central portion of the first nickel layer 61b may overlap with the first copper layer 61a and the second copper layer 61c, and the flange of the first nickel layer 61b may not overlap with the first copper layer 61a and the second copper layer 61c.

[0094] The second copper layer 61c is interposed between the first nickel layer 61b and the solder layer 61d. Because nickel solder intermetallic compounds have a higher volume shrinkage rate than copper solder intermetallic compounds, they are more prone to void formation and are more brittle. Since cracks initiate and propagate rapidly within voids, nickel solder intermetallic compounds are more prone to crack defects than copper solder intermetallic compounds. According to one embodiment of this disclosure, since the second copper layer 61c is disposed between the first nickel layer 61b and the solder layer 61d, the formation of nickel solder intermetallic compounds can be suppressed.

[0095] The thickness of the second copper layer 61c is less than the thickness of the first copper layer 61a. Because in one embodiment, the diffusion of copper contained in the first copper layer 61a into the interface between the second copper layer 61c and the solder layer 61d can be suppressed by the first nickel layer 61b, and the second copper layer 61c has a smaller thickness than the first copper layer 61a, the copper solder intermetallic compound can be formed as a thin film between the second copper layer 61c and the solder layer 61d.

[0096] A first UBM pattern 71a is provided between the external connecting bump 61 and the carrier bump 51, and between the external connecting bump 61 and the molding member 40. The first UBM pattern 71a includes a barrier metal layer located below the carrier bump 51 and the molding member 40, and a seed layer located below the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The first copper layer 61a, the first nickel layer 61b, and the second copper layer 61c of the external connecting bump 61 can be formed using the seed layer of the first UBM pattern 71a through an electroplating process.

[0097] Test pad 62 is disposed on the second test bump 53 exposed through the second opening OP2. Test pad 62 may have a planar area larger than that of the second test bump 53. Test pad 62 is disposed below the second test bump 53 and the molding member 40 surrounding the second test bump 53. Test pad 62 overlaps perpendicularly with the second test bump 53 and the molding member 40 surrounding the second test bump 53. In one embodiment, test pad 62 may include copper. Test pad 62 may be a copper layer. In one embodiment, test pad 62 may include nickel. Test pad 62 may be a nickel layer. In an embodiment, test pad 62 may include a first copper layer, a nickel layer below the first copper layer, a second copper layer below the nickel layer, and a solder layer below the second copper layer. In one embodiment, test pad 62 may include a nickel layer and a gold layer below the nickel layer.

[0098] A second UBM pattern 71b can be formed between the test pad 62 and the second test bump 53, and between the test pad 62 and the molding member 40. The second UBM pattern 71b may include a barrier metal layer located beneath the second test bump 53 and the molding member 40, and a seed layer located beneath the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The test pad 62 can be formed using the seed layer of the second UBM pattern 71b through an electroplating process.

[0099] The chip stack-up package 100 may also include a first alignment key AK1. The first alignment key AK1 may not overlap with the first semiconductor chip 10. During the formation of the external connection bump 61, the first alignment key AK1 can be used as a reference point (e.g., a zero point) to determine the position of the external connection bump 61. During the formation of the test pad 62, the first alignment key AK1 can be used as a reference point to determine the position of the test pad 62. During the cutting of the molding member 40 to individualize the chip stack-up package 100, the first alignment key AK1 can be used as a reference point to determine the cutting position of the molding member 40.

[0100] In one embodiment, the first alignment key AK1 may be formed together with the carrier bump 52 during the formation of the carrier bump 51. The first alignment key AK1 may be a bump disposed at the same height level as the carrier bump 51. The upper and side surfaces of the first alignment key AK1 may be surrounded by the molding member 40. The lower surface of the first alignment key AK1 may be exposed to the lower surface of the molding member 40. The first alignment key AK1 is not used for inputting or / and outputting data signals, power supply voltage, and ground voltage. Electrical signals may not be applied to the first alignment key AK1. The first alignment key AK1 may be electrically floated.

[0101] Reference Figure 2The first opening OP1 of the passivation layer 80 may have an inverted conical structure in which the width increases with increasing distance from the molding member 40. As described above, the passivation layer 80 may be formed of a polymer-based photosensitive material. A photosensitive material layer may be formed on the carrier bump 51 and the molding member 40, and the photosensitive material layer may be partially removed by an exposure process and a development process to form the first opening OP1. After the first opening OP1 is formed, the photosensitive material layer may be hardened by a curing process to form the passivation layer 80. During the curing process, the photosensitive material layer may shrink, and the width of the shrinkage of the photosensitive material layer may increase with increasing distance from the molding member 40. Therefore, the width of the first opening OP1 may increase with increasing distance from the molding member 40, and the first opening OP1 may have an inverted conical structure in which the width increases with increasing distance from the molding member 40.

[0102] The width of the first copper layer 61a of the external connection bump 61 is W1. The minimum width of the first opening OP1 of the passivation layer 80 is W2. W2 is greater than W1. The planar area of ​​the first opening OP1 can be greater than the planar area of ​​the external connection bump 61. The external connection bump 61 and the passivation layer 80 are spaced apart from each other. The passivation layer 80 does not contact the external connection bump 61.

[0103] Figure 3 and Figure 4 This is a cross-sectional view showing a first front bump, a carrier bump, an external connection bump, and a passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0104] Reference Figure 3 The conductive post 13Aa' of the first front protrusion 13A' includes a copper layer 13Aa1 and a nickel layer 13Aa2 below the copper layer 13Aa1. The nickel layer 13Aa2 covers the lower surface of the copper layer 13Aa1. The nickel layer 13Aa2 is disposed between the copper layer 13Aa1 and the solder layer 13Ab'.

[0105] The thickness of the copper layer 13Aa1 is greater than the thickness of the nickel layer 13Aa2. In one embodiment, the conductivity of the first front bump 13A' can be improved because the copper layer 13Aa1, made of copper which has a lower resistivity than nickel, is formed to be thicker than the nickel layer 13Aa2. Although not shown, a copper-solder intermetallic compound can be formed at the interface between the conductive pillar 13Aa' and the solder layer 13Ab'. The nickel layer 13Aa2 can suppress the diffusion of copper contained in the copper layer 13Aa1 to the interface between the conductive pillar 13Aa' and the solder layer 13Ab'. Therefore, in one embodiment, the formation of a thick copper-solder intermetallic compound can be suppressed.

[0106] The side surface of the nickel layer 13Aa2 may protrude more in the horizontal direction than the side surface of the copper layer 13Aa1. The center of the nickel layer 13Aa2 may overlap perpendicularly with the copper layer 13Aa1, and the flange portion of the nickel layer 13Aa2 may not overlap perpendicularly with the copper layer 13Aa1.

[0107] The carrier bump 51' includes a copper layer 51a and a nickel layer 51b on the copper layer 51a. The nickel layer 51b covers the upper surface of the copper layer 51a. The nickel layer 51b is disposed between the copper layer 51a and the solder layer 13Ab'. The thickness of the copper layer 51a is greater than the thickness of the nickel layer 51b.

[0108] Although not shown, a copper-solder intermetallic compound can be formed at the interface between the carrier bump 51' and the solder layer 13Ab' when bonding is performed. The nickel layer 51b can suppress the diffusion of copper contained in the copper layer 51a to the interface between the carrier bump 51' and the solder layer 13Ab'. Therefore, in one embodiment, the formation of a thick copper-solder intermetallic compound can be suppressed.

[0109] Reference Figure 4 The width of the first copper layer 61a of the external connecting bump 61 is W1. The maximum width of the first opening OP1-1 of the passivation layer 80-1 is W3. W3 is less than W1. The planar area of ​​the first opening OP1-1 of the passivation layer 80-1 can be smaller than the planar area of ​​the external connecting bump 61.

[0110] An external connection bump 61 is disposed below the carrier bump 51 exposed by the first opening OP1-1 and below the passivation layer 80-1 surrounding the carrier bump 51. The external connection bump 61 overlaps perpendicularly with the carrier bump 51 exposed by the first opening OP1-1 and the passivation layer 80-1 surrounding the first opening OP1-1. A first UBM pattern 71a-1 is formed between the external connection bump 61 and the carrier bump 51 and between the external connection bump 61 and the passivation layer 80-1.

[0111] Figure 5 This is a plan view illustrating a chip stacked package according to an embodiment of the present disclosure. Figure 5 This is a plan view of the chip stacked package as seen from the bottom of the molded component 40.

[0112] Reference Figure 5 Multiple bumps 51, 52, and 54 are disposed in the region that perpendicularly overlaps with the first semiconductor chip 10. The first alignment key AK1 is disposed on the outer side of the region that perpendicularly overlaps with the first semiconductor chip 10.

[0113] The first alignment key AK1 may have a different planar shape than the bumps 51, 52 and 54. The bumps 51, 52 and 54 may have a circular planar shape, while the first alignment key AK1 may have a hook-shaped or "ㄱ"-shaped planar shape. Figure 5 The first alignment key AK1 is shown in a planar shape with a hook shape, but the planar shape of the first alignment key AK1 can be changed to various shapes such as square or triangle.

[0114] The bumps include a carrier bump 51, a second dummy bump 52, and a second alignment bump 54. The second alignment bump 54 constitutes a second alignment key AK2. The second alignment bump 54 has a different arrangement than the carrier bump 51 and the second dummy bump 52. Therefore, semiconductor stacked package manufacturing equipment can identify the second alignment bump 54 to specify the precise location of the semiconductor chip.

[0115] The second alignment button AK2 can serve the same function as the first alignment button AK1. Figure 5 The illustration shows a case that includes both the first alignment key AK1 and the second alignment key AK2, but it is possible to include only one of the first alignment key AK1 and the second alignment key AK2.

[0116] Figure 6A and Figure 6B This is a diagram of the second alignment bump used in the specification according to an embodiment of this disclosure.

[0117] Reference Figure 6A During the formation of the carrier bump 51, the second alignment bump 54 can be formed together with the carrier bump 51. The second alignment bump 54 can be formed of the same material as the carrier bump 51. The second alignment bump 54 can have the same dimensions as the carrier bump 51.

[0118] The first alignment bump 13D is engaged with the second alignment bump 54. The first alignment bump 13D includes a conductive post 13Da and a solder layer 13Db.

[0119] The conductive post 13Da of the first alignment bump 13D can be formed together with the conductive post 13Aa of the first front bump 13A during the formation of the conductive post 13Aa of the first front bump 13A. The conductive post 13Da of the first alignment bump 13D can be made of the same material as the conductive post 13Aa of the first front bump 13A. The conductive post 13Da of the first alignment bump 13D can have the same dimensions as the conductive post 13Aa of the first front bump 13A.

[0120] The solder layer 13Db of the first alignment bump 13D can be formed together with the solder layer 13Ab of the first front bump 13A during the formation of the solder layer 13Ab of the first front bump 13A. The solder layer 13Db of the first alignment bump 13D can be formed of the same material as the solder layer 13Ab of the first front bump 13A.

[0121] A first alignment bump 13D is disposed above a second alignment bump 54. The first alignment bump 13D overlaps perpendicularly with the second alignment bump 54. The solder layer 13Db of the first alignment bump 13D is bonded to the second alignment bump 54. The side surfaces of the first alignment bump 13D and the second alignment bump 54 are surrounded by a molding member 40. The lower surface of the second alignment bump 54 may be exposed to the lower surface of the molding member 40.

[0122] The lower surface of the second alignment bump 54 is covered by a passivation layer 80. The second alignment bump 54 may not be used for input or / or output data signals, power supply voltage, and ground voltage. No electrical signals are applied to the second alignment bump 54. The second alignment bump 54 can be electrically floated.

[0123] Reference Figure 6B A third opening OP3 is formed in the passivation layer 80' to expose the lower surface of the second alignment bump 54'. An external connection bump 61' can be connected to the second alignment bump 54' exposed through the third opening OP3. The second alignment bump 54' can transmit one of a data signal, a power supply voltage, and a ground voltage.

[0124] Figures 7 to 9 The images show cross-sectional views of chip stack-up packages according to embodiments of the present disclosure, arranged in sequence.

[0125] Reference Figure 7 A first UBM layer 72 is formed on the first carrier substrate 90, the carrier bump 51, and the second dummy bump 52. A second test bump 53 is formed on the first UBM layer 72. Although not shown, alignment keys may be further formed on the first UBM layer 72 during the process of forming the carrier bump 51, the second dummy bump 52, and the second test bump 53.

[0126] Although not shown, a debonding layer may be further formed on the first carrier substrate 90 prior to the formation of the first UBM layer 72. In one embodiment, the debonding layer may have adhesive properties and may be composed of a material having adhesive strength that can be reduced by at least one of chemical and optical treatments.

[0127] The first UBM layer 72 includes a barrier metal layer and a seed layer on the barrier metal layer. The barrier metal layer may include titanium, and the seed layer may include copper. The barrier metal layer and the seed layer may be formed by a deposition method such as sputtering.

[0128] The carrier bump 51, the second dummy bump 52, and the second test bump 53 can be formed by forming a first electroplated resist pattern on the first UBM layer 72, having an opening area that provides a template for the carrier bump 51, the second dummy bump 52, and the second test bump 53, and then plating metal into the opening area of ​​the first electroplated resist pattern. After forming the carrier bump 51, the second dummy bump 52, and the second test bump 53, the first electroplated resist pattern can be removed.

[0129] In one embodiment, each of the carrier bump 51, the second dummy bump 52, and the second test bump 53 may be formed of a nickel layer grown on a seed layer by an electroplating process. In another embodiment, each of the carrier bump 51, the second dummy bump 52, and the second test bump 53 may be formed of a copper layer grown on a seed layer by an electroplating process and a nickel layer grown on the copper layer by an electroplating process.

[0130] Reference Figure 8 The first semiconductor chip 10, the second semiconductor chip 20 and the third semiconductor chip 30 are stacked on the first carrier substrate 90 to form a molding component 40.

[0131] The first semiconductor chip 10 includes a first front bump 13A located on its lower surface and a second rear bump 14 located on its upper surface. The first front bump 13A is connected to the first rear bump 14 through wiring of the first wiring structure 12 and a first through-hole 15. The first semiconductor chip 10 also includes a first dummy bump 13B and a first test bump 13C located on its lower surface.

[0132] The first front bump 13A includes a conductive post 13Aa and a solder layer 13Ab beneath the conductive post 13Aa. In one embodiment, the conductive post 13Aa of the first front bump 13A may be formed of a nickel layer. In another embodiment, the conductive post 13Aa of the first front bump 13A may be formed of a copper layer and a nickel layer beneath the copper layer. The solder layer 13Ab of the first front bump 13A comprises a tin-silver alloy.

[0133] The first dummy bump 13B includes a conductive post 13Ba and a solder layer 13Bb beneath the conductive post 13Ba. The first test bump 13C includes a conductive post 13Ca and a solder layer 13Cb beneath the conductive post 13Ca.

[0134] The conductive post 13Ba of the first dummy bump 13B and the conductive post 13Ca of the first test bump 13C are made of the same material as the conductive post 13Aa of the first front bump 13A. The solder layer 13Bb of the first dummy bump 13B and the solder layer 13Cb of the first test bump 13C are made of the same material as the solder layer 13Ab of the first front bump 13A.

[0135] The first semiconductor chip 10 is bonded to the first carrier substrate 90.

[0136] A first semiconductor chip 10 can be disposed on a first carrier substrate 90, such that the first front bump 13A, the first dummy bump 13B, and the first test bump 13C of the first semiconductor chip 10 contact the carrier bump 51, the second dummy bump 52, and the second test bump 53 disposed on the first carrier substrate 90, respectively. Then, reflow bonding is performed to bond the first front bump 13A, the first dummy bump 13B, and the first test bump 13C of the first semiconductor chip 10 to the carrier bump 51, the second dummy bump 52, and the second test bump 53, respectively.

[0137] The second semiconductor chip 20 includes a second front bump 23 located on its lower surface and a second rear bump 24 located on its upper surface. The second front bump 23 includes a conductive post 23a and a solder layer 23b below the conductive post 23a. The second front bump 23 is connected to the second rear bump 24 through a second through-hole 25 and wiring of a second wiring structure 22.

[0138] The second semiconductor chip 20 is stacked on the first semiconductor chip 10. The second semiconductor chip 20 is disposed on the first semiconductor chip 10 such that the second front bump 23 of the second semiconductor chip 20 contacts the first rear bump 14 of the first semiconductor chip 10.

[0139] The third semiconductor chip 30 includes a third front bump 33 located on its lower surface. The third front bump 33 includes a conductive post 33a and a solder layer 33b below the conductive post 33a.

[0140] A third semiconductor chip 30 is stacked on top of a second semiconductor chip 20. The third semiconductor chip 30 is disposed on the second semiconductor chip 20 such that the third front bump 33 of the third semiconductor chip 30 contacts the second rear bump 24 of the second semiconductor chip 20.

[0141] A large-scale reflow bonding process is performed to bond a second semiconductor chip 20 to a first semiconductor chip 10 and a third semiconductor chip 30 to the second semiconductor chip 20. In one embodiment, the large-scale reflow bonding process can bond multiple semiconductor chips together at once, which is beneficial for improving productivity.

[0142] A preliminary molding member is formed to fill the space between the first carrier substrate 90 and the first semiconductor chip 10, and to cover the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. Then, in one embodiment, a polishing process is performed on the upper surface of the preliminary molding member to form the molding member 40, thereby reducing the height of the chip stack package to a target value. During the polishing process, the upper surface of the third semiconductor chip 30 can be exposed, and the third semiconductor chip 30 can be polished together with the preliminary molding member, thereby reducing the thickness of the third semiconductor chip 30.

[0143] The molding member 40 can be formed as a molded underfill (MUF) shape that fills the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. Although in one embodiment the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 is filled with the molding member 40, in another embodiment the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 can be filled with an underfill member different from the molding member 40. In one embodiment, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 can be attached to each other using a non-conductive film via thermoforming, and the non-conductive film can be disposed in the space between the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30.

[0144] Reference Figure 9 Remove the first carrier substrate ( Figure 8 90) and the first UBM layer ( Figure 8 72). In one embodiment, the degradation of the material disposed on the first carrier substrate can be achieved by using at least one of chemical treatment and optical treatment. Figure 8 90) and the first UBM layer ( Figure 8 The adhesion of the debonding layer between (72) can then be separated by peeling off the first carrier substrate ( Figure 8 90%. In one embodiment, the first carrier substrate ( ) can be removed by a polishing process. Figure 8 90%. The first UBM layer can be removed by an etching process. Figure 8 72).

[0145] Subsequently, a passivation layer 80 is formed on the lower surface of the molded component 40 exposed by removing the first UBM layer. The passivation layer 80 covers the dummy bump 52. A first opening OP1 is formed in the passivation layer 80 to expose the carrier bump 51. A second opening OP2 is formed in the passivation layer 80 to expose the second test bump 53.

[0146] Furthermore, a second UBM layer is formed over the opening regions through the first opening OP1 and the second opening OP2 and over the passivation layer 80. A second electroplated resist pattern with opening regions for providing a template for the test pad 62 is formed on the second UBM layer, and metal is electroplated over the opening regions of the second electroplated resist pattern to form the test pad 62. After the test pad 62 is formed, the second electroplated resist pattern can be removed.

[0147] A third electroplated resist pattern is formed on the second UBM layer, having an opening area that provides a template for the external connection bump 61, and metal is electroplated in the opening area of ​​the third electroplated resist pattern to form the external connection bump 61. After the external connection bump 61 is formed, the third electroplated resist pattern can be removed.

[0148] The second UBM layer is a prestructure used to form the first UBM pattern 71a and the second UBM pattern 71b. The second UBM layer may include a barrier metal layer and a seed layer on the barrier metal layer. The barrier metal layer may include titanium, and the seed layer may include copper. The barrier metal layer and the seed layer may be formed by a deposition method such as sputtering. The first UBM pattern 71a and the second UBM pattern 71b may be formed by removing the second UBM layer, which is exposed again by removing the third electroplated resist pattern, after removing the third electroplated resist pattern.

[0149] In addition to this embodiment, in the comparative example, the first semiconductor chip is temporarily attached to the carrier substrate via an adhesive layer. Due to heat and pressure applied in subsequent processes such as the process of stacking a second and third semiconductor chip on the first semiconductor chip and molding processes, the first semiconductor chip may move or tilt in the x, y, and z directions, which may cause the semiconductor chip to deviate from its designated position. Therefore, in the comparative example, appearance defects or contact defects may occur. According to this embodiment, by attaching the first front bump 13A of the first semiconductor chip 10 to the carrier bump 51 of the carrier substrate 90, the first semiconductor chip 10 can be fixed without movement during the packaging manufacturing process. Therefore, in one embodiment, defects caused by movement of the first semiconductor chip 10 can be prevented or mitigated.

[0150] Figure 10 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure. Figure 11 yes Figure 10 A magnified view of part B, and Figure 12 and Figure 13 This is a cross-sectional view showing a first front bump, a carrier bump, an external connection bump, and a passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0151] refer to Figure 10 and Figure 11 The passivation layer 80-2 of the chip stacked package 200 includes a first opening OP1-2. The first opening OP1-2 has a tapered shape in which the width decreases as the first opening moves away from the first semiconductor chip 10. The second opening OP2-2 of the passivation layer 80-2 has a tapered shape in which the width decreases as the second opening moves away from the first semiconductor chip 10.

[0152] Before forming the first UBM layer on the carrier substrate, a photosensitive material layer can be formed, and a first opening OP1-2 and a second opening OP2-2 can be formed in the photosensitive material layer through exposure and development processes. After forming the first opening OP1-2 and the second opening OP2-2, the photosensitive material layer can be hardened by a curing process to form a passivation layer 80-2. During the curing process, the photosensitive material layer can shrink, and the shrinkage width of the photosensitive material layer can increase with the increase of the distance from the carrier substrate. Therefore, the width of the first opening OP1-2 and the width of the second opening OP2-2 can increase with the distance from the carrier substrate (i.e., Figure 8 The width of the first opening OP1-2 and the second opening OP2-2 decreases as the distance from the first semiconductor chip 10 disposed on the passivation layer 80-2 decreases.

[0153] The carrier bump 51-1 overlaps perpendicularly with the first opening OP1-2. The lower end of the carrier bump 51-1 is located inside the first opening OP1-2. The second test bump 53-1 overlaps perpendicularly with the second opening OP2-2. The lower end of the second test bump 53-1 is located inside the second opening OP2-2. The second dummy bump 52-1 is disposed on the passivation layer 80-2.

[0154] The carrier bump 51-1 has a width W4. The maximum width of the first opening OP1-2 is W3a. W3a is less than W4. The planar area of ​​the first opening OP1-2 can be smaller than the planar area of ​​the carrier bump 51-1. The carrier bump 51-1 is perpendicularly overlapped with the first opening OP1-2 and the passivation layer 80-2 surrounding the first opening OP1-2. The third UBM pattern 72a is perpendicularly overlapped with the carrier bump 51-1. The third UBM pattern 72a is disposed between the carrier bump 51-1 and the external connecting bump 61, and between the carrier bump 51-1 and the passivation layer 80-2.

[0155] The fourth UBM pattern 72b overlaps perpendicularly with the second dummy bump 52-1. The fourth UBM pattern 72b is inserted between the second dummy bump 52-1 and the passivation layer 80-2.

[0156] The planar area of ​​the second opening OP2-2 is smaller than the planar area of ​​the second test bump 53-1. The second test bump 53-1 overlaps perpendicularly with the second opening OP2-2 and the passivation layer 80-2 surrounding the second opening OP2-2. The fifth UBM pattern 72c overlaps perpendicularly with the second test bump 53-1. The fifth UBM pattern 72c is disposed between the second test bump 53-1 and the test pad 62, and between the second test bump 53-1 and the passivation layer 80-2.

[0157] After the carrier substrate is removed, an external connection bump 61 is formed beneath the third UBM pattern 72a exposed by the removal of the carrier substrate and the passivation layer 80-2 surrounding the third UBM pattern 72a. The external connection bump 61 is perpendicularly overlapped with the third UBM pattern 72a and the passivation layer 80-2 surrounding the third UBM pattern 72a. The first UBM pattern 71a is disposed between the external connection bump 61 and the third UBM pattern 72a, and between the external connection bump 61 and the passivation layer 80-2.

[0158] After removing the carrier substrate, test pad 62 is formed on the fifth UBM pattern 72c exposed by removing the carrier substrate and the passivation layer 80-2 surrounding the fifth UBM pattern 72c. Test pad 62 is perpendicularly overlapped with the fifth UBM pattern 72c and the passivation layer 80-2 surrounding the fifth UBM pattern 72c. A second UBM pattern 71b is disposed between test pad 62 and the fifth UBM pattern 72c, and between test pad 62 and the passivation layer 80-2.

[0159] Reference Figure 12 The carrier bump 51-2 has a recess RC on its upper surface that contacts the solder layer 13Ab of the first front bump 13A. The recess RC may have a shape corresponding to the shape of the first opening OP1-2 of the passivation layer 80-2. The solder layer 13Ab of the first front bump 13A is disposed in the recess RC of the carrier bump 51-2. The recess RC of the carrier bump 51-2 is filled with the solder layer 13Ab of the first front bump 13A.

[0160] Reference Figure 13 The carrier bump 51 has a width W4. The minimum width of the first opening OP1-3 is W2a. W2a is greater than W4. The planar area of ​​the first opening OP1-3 of the passivation layer 80-3 can be greater than the planar area of ​​the carrier bump 51. The lower part of the carrier bump 51 is disposed within the first opening OP1-3. The passivation layer 80-3 and the carrier bump 51 are configured to be spaced apart from each other. The passivation layer 80-3 does not contact the carrier bump 51.

[0161] The protrusion PS of the molded component 40B is disposed inside the first opening OP1-3 between the passivation layer 80-3 and the carrier protrusion 51. The protrusion PS of the molded component 40B is disposed between the passivation layer 80-3 and the carrier protrusion 51. The protrusion PS of the molded component 40B is in contact with the passivation layer 80-3 and the carrier protrusion 51.

[0162] The planar area of ​​the first opening OP1-3 of the passivation layer 80-3 is larger than the planar area of ​​the external connecting bump 61. The external connecting bump 61 overlaps perpendicularly with the carrier bump 51 and the protrusion PS of the molding member 40. The first UBM pattern 71a is disposed between the external connecting bump 61 and the third UBM pattern 72a-1 and between the external connecting bump 61 and the protrusion PS of the molding member 40B.

[0163] Figure 14 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure. Figure 15 yes Figure 14 A magnified view of part C. Figure 16 This is a cross-sectional view showing the first front bump, outer bump, and passivation layer of a chip stacked package according to an embodiment of the present disclosure.

[0164] Reference Figure 14 and Figure 15 The conductive post 13Aa of the first front bump, the conductive post 13Ba of the first dummy bump, and the conductive post 13Ca of the first test bump of the chip stacked package 300 are exposed on the lower surface of the molding member 40C. The lower surfaces of the conductive post 13Aa of the first front bump, the conductive post 13Ba of the first dummy bump, and the conductive post 13Ca of the first test bump can be disposed on the same plane as the lower surface of the molding member 40C.

[0165] Remove Figure 8 The carrier substrate and the first seed layer are used, and the surfaces exposed by removing the first seed layer can be polished to expose the conductive pillars 13Aa of the first front bump, the conductive pillars 13Ba of the first dummy bump, and the conductive pillars 13Ca of the first test bump. During the polishing process, the conductive pillars 13Aa, 13Ba, and 13Ca of the first test bump can be removed. Figure 8 Carrier bump 51 Figure 8 The second dummy bump 52 Figure 8 The second test bump 53, the solder layer 13Ab of the first front bump, the solder layer 13Bb of the first dummy bump and the solder layer 13Cb of the first test bump.

[0166] An external connection bump 61 is disposed on the conductive post 13Aa of the first front bump. The external connection bump 61 includes a first copper layer 61a, a first nickel layer 61b, a second copper layer 61c, and a solder layer 61d.

[0167] A passivation layer 80-4 is provided on the lower surface of the molded component 40C. A first opening OP1-4 is formed in the passivation layer 80-4 to expose the conductive post 13Aa of the first front bump. A second opening OP2-4 is formed in the passivation layer 80-4 to expose the conductive post 13Ca of the first test bump. The passivation layer 80-4 covers the conductive post 13Ba of the first dummy bump.

[0168] The width of the first copper layer 61a of the external connection bump 61 is W1. The minimum width of the first opening OP1-4 of the passivation layer 80-4 is W2. W2 is greater than W1. The first opening OP1-4 of the passivation layer 80-4 has a larger planar area than the external connection bump 61. The external connection bump 61 and the passivation layer 80-4 are spaced apart from each other. The passivation layer 80-4 does not contact the external connection bump 61.

[0169] The first opening OP1-4 has an inverted conical structure whose width increases with the distance from the molding member 40C. A photosensitive material layer can be formed on the conductive pillar 13Aa and the first front protrusion of the molding member 40C. The first opening OP1-4 can be formed in the photosensitive material layer through an exposure and development process. After forming the first opening OP1-4, the photosensitive material layer can be hardened by a curing process to form a passivation layer 80-4. During the curing process, the photosensitive material layer can shrink, and the width of the shrinkage increases with the distance from the carrier substrate. Therefore, the width of the first opening OP1-4 decreases as the distance from the molding member 40C decreases. The first opening OP1-4 has an inverted conical structure whose width increases with the distance from the molding member 40C.

[0170] The external connecting bump 61 has a larger planar area than the conductive post 13Aa of the first front bump. The external connecting bump 61 overlaps perpendicularly with the conductive post 13Aa and the molded member 40C surrounding the conductive post 13Aa.

[0171] The first UBM pattern 71a-2 overlaps perpendicularly with the external connecting bump 61. The first UBM pattern 71a-2 is disposed between the external connecting bump 61 and the conductive post 13Aa, and between the external connecting bump 61 and the molding member 40C.

[0172] A test pad 62 is provided on the conductive post 13Ca of the first test bump. The test pad 62 has a larger planar area than the conductive post 13Ca of the first test bump. The test pad 62 overlaps perpendicularly with the conductive post 13Ca and the molding member 40C surrounding the conductive post 13Ca. A second UBM pattern 71b-2 is provided between the test pad 62 and the conductive post 13Ca, and between the test pad 62 and the molding member 40C.

[0173] Reference Figure 16The width of the first copper layer 61a of the external connecting bump 61 is W1. The maximum width of the first opening OP1-5 of the passivation layer 80-5 is W3b. W3b is less than W1. The planar area of ​​the first opening OP1-5 can be smaller than the planar area of ​​the external connecting bump 61.

[0174] The external connection bump 61 is perpendicularly overlapped with the conductive post 13Aa of the first front bump exposed through the first opening OP1-5 and the passivation layer 80-5 surrounding the conductive post 13Aa. The first UBM layer 71a-3 is perpendicularly overlapped with the external connection bump 61. The first UBM layer 71a-3 is disposed between the external connection bump 61 and the conductive post 13Aa, and between the external connection bump 61 and the passivation layer 80-5.

[0175] Figure 17 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure. Figure 18 yes Figure 17 A magnified view of part D. Figure 19 It is shown Figure 18 A plan view of the first chip pad, the second chip pad, the first front bump, the first test bump, the external connection bump, and the test pad.

[0176] refer to Figure 17 According to embodiments of the present disclosure, a chip stacked package 400 includes two first test bumps 13C and two second test bumps 53 electrically connected between a test pad 62-4 and a first semiconductor chip 10.

[0177] Reference Figure 18 The first wiring structure 12 of the first semiconductor chip 10 includes an insulating layer 12D and wiring 12W. The insulating layer 12D is disposed on the lower surface of the first substrate 11. The insulating layer 12D covers the lower surface of the first substrate 11. The wiring 12W is disposed within the insulating layer 12D. The wiring 12W includes a first chip pad PAD1 and a second chip pad PAD2. The insulating layer 12D has an opening on its lower surface, through which the first chip pad PAD1 and the second chip pad PAD2 are exposed respectively.

[0178] The first substrate 11 includes a first integrated circuit. The first integrated circuit may include a through-silicon via (TSV) region, a physical (PHY) region, and a design-test (DFT) region. The PHY region may include input / output circuitry for communicating with external devices (such as processors) of the chip stack-up package. A first chip pad PAD1 may be connected to the PHY region.

[0179] The DFT area can communicate with external test equipment in test mode. The DFT area can transmit signals from the test equipment to the TSV area. The second chip pad PAD2 can be connected to the DFT area.

[0180] A first front bump 13A is disposed below a first chip pad PAD1. The first front bump 13A is connected to the first chip pad PAD1. The first front bump 13A includes a conductive post 13Aa and a solder layer 13Ab. The conductive post 13Aa is disposed below the first chip pad PAD1. The solder layer 13Ab is disposed below the conductive post 13Aa. In one embodiment, the conductive post 13Aa of the first front bump 13A may include nickel. The conductive post 13Aa of the first front bump 13A may be a nickel layer. Although this embodiment illustrates the case where the first front bump 13A is a nickel layer, other embodiments are not limited thereto. The first front bump may have a structure in which a copper layer and a nickel layer are stacked, as referred to below. Figure 20 The structure described herein, or a structure in which copper layers, nickel layers, and copper layers are stacked, is as follows (see reference below). Figure 21 As stated above.

[0181] Although not shown, a UBM pattern (not shown) can be disposed between the first chip pad PAD1 and the conductive post 13Aa of the first front bump 13A. The UBM pattern can connect the first front bump 13A and the first chip pad PAD1. The UBM pattern may include a barrier metal layer disposed below the first chip pad PAD1 and a seed layer disposed below the barrier metal layer. The barrier metal layer may include titanium. The barrier metal layer may be a titanium layer. The seed layer may include copper. The conductive post 13Aa of the first front bump 13A can be formed using the seed layer through an electroplating process.

[0182] The first front bump 13A of the first semiconductor chip 10 is bonded to the carrier bump 51. The first front bump 13A of the first semiconductor chip 10 overlaps with the carrier bump 51, and the solder layer 13Ab of the first front bump 13A is bonded to the carrier bump 51.

[0183] In one embodiment, the carrier bump 51 may include nickel. The carrier bump 51 may be a nickel layer. While this embodiment illustrates a case where the carrier bump 51 is a nickel layer, other embodiments are not limited thereto. The carrier bump may have a structure in which copper and nickel layers are stacked, as described below. Figure 20 The structure may also have a copper layer, a nickel layer, and a copper layer stacked together, as described below. Figure 21 As stated above.

[0184] An external connection bump 61 is provided below the carrier bump 51. A first UBM pattern 71a is provided between the external connection bump 61 and the carrier bump 51. The first UBM pattern 71a connects the carrier bump 51 and the external connection bump 61.

[0185] Signals received from external devices via external connection bump 61 are transmitted to the PHY region via the first UBM pattern 71a, carrier bump 51, first front bump 13A, and first chip pad PAD1. Then, signals transmitted to the PHY region can be transmitted to the second semiconductor chip 20 and the third semiconductor chip 30 via the TSV region, the first through electrode 15, and the second through electrode 25.

[0186] A first test bump 13C is disposed below the second chip pad PAD2. The first test bump 13C is connected to the second chip pad PAD2. The first test bump 13C includes a conductive pillar 13Ca and a solder layer 13Cb. The conductive pillar 13Ca is disposed below the second chip pad PAD2. The solder layer 13Cb is disposed below the conductive pillar 13Ca.

[0187] The conductive post 13Ca of the first test bump 13C can be formed simultaneously with the conductive post 13Aa of the first front bump 13A. The conductive post 13Ca of the first test bump 13C may include the same material as the conductive post 13Aa of the first front bump 13A.

[0188] Although not shown, a UBM pattern can be disposed between the second chip pad PAD2 and the conductive post 13Ca of the first test bump 13C. The UBM pattern can connect the second chip pad PAD2 and the first test bump 13C. The UBM pattern may include a barrier metal layer disposed below the second chip pad PAD2 and a seed layer disposed below the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The conductive post 13Ca of the first test bump 13C can be formed using the seed layer through an electroplating process.

[0189] The solder layer 13Cb of the first test bump 13C can be formed simultaneously with the solder layer 13Ab of the first front bump 13A. The solder layer 13Cb of the first test bump 13C may include the same material as the solder layer 13Ab of the first front bump 13A.

[0190] Two first test bumps 13C can be positioned below a second chip pad PAD2. The two first test bumps 13C can be connected together to a second chip pad PAD2. Two second test bumps 53 can be individually attached to the two first test bumps 13C.

[0191] The second test bump 53 can be formed simultaneously with the carrier bump 51. The second test bump 53 can be made of the same material as the carrier bump 51. In one embodiment, the second test bump 53 can be a nickel layer.

[0192] The lower surface of the carrier bump 51 and the lower surface of the second test bump 53 can be exposed to the lower surface of the molding member 40D. The lower surfaces of the carrier bump 51 and the second test bump 53 can be disposed on the same plane as the lower surface of the molding member 40D.

[0193] Test pad 62-4 is disposed on the lower surface of the molded component 40D and on the lower surface of the two second test bumps 53. Test pad 62-4 protrudes below the lower surface of the molded component 40D. The two second test bumps 53 are connected together to one test pad 62-4.

[0194] One of the first test bumps 13C and the second test bump 53 connected thereto constitute a first electrical path connecting the second chip pad PAD2 and the test pad 62-4. The remaining first test bumps 13C and the second test bump 53 connected thereto constitute a second electrical path connecting the second chip pad PAD2 and the test pad 62-4. The first electrical path and the second electrical path are connected in parallel between a second chip pad PAD2 and a test pad 62-4.

[0195] In test mode, the test pins placed on the probe card of the test apparatus can contact the test pad 62-4 to apply a signal to the test pad 62-4. The signal applied to the test pad 62-4 is transmitted to the second chip pad PAD2 through a first electrical path and a second electrical path formed by two second test bumps 53 and two first test bumps 13C. The signal transmitted to the second chip pad PAD2 can be transmitted to the second semiconductor chip 20 and the third semiconductor chip 30 through the DFT region, the TSV region, the first through electrode 15 and the second through electrode 25.

[0196] Because two electrical paths are connected in parallel between the second chip pad PAD2 and the test pad 62-4, the resistance of the electrical paths can be reduced compared to the case where only one electrical path is connected between the second chip pad and the test pad. Even if one of the two electrical paths is open, an electrical connection can be established through the remaining path. Therefore, compared to configuring only one electrical path between the second chip pad and the test pad, the possibility of a defect where the second chip pad PAD2 and the test pad 62-4 are not connected can be reduced.

[0197] exist Figure 18 In this embodiment, the number of first test bumps 13C and second test bumps 53 connecting a second chip pad PAD2 and a test pad 62-4 is two, but this disclosure is not limited thereto. The number of first test bumps 13C and second test bumps 53 connecting a second chip pad PAD2 and a test pad 62-4 can be one, three or more.

[0198] refer to Figure 19 The first chip pad PAD1 has a width W11a. The conductive post 13Aa of the first front bump has a width W12a. W11a is greater than W12a. The planar area of ​​the first chip pad PAD1 is greater than the planar area of ​​the conductive post 13Aa of the first front bump. The width of the external connection bump 61 is W13a. W13a is greater than both W11a and W12a. The planar area of ​​the external connection bump 61 is greater than the planar area of ​​the first chip pad PAD1 and the planar area of ​​the conductive post 13Aa of the first front bump.

[0199] The width of the second chip pad PAD2 is W11b. The conductive post 13Ca of the first test bump has a width W12b. W11b is greater than W12b. The planar area of ​​the second chip pad PAD2 is greater than the planar area of ​​the conductive post 13Ca of the first test bump.

[0200] The width of test pad 62-4 is greater than the width of the second chip pad PAD2 and the width of the conductive post 13Ca of the first test bump. The width of test pad 62-4 is W13b. W13b is greater than W11b and W12b. The planar area of ​​test pad 62-4 is greater than the planar area of ​​the second chip pad PAD2 and the planar area of ​​the conductive post 13Ca of the first test bump.

[0201] The width of the second chip pad PAD2 is greater than the width of the first chip pad PAD1. W11b is greater than W11a. The planar area of ​​the second chip pad PAD2 is greater than the planar area of ​​the first chip pad PAD1.

[0202] The width of the conductive post 13Aa of the first front bump and the width of the conductive post 13Ca of the first test bump can be the same. W12a and W12b can be the same. The dimensions of the conductive post 13Aa of the first front bump and the dimensions of the conductive post 13Ca of the first test bump can be the same.

[0203] Unlike the embodiments of this disclosure, if the conductive posts of the first front bump and the first test bump, manufactured in the same process, have different dimensions, there is a possibility of process defects due to process imbalance caused by dimensional mismatch between the patterns. According to the embodiments of this disclosure, the conductive posts 13Aa of the first front bump and the conductive posts 13Ca of the first test bump, manufactured in the same process, have the same dimensions, thereby reducing, mitigating, suppressing, or preventing process defects.

[0204] The width of test pad 62-4 is greater than the width of external connection bump 61. W13b is greater than W13a. The planar area of ​​test pad 62-4 is greater than the planar area of ​​external connection bump 61.

[0205] Testing can be performed across a wide range of temperatures to assess the operational reliability of the chip stack-up package based on temperature variations. Temperature changes can cause the chip stack-up package to shrink and expand, which may alter the position of the second chip pads.

[0206] Unlike the embodiments disclosed herein, the probe pins of the test apparatus can directly contact the second chip pads of the first semiconductor chip without testing the pads. Due to increased integration and circuit speed, the size of components included in the first semiconductor chip gradually decreases, and the size of the second chip pads also decreases accordingly. As the size of the second chip pads decreases, the alignment margin between the probe pins and the second chip pads can become tighter when the probe pins contact them. During testing, temperature changes may cause the position of the second chip pads to change, and the alignment margin between the probe pins and the second chip pads may become tighter. Therefore, there is a possibility that the probe pins will contact parts other than the second chip pads. This could damage the first semiconductor chip and cause test failure.

[0207] Because the second chip pad is positioned further inward than the lower surface of the wiring structure of the first semiconductor chip, the probe card may collide with the external connection bumps around the second chip pad when the probe pins contact it, potentially damaging the external connection bumps. Increasing the length of the probe pins can prevent this collision. However, as the probe pin length increases, the resistance of the probe pins also increases, which may increase measurement errors during testing.

[0208] According to embodiments of this disclosure, the test pad 62-4 can be disposed below the molding member 40D, thereby allowing the test pad 62-4 to be configured in a large size without being limited by the design of the first semiconductor chip 10. Therefore, the alignment margin between the probe pins and the test pad 62-4 is increased, thereby suppressing or preventing the probe pins from contacting any part other than the test pad 62-4.

[0209] According to embodiments of this disclosure, since the test pad 62-4 protrudes beyond the surface of the molded component 40D, the probe card will not collide with the external connection bump 61 when the probe pin contacts the test pad 62-4, even without using long probe pins. Therefore, short probe pins can be used, thereby reducing the resistance of the probe pins and reducing measurement errors during testing.

[0210] Figure 20 and Figure 21 This is a diagram illustrating a first front bump, a carrier bump, a first test bump, and a second test bump of a chip stacked package according to embodiments of the present disclosure.

[0211] refer to Figure 20 The first front protrusion 13A' has a reference Figure 3 The first test bump 13C' has the same structure as the first front bump 13A'. The conductive post 13Ca' of the first test bump 13C' has the same structure as the conductive post 13Aa' of the first front bump 13A'. During the formation of the conductive post 13Aa' of the first front bump 13A', the conductive post 13Ca' of the first test bump 13C' can be formed together with the conductive post 13Aa' of the first front bump 13A'.

[0212] The conductive post 13Ca' of the first test bump 13C' includes a copper layer 13Ca1 and a nickel layer 13Ca2 located below the copper layer 13Ca1. The nickel layer 13Ca2 is disposed on the lower surface of the copper layer 13Ca1. The nickel layer 13Ca2 is disposed between the copper layer 13Ca1 and the solder layer 13Cb'.

[0213] The thickness of the copper layer 13Ca1 is greater than the thickness of the nickel layer 13Ca2. The copper layer 13Ca1, made of copper with a lower resistivity than nickel, can be formed thicker than the nickel layer 13Ca2 to ensure higher conductivity of the first test bump 13C'. Although not shown, a copper-solder intermetallic compound forms at the interface between the conductive pillar 13Ca' and the solder layer 13Cb'. The nickel layer 13Ca2 prevents copper contained in the copper layer 13Ca1 from diffusing to the interface between the conductive pillar 13Ca' and the solder layer 13Cb', thereby suppressing the formation of a thick copper-solder intermetallic compound.

[0214] The side surface of the nickel layer 13Ca2 can protrude further than the side surface of the copper layer 13Ca1. The central portion of the nickel layer 13Ca2 can overlap with the copper layer 13Ca1, and the flange portion of the nickel layer 13Ca2 can not overlap with the copper layer 13Ca1.

[0215] The carrier bump 51' has a reference Figure 3 The carrier bump 51' has the same structure as the carrier bump 51'. The second test bump 53' includes a copper layer 53a and a nickel layer 53b on the copper layer 53a. The nickel layer 53b covers the upper surface of the copper layer 53a. The nickel layer 53b is disposed between the copper layer 53a and the solder layer 13Cb'. The thickness of the copper layer 53a is greater than the thickness of the nickel layer 53b. The copper layer 53a, made of copper with a lower resistivity than nickel, can be formed thicker than the nickel layer 53b, resulting in higher conductivity for the second test bump 53'.

[0216] Although not shown, when the second test bump 53' and solder layer 13Cb' are joined, a copper-solder intermetallic compound can form at the interface between the second test bump 53' and solder layer 13Cb'. The nickel layer 53b prevents copper contained in the copper layer 53a from diffusing to the interface between the second test bump 53' and solder layer 13Cb', thereby suppressing the formation of a thick copper-solder intermetallic compound.

[0217] Reference Figure 21 The first front protrusion 13A” includes a conductive post 13Aa” and a solder layer 13Ab” below the conductive post 13Aa”. The conductive post 13Aa includes a third copper layer 13Aa1”, a first nickel layer 13Aa2” below the third copper layer 13Aa1”, and a fourth copper layer 13Aa3” below the first nickel layer 13Aa2”. The solder layer 13Ab is disposed below the fourth copper layer 13Aa3”.

[0218] The thickness of the third copper layer 13Aa1” can be greater than the thickness of the first nickel layer 13Aa2”. The third copper layer 13Aa1”, made of copper with a lower resistivity than nickel, can be formed to be thicker than the first nickel layer 13Aa2”, thereby enabling the first front bump 13A” to have higher conductivity.

[0219] A first nickel layer 13Aa2” is inserted between a third copper layer 13Aa1” and a fourth copper layer 13Aa3”. A copper-solder intermetallic compound (not shown) may be formed between the conductive pillar 13Aa” and the solder layer 13Ab”. The first nickel layer 13Aa2” can suppress the diffusion of copper contained in the third copper layer 13Aa1” to the interface between the conductive pillar 13Aa” and the solder layer 13Ab”, thereby suppressing the formation of a thick copper-solder intermetallic compound. The side surface of the first nickel layer 13Aa2” may protrude beyond the side surfaces of the third copper layer 13Aa1” and the fourth copper layer 13Aa3”. The central portion of the first nickel layer 13Aa2” may overlap with the third copper layer 13Aa1” and the fourth copper layer 13Aa3”, and the flange portion of the first nickel layer 13Aa2” may not overlap with the third copper layer 13Aa1” and the fourth copper layer 13Aa3”.

[0220] The fourth copper layer 13Aa3” is inserted between the first nickel layer 13Aa2” and the solder layer 13Ab”. Because the fourth copper layer 13Aa3” is located between the first nickel layer 13Aa2” and the solder layer 13Ab”, the formation of nickel-solder intermetallic compounds can be suppressed.

[0221] The thickness of the fourth copper layer 13Aa3” is less than the thickness of the third copper layer 13Aa1”. Since the copper contained in the third copper layer 13Aa1” is suppressed by the first nickel layer 13Aa2” to diffuse to the interface between the conductive pillar 13Aa” and the solder layer 13Ab”, and the thickness of the fourth copper layer 13Aa3” is less than that of the third copper layer 13Aa1”, the copper-solder intermetallic compound can be formed as a thin film between the conductive pillar 13Aa” and the solder layer 13Ab”.

[0222] The carrier bump 51” includes a fifth copper layer 51a”, a second nickel layer 51b” on the fifth copper layer 51a”, and a sixth copper layer 51c” on the second nickel layer 51b”. The thickness of the fifth copper layer 51a” can be greater than the thickness of the second nickel layer 51b”. The fifth copper layer 51a”, made of copper with a lower resistivity than nickel, can be formed to be thicker than the second nickel layer 51b”, so that the carrier bump 51” can have higher conductivity.

[0223] A second nickel layer 51b” is interposed between a fifth copper layer 51a” and a sixth copper layer 51c”. A copper-solder intermetallic compound (not shown) may be formed between the carrier bump 51” and the solder layer 13Ab”. The second nickel layer 51b” can inhibit the diffusion of copper contained in the fifth copper layer 51a” to the interface between the carrier bump 51” and the solder layer 13Ab”, thereby inhibiting the formation of a thick copper-solder intermetallic compound. The side surface of the second nickel layer 51b” may protrude beyond the side surfaces of the fifth copper layer 51a” and the sixth copper layer 51c”. The central portion of the second nickel layer 51b” overlaps with the fifth copper layer 51a” and the sixth copper layer 51c”, and the flange portion of the second nickel layer 51b” may not overlap with the fifth copper layer 51a” and the sixth copper layer 51c”.

[0224] The sixth copper layer 51c” is inserted between the second nickel layer 51b” and the solder layer 13Ab”. Because the sixth copper layer 51c” is located between the second nickel layer 51b” and the solder layer 13Ab”, the formation of nickel-solder intermetallic compounds can be suppressed.

[0225] The thickness of the sixth copper layer 51c” is less than the thickness of the fifth copper layer 51a”. Since the copper contained in the fifth copper layer 51a” is suppressed from diffusing into the interface between the carrier bump 51” and the solder layer 13Ab” through the second nickel layer 51b”, and the sixth copper layer 51c” has a smaller thickness than the fifth copper layer 51a”, a copper-solder intermetallic compound can be formed as a thin film between the carrier bump 51” and the solder layer 13Ab”.

[0226] Solder layer 13Ab” is inserted between the fourth copper layer 13Aa3” of the first front bump 13A” and the sixth copper layer 51c” of the carrier bump 51”. Solder layer 13Ab” contacts the fourth copper layer 13Aa3” of the first front bump 13A” and the sixth copper layer 51c” of the carrier bump 51”.

[0227] The first test bump 13C” may have the same structure as the first front bump 13A”. The first test bump 13C” includes a conductive post 13Ca” and a solder layer 13Cb below the conductive post 13Ca”. The conductive post 13Ca” includes a seventh copper layer 13Ca1”, a third nickel layer 13Ca2” below the seventh copper layer 13Ca1”, and an eighth copper layer 13Ca3” below the third nickel layer 13Ca2”. The solder layer 13Cb is disposed below the eighth copper layer 13Ca3”.

[0228] The thickness of the seventh copper layer 13Ca1” can be greater than the thickness of the third nickel layer 13Ca2”. The seventh copper layer 13Ca1”, made of copper with a lower resistivity than nickel, can be formed to be thicker than the third nickel layer 13Ca2”, so that the first test bump 13C” has higher conductivity.

[0229] A third nickel layer 13Ca2” is inserted between the seventh copper layer 13Ca1” and the eighth copper layer 13Ca3”. A copper-solder intermetallic compound (not shown) may be formed between the conductive pillar 13Ca” and the solder layer 13Cb”. The third nickel layer 13Ca2” can suppress the diffusion of copper contained in the seventh copper layer 13Ca1” to the interface between the conductive pillar 13Ca” and the solder layer 13Cb”, thereby suppressing the formation of a thick copper-solder intermetallic compound. The side surface of the third nickel layer 13Ca2” may protrude beyond the side surfaces of the seventh copper layer 13Ca1” and the eighth copper layer 13Ca3”. The central portion of the third nickel layer 13Ca2” may overlap with the seventh copper layer 13Ca1” and the eighth copper layer 13Ca3”, and the flange portion of the third nickel layer 13Ca2” may not overlap with the seventh copper layer 13Ca1” and the eighth copper layer 13Ca3”.

[0230] The eighth copper layer 13Ca3” is inserted between the third nickel layer 13Ca2” and the solder layer 13Cb”. Since the eighth copper layer 13Ca3” is located between the third nickel layer 13Ca2” and the solder layer 13Cb”, the formation of nickel-solder intermetallic compounds can be suppressed.

[0231] The thickness of the eighth copper layer 13Ca3” is less than the thickness of the seventh copper layer 13Ca1”. Since the copper contained in the seventh copper layer 13Ca1” is suppressed by the third nickel layer 13Ca2” to diffuse to the interface between the conductive pillar 13Ca” and the solder layer 13Cb”, and the thickness of the eighth copper layer 13Ca3” is less than that of the seventh copper layer 13Ca1”, the copper-solder intermetallic compound can be formed as a thin film between the conductive pillar 13Ca” and the solder layer 13Cb”.

[0232] The second test bump 53” includes a ninth copper layer 53a”, a fourth nickel layer 53b” on the ninth copper layer 53a”, and a tenth copper layer 53c” on the fourth nickel layer 53b”. A solder layer 13Cb” is bonded on the tenth copper layer 53c”. The thickness of the ninth copper layer 53a” can be greater than the thickness of the fourth nickel layer 53b”. The ninth copper layer 53a”, made of copper with a lower resistivity than nickel, can be formed thicker than the fourth nickel layer 53b”, so that the second test bump 53” can be configured to have higher conductivity.

[0233] A fourth nickel layer 53b” is inserted between the ninth copper layer 53a” and the tenth copper layer 53c”. A copper-solder intermetallic compound can be formed between the second test bump 53” and the solder layer 13Cb”. The fourth nickel layer 53b” can inhibit the diffusion of copper contained in the ninth copper layer 53a” to the interface between the second test bump 53” and the solder layer 13Cb”, thereby inhibiting the formation of a thick copper-solder intermetallic compound. The side surface of the fourth nickel layer 53b” can protrude beyond the side surfaces of the ninth copper layer 53a” and the tenth copper layer 53c”. The central portion of the fourth nickel layer 53b” overlaps with the ninth copper layer 53a” and the tenth copper layer 53c”, and the flange portion of the fourth nickel layer 53b” may not overlap with the ninth copper layer 53a” and the tenth copper layer 53c”.

[0234] The tenth copper layer 53c” is inserted between the fourth nickel layer 53b” and the solder layer 13Cb”. The tenth copper layer 53c” is located between the fourth nickel layer 53b” and the solder layer 13Cb”, thereby suppressing the formation of nickel-solder intermetallic compounds.

[0235] The thickness of the tenth copper layer 53c” is less than that of the ninth copper layer 53a”. The fourth nickel layer 53b” inhibits the diffusion of copper contained in the ninth copper layer 53a” into the interface between the second test bump 53” and the solder layer 13Cb”, and the tenth copper layer 53c” has a smaller thickness than the ninth copper layer 53a”, so the copper-solder intermetallic compound can be formed as a thin film between the second test bump 53” and the solder layer 13Cb”.

[0236] The solder layer 13Cb” is inserted between the eighth copper layer 13Ca3” of the first test bump 13C” and the tenth copper layer 53c” of the second test bump 53”. The solder layer 13Cb” is in contact with the eighth copper layer 13Ca3” of the first test bump 13C” and the tenth copper layer 53c” of the second test bump 53”.

[0237] Figure 22 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure, and Figure 23 yes Figure 22 A magnified view of part E.

[0238] refer to Figure 22 In the chip stacked package 500 according to an embodiment of the present disclosure, the lower surfaces of the conductive post 13Aa of the front bump and the conductive post 13Ca of the first test bump are exposed through the lower surface of the molding member 40G. The lower surfaces of the conductive post 13Aa of the front bump and the conductive post 13Ca of the first test bump can be disposed on the same plane as the lower surface of the molding member 40G.

[0239] The conductive posts 13Ca of the two first test bumps are connected between a test pad 62-4 and the first semiconductor chip 10. The conductive posts 13Ca of the two first test bumps are jointly connected to a single test pad 62-4.

[0240] Reference Figure 23 The conductive post 13Aa of the first front bump is located below the first chip pad PAD1. The conductive post 13Aa of the first front bump is connected to the first chip pad PAD1.

[0241] An external connecting bump 61-1 is disposed below the conductive post 13Aa of the first front bump. The external connecting bump 61-1 has a larger planar area than the conductive post 13Aa of the first front bump. The external connecting bump 61-1 overlaps with the conductive post 13Aa and the molded member 40G surrounding the conductive post 13Aa.

[0242] The first UBM pattern 71a' overlaps with the external connecting protrusion 61-1. The first UBM pattern 71a' is disposed between the external connecting protrusion 61-1 and the conductive post 13Aa of the first front protrusion, and between the external connecting protrusion 61-1 and the molding member 40G. The first UBM pattern 71a' connects the external connecting protrusion 61-1 and the conductive post 13Aa of the first front protrusion.

[0243] The conductive post 13Ca of the first test bump is located below the second chip pad PAD2. Two conductive posts 13Ca of the first test bump are located below one second chip pad PAD2. The two conductive posts 13Ca of the first test bump are connected to one second chip pad PAD2. The conductive posts 13Ca of the first test bump can be formed simultaneously with the conductive posts 13Aa of the preceding bump. The conductive posts 13Ca of the first test bump can be formed of the same material as the conductive posts 13Aa of the preceding bump.

[0244] Test pad 62-5 is positioned below the molded component 40G and the conductive posts 13Ca of the first test bump. Test pad 62-5 protrudes below the lower surface of the molded component 40G. Test pad 62-5 overlaps with the conductive posts 13Ca of the two first test bumps and the molded component 40G surrounding the conductive posts 13Ca of the two first test bumps. The conductive posts 13Ca of the two first test bumps are jointly connected to one test pad 62-5. The conductive posts 13Ca of the two first test bumps form a first electrical path and a second electrical path connecting the second chip pad PAD2 and the test pad 62-5. The two electrical paths are connected in parallel between the second chip pad PAD2 and the test pad 62-5.

[0245] The second UBM pattern 71b-5 overlaps with the test pad 62-5. The second UBM pattern 71b-5 is positioned between the test pad 62-5 and the conductive post 13Ca of the first test bump, and between the test pad 62-5 and the molded component 40G. The second UBM pattern 71b-5 connects the test pad 62-5 and the conductive post 13Ca.

[0246] Figure 24 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure, and Figure 25 yes Figure 23 A magnified view of part F.

[0247] refer to Figure 24 and Figure 25 According to embodiments of the present disclosure, the chip stacked package 600 includes a first semiconductor chip 10, a second semiconductor chip 20 and a third semiconductor chip 30, a molding member 40H, a carrier bump 51, a second test bump 53, a redistribution layer 80, an external connection bump 61” and a test pad 62”.

[0248] The second semiconductor chip 20 is stacked on the first semiconductor chip 10, and the third semiconductor chip 30 is stacked on the second semiconductor chip 20.

[0249] A first semiconductor chip 10 is connected to a carrier bump 51 and a second test bump 53 via a first front bump 13A and a first test bump 13C. The first front bump 13A of the first semiconductor chip 10 is disposed on the carrier bump 51, and the solder layer 13Ab of the first front bump 13A is bonded to the carrier bump 51. The first test bump 13C of the first semiconductor chip 10 is disposed on the second test bump 53, and the solder layer 13Cb of the first test bump 13C is bonded to the second test bump 53. The first semiconductor chip 10 is physically and electrically connected to the carrier bump 51 via the first front bump 13A. The first semiconductor chip 10 is physically and electrically connected to the second test bump 53 via the first test bump 13C.

[0250] The molding component 40H surrounds the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the carrier bump 51, and the second test bump 53. The lower surfaces of the carrier bump 51 and the second test bump 53 are exposed to the lower surface of the molding component 40H. The lower surfaces of the carrier bump 51 and the second test bump 53 are disposed on the same plane as the lower surface of the molding component 40H.

[0251] A redistribution layer 80 is disposed on the lower surface of the molded component 40H, the lower surface of the carrier bump 51, and the lower surface of the second test bump 53. The redistribution layer 80 includes a dielectric layer 81 and connecting lines 82a and 82b. The dielectric layer 81 may include an insulating material. The insulating material may include a polymer-based photosensitive material. The connecting lines 82a and 82b may also be metallic wiring. The metallic wiring may include copper (Cu).

[0252] The dielectric layer 81 may include a first dielectric layer 81a and a second dielectric layer 81b located below the first dielectric layer 81a. The first dielectric layer 81a is disposed on the lower surface of the molding member 40H, the lower surface of the carrier bump 51, and the lower surface of the second test bump 53.

[0253] The connecting lines include a first connecting line 82a and a second connecting line 82b. The first connecting line 82a includes a through-hole portion and a wiring portion. The through-hole portion of the first connecting line 82a penetrates the first dielectric layer 81a perpendicularly and is connected to a corresponding carrier bump 51. The wiring portion of the first connecting line 82a is disposed below the through-hole portion and the first dielectric layer 81a. The through-hole portion and the wiring portion of the first connecting line 82a can be integrally formed.

[0254] The third UBM pattern 71c” overlaps with the first connecting line 82a. The third UBM pattern 71c” can be disposed between the first connecting line 82a and the carrier bump 51, and between the first connecting line 82a and the first dielectric layer 81a. The third UBM pattern 71c” can connect the first connecting line 82a and the carrier bump 51.

[0255] The third UBM pattern 71c may include a barrier metal layer disposed beneath the carrier bump 51 and the first dielectric layer 81a, and a seed layer disposed beneath the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The first connection line 82a may be formed using the seed layer through an electroplating process.

[0256] The second connection line 82b includes a through-hole portion and a wiring portion. The second connection line 82b includes two through-hole portions and one wiring portion. Each of the through-hole portions of the second connection line 82b perpendicularly penetrates the first dielectric layer 81a and is connected to a corresponding second test bump 53. The second connection line 82b is connected to two second test bumps 53 via the two through-hole portions. The wiring portion of the second connection line 82b is disposed below the through-hole portions of the second connection line 82b and the first dielectric layer 81a. The through-hole portions and the wiring portion of the second connection line 82b can be integrally formed.

[0257] exist Figure 24 and Figure 25 In this embodiment, the number of second test bumps 53 connected to a second connection line 82b is two, but this disclosure is not limited thereto. In other embodiments, the number of second test bumps connected to a second connection line may be one, three or more.

[0258] The fourth UBM pattern 71d” can overlap with the second connecting line 82b. The fourth UBM pattern 71d” can be disposed between the second connecting line 82b and the second test bump 53 and between the second connecting line 82b and the first dielectric layer 81a. The fourth UBM pattern 71d” can connect the second connecting line 82b and the second test bump 53.

[0259] The fourth UBM pattern 71d may include a barrier metal layer disposed below the second test bump 53 and the first dielectric layer 81a, and a seed layer disposed below the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The second connection line 82b may be formed using the seed layer through an electroplating process.

[0260] The second dielectric layer 81b is disposed below the first dielectric layer 81a, the first connecting line 82a, and the second connecting line 82b. The second dielectric layer 81b covers the lower surface of the first dielectric layer 81a, the side surface and the lower surface of the first connecting line 82a, and the side surface and the lower surface of the second connecting line 82b.

[0261] An external connection bump 61” is disposed below the redistribution layer 80. The external connection bump 61” penetrates the second dielectric layer 81b vertically and connects to the first connection line 82a. The external connection bump 61” includes a first copper layer 61a, a nickel layer 61b located below the first copper layer 61a, a second copper layer 61c located below the nickel layer 61b, and a solder layer 61d located below the second copper layer 61c. The first copper layer 61a of the external connection bump 61” penetrates the second dielectric layer 81b vertically and connects to the first connection line 82a. A first UBM pattern 71a” overlaps with the external connection bump 61”. The first UBM pattern 71a” is disposed between the external connection bump 61” and the first connection line 82a, and between the external connection bump 61” and the second dielectric layer 81b. The first UBM pattern 71a” connects the external connection bump 61” and the first connection line 82a.

[0262] Test pad 62” is disposed below redistribution layer 80. The lower surface of test pad 62” is disposed below the lower surface of redistribution layer 80. Test pad 62” penetrates the second dielectric layer 81b vertically and connects to the second interconnect 82b. Test pad 62” includes a via portion that penetrates the second dielectric layer 81b vertically. Second UBM pattern 17b” is disposed between test pad 62” and the second interconnect 82b, and between test pad 62” and the second dielectric layer 81b. Second UBM pattern 17b” connects test pad 62” and the second interconnect 82b.

[0263] The width of test pad 62” is greater than the width of the second chip pad PAD2. For example... Figure 25 As shown, the width of the second chip pad PAD2 is W21. The width of the test pad 62” is W22. W22 is greater than W21.

[0264] The distance or gap between test pad 62” and the external connection bump 61” closest to test pad 62” is greater than the distance or gap between the second chip pad PAD2 and the first chip pad PAD1 closest to the second chip pad PAD2. The distance between the second chip pad PAD2 and the first chip pad PAD1 closest to the second chip pad PAD2 is d1. The distance between test pad 62” and the external connection bump 61” closest to test pad 62” is d2. d2 is greater than d1.

[0265] Figure 26 This is a cross-sectional view of a chip stacked package according to an embodiment of the present disclosure, and Figure 27 yes Figure 26 A magnified view of part G.

[0266] refer to Figure 26 and Figure 27According to embodiments of the present disclosure, the chip stacked package 700 includes a redistribution substrate 90, a first semiconductor chip 10, a second semiconductor chip 20, a third semiconductor chip 30, a molding member 40K, an external connection bump 61-1”, and a test pad 62-1”.

[0267] The redistribution substrate 90 includes a first interconnect 92a, a second interconnect 92b, a first bump pad 93a, a second bump pad 93b, and a dielectric layer 91. The dielectric layer 91 may include an insulating material. The insulating material may include a polymer-based photosensitive material. The dielectric layer 91 includes a first dielectric layer 91a and a second dielectric layer 91b on top of the first dielectric layer 91a. The first interconnect 92a, the second interconnect 92b, the first bump pad 93a, and the second bump pad 93b may be metal wiring. The metal wiring may include copper.

[0268] A first connecting line 92a penetrates the first dielectric layer 91a perpendicularly and extends on the upper surface of the first dielectric layer 91a. The first connecting line 92a includes a via portion and a wiring portion. The via portion of the first connecting line 92a penetrates the first dielectric layer 91a perpendicularly. The wiring portion of the first connecting line 92a is disposed on both the via portion and the first dielectric layer 91a. The via portion and the wiring portion of the first connecting line 92a can be integrally formed.

[0269] The second connection line 92b penetrates the first dielectric layer 91a perpendicularly and extends on the upper surface of the first dielectric layer 91a. The second connection line 92b includes a via portion and a wiring portion. The via portion of the second connection line 92b penetrates the first dielectric layer 91a perpendicularly. The wiring portion of the second connection line 92b is formed on the via portion of the second connection line 92b and the first dielectric layer 91a. The via portion and the wiring portion of the second connection line 92b can be integrally formed.

[0270] An external connection bump 61-1” is disposed below the redistribution substrate 90. The via portion of the first connection line 92a penetrates the first dielectric layer 91a and is connected to the external connection bump 61-1”. The external connection bump 61-1” overlaps with the via portion of the first connection line 92a and the first dielectric layer 91a surrounding the via portion of the first connection line 92a.

[0271] The first UBM pattern 71a-1” is disposed on the external connection bump 61-1”. The first UBM pattern 71a-1” is inserted between the external connection bump 61-1” and the first connection line 92a, and between the external connection bump 61-1” and the first dielectric layer 91a. The first UBM pattern 71a-1” connects the external connection bump 61-1” and the first connection line 92a.

[0272] Test pad 62-1” is disposed below redistribution substrate 90. The via portion of second connection line 92b penetrates the first dielectric layer 91a and is connected to test pad 62-1”. Test pad 62-1” overlaps with the via portion of second connection line 92b and the first dielectric layer 91a surrounding the via portion of second connection line 92b.

[0273] The width of test pad 62-1” is greater than the width of the second chip pad PAD2. For example... Figure 27 As shown, the width of the second chip pad PAD2 is W31. The width of the test pad 62-1” is W32. W32 is greater than W31.

[0274] The distance between test pad 62-1” and the external connection bump 61-1” closest to test pad 62-1” is greater than the distance between the second chip pad PAD2 and the first chip pad PAD1 closest to the second chip pad PAD2. The distance between the second chip pad PAD2 and the first chip pad PAD1 closest to the second chip pad PAD2 is d1'. The distance between test pad 62-1” and the external connection bump 61-1” closest to test pad 62-1” is d2'. d2' is greater than d1'.

[0275] The second UBM pattern 71b-1” is disposed on the test pad 62-1”. The second UBM pattern 71b-1” is inserted between the test pad 62-1” and the second connection line 92b, and between the test pad 62-1” and the first dielectric layer 91a. The second UBM pattern 71b-1” connects the test pad 62-1” and the second connection line 92b.

[0276] The third UBM pattern 71c-1” is disposed below the first connecting line 92a. The third UBM pattern 71c-1” is inserted between the first connecting line 92a and the first UBM pattern 71a-1”, and between the first connecting line 92a and the first dielectric layer 91a. The third UBM pattern 71c-1” connects the first UBM pattern 71a-1” and the first connecting line 92a.

[0277] The third UBM pattern 71c-1” may include a barrier metal layer disposed on the first UBM pattern 71a-1” and the first dielectric layer 91a, and a seed layer disposed on the barrier metal layer. The barrier metal layer may include titanium. The barrier metal layer may be a titanium layer. The seed layer may include copper. The seed layer may be a copper layer. The first connection line 92a may be formed using the seed layer through an electroplating process.

[0278] The fourth UBM pattern 71d-1” is disposed below the second connecting line 92b. The fourth UBM pattern 71d-1” is inserted between the second connecting line 92b and the second UBM pattern 71b-1”, and between the second connecting line 92b and the first dielectric layer 91a. The fourth UBM pattern 71d-1” connects the second UBM pattern 71b-1” and the second connecting line 92b.

[0279] The fourth UBM pattern 71d-1” may include a barrier metal layer disposed on the second UBM pattern 71b-1” and the first dielectric layer 91a, and a seed layer disposed on the barrier metal layer. The barrier metal layer may include titanium. The seed layer may include copper. The second connection line 92b may be formed using the seed layer through an electroplating process.

[0280] The second dielectric layer 91b is disposed on the first dielectric layer 91a, the first connecting line 92a, and the second connecting line 92b. The second dielectric layer 91b covers the upper surface of the first dielectric layer 91a, the upper surface and side surface of the first connecting line 92a, and the upper surface and side surface of the second connecting line 92b.

[0281] A first bump pad 93a is disposed on a second dielectric layer 91b. The first bump pad 93a penetrates the second dielectric layer 91b perpendicularly and is connected to a first interconnect line 92a.

[0282] A second bump pad 93b is disposed on the second dielectric layer 91b. The second bump pad 93b penetrates the second dielectric layer 91b perpendicularly and is connected to a second interconnect 92b. Both second bump pads 93b are connected to a single second interconnect 92b. Figure 26 and Figure 27 In this embodiment, the number of second bump pads 93b connected to a second connection line 92b is two, but this disclosure is not limited thereto. In another embodiment, the number of second bump pads connected to a second connection line may be one, three or more.

[0283] The fifth UBM pattern 71e-1” is disposed below the first bump pad 93a. The fifth UBM pattern 71e-1” is inserted between the first bump pad 93a and the first connection line 92a, and between the first bump pad 93a and the second dielectric layer 91b. The fifth UBM pattern 71e-1” connects the first bump pad 93a and the first connection line 92a.

[0284] The fifth UBM pattern 71e-1 may include a barrier metal layer disposed on the first connection line 92a and the second dielectric layer 91b, and a seed layer disposed on the barrier metal layer. The barrier metal layer may include titanium. The barrier metal layer may be a titanium layer. The seed layer may include copper. The seed layer may be a copper layer. The first bump pad 93a may be formed using the seed layer through an electroplating process.

[0285] The sixth UBM pattern 71f-1” is disposed below the second bump pad 93b. The sixth UBM pattern 71f-1” is inserted between the second bump pad 93b and the second connection line 92b, and between the second bump pad 93b and the second dielectric layer 91b. The sixth UBM pattern 71f-1” connects the second bump pad 93b and the second connection line 92b.

[0286] The sixth UBM pattern 71f-1 may include a barrier metal layer disposed on the second connection line 92b and the second dielectric layer 91b, and a seed layer disposed on the barrier metal layer. The barrier metal layer may include titanium. The barrier metal layer may be a titanium layer. The seed layer may include copper. The seed layer may be a copper layer. The second bump pad 93b may be formed using the seed layer through an electroplating process.

[0287] A first semiconductor chip 10 is mounted on a redistribution substrate 90 via a first front bump 13A and a first test bump 13C. The first front bump 13A of the first semiconductor chip 10 is placed on a first bump pad 93a of the redistribution substrate 90, and the solder layer 13Cb of the first test bump 13C is bonded to the first bump pad 93a. The first test bump 13C of the first semiconductor chip 10 is placed on a second bump pad 93b of the redistribution substrate 90, and the solder layer 13Cb of the first test bump 13C is bonded to the second bump pad 93b. The first semiconductor chip 10 is physically and electrically connected to the redistribution substrate 90 via the first front bump 13A and the first test bump 13C.

[0288] A second semiconductor chip 20 is stacked on the first semiconductor chip 10, and a third semiconductor chip 30 is stacked on the second semiconductor chip 20. A molding member 40K surrounds the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30. The molding member 40K extends between the redistribution substrate 90 and the first semiconductor chip 10. The molding member 40K surrounds the first front bump 13A and the first test bump 13C.

[0289] Figure 28 This is a plan view showing the external connection bumps and test pads according to an embodiment of the present disclosure.

[0290] refer to Figure 28According to an embodiment of the present disclosure, the chip stacked package 800 includes a first region R1 in which connecting bumps 61-2 are arranged and a second region R2 located outside the first region R1.

[0291] The second region R2 can surround the first region R1. The first region R1 can be the central region of the chip stacked package 800. The second region R2 can be the edge region of the chip stacked package 800. The test pad 62-2 can be located in the second region R2. The distance between the test pad 62-2 and the external connection bump 61-2 closest to the test pad 62-2 is greater than the distance between adjacent external connection bumps 61-2. The distance between adjacent external connection bumps 61-2 is d11. The distance between the test pad 62-2 and the external connection bump 61-2 closest to the test pad 62-2 is d12. d12 is greater than d11.

[0292] Since the test pad 62-2 is located in the second region R2 outside the first region R1 where external connection bumps 61-2 are arranged, the distance between the test pad 62-2 and the external connection bump 61-2 closest to the test pad 62-2 can be configured to be greater than the distance between adjacent external connection bumps 61-2. Therefore, when the test pin of the test device contacts the test pad 62-2 in test mode, interference between the test pin and the external connection bump 61-2 can be suppressed or prevented.

[0293] The concepts have been disclosed in conjunction with the examples and embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concept of this disclosure. The embodiments disclosed herein should be considered from an illustrative rather than restrictive perspective. Therefore, the scope of this disclosure is not limited to the foregoing description. All variations within the meaning and scope of equivalents of the claims are included within its scope.

[0294] Cross-references to related applications

[0295] This application claims priority to Korean Patent Application No. 10-2024-0163963, filed on November 18, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2025-0119835, filed on August 27, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A chip stacked package, the chip stacked package comprising: A first semiconductor chip, the first semiconductor chip having a first test bump on a first surface; A second semiconductor chip is stacked on a second surface of the first semiconductor chip that is opposite to the first surface. A second test bump is engaged with the first test bump; A molded component surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump; as well as Test pads are disposed on the molded component and connected to the second test bump.

2. The chip stacked package according to claim 1, wherein, The first semiconductor chip includes: First substrate; and A wiring structure is disposed below the first substrate. The wiring structure includes chip pads connected to the first test bump, and The test pad has a larger planar area than the chip pad.

3. The chip stacked package according to claim 2, wherein, The first semiconductor chip includes a plurality of first test bumps, wherein the plurality of first test bumps include the first test bumps. The first test bumps among the plurality of first test bumps are collectively connected to the chip pads. Wherein, the second test bump among the plurality of second test bumps, including the second test bump, is respectively connected to the plurality of first test bumps, and The second test bumps among the plurality of second test bumps are all connected to the test pads.

4. The chip stacked package according to claim 1, further comprising: A front protrusion is disposed on the first surface of the first semiconductor chip; A carrier bump, which engages with the front bump; as well as An external connecting bump, which is positioned on the molded member and connected to the carrier bump. The molded component surrounds the front protrusion and the carrier protrusion.

5. The chip stacked package according to claim 4, wherein, The size of the first test bump is the same as the size of the front bump.

6. The chip stacked package according to claim 4, wherein, The test pad is located in a second region outside a first region of a plurality of external connection bumps, including the external connection bump.

7. The chip stacked package according to claim 6, wherein, The distance between the external connection bump closest to the test pad and the test pad is greater than the distance between adjacent external connection bumps.

8. The chip stacked package according to claim 4, wherein, The planar area of ​​the test pad is larger than the planar area of ​​the external connection bump.

9. The chip stacked package according to claim 1, wherein, The first test bump includes: First nickel layer; and A solder layer, which is located below the first nickel layer. The solder layer is in contact with the second test bump.

10. The chip stacked package according to claim 9, wherein, The second test bump includes a second nickel layer, and The solder layer is in contact with the second nickel layer.

11. The chip stacked package according to claim 1, wherein, The first test bump includes: First copper layer; A first nickel layer, the first nickel layer being below the first copper layer; and A solder layer, which is located below the first nickel layer. The solder layer is in contact with the second test bump.

12. The chip stacked package according to claim 11, wherein, The thickness of the first copper layer is greater than the thickness of the first nickel layer.

13. The chip stacked package according to claim 11, wherein, The second test bump includes: The second copper layer; and The second nickel layer is on top of the second copper layer. The solder layer is in contact with the first nickel layer and the second nickel layer.

14. The chip stacked package according to claim 13, wherein, The thickness of the second copper layer is greater than the thickness of the second nickel layer.

15. The chip stacked package according to claim 1, wherein, The first test bump includes: First copper layer; A first nickel layer, which is located below the first copper layer; A second copper layer, the second copper layer being below the first nickel layer; and Solder layer, the solder layer being below the second copper layer, The solder layer is in contact with the second test bump.

16. The chip stacked package according to claim 15, wherein, The thickness of the first copper layer is greater than the thickness of the first nickel layer.

17. The chip stacked package according to claim 15, wherein, The thickness of the second copper layer is less than the thickness of the first copper layer.

18. The chip stacked package according to claim 15, wherein, The second test bump includes: Third copper layer; A second nickel layer, the second nickel layer being on the third copper layer; and A fourth copper layer, which is on top of the second nickel layer, The solder layer is in contact with the second copper layer and the fourth copper layer.

19. The chip stacked package according to claim 18, wherein, The thickness of the third copper layer is greater than the thickness of the second nickel layer.

20. The chip stacked package according to claim 18, wherein, The thickness of the fourth copper layer is less than the thickness of the third copper layer.

21. A chip stacked package, the chip stacked package comprising: A first semiconductor chip, the first semiconductor chip having test bumps on a first surface; A second semiconductor chip is stacked on a second surface of the first semiconductor chip that is opposite to the first surface. A molded component surrounding the first semiconductor chip and the second semiconductor chip; as well as Test pads are disposed below the molded component and connected to the test bumps.

22. The chip stacked package according to claim 21, wherein, The first semiconductor chip includes: First substrate; and A wiring structure is disposed below the first substrate. The wiring structure includes chip pads connected to the test bump, and The test pad has a larger planar area than the chip pad.

23. The chip stacked package according to claim 22, wherein, The first semiconductor chip includes a plurality of test bumps, wherein the plurality of test bumps includes the test bumps. The test bumps among the plurality of test bumps are connected in parallel between the chip pads and the test pads.

24. The chip stacked package according to claim 21, further comprising: A front protrusion is disposed on the first surface of the first semiconductor chip; as well as An external connecting bump is disposed on the molded member and connected to the front bump; The molded component surrounds the front protrusion.

25. The chip stacked package according to claim 24, wherein, The planar area of ​​the test pad is larger than the planar area of ​​the external connection bump.

26. The chip stacked package according to claim 24, wherein, The size of the test bump is the same as the size of the front bump.

27. The chip stacked package according to claim 24, wherein, The test pad is located in a second region outside a first region of a plurality of external connection bumps, including the external connection bump.

28. The chip stacked package according to claim 27, wherein, The distance between the external connection bump closest to the test pad and the test pad is greater than the distance between adjacent external connection bumps.

29. A chip stacked package, the chip stacked package comprising: A first semiconductor chip, the first semiconductor chip having a first test bump on a first surface; A second semiconductor chip is stacked on a second surface of the first semiconductor chip that is opposite to the first surface. A second test bump is engaged with the first test bump; A molded component surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump; A redistribution layer is disposed on the molded member and the second test bump; as well as Test pads are disposed on the redistribution layer.

30. The chip stacked package according to claim 29, wherein, The first semiconductor chip includes: First substrate; and A wiring structure is disposed below the first substrate. The wiring structure includes a first chip pad connected to the first test bump, and The test pad has a larger planar area than the first chip pad.

31. The chip stacked package according to claim 30, wherein, The first semiconductor chip includes a plurality of first test bumps, wherein the plurality of first test bumps include the first test bumps. Among them, the first test bumps of the plurality of first test bumps are all connected to the first chip pad, and The second test bump in the plurality of second test bumps, including the second test bump, is respectively connected to the first test bump in the plurality of first test bumps.

32. The chip stacked package according to claim 31, further comprising: A front protrusion is disposed on the first surface of the first semiconductor chip; A carrier bump is disposed between the front bump and the redistribution layer; as well as External connection bumps are disposed below the redistribution layer. The molded component surrounds the front protrusion and the carrier protrusion.

33. The chip stacked package according to claim 32, wherein, The wiring structure also includes a second chip pad connected to the carrier bump, and The distance between the external connection bump and the test pad is greater than the distance between the first chip pad and the second chip pad.

34. The chip stacked package according to claim 32, wherein, The planar area of ​​the test pad is larger than the planar area of ​​the external connection bump.

35. The chip stacked package according to claim 34, wherein, Each of the plurality of first test bumps has the same size as the front bump.

36. The chip stacked package according to claim 32, wherein, The redistribution layer includes: A first dielectric layer is disposed below the molded component, the second test bump, and the carrier bump; A first connecting line is connected to the carrier bump by penetrating the first dielectric layer and extending below the first dielectric layer; A second connection line, the second connection line being connected to the second test bump by penetrating the first dielectric layer and extending below the first dielectric layer; and A second dielectric layer is disposed below the first dielectric layer, the first connection line, and the second connection line. The external connection bump penetrates the second dielectric layer and connects to the first connection line. The test pad penetrates the second dielectric layer and is connected to the second connection line.

37. The chip stacked package according to claim 32, wherein, The test pad is located in a second region outside a first region of a plurality of external connection bumps, including the external connection bump.

38. The chip stacked package according to claim 37, wherein, The distance between the external connection bump closest to the test pad and the test pad is greater than the distance between adjacent external connection bumps.

39. A chip stacked package, the chip stacked package comprising: Redistribution substrate; A first semiconductor chip, the first semiconductor chip having test bumps bonded to a first surface of the redistribution substrate; A second semiconductor chip, which is stacked on top of the first semiconductor chip; A molded component surrounding the first semiconductor chip and the second semiconductor chip; as well as Test pads are disposed on a second surface of the redistributed substrate opposite to the first surface.

40. The chip stacked package according to claim 39, wherein, The first semiconductor chip includes: First substrate; and A wiring structure is disposed below the first substrate. The wiring structure includes a first chip pad connected to the test bump, and The test pad has a larger planar area than the first chip pad.

41. The chip stacked package according to claim 40, wherein, The redistribution substrate includes: First dielectric layer; A first connection line is disposed on the first dielectric layer and connected to the test pad by penetrating the first dielectric layer; A second dielectric layer is disposed on the first dielectric layer and the first interconnect line; and A first bump pad is disposed on the second dielectric layer and connected to the first interconnect by penetrating the second dielectric layer. The test bump is engaged with the first bump pad.

42. The chip stacked package according to claim 41, wherein, The first semiconductor chip includes a plurality of test bumps, wherein the plurality of test bumps includes the test bumps. The redistributed substrate includes a plurality of first bump pads, wherein the plurality of first bump pads include the first bump pads. Wherein, the test bumps among the plurality of test bumps are respectively bonded to the first bump pads among the plurality of first bump pads, and The first bump pads among the plurality of first bump pads are all connected to the first connection line.

43. The chip stacked package according to claim 40, wherein, The first semiconductor chip also includes a front bump connected to the redistributed substrate. The chip stacked package further includes external connection bumps, which are disposed below the redistribution substrate and connected to the front bumps via the redistribution substrate. The molded component surrounds the front protrusion.

44. The chip stacked package according to claim 43, wherein, The wiring structure also includes a second chip pad connected to the front bump, and The distance between the external connection bump and the test pad is greater than the distance between the first chip pad and the second chip pad.

45. The chip stacked package according to claim 43, wherein, The test pads are arranged in a second region outside a first region of a plurality of external connection bumps, including the external connection bumps.

46. ​​The chip stacked package according to claim 45, wherein, The distance between the external connection bump closest to the test pad and the test pad is greater than the distance between adjacent external connection bumps.

Images