Semiconductor device structure and preparation method thereof
By simplifying the SiC JBS fabrication process, an inorganic isolation passivation layer can be directly formed, solving the problems of complex processes and high costs in existing technologies, and realizing efficient and low-cost semiconductor device production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG XINYUENENG SEMICON CO LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-05-19
AI Technical Summary
Existing SiC JBS preparation processes are complex, have low production efficiency, and high production costs.
By employing a process that eliminates the need for forming a field oxide layer, an inorganic isolation passivation layer is directly formed between the ion implantation region and the first electrode. This reduces the number of fabrication steps, improves production efficiency, and lowers costs by replacing the organic passivation layer with the inorganic isolation passivation layer.
It simplifies the manufacturing process, improves production efficiency, reduces production costs, and ensures the reliability of semiconductor devices.
Smart Images
Figure CN122069735A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology
[0002] 4H-SiC (4H-Silicon Carbide) possesses characteristics such as a high critical breakdown electric field, wide bandgap, and high thermal conductivity, giving SiC devices high breakdown voltage, low on-resistance, and high temperature resistance. SiC diodes include PN junction diodes and Schottky diodes. Due to the wide bandgap of SiC, the turn-on voltage of PN junction diodes is around 3V, resulting in a relatively large forward voltage drop. Furthermore, as bipolar devices, they exhibit a reverse recovery process, making SiC PN junction diodes unsuitable for high-frequency applications. In contrast, SiC SBDs (Schottky Barrier Diodes), as unipolar devices, do not have a reverse recovery process and offer very fast switching speeds. They also have a relatively low turn-on voltage (close to 1V) and correspondingly lower losses, giving them a significant advantage in high-frequency applications. Combining the fast recovery and low voltage drop characteristics of SBDs with the high breakdown voltage of PN junctions, the application of SiC JBSs (Junction Barrier Schottky Diodes) has seen rapid development.
[0003] However, existing SiC JBS preparation processes are relatively complex, have low production efficiency, and high production costs. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor device structure and its fabrication method to address the technical problems in the existing technology, thereby reducing process steps and improving production efficiency.
[0005] In a first aspect, this application provides a method for fabricating a semiconductor device structure, comprising:
[0006] A substrate structure of a first conductivity type is prepared, the substrate structure comprising: a substrate of the first conductivity type and an epitaxial layer of the first conductivity type located on the upper surface of the substrate; the substrate structure includes an active region and a terminal region located around the active region;
[0007] Multiple ion implantation regions of the second conductivity type are formed at intervals within the epitaxial layer of the active region and the terminal region;
[0008] A first electrode is formed at least on the upper surface of the active region;
[0009] An inorganic isolation passivation layer is formed, which covers the exposed upper surface of the epitaxial layer and the first electrode;
[0010] A first opening is formed within the inorganic isolation passivation layer, and the first opening exposes the first electrode;
[0011] A second electrode is formed on the lower surface of the substrate.
[0012] In some embodiments, the fabrication of the substrate structure of the first conductivity type includes:
[0013] Provide a substrate of the first conductivity type;
[0014] An epitaxial layer of a first conductivity type is formed on the upper surface of the substrate using an epitaxial process; the doping concentration of the first conductivity type dopant ions in the epitaxial layer is less than the doping concentration of the first conductivity type dopant ions in the substrate.
[0015] In some embodiments, forming a plurality of spaced-apart ion implantation regions of a second conductivity type within the epitaxial layer of the active region and the terminal region includes:
[0016] A barrier layer is formed on the upper surface of the epitaxial layer, the barrier layer covering the active region and the terminal region;
[0017] A first patterned photoresist layer is formed on the upper surface of the barrier layer;
[0018] Based on the first patterned photoresist layer, the barrier layer is etched to form a plurality of spaced second openings in the barrier layer of the active region and the terminal region. The second openings define the shape and position of the ion implantation region and expose the upper surface of the epitaxial layer.
[0019] Ion implantation is performed on the epitaxial layer based on the second opening to form the ion implantation region;
[0020] Remove the blocking layer and the first patterned photoresist layer.
[0021] In some embodiments, the width of the second opening adjacent to the active region within the barrier layer of the terminal region is greater than the width of other second openings within the barrier layer of the terminal region and the width of the second opening within the barrier layer of the active region.
[0022] In some embodiments, forming a first electrode at least on the upper surface of the active region includes:
[0023] A second patterned photoresist layer is formed on the upper surface of the epitaxial layer that forms the ion implantation region. The second patterned photoresist layer has a third opening, which at least exposes the active region.
[0024] An electrode material layer is formed on the upper surface of the second patterned photoresist layer and on the upper surface of the active region exposed by the third opening;
[0025] The electrode material layer located on the upper surface of the second patterned photoresist layer is removed by a stripping process, and the second patterned photoresist layer is also removed. The electrode material layer remaining on the upper surface of the active region is the first electrode.
[0026] In some embodiments, forming the inorganic isolation passivation layer includes:
[0027] A field oxide layer is formed, which covers the exposed upper surface of the epitaxial layer and the first electrode;
[0028] An inorganic passivation layer is formed on the upper surface of the field oxide layer, and the inorganic passivation layer and the field oxide layer together constitute the inorganic isolation passivation layer.
[0029] In some embodiments, the width of the first electrode is greater than the width of the active region; and / or the width of the first opening is less than the width of the first electrode.
[0030] In some embodiments, forming a second electrode on the lower surface of the substrate includes:
[0031] A metal silicide layer is formed on the lower surface of the substrate;
[0032] A metal electrode layer is formed on the lower surface of the metal silicide layer, and the metal electrode layer and the metal silicide layer together constitute the second electrode.
[0033] In some embodiments, forming a metal silicide layer on the lower surface of the substrate includes:
[0034] A metal layer is formed on the lower surface of the substrate;
[0035] The resulting structure is subjected to laser annealing so that the metal layer reacts with the substrate to form the metal silicide layer.
[0036] In a second aspect, this application provides a semiconductor device structure, which is prepared by the method for preparing a semiconductor device structure as described in the first aspect.
[0037] In the above embodiments, in the method for fabricating the semiconductor device structure of this application, there is no need to form a field oxide layer between forming the ion implantation region and forming the first electrode, which reduces the complexity of the fabrication process, improves production efficiency, and saves production costs; after forming the first electrode, an inorganic isolation passivation layer is formed, eliminating the need to prepare an organic passivation layer. This reduces the complexity of the fabrication process, improves production efficiency, and saves production costs while ensuring the reliability of the obtained semiconductor device. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device structure provided in one embodiment of this application;
[0040] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S10 of the method for fabricating a semiconductor device structure provided in an embodiment of this application.
[0041] Figures 3 to 4 This is a cross-sectional schematic diagram of the structure obtained in step S20 of the method for fabricating a semiconductor device structure provided in one embodiment of this application;
[0042] Figures 5 to 7 This is a cross-sectional schematic diagram of the structure obtained in step S30 of the method for fabricating a semiconductor device structure provided in one embodiment of this application;
[0043] Figure 8 This is a cross-sectional schematic diagram of the structure obtained in step S40 of the method for fabricating a semiconductor device structure provided in one embodiment of this application;
[0044] Figure 9 This is a cross-sectional schematic diagram of the structure obtained in step S50 of the method for fabricating a semiconductor device structure provided in one embodiment of this application;
[0045] Figure 10 This is a cross-sectional schematic diagram of the structure obtained in step S60 of the method for fabricating a semiconductor device structure provided in one embodiment of this application.
[0046] Explanation of reference numerals in the attached figures:
[0047] 10. Substrate structure; 101. Substrate; 102. Epitaxial layer; 103. Active region; 104. Termination region; 11. Barrier layer; 12. First patterned photoresist layer; 121. Second opening; 13. Ion implantation region; 14. First electrode; 141. Electrode material layer; 15. Second patterned photoresist layer; 151. Third opening; 16. Inorganic isolation passivation layer; 161. Field oxide layer; 162. Inorganic passivation layer; 163. First opening; 17. Second electrode. Detailed Implementation
[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0053] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.
[0054] In one embodiment, see Figure 1 This application provides a method for fabricating a semiconductor device structure, which may include the following steps: S10~S60.
[0055] S10: Prepare a substrate structure of the first conductivity type. The substrate structure includes: a substrate of the first conductivity type and an epitaxial layer of the first conductivity type located on the upper surface of the substrate; the substrate structure includes an active region (i.e., a cell region) and a terminal region located around the active region.
[0056] S20: Multiple ion implantation regions of the second conductivity type are formed in the epitaxial layer of the active region and the terminal region.
[0057] S30: A first electrode is formed at least on the upper surface of the active region.
[0058] S40: An inorganic isolation passivation layer is formed, which covers the exposed upper surface of the epitaxial layer and the first electrode.
[0059] S50: A first opening is formed within the inorganic isolation passivation layer, and the first opening exposes the first electrode.
[0060] S60: A second electrode is formed on the lower surface of the substrate.
[0061] In the method for fabricating the semiconductor device structure of this application, there is no need to form a field oxide layer between the formation of the ion implantation region and the formation of the first electrode, which reduces the complexity of the fabrication process, improves production efficiency, and saves production costs. After the formation of the first electrode, an inorganic isolation passivation layer is formed, eliminating the need to prepare an organic passivation layer. This reduces the complexity of the fabrication process, improves production efficiency, and saves production costs while ensuring the reliability of the obtained semiconductor device.
[0062] As an example, step S10, which involves preparing a substrate structure of the first conductivity type, may include the following steps: S101~S102.
[0063] S101: Provides a substrate of the first conductivity type.
[0064] S102: An epitaxial layer of a first conductivity type is formed on the upper surface of the substrate using an epitaxial process; the doping concentration of the first conductivity type dopant ions in the epitaxial layer is less than the doping concentration of the first conductivity type dopant ions in the substrate.
[0065] As an example, in step S20, forming multiple spaced-apart ion implantation regions of the second conductivity type in the epitaxial layer of the active region and the terminal region may include the following steps: S201~S205.
[0066] S201: A barrier layer is formed on the upper surface of the epitaxial layer, covering the active region and the terminal region.
[0067] S202: A first patterned photoresist layer is formed on the upper surface of the barrier layer.
[0068] S203: Based on the first patterned photoresist layer, etch the barrier layer to form multiple spaced second openings in the barrier layer of the active region and the terminal region. The second openings define the shape and position of the ion implantation region and expose the upper surface of the epitaxial layer.
[0069] S204: Ion implantation is performed on the epitaxial layer based on the second opening to form an ion implantation region.
[0070] S205: Remove the blocking layer and the first patterned photoresist layer.
[0071] As an example, the width of the second opening adjacent to the active region within the barrier layer of the terminal region is greater than the width of other second openings within the barrier layer of the terminal region and the width of the second opening within the barrier layer of the active region.
[0072] As an example, step S30, forming a first electrode at least on the upper surface of the active region, may include the following steps:
[0073] S301: A second patterned photoresist layer is formed on the upper surface of the epitaxial layer that forms the ion implantation region. The second patterned photoresist layer has a third opening, and the third opening exposes at least the active region.
[0074] S302: An electrode material layer is formed on the upper surface of the second patterned photoresist layer and the upper surface of the active region exposed by the third opening.
[0075] S303: The electrode material layer located on the upper surface of the second patterned photoresist layer is removed by a stripping process (e.g., film application and peeling process), and the second patterned photoresist layer is removed. The electrode material layer remaining on the upper surface of the active region is the first electrode.
[0076] As an example, step S40, forming an inorganic isolation passivation layer, may include the following steps:
[0077] S401: Form a field oxide layer, which covers the exposed upper surface of the epitaxial layer and the first electrode.
[0078] S402: An inorganic passivation layer is formed on the upper surface of the field oxide layer. The inorganic passivation layer and the field oxide layer together constitute an inorganic isolation passivation layer.
[0079] In the above example, after the first electrode is formed, an inorganic isolation passivation layer consisting of a field oxide layer and an inorganic passivation layer is formed, eliminating the need to prepare an organic passivation layer. This reduces the complexity of the fabrication process, improves production efficiency, and saves production costs, while ensuring the reliability of the obtained semiconductor device.
[0080] As an example, the width of the first electrode is greater than the width of the active region; and / or the width of the first opening is less than the width of the first electrode.
[0081] As an example, in step S60, forming a second electrode on the lower surface of the substrate may include the following steps: S601~S602.
[0082] S601: A metal silicide layer is formed on the lower surface of the substrate.
[0083] S602: A metal electrode layer is formed on the lower surface of the metal silicide layer, and the metal electrode layer and the metal silicide layer together constitute the second electrode.
[0084] As an example, in step S601, forming a metal silicide layer on the lower surface of the substrate may include the following steps: S6011~S6012.
[0085] S6011: A metal layer is formed on the lower surface of the substrate.
[0086] S6012: Perform laser annealing on the obtained structure to allow the metal layer to react with the substrate to form a metal silicide layer.
[0087] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0088] Below, in conjunction with Figures 1 to 10 An exemplary method for describing a semiconductor device structure according to this application is described. Figures 2 to 10 The accompanying drawings are step-by-step cross-sectional views illustrating an exemplary fabrication method of a semiconductor device structure according to this application. It should also be understood that the drawings are not drawn to scale and are for illustrative purposes only.
[0089] For example, please refer to Figure 2 In step S101, the provided substrate 101 can be a silicon carbide substrate; specifically, the substrate 101 can be a heavily doped silicon carbide substrate of a first conductivity type.
[0090] As an example, please continue reading Figure 2 The epitaxial layer 102 formed in step S102 can be a silicon carbide epitaxial layer. Specifically, the epitaxial layer 102 formed can be a lightly doped silicon carbide epitaxial layer of the first conductivity type.
[0091] It should be noted that "heavily doped" can refer to a doping concentration greater than or equal to 1e18cm. -3 The doping concentration of dopant ions of the first conductivity type in the substrate 101 provided in step S101 can be greater than or equal to 1e18cm⁻¹.-3 The term "lightly doped" refers to a doping concentration of less than 1e18cm. -3 The doping concentration of dopant ions of the first conductivity type within the epitaxial layer 102 formed in step S102 can be greater than or equal to 1e18cm. -3 The doping concentration of doped ions in epitaxial layer 102 can be less than 1e18cm. -3 For example, the doping concentration of doped ions in epitaxial layer 102 can be 1e17cm. -3 1e16cm -3 1e15cm -3 Or lower.
[0092] As an example, the thickness of the epitaxial layer 102 can be less than the thickness of the substrate 101.
[0093] As an example, the active region 103 and the terminal region 104 of the substrate structure 10 are connected.
[0094] For example, please refer to Figure 3 In step S201, a barrier layer 11 may be formed using a deposition process, but not limited to this one. The barrier layer 11 may be an ion barrier layer. Specifically, the barrier layer 11 may include, but is not limited to, silicon dioxide (SiO2). 2 )layer.
[0095] As an example, the thickness of the barrier layer 11 can be set according to actual needs. In this embodiment, the thickness of the barrier layer 11 can be 1.5μm to 2.5μm; specifically, the thickness of the barrier layer 11 can be 1.5μm, 2.0μm and 2.5μm.
[0096] As an example, in step S202, a first photoresist layer (not shown) can be formed on the upper surface of the barrier layer 11 by a coating process; the first photoresist layer is exposed and developed to form a first patterned photoresist layer 12; the first patterned photoresist layer 12 defines the shape and position of the second opening.
[0097] As an example, in step S203, the first patterned photoresist layer 12 can be used as an etching mask layer, and the barrier layer 11 can be etched using a dry etching process to form a second opening 121 in the barrier layer 11.
[0098] As an example, the barrier layer 11 has multiple second openings 121 in the regions corresponding to the active region 103 and the terminal region 104. Specifically, the width of the second opening 121 adjacent to the active region 103 in the barrier layer 11 corresponding to the terminal region 104 is greater than the width of other second openings 121 in the barrier layer 11 corresponding to the terminal region 104 and the width of the second opening 121 in the barrier layer 11 corresponding to the active region 103; that is, the width of the second opening 121 closest to the active region 103 in the barrier layer 11 corresponding to the terminal region 104 is greater than the width of other second openings 121.
[0099] As an example, in step S204, the first patterned photoresist layer 12 and the barrier layer 11 can be used together as the ion implantation barrier layer. An ion implantation process is then employed to implant ions of a second conductivity type into the epitaxial layer 102 based on the second opening 121, thereby forming multiple ion implantation regions 13 of the second conductivity type. The cross-sectional view of the structure obtained in step S204 is shown below. Figure 3 As shown.
[0100] As an example, the first conductivity type can be N-type and the second conductivity type can be P-type; alternatively, the first conductivity type can be P-type and the second conductivity type can be N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in step S20, Al (aluminum) ions can be implanted into the epitaxial layer 102 through the second opening 121 to form an ion implantation region 13 within the epitaxial layer 102. Figure 3 As shown, both the active region 103 and the terminal region 104 have multiple ion implantation regions 13.
[0101] As an example, the width of the ion implantation region 13 adjacent to the active region 103 in the terminal region 104 is greater than the width of the other ion implantation regions 13 in the terminal region 104 and the width of the ion implantation region 13 in the active region 103; that is, the width of the ion implantation region 13 closest to the active region 103 in the terminal region 104 is greater than the width of the other ion implantation regions 13.
[0102] As an example, each ion implantation region 13 can be a heavily doped region; the depth of each ion implantation region 13 is less than the thickness of the epitaxial layer 102.
[0103] As an example, in step S205, etching or polishing processes can be used to remove the first patterned photoresist layer 12 and the barrier layer 11; alternatively, an ashing process can be used to remove the first patterned photoresist layer 12 first, followed by etching or polishing processes to remove the barrier layer 11. A cross-sectional structural diagram of the structure obtained in step S205 is shown below. Figure 4 As shown.
[0104] For example, please refer to Figure 5In step S301, a second photoresist layer (not shown) can be formed on the upper surface of the ion implantation region 13 by a coating process; the second photoresist layer is exposed and developed to form a second patterned photoresist layer 15; the third opening 151 in the second patterned photoresist layer 15 defines the shape and position of the first electrode 14.
[0105] For example, please refer to Figure 6 In step S302, an electrode material layer 141 is formed on the upper surface of the second patterned photoresist layer 15 and the upper surface of the active region 103 exposed by the third opening 151.
[0106] As an example, the electrode material layer 141 can be formed using processes such as vapor deposition, electroplating, or sputtering.
[0107] For example, please refer to Figure 7 In step S303, the electrode material layer 141 located on the upper surface of the second patterned photoresist layer 15 can be removed by a peeling process such as film application and peeling; then, organic solvent cleaning is performed to remove the second patterned photoresist layer 15, and the residual electrode material on the upper surface of the second patterned photoresist layer 15 is also removed.
[0108] As an example, the first electrode 14 can be a single metal layer or a multi-layer metal stack; in this embodiment, the first electrode 14 may include a titanium (Ti) layer, a titanium nitride (TiN) layer and a copper-aluminum alloy (AiCu) layer stacked sequentially from bottom to top.
[0109] As an example, the width of the first electrode 14 can be greater than or equal to the width of the active region 103; Figure 7 The example used is that the width of the first electrode 14 is greater than the width of the active region 103.
[0110] For example, please refer to Figure 8 In step S401, a field oxide layer 161 can be formed by deposition or thermal oxidation processes, which can achieve the isolation function between devices.
[0111] As an example, the thickness of the field oxide layer 161 can be set according to actual needs. In this embodiment, the thickness of the field oxide layer 161 can be 0.5μm to 2μm; specifically, the thickness of the field oxide layer 161 can be 0.5μm, 1μm, 1.5μm or 2μm.
[0112] As an example, the field oxide layer 161 can be a silicon oxide layer based on TEOS (tetraethoxysilane).
[0113] As an example, please continue reading Figure 8In step S402, an inorganic passivation layer 162 can be formed on the upper surface of the field oxide layer 161 using a deposition process, but not limited to the method described above. The inorganic passivation layer 162 can achieve passivation between devices.
[0114] As an example, the thickness of the inorganic passivation layer 162 can be set according to actual needs. In this embodiment, the thickness of the inorganic passivation layer 162 can be 0.5μm to 2μm; specifically, the thickness of the inorganic passivation layer 162 can be 0.5μm, 1μm, 1.5μm or 2μm.
[0115] As an example, the inorganic passivation layer 162 may include, but is not limited to, a silicon nitride (SiN) layer.
[0116] For example, please refer to Figure 9 In step S50, a first opening 163 is formed in the inorganic isolation passivation layer 16, exposing the first electrode 14. This step may include the following: forming a third photoresist layer (not shown) on the upper surface of the inorganic isolation passivation layer 16 using a spin coating process, but not limited to: exposing and developing the third photoresist layer to obtain a third patterned photoresist layer (not shown), which defines the shape and position of the first opening 163; etching the inorganic isolation passivation layer 16 based on the third patterned photoresist layer to form the first opening 163 within the inorganic isolation passivation layer 16; and removing the third patterned photoresist layer using an organic solvent cleaning or ashing process.
[0117] As an example, the width of the first opening 163 may be smaller than the width of the first electrode 14.
[0118] As an example, the first opening 163 can serve as a bonding area for subsequent wire bonding, and the wire formed by the bonding can contact the first electrode 14 for electrical lead-out of the first electrode 14.
[0119] For example, please refer to Figure 10 In step S60, a second electrode 17 can be formed on the lower surface of the substrate 101 by performing a back-side process.
[0120] As an example, in step S6011, a metal layer (not shown) can be formed on the lower surface of the substrate 101 by a sputtering process, an electroplating process, or a vapor deposition process; the formed metal layer may include a nickel (Ni) layer or a titanium (Ti) layer.
[0121] As an example, in step S6012, the structure obtained in step S6011 can be laser annealed to cause the metal layer to undergo a silicide reaction with the substrate 101 to form a metal silicide layer (not shown).
[0122] As an example, in step S602, a metal electrode layer (not shown) can be formed on the lower surface of the metal silicide layer using a sputtering process, an electroplating process, or a vapor deposition process. The metal electrode layer may include, but is not limited to, Ti (titanium), Ni (nickel), or Ag (silver) metal layers.
[0123] After step S60, the resulting semiconductor device structure can be a SiC JBS device.
[0124] In another embodiment, please continue to refer to Figures 1 to 10 This application also provides a semiconductor device structure, the semiconductor device structure of this application is composed of... Figures 1 to 10 The semiconductor device structure is prepared by the method described in the corresponding embodiments. For a detailed description of the semiconductor device structure, please refer to [link to relevant documentation]. Figures 1 to 10 The relevant descriptions will not be repeated here.
[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor device structure, characterized in that, include: A substrate structure of a first conductivity type is prepared, the substrate structure comprising: a substrate of the first conductivity type and an epitaxial layer of the first conductivity type located on the upper surface of the substrate; the substrate structure includes an active region and a terminal region located around the active region; Multiple ion implantation regions of the second conductivity type are formed at intervals within the epitaxial layer of the active region and the terminal region; A first electrode is formed at least on the upper surface of the active region; An inorganic isolation passivation layer is formed, which covers the exposed upper surface of the epitaxial layer and the first electrode; A first opening is formed within the inorganic isolation passivation layer, and the first opening exposes the first electrode; A second electrode is formed on the lower surface of the substrate.
2. The preparation method according to claim 1, characterized in that, The fabrication of the substrate structure of the first conductivity type includes: Provide a substrate of the first conductivity type; An epitaxial layer of a first conductivity type is formed on the upper surface of the substrate using an epitaxial process; the doping concentration of the first conductivity type dopant ions in the epitaxial layer is less than the doping concentration of the first conductivity type dopant ions in the substrate.
3. The preparation method according to claim 1, characterized in that, The formation of multiple spaced-apart ion implantation regions of the second conductivity type within the epitaxial layer of the active region and the terminal region includes: A barrier layer is formed on the upper surface of the epitaxial layer, the barrier layer covering the active region and the terminal region; A first patterned photoresist layer is formed on the upper surface of the barrier layer; Based on the first patterned photoresist layer, the barrier layer is etched to form a plurality of spaced second openings in the barrier layer of the active region and the terminal region. The second openings define the shape and position of the ion implantation region and expose the upper surface of the epitaxial layer. Ion implantation is performed on the epitaxial layer based on the second opening to form the ion implantation region; Remove the blocking layer and the first patterned photoresist layer.
4. The preparation method according to claim 3, characterized in that, The width of the second opening adjacent to the active region within the barrier layer of the terminal region is greater than the width of the other second openings within the barrier layer of the terminal region and the width of the second opening within the barrier layer of the active region.
5. The preparation method according to claim 1, characterized in that, The formation of the first electrode at least on the upper surface of the active region includes: A second patterned photoresist layer is formed on the upper surface of the epitaxial layer that forms the ion implantation region. The second patterned photoresist layer has a third opening, which at least exposes the active region. An electrode material layer is formed on the upper surface of the second patterned photoresist layer and on the upper surface of the active region exposed by the third opening; The electrode material layer located on the upper surface of the second patterned photoresist layer is removed by a stripping process, and the second patterned photoresist layer is also removed. The electrode material layer remaining on the upper surface of the active region is the first electrode.
6. The preparation method according to claim 1, characterized in that, The formation of the inorganic isolation passivation layer includes: A field oxide layer is formed, which covers the exposed upper surface of the epitaxial layer and the first electrode; An inorganic passivation layer is formed on the upper surface of the field oxide layer, and the inorganic passivation layer and the field oxide layer together constitute the inorganic isolation passivation layer.
7. The preparation method according to claim 1, characterized in that, The width of the first electrode is greater than the width of the active region; and / or the width of the first opening is less than the width of the first electrode.
8. The preparation method according to any one of claims 1 to 7, characterized in that, The formation of a second electrode on the lower surface of the substrate includes: A metal silicide layer is formed on the lower surface of the substrate; A metal electrode layer is formed on the lower surface of the metal silicide layer, and the metal electrode layer and the metal silicide layer together constitute the second electrode.
9. The preparation method according to claim 8, characterized in that, The formation of a metal silicide layer on the lower surface of the substrate includes: A metal layer is formed on the lower surface of the substrate; The resulting structure is subjected to laser annealing so that the metal layer reacts with the substrate to form the metal silicide layer.
10. A semiconductor device structure, characterized in that, The semiconductor device structure is prepared by the method described in any one of claims 1 to 9.