Semiconductor device and preparation method thereof
By setting a hard intermediate structure across the via in GaN-based RF power devices, the problem of via collapse caused by external force deformation of the source metal layer is solved, thereby improving the reliability and stability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2025-10-22
- Publication Date
- 2026-05-19
AI Technical Summary
During the manufacturing process of GaN-based RF power devices, the source metal layer is prone to deformation due to external pressure, which can lead to via collapse and affect device reliability.
A hard intermediate structure is set at the target location of the epitaxial layer, which spans the via but does not completely cover the via, and forms a support between the source metal layer and the metal plating on top of the via to prevent deformation of the metal layer.
This improves device reliability, prevents via collapse, and enhances device stability.
Smart Images
Figure CN122069740A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology
[0002] In the manufacturing process of GaN (gallium nitride) based RF power devices, VIA (metallized via) holes are typically placed in the region opposite the source metal layer to achieve the device's ground connection. In conventional device designs, the source metal layer adopts a planar structure, covered only by a thin silicon nitride (SiN) protective layer. This structure is equivalent to having only a thin metal film in the via region. Due to the inherent ductility of metal materials, when the device is subjected to external pressure, the metal film in this region is prone to deformation, causing the via to collapse and thus affecting the device's reliability. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, so as to avoid deformation of the source metal layer to a certain extent, prevent via collapse, and improve device reliability.
[0004] This invention provides a method for fabricating a semiconductor device, comprising the following steps: Step 100: Provide a substrate, grow an epitaxial layer capable of generating a two-dimensional electron gas on one side of the substrate, and perform ion implantation on the source and drain regions of the epitaxial layer to form an ohmic contact region. Step 200: A channel region is formed between the source and drain regions of the epitaxial layer. Ion implantation is performed on the epitaxial layer outside the channel region and the ohmic contact region to form an isolation region that no longer generates two-dimensional electron gas. Step 300: The epitaxial layer of the source region has a target position opposite to the via. A hard intermediate structure is set at the target position of the epitaxial layer so that the intermediate structure spans across the via but does not completely cover the via. Step 400: Arrange a source metal layer on the epitaxial layer of the source region; Step 500: Etch vias from the side of the substrate away from the epitaxial layer to the middle structure, and apply a metal plating layer to the vias so that the metal plating layer of the vias is connected to the source metal layer.
[0005] Furthermore, the specific process of step 300 is as follows: A hard material layer is deposited on the epitaxial layer, and the hard material layer is etched to form an intermediate structure.
[0006] Furthermore, the specific process of step 300 is as follows: The epitaxial layer at the target location is etched to remove a portion of the area and form an intermediate structure.
[0007] Furthermore, in step 300, after the epitaxial layer forms the intermediate structure through etching, the following step is also included: The etched depressions are filled with a conductive material layer and then planarized.
[0008] Furthermore, the intermediate structure is elongated, and there are multiple intermediate structures arranged side by side or intersecting each other.
[0009] Furthermore, when there are multiple intermediate structures arranged in a cross pattern, the two ends of each intermediate structure gradually narrow towards the middle along its length.
[0010] Furthermore, step 400 also includes the following steps: A drain metal layer is disposed in the drain region of the epitaxial layer, and a gate metal layer is disposed in the channel region of the epitaxial layer. Gate wire bonding metal pads and drain wire bonding metal pads are arranged in the isolation region of the epitaxial layer to connect the gate metal layer and the gate wire bonding metal pads, and to connect the drain metal layer and the drain wire bonding metal layer.
[0011] Furthermore, the intermediate structure is a SiN intermediate structure or a SiO2 intermediate structure.
[0012] Furthermore, the substrate is a SiC substrate, and the epitaxial layer is an AlGaN / GaN epitaxial layer.
[0013] The present invention also provides a semiconductor device, which is prepared by any of the semiconductor device preparation methods described above.
[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: The semiconductor device fabrication method provided by this invention includes the following steps: First, a substrate is provided, and an epitaxial layer capable of generating a two-dimensional electron gas is grown on one side of the substrate. Ion implantation is performed on the source and drain regions of the epitaxial layer to form an ohmic contact region. Next, a channel region is formed between the source and drain regions of the epitaxial layer, and ion implantation is performed on the epitaxial layer outside the channel region and the ohmic contact region to form an isolation region that no longer generates a two-dimensional electron gas. Next, the epitaxial layer in the source region has a target position opposite to the via, and a hard intermediate structure is set at the target position of the epitaxial layer so that the intermediate structure can cross the via but not completely cover the via. Next, a source metal layer is disposed on the epitaxial layer in the source region. Next, the via is etched from the side of the substrate away from the epitaxial layer to the intermediate structure, and a metal plating layer is set on the via so that the metal plating layer of the via is connected to the source metal layer. This allows the intermediate structure to be encased by the source metal layer and the metal plating on top of the via, so that the rigid intermediate structure can play a supporting role between the source metal layer and the metal plating on top of the via, preventing the source metal layer from deforming due to external forces, preventing via collapse, and improving device reliability.
[0015] The present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method described above, and thus the semiconductor device also has the beneficial effects of the semiconductor device preparation method. Attached Figure Description
[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 A schematic diagram illustrating steps 100 and 200 of the semiconductor device fabrication method provided in the embodiments of the present invention; Figure 2 A schematic diagram illustrating step 300 of the semiconductor device fabrication method provided in an embodiment of the present invention; Figure 3 A schematic diagram illustrating step 400 of the semiconductor device fabrication method provided in an embodiment of the present invention; Figure 4 A schematic diagram (top view) of a semiconductor device fabricated by the semiconductor device fabrication method provided in the embodiments of the present invention. Figure 5 for Figure 4 Cross-sectional view at point AA; Figure 6A schematic diagram (top view) of another semiconductor device prepared by the semiconductor device preparation method provided in the embodiments of the present invention. Figure 7 for Figure 6 Cross-sectional view at point BB.
[0018] Figure label: 1-Substrate, 10-Epipolar layer, 11-Source region, 12-Drain region, 13-Channel region, 2-Source metal layer, 3-Drain metal layer, 4-Gate metal layer, 5-Drain wire bonding metal pad, 6-Gate wire bonding metal pad, 7-Via, 71-Metal plating, 8-Intermediate structure, 9-Conductive material layer. Detailed Implementation
[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0020] The components of the embodiments of the invention described and shown in the accompanying drawings can typically be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.
[0021] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0024] The following reference Figures 1 to 7 This application describes a semiconductor device and a method for fabricating the same, based on some embodiments.
[0025] This application provides a method for fabricating a semiconductor device. Figures 1 to 3 A schematic diagram of each step in the preparation method is shown. Figure 4 A top view of a semiconductor device prepared by this method is shown. Figure 5 It shows Figure 4 A cross-sectional view at point AA.
[0026] The preparation method includes the following steps: Step 100: Provide a substrate 1, such as Figure 1 As shown, an epitaxial layer 10 capable of generating a two-dimensional electron gas is grown on one side surface (e.g., the front side) of the substrate 1. The epitaxial layer 10 has a source region 11 for arranging the source metal layer 2 and a drain region 12 for arranging the drain metal layer 3. Ion implantation is performed on the epitaxial layer 10 of the source region 11 and the drain region 12, that is, the epitaxial layer 10 is bombarded with a heavy dose of ions, so that the epitaxial layer 10 of the source region 11 and the drain region 12 can conduct electricity to form an ohmic contact region. Thus, the two-dimensional electron gas generated by the epitaxial layer 10 can be connected to the interconnected metal structure (e.g., the source metal layer 2 and via 7 in subsequent steps) through the ohmic contact region.
[0027] Step 200, the epitaxial layer 10 also has a channel region 13, such as Figure 1 As shown, the channel region 13 is located between the source region 11 and the drain region 12. For example, the epitaxial layer 10 has two source regions 11 arranged side by side with a gap between them, and the drain region 12 is located between the two source regions 11. The drain region 12 and the source regions 11 on both sides form a channel region 13.
[0028] Ion implantation is performed on the epitaxial layer 10 outside the ohmic contact region and the channel region 13 to form an isolation region. That is, the epitaxial layer 10 in the isolation region is bombarded with a light dose of ions to destroy the crystal structure of the epitaxial layer 10 in the region, so that the epitaxial layer 10 in the isolation region no longer generates two-dimensional electron gas. At the same time, since the ohmic contact region has been ion implanted in step 100, the epitaxial layer 10 in the ohmic contact region no longer generates two-dimensional electron gas, so that only the two-dimensional electron gas in the channel region 13 is retained, so that the two-dimensional electron gas in the channel region 13 connects the source region 11 and the drain region 12.
[0029] Step 300: The epitaxial layer 10 of the source region 11 has a target location, which is opposite to the via 7 of the semiconductor device; a hard intermediate structure 8 is formed at the target location of the epitaxial layer 10, combined with... Figure 2 and Figure 4As shown, the intermediate structure 8 is positioned across the via 7 but does not completely cover the via 7. For example, the intermediate structure 8 is a long strip structure with a predetermined length and a predetermined width. Its length is greater than the diameter of the via 7 so that it can be positioned across the via 7; its width is less than the diameter of the via 7 so that it does not completely cover the via 7.
[0030] Step 400, such as Figure 3 As shown, a source metal layer 2 is disposed at the source region 11 of the epitaxial layer 10, a drain metal layer 3 is disposed at the drain region 12 of the epitaxial layer 10, and a gate metal layer 4 is disposed at the channel region 13 of the epitaxial layer 10; at the same time, a gate bonding metal pad 6 and a drain bonding metal pad 5 are disposed in the isolation region of the epitaxial layer 10, and the gate metal layer 4 is connected to the gate bonding metal pad 6, and the drain metal layer 3 is connected to the drain bonding metal layer.
[0031] Step 500: The side of substrate 1 facing away from epitaxial layer 10 is the back side of substrate 1, such as... Figure 4 and Figure 5 As shown, via etching is performed on the substrate 1 from the back side of the substrate 1 at a position opposite to the target location, down to the intermediate structure 8. Then, a metal plating layer 71 is applied to the via 7; that is, the metal plating layer 71 is applied to the circumferential sidewalls of the via 7, the top of the via 7 facing the front side of the substrate 1, and around the bottom opening of the via 7, so that the metal plating layer 71 at the top of the via 7 is in direct contact with the source metal layer 2, and can be grounded through the metal plating layer 71 around the circumferential sidewalls and the bottom opening of the via 7. At this time, the intermediate structure 8 is wrapped by the source metal layer 2 and the metal plating layer 71 at the top of the via 7, so that the rigid intermediate structure 8 can play a supporting role between the source metal layer 2 and the metal plating layer 71 at the top of the via 7, so as to prevent the source metal layer 2 from deforming due to external forces, prevent the via 7 from collapsing, and improve the reliability of the device.
[0032] Regarding step 300, such as Figure 4 and 5 As shown, one method for forming the intermediate structure 8 is to deposit a hard material layer with a predetermined thickness on the epitaxial layer 10, and then etch the hard material layer to remove part of the hard material layer, with the remaining part used as the intermediate structure 8.
[0033] At this time, the intermediate structure 8 protrudes from the epitaxial layer 10. When the source metal layer 2 is formed in step 400, the source metal layer 2 will cover the intermediate structure 8 and form a protrusion at the intermediate structure 8. When the via 7 is etched in step 500, the epitaxial layer 10 needs to be etched so that the metal plating layer 71 at the top of the via 7 can contact and connect with the source metal layer 2.
[0034] In this embodiment, preferably, the hard material layer is a SiN hard material layer or a SiO2 hard material layer, that is, the formed intermediate structure 8 is a SiN intermediate structure 8 or a SiO2 intermediate structure 8.
[0035] Regarding step 300, such as Figure 6 and Figure 7 As shown, another method for forming the intermediate structure 8 is to etch the epitaxial layer 10 at the target location opposite to the via 7 to remove part of the epitaxial layer 10 at the target location, and use the remaining part as the intermediate structure 8.
[0036] As described below, the epitaxial layer 10 is an AlGaN (aluminum gallium nitride) / GaN (gallium nitride) epitaxial layer 10, that is, the epitaxial layer 10 is an AlGaN / GaN stacked structure. The hardness of AlGaN and GaN materials is comparable to that of SiN, and they can also effectively support the source metal layer 2 to prevent the source metal layer 2 from deforming.
[0037] At this time, when etching the via in step 500, it is not necessary to etch the epitaxial layer 10; it is only necessary to etch away the substrate 1 at the target location.
[0038] Meanwhile, in this method, after the epitaxial layer 10 is etched to form the intermediate structure 8 in step 300, the method further includes the following steps: filling the recessed area formed by the etching of the epitaxial layer 10 with a conductive metal material layer 9 and performing planarization treatment, so that the metal plating layer 71 at the top of the via 7 is connected to the source metal layer 2 through the conductive material, so that the conductive material layer 9 can play a conductive role. Compared with the method of not etching the epitaxial layer 10 and only using the epitaxial layer 10 after ohmic contact treatment for support and conduction, the grounding via formed by this method has better grounding performance.
[0039] Regarding the intermediate structure 8, in one embodiment of this application, preferably, the intermediate structure 8 is elongated, such as... Figure 2 The middle structure 8 is shown on the right side.
[0040] There is at least one intermediate structure 8. When there are multiple intermediate structures 8 (including two), the multiple intermediate structures 8 are arranged side by side with intervals or cross each other.
[0041] Preferably, when multiple intermediate structures 8 are arranged radially and intersectingly, such as... Figure 2 The middle structure 8 shown on the left gradually narrows from both ends towards the middle along its length. This arrangement of the middle structure 8 provides stronger support and maximizes the grounding of the source metal layer 2.
[0042] In one embodiment of this application, preferably, the substrate 1 is a SiC substrate, and the epitaxial layer 10 is an AlGaN / GaN epitaxial layer. The SiC substrate has high thermal conductivity, which can conduct the heat of the channel region 13 to the packaging substrate of the device. The two-dimensional electron gas generated by the AlGaN / GaN epitaxial layer has high electron mobility and electron saturation velocity, enabling the device to achieve higher drain efficiency.
[0043] This application also provides a semiconductor device, which is prepared by the semiconductor device preparation method of any of the above embodiments. Therefore, the semiconductor device has all the beneficial effects of the semiconductor device preparation method, which will not be described in detail here.
[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Step 100: Provide a substrate, grow an epitaxial layer capable of generating a two-dimensional electron gas on one side of the substrate, and perform ion implantation on the source and drain regions of the epitaxial layer to form an ohmic contact region. Step 200: A channel region is formed between the source and drain regions of the epitaxial layer. Ion implantation is performed on the epitaxial layer outside the channel region and the ohmic contact region to form an isolation region that no longer generates two-dimensional electron gas. Step 300: The epitaxial layer of the source region has a target position opposite to the via. A hard intermediate structure is set at the target position of the epitaxial layer so that the intermediate structure spans across the via but does not completely cover the via. Step 400: Arrange a source metal layer on the epitaxial layer of the source region; Step 500: Etch vias from the side of the substrate away from the epitaxial layer to the middle structure, and apply a metal plating layer to the vias so that the metal plating layer of the vias is connected to the source metal layer.
2. The semiconductor device fabrication method according to claim 1, characterized in that, The specific process of step 300 is as follows: A hard material layer is deposited on the epitaxial layer, and the hard material layer is etched to form an intermediate structure.
3. The semiconductor device fabrication method according to claim 1, characterized in that, The specific process of step 300 is as follows: The epitaxial layer at the target location is etched to remove a portion of the area and form an intermediate structure.
4. The semiconductor device fabrication method according to claim 3, characterized in that, In step 300, after the epitaxial layer forms the intermediate structure by etching, the following step is also included: The etched depressions are filled with a conductive material layer and then planarized.
5. The semiconductor device fabrication method according to claim 1, characterized in that, The intermediate structure is long and narrow, and there are multiple intermediate structures arranged side by side or intersecting each other.
6. The semiconductor device fabrication method according to claim 1, characterized in that, When there are multiple intermediate structures arranged in a cross pattern, the two ends of the intermediate structure gradually narrow towards the middle along its own length direction.
7. The semiconductor device fabrication method according to claim 1, characterized in that, Step 400 further includes the following steps: A drain metal layer is disposed in the drain region of the epitaxial layer, and a gate metal layer is disposed in the channel region of the epitaxial layer. Gate wire bonding metal pads and drain wire bonding metal pads are arranged in the isolation region of the epitaxial layer to connect the gate metal layer and the gate wire bonding metal pads, and to connect the drain metal layer and the drain wire bonding metal layer.
8. The semiconductor device fabrication method according to claim 1, characterized in that, The intermediate structure is a SiN intermediate structure or a SiO2 intermediate structure.
9. The semiconductor device fabrication method according to claim 1, characterized in that, The substrate is a SiC substrate, and the epitaxial layer is an AlGaN / GaN epitaxial layer.
10. A semiconductor device, characterized in that, The semiconductor device is prepared by the semiconductor device preparation method according to any one of claims 1 to 9.