Gallium nitride MOS device for improving joint load of quadruped robot and packaging method of gallium nitride MOS device
By integrating gallium nitride (GaN) with a MOS structure and employing common-gate control and stepped doping design, the voltage overshoot and current surge issues of GaN MOS devices during high-load shutdown are solved, improving the reliability and safety of the devices and making them suitable for high-frequency, high-power-density applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU SPECTRUM SEMICON TECH CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-05-19
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing gallium nitride MOS devices are prone to voltage overshoot and sudden current changes during high-load shutdown, leading to local electric field concentration and increased thermal effects, which affect the reliability and safety of the device under extreme operating conditions.
The system integrates gallium nitride (GaN) and MOS structures on the same substrate and achieves common gate control through the master gate. It combines a stepped doping structure with low-doped N- and high-doped N+ layers, a heavily doped aluminum gallium nitride (AlGaN) layer, and a discontinuous particle N+ layer design to optimize the electric field distribution and current path, reduce on-resistance, and enhance current control capability.
It effectively suppresses voltage overshoot and current surge during high-load shutdown, improves the dynamic response and stability of the device, enhances its tolerance to transient overvoltage and overcurrent, increases carrier concentration and ohmic contact characteristics, and prevents breakdown failure.
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Figure CN122069748A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to gallium nitride MOS devices and their packaging methods for improving the joint load of quadruped robots. Background Technology
[0002] During high-load shutdown, existing gallium nitride MOS devices are prone to voltage overshoot and sudden current changes due to limitations in device structure and material properties. This leads to local electric field concentration and increased thermal effects, which in turn causes device breakdown failure, seriously affecting the reliability and safety of the device under extreme operating conditions.
[0003] An existing patent discloses a method for fabricating an enhanced HEMT device (publication number CN104538302A). This prior art fails to provide an effective device structure design and packaging method to suppress electrothermal stress during shutdown transients, thus failing to guarantee the safe shutdown and long-term stability of the device under extreme operating conditions. Summary of the Invention
[0004] This invention provides a gallium nitride MOS device and its packaging method to improve the joint load of quadruped robots in order to solve existing technical problems, effectively suppressing the problems of voltage overshoot and current surge during high load shutdown.
[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a gallium nitride MOS device for improving the joint load of a quadruped robot, comprising a substrate, a gallium nitride structure, and a MOS structure; the gallium nitride structure comprises, from bottom to top, a buffer layer, a gallium nitride layer, an aluminum gallium nitride layer, a p-type gallium nitride layer, and a gallium nitride gate, and the upper left and right sides of the aluminum gallium nitride layer further include gallium nitride source and gallium nitride drain; The MOS structure, from bottom to top, includes an N-diffusion layer and a MOS gate. The N-diffusion layer has a source P-well layer and a drain P-well layer on its left and right sides, respectively. The MOS gate has a MOS source and a MOS drain on its left and right sides, respectively. The gallium nitride structure and the MOS structure are located on the left and right sides of the substrate, respectively. The gallium nitride drain is in direct contact with the MOS source. A dielectric layer is deposited on the gallium nitride gate, gallium nitride drain, MOS source, and above the MOS gate, as well as between the gallium nitride structure and the MOS structure. A master control gate is deposited above the gallium nitride gate and the MOS gate, wherein the master control gate is in direct contact with the gallium nitride gate and the MOS gate.
[0006] Furthermore, the gallium nitride source serves as the source of the gallium nitride MOS device; the MOS drain serves as the drain of the gallium nitride MOS device; and the master control gate serves as the gate of the gallium nitride MOS device.
[0007] Furthermore, the dielectric layer also includes the space between the MOS gate and the N-diffusion layer, between the gallium nitride source and the gallium nitride gate, and between the MOS drain and the MOS gate.
[0008] Furthermore, a lightly doped N-layer is formed inside the N-diffusion layer and between the source P-well layer and the drain P-well layer by ion implantation.
[0009] Furthermore, a highly doped N+ layer is formed inside the low-doped N- layer through ion implantation, and the two ends of the highly doped N+ layer are in direct contact with the source P-well layer and the drain P-well layer, respectively.
[0010] Furthermore, the interior of the low-doped N- layer is formed by ion implantation into a granular N+ layer consisting of several semi-circular particles, wherein the two ends of the granular N+ layer are in direct contact with the source P-well layer and the drain P-well layer, respectively.
[0011] Furthermore, an aluminum gallium nitride heavily doped layer is formed between the gallium nitride layer and the aluminum gallium nitride layer by ion implantation; By incorporating an ion-implanted, heavily doped aluminum gallium nitride (GaN) layer between the gallium nitride (GaN) and aluminum gallium nitride (GaN) layers, the contact resistance and heterojunction interface barrier between the GaN and GaN layers are significantly reduced, thereby effectively improving the transport characteristics of the two-dimensional electron gas (2DEG). Specifically, this heavily doped layer increases carrier concentration, optimizes ohmic contact characteristics, and reduces the device's on-resistance. During high-load shutdown, the lower on-resistance helps suppress voltage overshoot and current surges, thus improving the device's reliability and safety under extreme operating conditions and preventing breakdown failures caused by localized overheating or electric field concentration.
[0012] Furthermore, an N+ doped layer is formed in the upper half of the N diffusion layer by ion implantation, and the cross-sectional profile of the N+ doped layer is convex.
[0013] A packaging method for gallium nitride MOS devices to improve the joint load of quadruped robots includes the following steps: S1. A gallium nitride structure and a MOS structure are respectively fabricated on the substrate, wherein the gallium nitride drain is in direct contact with the MOS source to achieve electrical connection; S2. Deposit a dielectric layer over the gallium nitride structure and the MOS structure, and pattern the dielectric layer to expose at least the surfaces of the gallium nitride gate, gallium nitride drain, MOS source, and MOS gate. S3. A conductive material is deposited above the dielectric layer to form a master control gate. The master control gate fills the patterned etched area and is in direct contact with the gallium nitride gate and MOS gate below. S4. Thin the wafer and deposit a back metal layer on the back side of the substrate; S5. The wafer is divided into independent chips by a dicing process, and the source (i.e. gallium nitride source), drain (i.e. MOS drain) and gate (i.e. main control gate) of the chip are connected to the lead frame or substrate by wire bonding or conductive adhesive bonding. S6. Epoxy resin or ceramic materials are used for encapsulation to form a package to protect the internal chip structure, ultimately resulting in a gallium nitride MOS device that improves the joint load of a quadruped robot.
[0014] The gallium nitride MOS device and its packaging method for improving the joint load of quadruped robots provided by this invention have the following advantages compared with the prior art: 1. This invention integrates gallium nitride (GaN) structures and MOS structures on the same substrate and uses a master gate to achieve common gate control, thereby realizing the functional fusion of the two devices. While retaining the advantages of high frequency and high voltage of GaN, it enhances the current control capability, effectively suppresses voltage overshoot and current surge during high load shutdown, and significantly improves the dynamic response and stability of the device.
[0015] 2. This invention introduces a stepped doping structure consisting of a low-doped N- layer and a high-doped N+ layer in the N-diffusion layer of the MOS structure, which optimizes the electric field distribution and reduces the on-resistance, making the current path more uniform. It can smooth the current decay and reduce voltage spikes at the moment of shutdown under high load, thereby greatly improving the device's turn-off safety and reliability under high voltage conditions.
[0016] 3. This invention innovatively sets up a particle N+ layer composed of multiple semi-circular particles within a low-doped N- layer, forming a discontinuous high-doped region. This effectively disperses current and suppresses local current accumulation without significantly increasing the on-resistance, reducing thermal stress and electric field strength, and enhancing the device's tolerance to transient overvoltage and overcurrent. It is particularly suitable for high-frequency and high-power-density applications.
[0017] 4. This invention forms a heavily doped aluminum gallium nitride layer between the gallium nitride layer and the aluminum gallium nitride layer by ion implantation, which significantly reduces the heterojunction interface barrier, improves the transport characteristics of the two-dimensional electron gas, increases the carrier concentration and optimizes the ohmic contact, thereby reducing the on-resistance, suppressing voltage overshoot and current surge during high load shutdown, preventing local overheating or breakdown failure, and enhancing safety under extreme operating conditions.
[0018] 5. In this invention, an N+ doped layer with a "convex" shaped cross section is formed by ion implantation in the upper half region of the N diffusion layer, which realizes local enhancement of the current path. Without affecting the breakdown voltage, it improves the conduction performance and switching response speed, guides the current to be released quickly and evenly at the moment of turn-off, reduces current accumulation and voltage spikes, and achieves dual optimization of performance and reliability. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of the structure of Embodiment 5 of the present invention.
[0020] In the figure: 1. Substrate; 2. Gallium nitride structure; 3. Dielectric layer; 4. MOS structure; 5. Main control gate; 201. Buffer layer; 202. Gallium nitride layer; 203. Aluminum gallium nitride layer; 204. Gallium nitride source; 205. P-type gallium nitride layer; 206. Gallium nitride gate; 207. Gallium nitride drain; 208. Heavily doped aluminum gallium nitride layer; 401. N-diffusion layer; 402. Source P-well layer; 403. Drain P-well layer; 404. MOS drain; 405. MOS source; 406. MOS gate; 407. Lightly doped N- layer; 408. Heavily doped N+ layer; 409. Particulate N+ layer; 410. N+ doped layer. Detailed Implementation
[0021] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a gallium nitride MOS device for improving the joint load of a quadruped robot is provided, including a substrate 1, a gallium nitride structure 2, and a MOS structure 4; the gallium nitride structure 2 includes, from bottom to top, a buffer layer 201, a gallium nitride layer 202, an aluminum gallium nitride layer 203, a P-type gallium nitride layer 205, and a gallium nitride gate 206, and the upper left and right sides of the aluminum gallium nitride layer 203 also include a gallium nitride source 204 and a gallium nitride drain 207; the MOS structure 4 includes, from bottom to top, an N-diffusion layer 401 and a MOS gate 406, the inner left and right sides of the N-diffusion layer 401 are respectively provided with a source P-well layer 402 and a drain P-well layer 403, the left and right sides of the MOS gate 406 are respectively a MOS source 405 and a MOS drain 404, the gallium nitride structure 2 and the MOS structure 4 are respectively located on the left and right sides of the substrate 1, wherein the gallium nitride drain 207 is in direct contact with the MOS source 405; A dielectric layer 3 is deposited above the gallium nitride gate 206, gallium nitride drain 207, MOS source 405, and between the gallium nitride structure 2 and the MOS structure 4. A master control gate 5 is deposited above the gallium nitride gate 206 and the MOS gate 406, and the master control gate 5 is in direct contact with the gallium nitride gate 206 and the MOS gate 406. The gallium nitride source 204 serves as the source of the gallium nitride MOS device; the MOS drain 404 serves as the drain of the gallium nitride MOS device; and the master control gate 5 serves as the gate of the gallium nitride MOS device. The dielectric layer 3 also includes layers between the MOS gate 406 and the N-diffusion layer 401, between the gallium nitride source 204 and the gallium nitride gate 206, and between the MOS drain 404 and the MOS gate 406.
[0023] This embodiment integrates the gallium nitride (GaN) structure 2 and the MOS structure 4 on the left and right sides of the same substrate 1, and achieves direct contact between the GaN drain 207 and the MOS source 405, forming a novel GaN-MOS hybrid integrated device. Simultaneously, the GaN gate 206 and the MOS gate 406 are electrically connected through the main control gate 5, sharing the same control signal. This structure achieves functional integration of GaN devices and silicon-based MOS devices, retaining the excellent performance of gallium nitride materials under high frequency and high voltage, while utilizing the MOS structure to enhance the device's current control capability and switching stability.
[0024] During high-load shutdown, this integrated structure effectively suppresses sudden current changes and voltage overshoot, preventing breakdown failures caused by localized electric field concentration or thermal effects. Unified control of the master gate ensures synchronous response between the GaN and MOS sections, improving the device's dynamic response and system robustness, making it particularly suitable for power electronic systems with extremely high safety requirements.
[0025] Example 2 like Figure 2As shown, according to one aspect of the present invention, a gallium nitride MOS device for improving the joint load of a quadruped robot is provided, including a substrate 1, a gallium nitride structure 2, and a MOS structure 4; the gallium nitride structure 2 includes, from bottom to top, a buffer layer 201, a gallium nitride layer 202, an aluminum gallium nitride layer 203, a P-type gallium nitride layer 205, and a gallium nitride gate 206, and gallium nitride source 204 and gallium nitride drain 207 are also provided on the left and right sides above the aluminum gallium nitride layer 203; the MOS structure 4 includes, from bottom to top, an N-diffusion layer 401 and a MOS gate 406, and source P-well layers 402 and drain P-well layers 403 are respectively provided on the left and right sides inside the N-diffusion layer 401, and MOS source 405 and MOS drain 404 are respectively on the left and right sides of the MOS gate 406; a lightly doped N-layer 407 is formed inside the N-diffusion layer 401 and between the source P-well layer 402 and the drain P-well layer 403 by ion implantation. A highly doped N+ layer 408 is formed inside the low-doped N- layer 407 by ion implantation. The two ends of the highly doped N+ layer 408 are in direct contact with the source P-well layer 402 and the drain P-well layer 403, respectively.
[0026] In this embodiment, a lightly doped N- layer 407 is introduced within the N-diffusion layer 401 of the MOS structure 4, and a heavily doped N+ layer 408 is further implanted inside it to form a stepped doped structure. This design optimizes the electric field distribution of the MOS portion, reduces the on-resistance between the drain and source, and enhances the uniformity of the current path, avoiding the formation of local hot spots.
[0027] During high-load shutdown, this structure helps smooth the current decay process and reduce voltage spikes, thereby improving device shutdown safety. Precise control of doping concentration and distribution through ion implantation ensures low conduction losses and improves reliability and lifespan under high-voltage and high-current conditions.
[0028] Example 3 like Figure 3As shown, according to one aspect of the present invention, a gallium nitride MOS device for improving the joint load of a quadruped robot is provided, including a substrate 1, a gallium nitride structure 2, and a MOS structure 4; the gallium nitride structure 2 includes, from bottom to top, a buffer layer 201, a gallium nitride layer 202, an aluminum gallium nitride layer 203, a P-type gallium nitride layer 205, and a gallium nitride gate 206, and gallium nitride source 204 and gallium nitride drain 207 are also provided on the left and right sides above the aluminum gallium nitride layer 203; the MOS structure 4 includes, from bottom to top, an N-diffusion layer 401 and a MOS gate 406, and source P-well layers 402 and drain P-well layers 403 are respectively provided on the left and right sides inside the N-diffusion layer 401, and MOS source 405 and MOS drain 404 are respectively on the left and right sides of the MOS gate 406; a lightly doped N-layer 407 is formed inside the N-diffusion layer 401 and between the source P-well layer 402 and the drain P-well layer 403 by ion implantation. The interior of the lightly doped N- layer 407 is formed by ion implantation into a particle N+ layer 409 consisting of several semi-circular particles, wherein the two ends of the particle N+ layer 409 are in direct contact with the source P-well layer 402 and the drain P-well layer 403, respectively.
[0029] This embodiment innovatively introduces a particle N+ layer 409 composed of multiple semi-circular particles into the low-doped N- layer 407, forming a discontinuous high-doped region. This structure effectively improves the uniformity of current distribution without significantly increasing the on-resistance, and plays a role in dispersing the electric field and suppressing current accumulation during the turn-off process.
[0030] During high-load shutdown, the N+ layer 409 particles can guide current to flow along multiple paths, preventing current concentration in a single channel and thus reducing local thermal stress and electric field intensity. This structural design not only improves the device's shutdown safety but also enhances its tolerance to transient overvoltage and overcurrent, making it suitable for high-frequency, high-power-density applications.
[0031] Example 4 like Figure 4As shown, according to one aspect of the present invention, a gallium nitride MOS device for improving the joint load of a quadruped robot is provided, comprising a substrate 1, a gallium nitride structure 2, and a MOS structure 4; the gallium nitride structure 2 comprises, from bottom to top, a buffer layer 201, a gallium nitride layer 202, an aluminum gallium nitride layer 203, a p-type gallium nitride layer 205, and a gallium nitride gate 206, and the upper left and right sides of the aluminum gallium nitride layer 203 further include gallium nitride source 204 and gallium nitride drain 207; the MOS structure 4 comprises, from bottom to top, an N-diffusion layer 401 and a MOS gate 406, the inner left and right sides of the N-diffusion layer 401 are respectively provided with a source P-well layer 402 and a drain P-well layer 403, and the left and right sides of the MOS gate 406 are respectively a MOS source 405 and a MOS drain 404; an aluminum gallium nitride heavily doped layer 208 is formed between the gallium nitride layer 202 and the aluminum gallium nitride layer 203 by ion implantation; By placing an ion-implanted heavily doped aluminum gallium nitride (AGaN) layer 208 between the gallium nitride (GaN) layer 202 and the aluminum gallium nitride (AGaN) layer 203, the contact resistance and heterojunction interface barrier between the GaN layer 202 and the AGaN layer 203 are significantly reduced, thereby effectively improving the transport characteristics of the two-dimensional electron gas (2DEG). Specifically, this heavily doped layer can increase the carrier concentration, optimize ohmic contact characteristics, and reduce the on-resistance of the device. At the moment of high-load shutdown, the lower on-resistance helps to suppress voltage overshoot and current surges, thereby improving the reliability and safety of the device under extreme operating conditions and preventing breakdown failure caused by local overheating or electric field concentration.
[0032] In this embodiment, a heavily doped aluminum gallium nitride layer 208 is formed between the gallium nitride layer 202 and the aluminum gallium nitride layer 203 by ion implantation. This significantly reduces the heterojunction interface barrier and improves the transport characteristics of the two-dimensional electron gas (2DEG). This heavily doped layer increases the carrier concentration and optimizes the ohmic contact performance, thereby effectively reducing the on-resistance of the device.
[0033] During high-load shutdown, the lower on-resistance helps suppress voltage overshoot and current surges, preventing breakdown failures caused by localized overheating or electric field concentration. This structural design not only improves the device's high-frequency performance and switching speed but also significantly enhances its reliability and safety under extreme operating conditions.
[0034] Example 5 like Figure 5As shown, according to one aspect of the present invention, a gallium nitride MOS device for improving the joint load of a quadruped robot is provided, including a substrate 1, a gallium nitride structure 2, and a MOS structure 4; the gallium nitride structure 2 includes, from bottom to top, a buffer layer 201, a gallium nitride layer 202, an aluminum gallium nitride layer 203, a P-type gallium nitride layer 205, and a gallium nitride gate 206, and the upper left and right sides of the aluminum gallium nitride layer 203 also include a gallium nitride source 204 and a gallium nitride drain 207; the MOS structure 4 includes, from bottom to top, an N-diffusion layer 401 and a MOS gate 406, the inner left and right sides of the N-diffusion layer 401 are respectively provided with a source P-well layer 402 and a drain P-well layer 403, and the left and right sides of the MOS gate 406 are respectively a MOS source 405 and a MOS drain 404; the upper half region of the inner part of the N-diffusion layer 401 is formed with an N+ doped layer 401 by ion implantation, and the cross-sectional profile of the N+ doped layer 401 is convex.
[0035] In this embodiment, an N+ doped layer 410 with a convex cross-section is formed by ion implantation in the upper half of the N diffusion layer 401, achieving local enhancement of the current path. This structure optimizes the current transport capability of the MOS section, while improving the device's conduction performance and switching response speed without affecting the breakdown voltage.
[0036] During high-load shutdown, this structure helps guide the current to be released quickly and evenly at the moment of shutdown, reducing current accumulation and voltage spikes, thereby improving the device's shutdown safety. By precisely controlling the geometry and doping concentration of the doped regions, both performance and reliability are optimized, making it suitable for high-power applications with stringent safety and efficiency requirements.
[0037] Example 6 like Figure 1 As shown, a method for packaging gallium nitride MOS devices to improve the joint load of a quadruped robot includes the following steps: Step 1: Fabricate gallium nitride structure 2 and MOS structure 4 on substrate 1, respectively, wherein the gallium nitride drain 207 and the MOS source 405 are in direct contact to achieve electrical connection; Gallium nitride (GaN) and MOS (MOS) structures are fabricated separately on a substrate, and electrical connection is achieved through direct contact between the GaN drain and the MOS source. This step integrates the GaN device and the MOS device on the same substrate using a monolithic integration method, realizing wafer-level fusion of two heterogeneous material structures. This provides a physical basis for subsequent common-gate control, while shortening the interconnect path, reducing parasitic inductance and resistance, and helping to improve the response speed and stability of the device during high-frequency switching.
[0038] Step 2: Deposit dielectric layer 3 over gallium nitride structure 2 and MOS structure 4, and pattern the dielectric layer 3 to expose at least the surface of gallium nitride gate 206, gallium nitride drain 207, MOS source 405 and MOS gate 406. A dielectric layer is deposited above the gallium nitride (GaN) and MOS structures, and then patterned and etched to expose the surfaces of the GaN gate, GaN drain, MOS source, and MOS gate. This step achieves electrical isolation of the device surface through dielectric layer deposition, preventing short circuits or leakage. At the same time, the patterned etching precisely exposes key electrode areas, reserving interconnect windows for the formation of the main control gate and ensuring good ohmic contact between the subsequent conductive material and the underlying electrodes.
[0039] Step 3: Deposit conductive material on top of dielectric layer 3 to form main control gate 5. Main control gate 5 fills the patterned etched area and is in direct contact with the gallium nitride gate 206 and MOS gate 406 below. A conductive material is deposited above the dielectric layer to form the master gate, which fills the etched area and directly contacts the underlying gallium nitride gate and MOS gate. This step achieves unified gate control for the GaN and MOS portions through a shared electrode structure, eliminating the switching timing mismatch problem caused by asynchronous gate drive in discrete devices, thereby improving the dynamic consistency and control accuracy of the device during high-load shutdown.
[0040] Step 4: Thin the wafer and deposit a back metal layer on the back side of substrate 1; The wafer is thinned, and a back metal layer is deposited on the back side of the substrate. This step reduces the thermal resistance and electrical resistance of the substrate through the thinning process, which helps to improve the heat dissipation and current carrying capacity of the device. At the same time, the deposition of the back metal layer provides a good back ground or heat dissipation path for the device, further enhancing its thermal stability and reliability under high power operating conditions.
[0041] Step 5: Divide the wafer into individual chips using a dicing process, and connect the source (i.e., gallium nitride source 204), drain (i.e., MOS drain 404), and gate (i.e., main control gate 5) of the chips to the lead frame or substrate by wire bonding or conductive adhesive bonding. The wafer is diced into individual chips using a dicing process. The source, drain, and gate of each chip are then connected to a lead frame or substrate via wire bonding or conductive adhesive. This step facilitates the transition from the wafer level to the packaging level. By using low-inductance, low-resistance interconnects, the device electrodes are led to external circuits, ensuring that current is released quickly and evenly during high-load shutdown, thus avoiding localized overvoltage or current accumulation caused by poor interconnects.
[0042] Step 6: Use epoxy resin or ceramic materials for molding to form an encapsulation to protect the internal chip structure, ultimately obtaining a gallium nitride MOS device that improves the joint load of the quadruped robot; Epoxy resin or ceramic materials are used for molding to form an encapsulation to protect the internal chip structure. This step provides mechanical support and environmental protection through the encapsulation material, preventing damage to the chip from moisture, dust, or mechanical stress. At the same time, the thermal conductivity of the material optimizes the overall heat dissipation capacity of the device, ensuring that the device maintains structural integrity and electrical stability under extreme conditions such as high-load shutdown.
[0043] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A gallium nitride MOS device for improving the joint load of a quadruped robot, comprising a substrate (1), a gallium nitride structure (2), and a MOS structure (4); the gallium nitride structure (2) comprises, from bottom to top, a buffer layer (201), a gallium nitride layer (202), an aluminum gallium nitride layer (203), a p-type gallium nitride layer (205), and a gallium nitride gate (206); the aluminum gallium nitride layer (203) also includes a gallium nitride source (204) and a gallium nitride drain (207) on the upper left and right sides. The MOS structure (4) includes, from bottom to top, an N-diffusion layer (401) and a MOS gate (406). The N-diffusion layer (401) has a source P-well layer (402) and a drain P-well layer (403) on its left and right sides, respectively. The MOS gate (406) has a MOS source (405) and a MOS drain (404) on its left and right sides, respectively. Its characteristic is that: The gallium nitride structure (2) and the MOS structure (4) are located on the left and right sides of the substrate (1), respectively, wherein the gallium nitride drain (207) is in direct contact with the MOS source (405); A dielectric layer (3) is deposited above the gallium nitride gate (206), gallium nitride drain (207), MOS source (405), and MOS gate (406), and between the gallium nitride structure (2) and the MOS structure (4). A master control gate (5) is deposited above the gallium nitride gate (206) and the MOS gate (406), wherein the master control gate (5) is in direct contact with the gallium nitride gate (206) and the MOS gate (406).
2. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 1, characterized in that: The gallium nitride source (204) serves as the source of the gallium nitride MOS device; the MOS drain (404) serves as the drain of the gallium nitride MOS device; and the master control gate (5) serves as the gate of the gallium nitride MOS device.
3. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 1, characterized in that: The dielectric layer (3) also includes the space between the MOS gate (406) and the N diffusion layer (401), between the gallium nitride source (204) and the gallium nitride gate (206), and between the MOS drain (404) and the MOS gate (406).
4. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 1, characterized in that: The N-diffusion layer (401) is located inside the source P-well layer (402) and between the drain P-well layer (403) and has a low-doped N-layer (407) formed by ion implantation.
5. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 4, characterized in that: The interior of the low-doped N- layer (407) is formed by ion implantation of a highly doped N+ layer (408), and the two ends of the highly doped N+ layer (408) are in direct contact with the source P-well layer (402) and the drain P-well layer (403), respectively.
6. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 4, characterized in that: The interior of the low-doped N-layer (407) is formed by ion implantation into a particle N+ layer (409) consisting of several semi-circular particles, wherein the two ends of the particle N+ layer (409) are in direct contact with the source P-well layer (402) and the drain P-well layer (403), respectively.
7. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 1, characterized in that: A heavily doped aluminum gallium nitride layer (208) is formed between the gallium nitride layer (202) and the aluminum gallium nitride layer (203) by ion implantation.
8. The gallium nitride MOS device for improving the joint load of a quadruped robot according to claim 1, characterized in that: The upper half of the inner region of the N diffusion layer (401) is formed with an N+ doped layer (401) by ion implantation, and the cross-sectional profile of the N+ doped layer (401) is convex.
9. A packaging method for gallium nitride MOS devices to improve the joint load of quadruped robots, characterized in that, The gallium nitride MOS device for improving the joint load of a quadruped robot as described in claim 1, and the packaging method of the gallium nitride MOS device for improving the joint load of a quadruped robot, includes the following steps: S1. A gallium nitride structure (2) and a MOS structure (4) are respectively fabricated on the substrate (1), wherein the gallium nitride drain (207) is in direct contact with the MOS source (405) to achieve electrical connection; S2. Deposit a dielectric layer (3) over the gallium nitride structure (2) and the MOS structure (4), and pattern the dielectric layer (3) to expose at least the surfaces of the gallium nitride gate (206), the gallium nitride drain (207), the MOS source (405) and the MOS gate (406); S3. A conductive material is deposited above the dielectric layer (3) to form a main control gate (5). The main control gate (5) fills the patterned etched area and is in direct contact with the gallium nitride gate (206) and MOS gate (406) below. S4. Thin the wafer and deposit a back metal layer on the back side of the substrate (1); S5. The wafer is divided into independent gallium nitride MOS devices by a dicing process, and the source, drain and gate of the gallium nitride MOS devices are connected to the lead frame or substrate by wire bonding or conductive adhesive bonding. S6. Use epoxy resin or ceramic materials to form a package.