Power device with graded channel

Abstract

The invention relates to a power device with graded channels. The invention discloses a power device. The power device comprises a semiconductor substrate; a drift layer of first conductivity disposed over a first side of the semiconductor substrate; the grid electrode is arranged on the drift layer; and a graded channel, the graded channel comprising a lightly doped region of a second conductivity and a heavily doped capsule region of the second conductivity, the heavily doped capsule region vertically extending from an upper surface adjacent to the semiconductor substrate to a heavily doped region of the second conductivity below the lightly doped region and the heavily doped capsule region.

Description

[0001] This application is a divisional application of application No. 202011149950.2, filed on October 23, 2020, entitled "Power Device with Hierarchical Channel". Technical Field

[0002] This disclosure relates to silicon carbide (SiC) power semiconductor devices. Background Technology

[0003] Power semiconductor devices are used in many different industries. Some of these industries, such as telecommunications, computing, and billing systems, are rapidly evolving. Compared to silicon (Si) power devices, silicon carbide (SiC) power devices (e.g., MOSFETs) offer lower on-resistance, higher breakdown electric field, higher switching speed, and higher operating temperature. These characteristics make SiC power devices a better candidate because of their smaller size.

[0004] However, as the size of SiC devices shrinks, physical properties such as threshold voltage, on-resistance, and punch-through are strongly influenced by the geometric profile. For example, the gate surface profile and high interface state density at SiO2 / SiC can lead to low channel mobility and threshold voltage instability. Summary of the Invention

[0005] In one embodiment, the power semiconductor device includes: a silicon carbide substrate; a gate disposed on a first side of the silicon carbide substrate; and a hierarchical channel including a first region having a first dopant concentration and a second region having a second dopant concentration. The second dopant concentration is greater than the first dopant concentration.

[0006] In another embodiment, the power device further includes: a drift layer disposed on the silicon carbide substrate; a reverse well; and a capsule region disposed within the reverse well.

[0007] In one embodiment, the first region of the hierarchical channel includes a lightly doped region of the retrograde well, and the second region of the hierarchical channel includes the capsule region.

[0008] In one embodiment, the drift layer has n-type conductivity, and the retrograde well has p-type conductivity. The sac region has p-type conductivity.

[0009] In one embodiment, the power device is a MOSFET, and the sac region has a halo shape when viewed from above.

[0010] In one embodiment, the concentration of the second dopant is at least 5 times that of the concentration of the first dopant. In another embodiment, the concentration of the second dopant is at least 10 times that of the concentration of the first dopant.

[0011] In one embodiment, the power device further includes: a source region disposed on the first side of the silicon carbide substrate; a drift layer disposed on the silicon carbide substrate and having a hexagonal crystal structure; a reverse well; a capsule region disposed within the reverse well; and a drain electrode disposed on the second side of the silicon carbide substrate.

[0012] In one embodiment, the source region has n-type conductivity and the reverse well has p-type conductivity.

[0013] In one embodiment, a method for forming a power semiconductor device is disclosed. The method includes: providing a silicon carbide layer with first conductivity; forming a reverse well with second conductivity, the reverse well having a lightly doped region near a surface of the silicon carbide layer and a heavily doped region disposed below the lightly doped region; forming a capsule region of the second conductivity within the reverse well, the capsule region being the heavily doped region; and forming a gate on the surface of the silicon carbide layer.

[0014] In one embodiment, the bladder region and the lightly doped region of the reverse well define a hierarchical channel for the power semiconductor device.

[0015] In one embodiment, the method further includes depositing a first material layer on the silicon carbide layer; and patterning the first material layer to obtain a first spacer. The capsule region is formed by injecting a first dopant with a second conductivity into the inverted well using the first spacer as an implantation mask.

[0016] In one embodiment, the first spacer prevents the first dopant from being implanted into a portion of the lightly doped region of the retrograde well, and the first dopant is implanted into the retrograde well without an implantation tilt angle.

[0017] In one embodiment, the method further includes depositing a hard mask layer on the silicon carbide layer and patterning the hard mask layer. The first material layer is deposited on the patterned hard mask layer, and the first spacer is disposed on the sidewall of the patterned hard mask layer. Attached Figure Description

[0018] Figure 1 An example of a power semiconductor device according to one embodiment is shown.

[0019] Figures 2 to 8 An example is illustrated of a method for manufacturing a power semiconductor device having a hierarchical channel according to one embodiment. Detailed Implementation

[0020] Embodiments of this patent application relate to silicon carbide power semiconductor devices. These power devices may be MOSFETs, IGBTs, etc. For ease of explanation, the power device may be described herein as a MOSFET.

[0021] In one embodiment, the power semiconductor device has a channel with a graded doping profile. The power device may be a SiC MOSFET with a retrograde P-well, such as a 4H-SiC MOSFET. A locally heavily doped pod region is formed adjacent to the source region. The graded channel has lightly doped and heavily doped regions. This graded channel improves threshold voltage control and prevents punch-through effects. The graded channel also allows for a reduction in channel length without significantly adverse short-channel effects. The heavily doped pod region is formed in the P-well by implanting dopant without applying a tilt angle. In one specific embodiment, a spacer is used as an implantation mask, allowing the heavily doped pod region to be formed using a self-aligned implantation step.

[0022] Detailed embodiments are provided below with reference to the accompanying drawings. The scope of this disclosure is limited only by the claims and covers many alternatives, modifications, and equivalents. Although the steps of various processes are presented in a given order, the embodiments are not necessarily limited to the listed order. In some embodiments, certain operations may be performed simultaneously in a sequence other than that described, or not at all.

[0023] Numerous specific details are set forth in the following description. These details are provided to facilitate a thorough understanding of the scope of this disclosure through specific examples, and to allow for the practice of embodiments according to the claims without some of these specific details. Therefore, the specific embodiments of this disclosure are illustrative and not intended to be exclusive or limiting. For clarity, technical materials known in the art related to this disclosure have not been described in detail so as not to unnecessarily obscure this disclosure.

[0024] Figure 1An example of a power semiconductor device 100 according to one embodiment is illustrated. The power device 100 may be a SiC MOSFET, such as 4H-SiC, formed on a SiC substrate having a hexagonal crystal structure. The power device 100 includes a heavily doped SiC substrate 102 having n-type conductivity and a lightly doped SiC layer 104 having n-type conductivity epitaxially grown on the substrate 102. A gate 106 is disposed above the upper surface of the n-layer 104 (or drift layer). In other words, the gate 106 is disposed on the front side of the power device 100. In one embodiment, the gate 106 comprises polysilicon. A gate insulating layer 108 is disposed between the gate 106 and the n-layer 104. In one embodiment, the gate insulating layer 108 is thermally grown silicon oxide, but in other embodiments it may be other dielectric materials, such as silicon nitride. A gate spacer 110 is formed on the gate 106 to protect the gate.

[0025] A P-well 112 is disposed in the upper portion of the n-layer 104 and overlaps with the gate 106 to define a channel region. In one embodiment, the P-well is a reverse well with a reverse doping profile, wherein a region 112a near the upper surface of the n-layer 104 is lightly doped, and a deeper region 112b within the P-well is heavily doped. As used herein, the upper surface of the n-layer 104 may be referred to as the surface of the n-layer 104 (or power device 100).

[0026] An n-type conductive source region 114 is formed on the surface of the power device 100 located in the P-well 112. The source region 114 overlaps with the gate 106, allowing them to be electrically coupled.

[0027] A p-type conductive pocket 116 is formed within a P-well 112 adjacent to the source region 114. In one embodiment, the pocket 116 extends vertically from at least the surface of the power device 100 into the heavily doped region 112b of the P-well. In one embodiment, the pocket 116 may have a halo shape when viewed from above. The pocket (P-pocket) 116 is heavily doped and serves as part of the hierarchical channel of the power device 100. In one embodiment, the P-pocket 116 is formed using an implantation method that does not utilize a tilt angle, which simplifies the implantation process, as will be explained later.

[0028] The channel region 118 of the power device 100 extends from the source region 114 to the n-layer 104 (or to the edge of the P-well 112). The channel region 118 is a hierarchical channel comprising a lightly doped region 112a of the P-well and a heavily doped P-capsule region 116. The dopant concentration of the heavily doped P-capsule region 116 may be 5 to 20 times that of the lightly doped region 112a. In one embodiment, the dopant concentration of the heavily doped P-capsule region 116 may be approximately 10 times that of the lightly doped region 112a.

[0029] The lower impurity concentration in this lightly doped region reduces the surface roughness at the interface (e.g., SiO2 / SiC interface) between the gate insulating layer 108 and the n-layer 104. This reduction in surface roughness increases carrier mobility in the channel and reduces the on-resistance of the power device. The reduced surface roughness also reduces threshold voltage instability caused by Coulomb scattering due to charge trapping at the interface region.

[0030] The hierarchical channel 118 (e.g., the P-cell region 116 located adjacent to the source region 114) helps control threshold voltage instability and punch-through effects. Therefore, threshold voltage variation can be minimized regardless of changes in local doping distribution, as explained later. Additionally, short channels can be used to achieve low on-resistance and C0. GS This will not result in a significant adverse short-channel effect.

[0031] See again Figure 1 A heavily doped body 120 with p-type conductivity is formed in the lower part of the P-well 112 and extends into the n-layer 104 below the P-well 112. The P-body 120 provides the power device 100 with enhanced non-clamping inductive switching capability.

[0032] A heavily doped barrier region 122 with p-type conductivity is formed on the upper surface adjacent to the source region 112. The barrier region 122 guides current to the hierarchical channel 118 and prevents the formation of parasitic transistors.

[0033] Drain contact metal 124 is formed on substrate 102 on the back side of power device 100. In embodiments, drain contact metal 124 comprises aluminum and may also comprise titanium, nickel and silver.

[0034] Figures 2-8 A process for manufacturing a SiC MOSFET according to one embodiment is illustrated. As those skilled in the art will understand, this manufacturing process can be applied to other types of power semiconductor devices, such as SiC IGBTs. Similarly, dimensions, dopant concentrations, materials used, types of dopants used, etc., are provided below for illustrative purposes and are not intended to limit the scope of the invention.

[0035] Figure 2 A substrate 200 according to one embodiment is shown. The substrate 200 includes a SiC substrate 202 heavily doped with n-type impurities or dopants. The SiC substrate 202 has a 4H hexagonal crystal structure, but may have other crystal structures depending on the specific embodiment. A SiC layer 204 is epitaxially grown on the SiC substrate 202. The SiC layer 204 is lightly doped with n-type impurities and prevents current flow until a voltage is applied to the power device 100. The SiC layer 204 may also be referred to as a drift layer or drift region.

[0036] A first buffer layer 206 is formed over the drift layer 204. In one embodiment, the first buffer layer 206 is a thermally grown oxide layer. The first buffer layer 206 has a sufficient thickness (e.g., about 300 angstroms to 1000 angstroms) to protect the drift layer 204 during subsequent etching processes. A second buffer layer 208 with a thickness of about 500 angstroms to 1500 angstroms is formed over the first buffer layer 206, and the second buffer layer serves as an endpoint detection layer during subsequent hard mask etching steps. In one embodiment, the second buffer layer 208 is a polysilicon layer.

[0037] Dashed line 210 illustrates a portion of a substrate 200 used to illustrate a manufacturing process according to one embodiment. (The text will use...) Figures 3 to 8 To describe the manufacturing process.

[0038] See Figure 3 A hard mask layer 210 is formed on top of the polysilicon buffer layer 208. In one embodiment, the hard mask layer 210 is an oxide grown using plasma-enhanced CVD. The hard mask layer 210 is etched to define a P-well region. A second buffer layer 208 beneath the hard mask layer 210 serves as an etch stop layer. The second buffer layer 208 is etched using a patterned hard mask 210.

[0039] P-type conductive dopants (or ions) are implanted through the first buffer layer 206 exposed by etching the second buffer layer 208 to form a reverse distribution and 5×10 17 / cm 3 Up to 5×10 18 / cm 3 The P-well 212 has a low doping concentration. In one specific embodiment, Al ions are implanted into the drift layer 204 using a relatively high implantation energy of about 450 keV to implant the ions deeply into the drift layer, for example, about 0.4 µm. This implantation forms an inverted doping distribution having a lightly doped region 212a near the surface and a heavily doped region 212b below it.

[0040] See Figure 4A first material layer 214 is deposited on the substrate. In one embodiment, the first material layer is polysilicon and is deposited to a thickness of approximately 0.2 µm to 0.6 µm. The first layer 214 is etched to form a first spacer 214a. In one embodiment, the first spacer 214a has a lateral dimension of approximately 0.2 µm to approximately 0.6 µm. A first buffer layer 206 protects the drift layer 204 during this etching step.

[0041] A heavily doped region 218 with p-type conductivity is formed by implanting p-type dopants (e.g., Al ions) into the P-well. A first spacer 214a prevents p-type dopants from being implanted beneath it, thus keeping this portion of the P-well 212 as a lightly doped region. In one embodiment, the implantation is a self-aligned implantation step performed without a tilt angle, which significantly simplifies the implantation process. Unlike implantation steps on silicon substrates, implantation on SiC substrates is typically performed at high temperatures while carefully monitoring the temperature. If a tilt angle is added, the device needs to be rotated during implantation, and the cables required for temperature monitoring during such implantation make the process challenging. Self-aligned implantation using the first spacer 214a eliminates the need to rotate the device while performing the implantation step.

[0042] In one embodiment, the implantation step is performed using Al ions at approximately 180 keV with a projected range of approximately 0.1 μm. The capsule region 218 may have a diameter of approximately 8 × 10⁻⁶. 17 / cm 3 The concentration of dopants.

[0043] See Figure 5 A second material layer 222 is deposited over the first spacer 214a. In one embodiment, the second material layer 222 is polysilicon and is deposited to a thickness of 0.1µm-0.3µm. The second layer 222 is etched to form the second spacer 222a. In one embodiment, the second spacer 222a has a lateral dimension of about 0.1µm to about 0.3µm. A second buffer layer 206 protects the drift layer 204 during this etching step.

[0044] A source region 226 with n-type conductivity is formed by implanting an n-type dopant into the P-well and region 218. In one embodiment, this implantation is performed using phosphorus ions with a projected range of about 0.1 μm at about 150 keV. Alternatively, in other embodiments, nitrogen ions or both phosphorus and nitrogen ions may be used. The source region 226 has a conductivity of about 1 × 10⁻⁶. 20 / cm 3 The concentration of dopants.

[0045] The second spacer 222a prevents n-type dopants from being implanted beneath it. Therefore, a portion of region 218 remains a heavily doped p-type region. This remaining portion is referred to as capsule region 218a (or P-capsule region). The heavily doped P-capsule region 218a and the lightly doped region 212a define a hierarchical channel 220 that allows for a shorter channel length without the problems associated with short-channel effects. The P-capsule region 218a helps control threshold voltage instability, which can be caused by variations in dopant distribution from etching and multiple implantation steps. In one embodiment, the P-capsule region 218a has a halo shape when viewed from above.

[0046] See Figure 6 A third material layer 228 is deposited on top of the second spacer 222a. In one embodiment, the third layer 228 is polysilicon and is deposited to a thickness of 0.2µm-0.6µm. The third layer 228 is etched to form the third spacer 228a. A second buffer layer 206 protects the drift layer 204 during this etching step.

[0047] A p-type conductive body 232 (or P-body) is formed by implanting p-type dopant through the P-well 212. In one embodiment, this implantation is performed using aluminum ions at approximately 450 keV with a projected range of approximately 0.4 μm. The P-body 232 is disposed below the source region 226 and extends vertically below the P-well 212. The P-body 232 has a diameter of approximately 3 × 10⁻⁶. 18 / cm 3 The concentration of dopants.

[0048] See Figure 7 The hard mask 210, as well as the first spacer 214a, the second spacer 222a, and the third spacer 228a, are removed. The remaining second buffer layer 206 is also removed.

[0049] A photoresist layer 236 is deposited and patterned to define a blocking region 234 with p-type conductivity, such that a source region 226 is disposed between the hierarchical channel 220 and the blocking region 234. In one embodiment, aluminum ions are implanted into the blocking region 234, and the photoresist layer 236 is thick enough to serve as an implantation mask.

[0050] High-temperature annealing (HTA) is performed to activate the dopants implanted into the substrate. In one embodiment, HTA is performed at approximately 1650 degrees Celsius and after a graphite coating (not shown) has been formed over the substrate. This graphite coating serves to prevent the SiC material from evaporating during HTA. The graphite coating is removed after HTA.

[0051] In one implementation, a JFET engineering process may optionally be performed to reduce the effective channel length of the power device (e.g., a SiC MOSFET). For example, an n-type dopant, such as nitrogen ions, may be implanted near the surface (or front side) of the MOSFET. Multiple implantations of the dopant may be performed using approximately 30 keV, approximately 140 keV, approximately 230 keV, and approximately 430 keV, providing approximately 1 × 10⁻⁶ Ω for each region. 17 / cm 3 The doping concentration. In one embodiment, the JFET engineering process is performed after the removal of the hard mask 210 and before the HTA.

[0052] See Figure 8 A gate insulating layer 238 is formed on the drift layer 204 on the front side of the substrate. In one embodiment, the gate insulating layer 238 is a thermally grown oxide. A gate material is deposited and patterned to form a gate 240. In one embodiment, the gate material is polysilicon. Gate spacers 242 are formed to protect the gate 240.

[0053] The power semiconductor device formed according to one implementation scheme can be a SiC MOSFET, etc. Figure 1 An example of this type of power device is shown.

[0054] Examples of embodiments in the form of claims

[0055] A1. A method for forming a power semiconductor device, the method comprising:

[0056] A silicon carbide layer providing the first conductivity;

[0057] A reverse well with a second conductivity is formed, the reverse well having a lightly doped region near the surface of the silicon carbide layer and a heavily doped region disposed below the lightly doped region;

[0058] A capsule region exhibiting the second conductivity is formed within the retrograde well, the capsule region being a heavily doped region; and

[0059] A gate is formed on the surface of the silicon carbide layer.

[0060] A2. The method of claim A1, wherein the capsule region and the lightly doped region of the reverse well define a hierarchical channel for the power semiconductor device.

[0061] A3. The method according to claim A2, further comprising:

[0062] A first material layer is deposited on the silicon carbide layer; and

[0063] Patterning the first material layer to obtain the first spacer.

[0064] The capsule region is formed by injecting the first dopant with the second conductivity into the reverse well using the first spacer as an injection mask.

[0065] A4. The method of claim A3, wherein the first spacer prevents the first dopant from being injected into a portion of the lightly doped region of the retrograde well, and the first dopant is injected into the retrograde well without an injection tilt angle.

[0066] A5. The method according to claim A4, further comprising:

[0067] A hard mask layer is deposited on the silicon carbide layer; and

[0068] Pattern the hard mask layer,

[0069] The first material layer is deposited on the patterned hard mask layer, and the first spacer is disposed on the sidewall of the patterned hard mask layer.

[0070] A6. The method of claim A5, wherein the first spacer has a lateral dimension of about 0.2 µm to about 0.6 µm.

[0071] A7. The method according to claim A1, wherein the power semiconductor device is a MOSFET.

[0072] A8. The method according to claim A1, wherein the cyst region has a halo shape when viewed from above.

[0073] A9. The method according to claim A1, wherein the dopant concentration of the capsule region is at least 5 times the dopant concentration of the lightly doped region.

[0074] Various aspects of this disclosure have been described together with specific embodiments presented as examples. Many substitutions, modifications, and variations can be made to the embodiments described herein without departing from the scope of the claims below. For example, the power device may have a metal pattern of different thickness on the front side and another metal pattern of different thickness on the back side to enable lifetime control processing from both sides. Therefore, the embodiments described herein are intended to be illustrative rather than restrictive.

Claims

1. A power semiconductor device, comprising: Semiconductor substrate; A first conductive drift layer disposed on a first side of the semiconductor substrate; A gate disposed above the drift layer; as well as A hierarchical channel, the hierarchical channel including a lightly doped region of second conductivity and a heavily doped capsule region of second conductivity, the heavily doped capsule region extending vertically from the upper surface adjacent to the semiconductor substrate to the second heavily doped region of second conductivity located below the lightly doped region and the heavily doped capsule region.

2. The power semiconductor device according to claim 1, further comprising: The source region is disposed on the first side of the semiconductor substrate, and the heavily doped capsule region is disposed between the source region and the lightly doped region.

3. The power semiconductor device according to claim 2, wherein, The source region is positioned above and in contact with the heavily doped region.

4. The power semiconductor device according to claim 2, further comprising a drain electrode disposed on a second side of the semiconductor substrate, wherein, The power semiconductor device is a MOSFET.

5. The power semiconductor device according to claim 1, wherein, In the top view, the heavily doped capsule region has a halo-like shape.

6. The power semiconductor device according to claim 1, wherein, The lightly doped region has a first dopant concentration, and the heavily doped capsule region has a second dopant concentration, wherein the second dopant concentration is at least 5 times the first dopant concentration.

7. The power semiconductor device according to claim 1, wherein, The first conductivity is N-type conductivity, and the second conductivity is P-type conductivity.

8. The power semiconductor device according to claim 1, wherein, The lightly doped region is disposed between the heavily doped capsule region and a portion of the drift layer.

9. A method for forming a power semiconductor device, comprising: Provides a semiconductor layer; A first conductive drift layer is formed on the first side of the semiconductor layer; A heavily doped region with a second conductivity is formed, wherein the type of the first conductivity is different from the type of the second conductivity; A hierarchical channel with second conductivity is formed above the heavily doped region. The hierarchical channel includes a lightly doped region and a capsule region. The capsule region is a heavily doped region that extends vertically through the lightly doped region and downwards to the heavily doped region. as well as A gate is formed on the drift layer.

10. The method of claim 9, further comprising: A source region is formed, wherein the capsule region is disposed between the source region and the lightly doped region.

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