Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate; a lower channel pattern on the surface of the substrate; the upper channel pattern is positioned on the lower channel pattern; a gate structure extending around the lower channel pattern and the upper channel pattern; a lower source / drain pattern on a sidewall of the lower channel pattern; an upper source / drain pattern on a sidewall of the upper channel pattern; a connection electrode electrically connecting the first upper source / drain pattern to the first lower source / drain pattern; and a protection pattern between the gate structure and the connection electrode, in which the protection pattern includes a first protection pattern and a second protection pattern on the first protection pattern, and the second protection pattern includes an insulating material having a dielectric constant less than a dielectric constant of the first protection pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] A semiconductor is a material whose conductivity falls between that of a conductor and a non-conductor, and specifically, a material that conducts electricity under certain conditions. Various semiconductor devices can be manufactured using these semiconductor materials; for example, memory devices can be produced. These semiconductor devices can be used in a wide variety of electronic devices.

[0003] With the gradual development of the electronics industry, the performance requirements for semiconductor devices are also increasing. For example, there are growing demands for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these requirements, the internal structure of semiconductor devices is becoming increasingly complex, and their integration density is increasing. Summary of the Invention

[0004] This disclosure attempts to provide a semiconductor device with improved electrical properties and a method for manufacturing the semiconductor device.

[0005] The effects of the present invention are not limited to those described above, and those skilled in the art will clearly understand from the following description other effects not mentioned.

[0006] Some embodiments of this disclosure provide a semiconductor device comprising: a substrate; a lower channel pattern located on a surface of the substrate; an upper channel pattern located on the lower channel pattern; a gate structure extending around the lower channel pattern and the upper channel pattern; a lower source / drain pattern located on a sidewall of the lower channel pattern; an upper source / drain pattern located on a sidewall of the upper channel pattern; a connection electrode electrically connecting a first upper source / drain pattern in the upper source / drain pattern to a first lower source / drain pattern in the lower source / drain pattern; and a protective pattern located between the gate structure and the connection electrode, wherein the protective pattern includes a first protective pattern and a second protective pattern located on the first protective pattern, and the second protective pattern includes a second insulating material having a second dielectric constant having a first dielectric constant less than that of a first insulating material of the first protective pattern.

[0007] Other embodiments of this disclosure provide a semiconductor device comprising: a substrate; a lower channel pattern located on a surface of the substrate; an upper channel pattern located above the lower channel pattern; a gate structure extending around the lower channel pattern and the upper channel pattern; a lower source / drain pattern located on a sidewall of the lower channel pattern; an upper source / drain pattern located on a sidewall of the upper channel pattern; a connection electrode electrically connecting a first upper source / drain pattern in the upper source / drain pattern to a first lower source / drain pattern in the lower source / drain pattern; and a protective pattern located between a first portion of a side surface of the gate structure and the connection electrode, wherein a first air gap is located between the connection electrode and a second portion of the side surface of the gate structure.

[0008] Other embodiments of this disclosure provide a semiconductor device comprising: a substrate; a lower channel pattern located on a surface of the substrate; an upper channel pattern located above the lower channel pattern; an intermediate insulating pattern located between the upper channel pattern and the lower channel pattern; a gate structure extending around the lower channel pattern and the upper channel pattern; a gate spacer located on a portion of a side surface of the gate structure; a lower source / drain pattern located on a sidewall of the lower channel pattern; an upper source / drain pattern located on a sidewall of the upper channel pattern; and a connection electrode extending in a first direction perpendicular to the surface of the substrate to... The upper source / drain pattern includes a first upper source / drain pattern and has an end electrically connected to a first lower source / drain pattern in the lower source / drain pattern; an upper contact electrode located on the upper surface of a second upper source / drain pattern in the upper source / drain pattern, the second upper source / drain pattern being adjacent to the first upper source / drain pattern and extending into the second upper source / drain pattern; and a protective pattern located between the gate spacer and the connection electrode and between the gate spacer and the upper contact electrode, wherein the protective pattern includes a first protective pattern and a second protective pattern located on the first protective pattern, the second protective pattern including an insulating material having a dielectric constant smaller than that of the first protective pattern.

[0009] A semiconductor device according to some embodiments may include a protective pattern between a gate structure and a connection electrode, and at least a portion of the protective pattern may include a low-k dielectric material. The semiconductor device according to embodiments may include an air gap between two source / drain patterns arranged upwards and downwards.

[0010] According to some embodiments, the parasitic capacitance inside a semiconductor device can be reduced, thereby improving the electrical characteristics of the semiconductor device. Attached Figure Description

[0011] Figure 1 This is a top view showing a semiconductor device according to some embodiments.

[0012] Figure 2 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram.

[0013] Figure 3 yes Figure 2 An enlarged cross-sectional view of region "A" in the image.

[0014] Figure 4 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I2-I2' in the diagram.

[0015] Figure 5 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I3-I3' in the diagram.

[0016] Figure 6 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I4-I4' in the diagram.

[0017] Figure 7 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram.

[0018] Figure 8 yes Figure 7 An enlarged cross-sectional view of region "A" in the image.

[0019] Figure 9 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram.

[0020] Figure 10 yes Figure 9 An enlarged cross-sectional view of region "A" in the image.

[0021] Figure 11 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram.

[0022] Figure 12 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I2-I2' in the diagram.

[0023] Figure 13 yes Figure 11 An enlarged cross-sectional view of region "B" in the image.

[0024] Figures 14 to 49 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0025] In the following detailed description, certain embodiments of this disclosure are illustrated and described by way of example only. This disclosure can be implemented in various ways and is not limited to the following embodiments.

[0026] The accompanying drawings and descriptions are intended to be illustrative rather than restrictive. Throughout the specification, similar reference numerals denote similar elements.

[0027] Furthermore, for ease of understanding and description, the dimensions and thicknesses of each configuration shown in the accompanying drawings are arbitrary, but this disclosure is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of understanding and description.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is referred to as "on another element," it can be directly "on another element," or there may be intermediate elements present. In contrast, when an element is referred to as "directly on another element," there are no intermediate elements present.

[0029] Furthermore, unless there is an explicit description to the contrary, the term "comprise" and its variations (such as "comprises" or "comprising") should be understood as indicating that the said element is included, but not excluding any other element.

[0030] Furthermore, throughout the instruction manual, when "on a plane" is mentioned, it means viewing the target component from above, while when "on a cross section" is mentioned, it means viewing the cross section obtained by vertically cutting the target component from the side.

[0031] Furthermore, throughout the specification, two directions parallel to and intersecting the upper surface of the substrate are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is defined as the third direction D3. In one example, the first direction D1 and the second direction D2 may be orthogonal to each other and / or intersect each other.

[0032] In the following text, reference will be made to Figures 1 to 6 Semiconductor devices according to some embodiments of this disclosure are described. Specifically, Figure 1 This is a top view illustrating a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram. Figure 3 yes Figure 2 An enlarged cross-sectional view of region "A" in the image. Figure 4 It is along Figure 1 A cross-sectional view of the semiconductor device taken by line I2-I2' in the diagram. Figure 5 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I3-I3' in the diagram, and Figure 6 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I4-I4' in the diagram.

[0033] See Figures 1 to 6 According to some embodiments, a semiconductor device may include a substrate 101, a lower channel pattern 140A on the substrate 101, an upper channel pattern 140B on the lower channel pattern 140A, a gate structure 160 extending around or around the lower channel pattern 140A and the upper channel pattern 140B, a lower source / drain pattern 150A on the opposite side of the lower channel pattern 140A, an upper source / drain pattern 150B on the opposite side of the upper channel pattern 140B, a connection electrode 199 connecting the upper source / drain pattern 150B and the lower source / drain pattern 150A, and a protective pattern 187 located between the gate structure 160 and the connection electrode 199.

[0034] The substrate 101 may be silicon-on-insulator (SOI) or bulk silicon. In some embodiments, the substrate 101 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0035] Substrate 101 may include an upper surface and a lower surface. The upper and lower surfaces of substrate 101 may be formed as planes parallel to a first direction D1 and a second direction D2 intersecting the first direction D1. The upper surface of substrate 101 may be a surface opposite to the lower surface of substrate 101 in a third direction D3. The upper surface of substrate 101 may be referred to as the front side. The lower surface of substrate 101 may be referred to as the back side.

[0036] The semiconductor device according to the embodiments may further include an active pattern 105 disposed on the substrate 101. The active pattern 105 may be grown from the substrate 101 by an epitaxial growth method, or may be formed by etching a portion of the substrate 101. In some embodiments, the active pattern 105 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In some embodiments, the active pattern 105 may include a compound semiconductor. The side surfaces of the active pattern 105 may be covered by or overlap with the field insulating layer 107 described below.

[0037] The active pattern 105 may protrude from the upper surface of the substrate 101 in a third direction D3. The active pattern 105 may extend in a first direction D1. (See reference) Figure 2 , Figure 4 and Figure 6 The active pattern 105 may be located below the source / drain pattern 150. The active pattern 105 may overlap with the source / drain pattern 150 on a third-direction D3. The active pattern 105 may also be located below the gate structure 160 and / or the channel pattern 140. The active pattern 105 may overlap with the gate structure 160 and / or the channel pattern 140 on a third-direction D3. The height of the active pattern 105 protruding on the third-direction D3 may vary depending on its position. For example, the height of the active pattern 105 overlapping the source / drain pattern 150 on the third-direction D3 may be lower than the height of the active pattern 105 overlapping the gate structure 160 and / or the channel pattern 140 on the third-direction D3. However, this disclosure is not limited thereto, and the active pattern 105 may have a constant height.

[0038] The semiconductor device according to the embodiments may include at least one transistor structure. For example, the semiconductor device according to the embodiments may include a first transistor structure and a second transistor structure, the first transistor structure including a plurality of lower channel patterns 140A and the second transistor structure including a plurality of upper channel patterns 140B. The first transistor structure and the second transistor structure according to the embodiments may be formed as a gate-all-around field-effect transistor (GAAFET) structure, such as a multi-bridge channel field-effect transistor (MBCFETTM), wherein, in a planar view, the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B are surrounded by a gate structure 160. That is, the gate structure 160 may extend around the plurality of upper channel patterns 140B.

[0039] According to the embodiments, the first and second transistor structures can be formed as a three-dimensional stacked FET (3DSFET) structure stacked on the third-direction D3. In this case, the first transistor structure can be either an N-type MOSFET or a P-type MOSFET, while the second transistor structure can be either a P-type MOSFET or an N-type MOSFET. In the embodiments, the first and second transistor structures can be N-type MOSFETs and P-type MOSFETs, respectively, but are not limited thereto. Hereinafter, the case where a plurality of lower channel patterns 140A and a plurality of upper channel patterns 140B are stacked on the third-direction D3 to form a 3D-SFET structure will be described. However, this disclosure is not limited to this case.

[0040] Multiple channel patterns 140 may be located on substrate 101. In an embodiment, the multiple channel patterns 140 may include multiple lower channel patterns 140A located on substrate 101 and multiple upper channel patterns 140B located on the multiple lower channel patterns 140A.

[0041] Multiple lower trench patterns 140A may be located on the upper surface of the substrate 101. The multiple lower trench patterns 140A may be spaced apart from each other in a third direction D3. Here, the third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 may be the thickness direction of the substrate 101.

[0042] In an embodiment, such as Figure 5 As shown, the widths of the plurality of lower channel patterns 140A in the second direction D2 can be substantially the same. In some embodiments, the widths of the plurality of lower channel patterns 140A in the second direction D2 can decrease as the distance from the upper surface of the substrate 101 increases. Figure 2 As shown, the widths of the plurality of lower channel patterns 140A in the first direction D1 can be substantially the same. In some embodiments, the widths of the plurality of lower channel patterns 140A in the first direction D1 can decrease as the distance from the upper surface of the substrate 101 increases.

[0043] Multiple upper channel patterns 140B can be located on multiple lower channel patterns 140A. Specifically, the multiple upper channel patterns 140B can be configured to be spaced apart from the multiple lower channel patterns 140A on a third direction D3. For example, as Figure 2 and Figure 5 As shown, the intermediate insulation pattern 181, described later, can be located on a plurality of lower channel patterns 140A, and a plurality of upper channel patterns 140B can be located on the intermediate insulation pattern 181. The upper channel patterns 140B can be configured to be spaced apart from the plurality of lower channel patterns 140A by the intermediate insulation pattern 181 in the third direction D3. The plurality of upper channel patterns 140B can be configured to be spaced apart from each other in the third direction D3.

[0044] In an embodiment, such as Figure 5 As shown, the widths of the plurality of upper channel patterns 140B in the second direction D2 can be substantially the same. In some embodiments, the widths of the plurality of upper channel patterns 140B in the second direction D2 can decrease as the distance from the upper surface of the substrate 101 increases. Figure 2 As shown, the widths of the plurality of upper channel patterns 140B in the first direction D1 can be substantially the same. In some embodiments, the widths of the plurality of upper channel patterns 140B in the first direction D1 can decrease as the distance from the upper surface of the substrate 101 increases.

[0045] The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B can be multi-channel active patterns. In an embodiment, the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B can have a nanosheet shape and can be semiconductor patterns comprising semiconductor material.

[0046] Multiple lower channel patterns 140A and multiple upper channel patterns 140B can be formed by etching portions of substrate 101, or can include epitaxial layers grown from substrate 101. The multiple lower channel patterns 140A and multiple upper channel patterns 140B can include elemental semiconductor materials, such as silicon (Si) or germanium (Ge). Furthermore, the multiple lower channel patterns 140A and multiple upper channel patterns 140B can include compound semiconductors, such as group IV-IV compound semiconductors or group III-V compound semiconductors.

[0047] IV-IV compound semiconductors can be binary or ternary compounds, for example, comprising at least two of carbon (C), silicon (Si), germanium (Ge), and / or tin (Sn).

[0048] III-V compound semiconductors can be, for example, binary, ternary, or quaternary compounds, which are composed of at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) combined with one of the group V elements phosphorus (P), arsenic (As), and / or antimony (Sb).

[0049] In one embodiment, the plurality of channel patterns 140 may include silicon (Si). As another example, the plurality of channel patterns 140 may include silicon germanium (SiGe).

[0050] exist Figure 2 and / or Figure 5In the illustration, two lower channel patterns 140A and two upper channel patterns 140B are shown stacked spaced apart along a third direction D3, but this is for ease of description only and the disclosure is not limited thereto. For example, three or more lower channel patterns 140A and / or three or more upper channel patterns 140B may be stacked while being spaced apart along a third direction D3. In some embodiments, one lower channel pattern 140A and / or one upper channel pattern 140B may be stacked while being spaced apart along a third direction D3.

[0051] The semiconductor device according to the embodiment may further include an intermediate insulating pattern 181. The intermediate insulating pattern 181 may be located on a plurality of lower channel patterns 140A. The intermediate insulating pattern 181 may be disposed between the uppermost lower channel pattern 140A and the lowermost upper channel pattern 140B. In addition, the intermediate insulating pattern 181 may be disposed between the uppermost lower gate structure 160A and the lowermost upper gate structure 160B.

[0052] The intermediate insulating pattern 181 may include multiple layers. (See reference) Figure 2 and Figure 5 The intermediate insulation pattern 181 may include a first intermediate insulation pattern 181A, a second intermediate insulation pattern 181B located on the first intermediate insulation pattern 181A, and a third intermediate insulation pattern 181S located between the first intermediate insulation pattern 181A and the second intermediate insulation pattern 181B.

[0053] In one embodiment, the widths of the second intermediate insulating pattern 181B and the third intermediate insulating pattern 181S in the first direction D1 may be substantially the same. In another embodiment, the width of the first intermediate insulating pattern 181A in the first direction D1 may be greater than the widths of the second intermediate insulating pattern 181B and the third intermediate insulating pattern 181S in the first direction D1. However, this disclosure is not limited thereto, and the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S may have substantially the same width in the first direction D1.

[0054] The intermediate insulation pattern 181 may include various insulating materials. For example, the intermediate insulation pattern 181 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The intermediate insulation pattern 181 may space a plurality of lower channel patterns 140A and a plurality of upper channel patterns 140B apart from each other.

[0055] In an embodiment, the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B may include the same insulating material, while the third intermediate insulating pattern 181S may include an insulating material different from the other two intermediate insulating patterns 181A and 181B. However, this disclosure is not limited thereto, and the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S may also include the same insulating material. In this case, the boundary between the third intermediate insulating pattern 181S and the first intermediate insulating pattern 181S, as well as the boundary between the third intermediate insulating pattern 181A and the second intermediate insulating pattern 181B, may not be visually identifiable.

[0056] and Figure 2 and Figure 5 As shown, the intermediate insulation pattern 181 can be formed as a single layer. Even in this case, the multiple upper channel patterns 140B and the multiple lower channel patterns 140A can be spaced apart from each other by the intermediate insulation pattern 181.

[0057] The semiconductor device according to the embodiment may further include a field insulating layer 107 located on the substrate 101. The field insulating layer 107 may cover at least a portion of the side surface of the active pattern 105 or overlap with at least a portion of the side surface of the active pattern 105. For example, as Figures 4 to 6 As shown, the field insulating layer 107 may cover at least a portion of the side surface of the active pattern 105 or overlap with at least a portion of the side surface of the active pattern 105. A portion of the side surface of the active pattern 105 may be covered by or overlap with the field insulating layer 107, and the remaining portion of the side surface of the active pattern 105 may be covered by or overlap with the gate structure 160. Although Figure 5 The illustration shows a field insulating layer 107 covering or overlapping a portion of the side surface of the active pattern 105, with the remaining portion covered or overlapping the gate structure 160; however, this disclosure is not limited thereto. For example, the field insulating layer 107 may cover or overlap the entire side surface of the active pattern 105. The field insulating layer 107 may overlap the active pattern 105 in the second direction D2. The field insulating layer 107 may not be disposed on the upper surface of the active pattern 105.

[0058] The field insulating layer 107 may include, for example, an oxide film, a nitride film, an oxide oxynitride film, or a combination thereof. The field insulating layer 107 is shown as a single-layer film, but this is for illustrative purposes only, and the present disclosure is not limited thereto.

[0059] Gate structure 160 may be located on pattern 105. Gate structure 160 may extend in a second direction D2. Gate structures 160 may be spaced apart from each other in a first direction D1. Gate structure 160 may be located on active pattern 105. Gate structure 160 may intersect with active pattern 105. Gate structure 160 may surround each of a plurality of channel patterns 140.

[0060] In an embodiment, the first transistor structure and the second transistor structure can be configured to share a single gate structure 160. Specifically, the first transistor structure may include a plurality of lower channel patterns 140A, a gate structure 160 surrounding the plurality of lower channel patterns 140A, and a lower source / drain pattern 150A connected to the plurality of lower channel patterns 140A on one side of the gate structure 160. The second transistor structure may include a plurality of upper channel patterns 140B, a gate structure 160 extending around the plurality of upper channel patterns 140B, and an upper source / drain pattern 150B connected to the plurality of upper channel patterns 140B on one side of the gate structure 160. In this case, as shown... Figure 5 As shown, a gate structure 160 extends around or around a plurality of lower channel patterns 140A and a plurality of upper channel patterns 140B, such that the first transistor structure and the second transistor structure can share a gate structure 160.

[0061] The gate structure 160 may include a lower gate structure 160A, an upper gate structure 160B, and a main gate structure 160M. The lower gate structure 160A may be located between a plurality of adjacent lower channel patterns 140A on the third-direction D3, between the substrate 101 and the lowermost lower channel pattern 140A, and between the uppermost lower channel pattern 140A and the intermediate insulating pattern 181. The upper gate structure 160B may be located between a plurality of adjacent upper channel patterns 140B on the third-direction D3, and between the lowermost upper channel pattern 140B and the intermediate insulating pattern 181. The main gate structure 160M may be disposed on the uppermost upper channel pattern 140B.

[0062] The lower gate structure 160A may be adjacent to the lower source / drain pattern 150A, which will be described later. The upper gate structure 160B may be adjacent to the upper source / drain pattern 150B, which will be described later. The main gate structure 160M may be located on the lower gate structure 160A, the upper gate structure 160B, and a plurality of upper channel patterns 140B.

[0063] According to an embodiment, the lower gate structure 160A and the upper gate structure 160B can be stacked alternately with a plurality of channel patterns 140. (See reference...) Figure 2 and Figure 5The lower gate structure 160A and multiple lower channel patterns 140A can be stacked alternately. Although Figure 2 and Figure 5 Three lower gate structures 160A and two lower channel patterns 140A are shown stacked alternately, but the number of alternately stacked lower gate structures 160A and lower channel patterns 140A is not limited. (Reference) Figure 2 and Figure 5 The upper gate structure 160B and multiple upper channel patterns 140B can be stacked alternately. Although Figure 2 and Figure 5 Two upper gate structures 160B and two lower channel patterns 140B are shown stacked alternately, but the number of alternating upper gate structures 160B and the number of upper channel patterns 140B are not limited.

[0064] Each of the lower gate structure 160A and the upper gate structure 160B may include gate electrodes 165A and 165B and gate insulating films 162A and 162B.

[0065] Gate electrodes 165A and 165B may be located on active pattern 105. For example, lower gate electrode 165A may be located on active pattern 105, and upper gate electrode 165B may be located on lower gate electrode 165A. Gate electrodes 165A and 165B may intersect with active pattern 105. For example, active pattern 105 may extend in a first direction D1, and gate electrodes 165A and 165B may extend in a second direction D2. In a plan view, gate electrodes 165A and 165B may extend around or around multiple channel patterns 140. For example, in a plan view, lower gate electrode 165A may extend around or around multiple lower channel patterns 140A, and upper gate electrode 165B may extend around or around multiple upper channel patterns 140B.

[0066] Furthermore, at least some of the gate electrodes 165A and 165B may be located between multiple channel patterns 140. For example, the lower gate electrode 165A may be disposed between multiple lower channel patterns 140A, and the upper gate electrode 165B may be disposed between multiple upper channel patterns 140B.

[0067] Gate electrodes 165A and 165B may include conductive materials. Gate electrodes 165A and 165B may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and / or conductive metal oxide nitride. Gate electrodes 165A and 165B may include, for example, titanium nitride (TiN), titanium carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten. The conductive metal oxide and conductive metal nitride may include, but are not limited to, at least one of the above-mentioned materials, such as W, aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof. The conductive metal oxide and conductive metal nitride may include, but are not limited to, the oxides of the above-mentioned materials. Gate electrodes 165A and 165B may include the same material, but are not limited to, and gate electrodes 165A and 165B may also include different materials.

[0068] Gate insulating films 162A and 162B may be disposed along the periphery of the plurality of channel patterns 140. For example, the lower gate insulating film 162A may be disposed along the periphery of each of the plurality of lower channel patterns 140A, and the upper gate insulating film 162B may be disposed along the periphery of each of the plurality of upper channel patterns 140B. The lower gate insulating film 162A may be disposed along the upper surface of the active pattern 105 overlapping the gate structure 160 on the third direction D3.

[0069] The lower gate insulating film 162A can be in direct contact with the active pattern 105, the plurality of lower channel patterns 140A, and the first intermediate insulating pattern 181A. The upper gate insulating film 162B can be in direct contact with the plurality of upper channel patterns 140B and the second intermediate insulating pattern 181B. The gate insulating films 162A and 162B can be located between the plurality of channel patterns 140 and the gate electrodes 165A and 165B. The gate insulating films 162A and 162B can include various insulating materials.

[0070] In the embodiments, gate insulating films 162A and 162B are shown as single-layer films, but are not limited thereto. For example, gate insulating films 162A and 162B may be multilayer films comprising silicon oxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material may include materials having a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (Al2O3), or tantalum oxide (TaO).

[0071] The main gate structure 160M can be located on the upper gate structure 160B and multiple upper channel patterns 140B. The main gate structure 160M can be disposed on the upper surface of the uppermost upper channel pattern 140B among the multiple upper channel patterns 140B.

[0072] The main gate structure 160M may include a main gate electrode 165M and a main gate insulating film 162M.

[0073] The main gate electrode 165M can be located on the upper gate structure 160B and the plurality of upper channel patterns 140B. The main gate electrode 165M can be disposed on the upper surface of the uppermost upper channel pattern 140B among the plurality of upper channel patterns 140B. Therefore, in a cross-sectional view, the four sides of the plurality of channel patterns 140B can be surrounded by the gate electrodes 165A and 165B and the main gate electrode 165M. The main gate electrode 165M can include the same conductive material as the gate electrodes 165A and 165B. For example, the main gate electrode 165M can include at least one of metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide and / or conductive metal oxynitride.

[0074] The main gate insulating film 162M may extend along one side of the main gate electrode 165M. The main gate insulating film 162M may extend along the gate spacer 164 described below. The main gate insulating film 162M may include various insulating materials.

[0075] In this embodiment, the main gate insulating film 162M is shown as a single-layer film, but is not limited thereto. For example, the main gate insulating film 162M may be made of a multilayer film comprising silicon oxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material may include materials having a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (Al2O3), or tantalum oxide (TaO).

[0076] The semiconductor device according to the embodiment may further include a gate spacer 164 and a capping layer 166.

[0077] The capping layer 166 may be located on the main gate structure 160M. The upper surface of the capping layer 166 may be on the same plane as the upper surface of the upper contact electrode 191, which will be described later. The opposite side surface of the capping layer 166 may contact the gate spacer 164. Unlike the illustration, the capping layer 166 may cover the upper surface of the gate spacer 164 or overlap with the upper surface of the gate spacer 164.

[0078] The capping layer 166 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. The capping layer 166 may include a material that has etch selectivity relative to the second interlayer insulating layer 173 described below.

[0079] Gate spacer 164 may be located on the side of the main gate electrode 165M. In an embodiment, gate spacer 164 may also be disposed on the side surface of capping layer 166. Gate spacer 164 may not be disposed on the side surfaces of the lower gate electrode 165A and the upper gate electrode 165B. Gate spacer 164 may not be disposed on the side surface of each of the lower channel pattern 140A and the upper channel pattern 140B. Gate spacer 164 may not be disposed between the active pattern 105 and the channel patterns 140A and 140B. Gate spacer 164 may not be disposed between a plurality of adjacent channel patterns 140A and 140B on a third-direction D3. Although gate spacer 164 is shown as a single-layer film, this is only for the purpose of description, and the present disclosure is not limited thereto.

[0080] The gate spacer 164 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride oxynitride (SiOBN), silicon oxycarbonate (SiOC), and / or combinations thereof. Although the gate spacer 164 is shown as a monolayer film, this is only for the purpose of description, and the present disclosure is not limited thereto.

[0081] Source / drain patterns 150 may be located on at least one side of gate structure 160. For example, source / drain patterns 150 may be located on opposite sides of gate structure 160. For example, each source / drain pattern 150 may be located between two gate structures 160 arranged to be spaced apart from each other in a first direction D1. Source / drain patterns 150 may be located on active pattern 105. Source / drain patterns 150 may contact the side surfaces of a plurality of channel patterns 140. Source / drain patterns 150 may be connected to a plurality of channel patterns 140. According to an embodiment, source / drain patterns 150 may include a lower source / drain pattern 150A and an upper source / drain pattern 150B.

[0082] Lower source / drain patterns 150A may be located on active patterns 105. The lower surface of each lower source / drain pattern 150A may contact the upper surface of active patterns 105. Lower source / drain patterns 150A may be located on at least one side of lower gate structures 160A. For example, lower source / drain patterns 150A may be located on opposite sides of lower gate structures 160A. For example, each lower source / drain pattern 150A may be located between two lower gate structures 160A arranged to be spaced apart from each other in a first direction D1. Lower source / drain patterns 150A may be connected to a plurality of lower channel patterns 140A.

[0083] The lower source / drain pattern 150A can be an epitaxial pattern formed by a selective epitaxial growth process using a portion of the active pattern 105 and multiple lower channel patterns 140A as seeds. The lower source / drain pattern 150A can be used as the source / drain of a first transistor structure that utilizes multiple lower channel patterns 140A as the channel region.

[0084] The lower source / drain pattern 150A may include a semiconductor material. The lower source / drain pattern 150A may include, for example, silicon (Si) or germanium (Ge). Furthermore, the lower source / drain pattern 150A may include, for example, at least two or more binary or ternary compounds selected from carbon (C), silicon (Si), germanium (Ge), and / or tin (Sn). For example, the lower source / drain pattern 150A may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but is not limited thereto. In embodiments, the lower source / drain pattern 150A is shown as a single layer, but is not limited thereto, and the lower source / drain pattern 150A may be formed of two or more layers. For example, the lower source / drain pattern 150A may include a first layer and a second layer, the first layer being conformally disposed in a recess region defined by the side surfaces of the lower channel pattern 140A and the lower gate structure 160A and the upper surface of the active pattern 105, and the second layer filling the recess region located above the first layer. In this case, the concentrations of silicon (Si) or germanium (Ge) included in the first and second layers can be different from each other. For example, the concentration of germanium (Ge) included in the first layer can be greater than the concentration of germanium (Ge) included in the second layer.

[0085] In this embodiment, the lower source / drain pattern 150A may be doped with impurities. For example, when the first transistor structure is a P-type MOSFET, the lower source / drain pattern 150A may include P-type impurities. For example, the lower source / drain pattern 150A may include boron (B), aluminum (Al), gallium (Ga), or a combination thereof.

[0086] The semiconductor device according to an embodiment may further include a dummy semiconductor pattern 143 located below the lower source / drain pattern 150A. The dummy semiconductor pattern 143 may be configured to connect the lower source / drain pattern 150A to wiring. For example, when the semiconductor device according to an embodiment includes wiring disposed below the substrate 101, at least a portion of the dummy semiconductor pattern 143 may be disposed between the lower source / drain pattern 150A and the wiring below the substrate 101 to connect the lower source / drain pattern 150A and the wiring below the substrate 101. Figure 2 As shown in the diagram, the dummy semiconductor pattern 143 may not be located below some of the lower source / drain patterns 150A.

[0087] refer to Figure 4 The dummy semiconductor pattern 143 can extend towards the upper surface of the substrate 101 from within the active pattern 105. The lower surface of the dummy semiconductor pattern 143 can be located between the lower surface of the lower source / drain pattern 150A and the upper surface of the substrate 101. The upper surface of the dummy semiconductor pattern 143 can contact the lower surface of the lower source / drain pattern 150A. (Reference) Figure 2 and Figure 4 The side surface of the dummy semiconductor pattern 143 can be covered by the active pattern 105 and the field insulating layer 107, or overlap with the active pattern 105 and the field insulating layer 107.

[0088] The dummy semiconductor pattern 143 may include a semiconductor material. In an embodiment, the dummy semiconductor pattern 143 may include the same material as the lower source / drain pattern 150A. For example, the dummy semiconductor pattern 143 may include silicon germanium (SiGe). In this case, the concentration of germanium (Ge) in the dummy semiconductor pattern 143 may be different from the concentration of germanium (Ge) in the lower source / drain pattern 150A.

[0089] The semiconductor device according to the embodiment may further include a lower etch stop film 185A located on the lower source / drain pattern 150A. The lower etch stop film 185A may be located between the lower source / drain pattern 150A and the upper source / drain pattern 150B, which will be described later.

[0090] The lower etch stop film 185A may cover or overlap with the lower source / drain pattern 150A. The lower etch stop film 185A may be located on at least a portion of the upper and side surfaces of the lower source / drain pattern 150A. For example, refer to... Figure 4 and Figure 6The lower etch stop film 185A can be located on both side surfaces of the first interlayer insulating layer 171, which will be described later, along the second direction D2, within the entire side surface region of the lower source / drain pattern 150A. For example, refer to... Figure 2 The lower etch stop film 185A may not be located on the two side surfaces of the lower gate structure 160A and the lower channel pattern 140A along the first direction D1 within the entire side surface region of the lower source / drain pattern 150A.

[0091] The bottom etch stop film 185A can also be located on the field insulating layer 107. That is, the bottom etch stop film 185A can be conformally disposed along the upper and side surfaces of the bottom source / drain pattern 150A and the upper surface of the field insulating layer 107.

[0092] The lower etch stop film 185A can also be located on the side surface of the intermediate insulating pattern 181. The lower etch stop film 185A can cover the side surface of the intermediate insulating pattern 181 or overlap with the side surface of the intermediate insulating pattern 181. (See reference) Figure 2 The lower etch stop film 185A can be conformally disposed in the region defined by the facing side surfaces of two adjacent intermediate insulating patterns 181 and the upper surface of the lower source / drain pattern 150A.

[0093] The upper surface of the lower etch stop film 185A may be disposed on the same plane as the upper surface of the intermediate insulating pattern 181. The upper surface of the lower etch stop film 185A may contact a portion of the lower surface of the upper source / drain pattern 150B, which will be described later. The lower etch stop film 185A may not be located on the upper surface of the intermediate insulating pattern 181.

[0094] and Figure 2 As shown, the lower etch stop film 185A may cover only a portion of the side surface of the intermediate insulating pattern 181 or overlap with a portion of the side surface of the intermediate insulating pattern 181. For example, the lower etch stop film 185A may cover only the side surface of one or both of the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S, or overlap only with the side surface of one or both of the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S. For example, the lower etch stop film 185A may cover only a portion of the side surface of the first intermediate insulating pattern 181A and the side surface of the third intermediate insulating pattern 181S, or overlap only with a portion of the side surface of the first intermediate insulating pattern 181A and the side surface of the third intermediate insulating pattern 181S. For example, the lower etch stop film 185A may only cover at least a portion of the side surface of the first intermediate insulating pattern 181A, or may only overlap with at least a portion of the side surface of the first intermediate insulating pattern 181A.

[0095] and Figures 1 to 6 As shown, the lower etch stop film 185A can be omitted. In this case, the side surface of the lower source / drain pattern 150A can be covered by or overlapped with the first interlayer insulating layer 171, which will be described later.

[0096] The down-etch stop film 185A may include an insulating material. The down-etch stop film 185A may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof. The down-etch stop film 185a is shown as a monolayer film, but this is only for ease of description, and this disclosure is not limited thereto.

[0097] The semiconductor device according to the embodiment may further include a first interlayer insulating layer 171, which is located on the field insulating layer 107 and on the side surface of the lower source / drain pattern 150A. In the embodiment, a lower etch stop film 185A may be located between the first interlayer insulating layer 171 and the field insulating layer 107.

[0098] The first interlayer insulating layer 171 may be located on the lower etch stop film 185A. In an embodiment, the first interlayer insulating layer 171 may be located on the side surface of the lower source / drain pattern 150A. The first interlayer insulating layer 171 may cover the side surface of the lower source / drain pattern 150A, or overlap with the side surface of the lower source / drain pattern 150A. The first interlayer insulating layer 171 may be located on the field insulating layer 107.

[0099] In this embodiment, the first interlayer insulating layer 171 may not be disposed on the upper surface of the lower source / drain pattern 150A. The first interlayer insulating layer 171 may not overlap with the intermediate insulating pattern 181 in the horizontal direction (e.g., the first direction d1). Reference Figure 2 The first interlayer insulation layer 171 may not be provided between the two facing side surfaces of two adjacent intermediate insulation patterns 181.

[0100] The first interlayer insulating layer 171 may have a flat upper surface. The upper surface of the first interlayer insulating layer 171 may be disposed on the same plane as the upper surface of the lower etch stop film 185A covering the lower source / drain pattern 150A or overlapping the upper surface of the lower etch stop film 185A with the upper surface of the lower source / drain pattern 150A.

[0101] The first interlayer insulating layer 171 may include an insulating material. The first interlayer insulating layer 171 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof. Although the first interlayer insulating layer 171 is shown as a single-layer film for ease of description only, this is for illustrative purposes only, and the present disclosure is not limited thereto.

[0102] According to an embodiment, the upper source / drain pattern 150B of the semiconductor device can be disposed on the lower source / drain pattern 150A. The upper source / drain pattern 150B can be configured to be spaced apart from the lower source / drain pattern 150A on a third-direction D3. (Reference) Figure 2 , Figure 4 and Figure 6 The upper source / drain pattern 150B and the lower source / drain pattern 150A can be spaced apart from each other on the third direction D3 by a first interlayer insulating layer 171 and a lower etch stop film 185A. In an embodiment, the air gap AG, described later, can be located between the lower source / drain pattern 150A and the upper source / drain pattern 150B.

[0103] The upper source / drain pattern 150B may be located on at least one side of the upper gate structure 160. For example, the upper source / drain pattern 150B may be located on opposite sides of the upper gate structure 160B. For example, each upper source / drain pattern 150B may be located between two upper gate structures 160B arranged to be spaced apart from each other in the first direction D1. The upper source / drain pattern 150B may be connected to a plurality of upper channel patterns 140B. The upper source / drain pattern 150B may contact the side surfaces of the plurality of upper channel patterns 140B.

[0104] The upper source / drain pattern 150B can be an epitaxial pattern formed by a selective epitaxial growth process using multiple upper channel patterns 140B as seeds. In this case, the upper source / drain pattern 150B can be a pattern formed by using the opposing side surfaces of multiple upper channel patterns 140B as seeds.

[0105] The upper source / drain pattern 150B can be used as the source / drain of a second transistor structure using multiple upper channel patterns 140B as the channel region.

[0106] In an embodiment, such as Figure 2As shown, the upper surface of the upper source / drain pattern 150B can be disposed at a horizontal height substantially the same as the upper surface of the uppermost upper channel pattern 140B. In this embodiment, the lower surface of the upper source / drain pattern 150B can be disposed at a horizontal height higher or lower than the lower surface of the lowermost upper gate structure 160B. That is, the distance between the upper surface of the upper source / drain pattern 150B and the upper surface of the substrate 101 can be substantially the same as the distance between the upper surface of the uppermost upper channel pattern 140B and the upper surface of the substrate 101. Furthermore, the lower surface of the upper source / drain pattern 150B can be disposed at a horizontal height substantially the same as the upper surface of the first interlayer insulating layer 171. The lower surface of the upper source / drain pattern 150B can be disposed at a height substantially the same as the lower surface of the lowermost upper gate structure 160B. However, this disclosure is not limited thereto, and the upper surface of the upper source / drain pattern 150B may be set at a height that is higher or lower than the upper surface of the lowermost upper channel pattern 140B.

[0107] The upper source / drain pattern 150B may include a semiconductor material. The upper source / drain pattern 150B may include the same material as the lower source / drain pattern 150A. The upper source / drain pattern 150B may include, for example, silicon (Si) or germanium (Ge). Furthermore, the upper source / drain pattern 150B may include, for example, at least two or more binary or ternary compounds comprising carbon (C), silicon (Si), germanium (Ge), and / or tin (Sn). For example, the upper source / drain pattern 150B may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), and / or similar materials, but is not limited thereto. In this embodiment, the upper source / drain pattern 150B is shown as a single layer, but is not limited thereto, and the upper source / drain pattern 150B may be formed of two or more layers. When the source / drain pattern 150B comprises two or more layers, the concentration of silicon (Si) or germanium (Ge) in each layer can be different from each other.

[0108] In this embodiment, the upper source / drain pattern 150B may be doped with impurities. For example, when the second transistor structure is an N-type MOSFET, the upper source / drain pattern 150B may include N-type impurities. For example, the upper source / drain pattern 150B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof.

[0109] In the semiconductor device according to the embodiment, an air gap AG may be located between the lower source / drain pattern 150A and the upper source / drain pattern 150B. The air gap AG may refer to an empty space located between one layer and another. For example, the air gap AG may include air or gas used in the process of manufacturing the semiconductor device. The lower source / drain pattern 150A and the upper source / drain pattern 150B may be configured to be spaced apart from each other on a third direction D3, with the air gap AG interposed therebetween.

[0110] The air gap AG can be located between two adjacent intermediate insulation patterns 181. (Reference) Figure 2 Two adjacent intermediate insulating patterns 181 can be spaced apart from each other along a first direction D1, with an air gap AG between them. Specifically, the air gap AG can be disposed between two facing side surfaces of the two adjacent intermediate insulating patterns 181 along the first direction D1. In an embodiment, a lower etch stop film 185A and an upper etch stop film 185B, described later, can be positioned between the intermediate insulating patterns 181 and the air gap AG.

[0111] refer to Figure 4 and Figure 6 The upper etch stop film 185B, described later, may be located between the air gap AG and the upper source / drain pattern 150B. The lower etch stop film 185A and the upper etch stop film 185B may be located between the air gap AG and the lower source / drain pattern 150A.

[0112] In embodiments, the air gap AG can have a smaller (i.e., less) dielectric constant compared to the dielectric constant of the insulating material included in the insulating layer and insulating pattern disposed around the surrounding region. For example, the air gap AG can have a lower dielectric constant compared to the interlayer insulating layers 171 and 173, the etch stop films 185A and 185B, and the field insulating layer 107. For example, the air gap AG can be filled with air, and the dielectric constant of air can be approximately 1. Since the semiconductor device according to the embodiment includes the air gap AG, internal parasitic capacitance can be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0113] The semiconductor device according to the embodiment may also include an upper etch stop film 185B located on the lower source / drain pattern 150A.

[0114] The upper etch stop film 185B may cover the upper source / drain pattern 150B. In an embodiment, the upper etch stop film 185B may surround the four surfaces of the upper source / drain pattern 150B. Specifically, in a cross-sectional view, the upper etch stop film 185B may surround the upper surface, lower surface, and two side surfaces facing along the second direction D2 of the upper source / drain pattern 150B, or extend around the upper surface, lower surface, and two side surfaces facing along the second direction D2 of the upper source / drain pattern 150B. The upper etch stop film 185B may not be disposed on the two side surfaces facing the upper gate structure 160B and the upper channel pattern 140B along the first direction D1 in the entire side surface region of the upper source / drain pattern 150B. That is, the upper etch stop film 185B may be conformally disposed along at least a portion of the upper surface, a portion of the side surface, and the lower surface of the upper source / drain pattern 150B.

[0115] The upper etch stop film 185B may be located between the lower surface of the upper source / drain pattern 150B and the air gap AG. The upper etch stop film 185B may be located between the side surface of the upper source / drain pattern 150B and the second interlayer insulating layer 173, which will be described later. The upper etch stop film 185B may be located between the upper surface of the upper source / drain pattern 150B and the second interlayer insulating layer 173.

[0116] In this embodiment, a portion of the upper etch stop film 185B may be penetrated by the upper contact electrode 191 or the connection electrode 199, which will be described later. That is, the upper contact electrode 191 or the connection electrode 199 may extend into the upper etch stop film 185B. Specifically, a portion of the upper etch stop film 185B located on the upper surface of the upper source / drain pattern 150B may be penetrated by the upper contact electrode 191 or the connection electrode 199. That is, the upper contact electrode 191 or the connection electrode 199 may extend into the upper source / drain pattern 150B.

[0117] The upper etch stop film 185B can also be located on the side surface of the gate spacer 164. (See reference) Figure 2 The upper etch stop film 185B may be located between the gate spacer 164 and the upper contact electrode 191 or connection electrode 199, which will be described later. The upper surface of the upper etch stop film 185B may be on the same plane as the upper surfaces of the gate spacer 164 and the capping layer 166. The upper etch stop film 185B may not be provided on the upper surfaces of the gate spacer 164 and the capping layer 166.

[0118] In an embodiment, the upper etch stop film 185B may be conformally disposed on the upper surface of the upper source / drain pattern 150B and the side surface of the gate spacer 164.

[0119] The upper etch stop film 185B can also be located on the side surface of the intermediate insulating pattern 181. Specifically, the upper etch stop film 185B can be disposed on the side surface of the lower etch stop film 185A covering the side surface of the intermediate insulating pattern 181. The upper etch stop film 185B can also be disposed on the upper surface of the lower source / drain pattern 150A. Specifically, the upper etch stop film 185B can be disposed on the upper surface of the etch stop film 185A covering the lower source / drain pattern 150A or on the upper surface of the lower etch stop film 185A overlapping the upper surface of the lower source / drain pattern 150A. The upper etch stop film 185B can be conformally formed in the area defined by the upper surface of the area covering the upper surface of the lower source / drain pattern 150A or overlapping the upper surface of the lower source / drain pattern 150A, the side surface of the area covering the side surface of the intermediate insulating pattern 181 or overlapping the side surface of the intermediate insulating pattern 181, and the lower surface of the upper source / drain pattern 150B.

[0120] The upper etch stop film 185B can also be located on the first interlayer insulating layer 171. (See reference) Figure 2 and Figure 4 The upper etch stop film 185B may cover or overlap with the upper surface of the first interlayer insulating layer 171 in the region where it overlaps with the field insulating layer 107 on the third-direction D3. The upper etch stop film 185B may be located between the second interlayer insulating layer 173 and the first interlayer insulating layer 171, described later, in the region where it overlaps with the first interlayer insulating layer 171 on the third-direction D3. The upper etch stop film 185B may be located between the lower source / drain pattern 150A and the air gap AG in the region where it overlaps with the lower source / drain pattern 150A on the third-direction D3, or between the lower etch stop film 185A and the air gap AG.

[0121] and Figures 1 to 6 The difference shown can be that the upper etch stop film 185B can be omitted. In this case, the upper and side surfaces of the upper source / drain pattern 150B can contact the second interlayer insulating layer 173.

[0122] The upper etch stop film 185B may include an insulating material. In an embodiment, the upper etch stop film 185B may include the same insulating material as the lower etch stop film 185A. However, this disclosure is not limited thereto, and the upper etch stop film 185B may include a different insulating material than the lower etch stop film 185A. The upper etch stop film 185B may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof. The upper etch stop film 185B is shown as a monolayer film, but this is only for ease of description, and this disclosure is not limited thereto.

[0123] The semiconductor device according to the embodiment may further include a second interlayer insulating layer 173 located on the first interlayer insulating layer 171. The second interlayer insulating layer 173 may cover the upper source / drain pattern 150B together with the upper etch stop film 185B or overlap with the upper source / drain pattern 150B. The second interlayer insulating layer 173 may be located on the upper etch stop film 185B. The second interlayer insulating layer 173 may be disposed on a portion of the upper surface of the upper source / drain pattern 150B and on the side surface of the upper source / drain pattern 150B. The second interlayer insulating layer 173 may cover the side surface of the upper etch stop film 185B located on the side surface of the upper source / drain pattern 150B, or overlap with the side surface of the upper etch stop film 185B located on the side surface of the upper source / drain pattern 150B. Although not clearly illustrated, the second interlayer insulating layer 173 may be located between two main gate structures 160M that are adjacent to each other along the first direction D1. The second interlayer insulating layer 173 may also be located on the first interlayer insulating layer 171. The second interlayer insulating layer 173 may cover at least a portion of the upper surface of the upper etch stop film 185B that overlaps with the first interlayer insulating layer 171 on the third direction D3, or overlap with the at least a portion thereof.

[0124] In an embodiment, the second interlayer insulating layer 173 may not overlap with the lower source / drain pattern 150A and the upper source / drain pattern 150B on the third direction D3, or it may overlap only in a portion of the region. (See reference...) Figure 2 and Figure 4 In this embodiment, the air gap AG can be disposed between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B, and the second interlayer insulating layer 173 may not be disposed in the region where the air gap AG is located. Between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B, the second interlayer insulating layer 173 can be disposed on the opposite side of the region where the air gap AG is located. (See reference...) Figure 2 and Figure 4In an embodiment, the second interlayer insulation layer 173 located on the opposite side of the region where the air gap AG is located may include a portion of the region on the third direction D3 that overlaps with the lower source / drain pattern 150A and the upper source / drain pattern 150B.

[0125] Although not clearly shown, at least a portion of the second interlayer insulating layer 173 may overlap with the main gate structure 160M in the first direction D1. The second interlayer insulating layer 173 may have a planar upper surface. The upper surface of the second interlayer insulating layer 173 may be disposed in the same plane as the upper surfaces of the gate spacer 164 and the capping layer 166. The second interlayer insulating layer 173 may not be disposed on the upper surfaces of the gate spacer 164 and the capping layer 166.

[0126] The second interlayer insulating layer 173 may include an insulating material. The second interlayer insulating layer 173 may include the same insulating material as the first interlayer insulating layer 171. However, this disclosure is not limited thereto, and the second interlayer insulating layer 173 may include an insulating material different from the first interlayer insulating layer 171. The second interlayer insulating layer 173 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof. Although the second interlayer insulating layer 173 is shown as a single-layer film for ease of description only, this is for the purpose of description only, and this disclosure is not limited thereto.

[0127] The connecting electrode 199 can connect the lower source / drain pattern 150A and the upper source / drain pattern 150B. Specifically, the connecting electrode 199 can electrically connect the lower source / drain pattern 150A and the upper source / drain pattern 150B, which are configured to be spaced apart from each other on the third direction D3.

[0128] A connecting electrode 199 may be disposed between the lower source / drain pattern 150A and the upper source / drain pattern 150B. The connecting electrode 199 may penetrate or extend into either of the upper source / drain patterns 150B in the third direction D3. The connecting electrode 199 may penetrate or extend into either of the upper source / drain patterns 150B in the third direction D3 and extend in a direction along the upper surface of the substrate 101. One end of the connecting electrode 199 extending in the direction along the upper surface of the substrate 101 may (e.g., physically and / or electrically) be connected to either of the lower source / drain patterns 150A. One end of a connection electrode 199 extending along the upper surface of the substrate 101 may (e.g., physically and / or electrically) be connected to the upper surface of a lower source / drain pattern 150A directly below the upper source / drain pattern 150B penetrated by the connection electrode 199. That is, the connection electrode 199 may extend into the upper source / drain pattern 150B. In an embodiment, the connection electrode 199 may penetrate at least a portion of the upper etch stop film 185B disposed on the upper and lower surfaces of the upper source / drain pattern 150B, or extend to at least a portion of the upper etch stop film 185B disposed on the upper and lower surfaces of the upper source / drain pattern 150B. In an embodiment, the connecting electrode 199 may penetrate or extend into at least a portion of the lower etch stop film 185A that covers the upper surface of the lower source / drain pattern 150A or overlaps with the upper surface of the lower source / drain pattern 150A, or extend into at least a portion of the lower etch stop film 185A that covers the upper surface of the lower source / drain pattern 150A or overlaps with the upper surface of the lower source / drain pattern 150A.

[0129] refer to Figure 1 , Figure 2 and Figure 6 A portion of the side surface of the connecting electrode 199 may be surrounded by the upper source / drain pattern 150B. In an embodiment, a portion of the connecting electrode 199 located at a horizontal height higher than the upper surface of the upper source / drain pattern 150B may be surrounded by the protective pattern 187, described later. A portion of the side surface of the connecting electrode 199 may be surrounded by an air gap AG located between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B. The air gap AG may be disposed between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B, between the connecting electrode 199 and the intermediate insulating pattern 181, and between the connecting electrode 199 and the second insulating layer 173.

[0130] and Figure 2 and Figure 6As shown, the air gap AG may not be located around the connecting electrode 199 between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B. In this case, the connecting electrode 199 or the second interlayer insulating layer 173 may be located in the area where the air gap AG is located. In this case, a portion of the side surface of the connecting electrode 199 may contact the interlayer insulating layer 173 located between the upper surface of the lower source / drain pattern 150A and the upper source / drain pattern 150B.

[0131] The upper surface of the connecting electrode 199 can be disposed on the same plane as the upper surface of the cover layer 166, the upper surface of the gate spacer 164, and the upper surface of the second interlayer insulating layer 173.

[0132] refer to Figure 2 and Figure 6 The connecting electrode 199 can be configured to be recessed into a predetermined depth of the lower source / drain pattern 150A. For example, the connecting electrode 199 can penetrate a portion of the lower etch stop film 185A and upper etch stop film 185B located on the upper surface of the lower source / drain pattern 150A, or extend to a portion of the lower etch stop film 185A and upper etch stop film 185B located on the upper surface of the lower source / drain pattern 150A, and can extend to a predetermined depth inside the lower source / drain pattern 150A. In this case, a portion of the side surface and lower surface of the connecting electrode 199 can contact the upper surface of the lower source / drain pattern 150A.

[0133] In an embodiment, the width of the connecting electrode 199 in the horizontal direction (e.g., the first direction D1 and / or the second direction D2) may not be constant. (See reference...) Figure 3 The connecting electrode 199 may include a first portion 199A and a second portion 199B. The first portion 199A overlaps with the first protective pattern 187A in the horizontal direction, and the second portion 199B overlaps with the second protective pattern 187B in the horizontal direction. In an embodiment, the width W1 of the first portion 199A in the horizontal direction may be greater than the width W2 of the second portion 199B in the horizontal direction. However, this disclosure is not limited thereto; the width of the first portion 199A in the horizontal direction may be substantially the same as the width of the second portion 199B in the horizontal direction. For example, when the width of the first protective pattern 187A and the width of the second protective pattern 187B described below are substantially the same, the widths of the first portion 199A and the second portion 199B in the horizontal direction may also be substantially the same. Figure 2 and Figure 6 As shown in the diagram, the connecting electrode 199 may have a sloping side surface, wherein the width of the lower part becomes narrower than the width of the upper part, depending on the aspect ratio.

[0134] Although not in Figures 1 to 6 As clearly shown, however, the connection electrode 199 can be connected to an external terminal to receive voltage (or current) from or supply voltage (or current) to an external terminal. For example, the connection electrode 199 can be connected to an output terminal.

[0135] The connecting electrode 199 may include a conductive material. For example, the connecting electrode 199 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and / or a conductive metal carbonitride.

[0136] In an embodiment, the lower source / drain pattern 150A and the upper source / drain pattern 150B are electrically connected to each other by a connecting electrode 199 passing through or extending into the upper source / drain pattern 150B, in manufacturing processes such as... Figures 1 to 6 When using the semiconductor devices shown, the process margin can be improved.

[0137] The semiconductor device according to the embodiment may further include an upper contact electrode 191. The upper contact electrode 191 may be disposed on an upper source / drain pattern 150B. The upper contact electrode 191 may also be disposed on another upper source / drain pattern 150B adjacent to the upper source / drain pattern 150B penetrated by the connected electrode 199. The upper contact electrode 191 may be located between two main gate structures 160M spaced apart from each other in the first direction D1. The upper contact electrode 191 may contact the side surface of the protective pattern 187, described later. Figure 2 As shown, in the region where the upper contact electrode 191 contacts the protective pattern 187, the width of the upper contact electrode 191 in the horizontal direction (e.g., the first direction D1 or the second direction D2) can be constant. In another embodiment, with Figure 2 As shown, the width of the upper contact electrode 191 in the horizontal direction may not be constant. For example, the upper contact electrode 191 may have sloping side surfaces, where the width at the bottom becomes narrower than the width at the top, depending on the aspect ratio. For example, the width of the upper contact electrode 191 in the horizontal direction may have a shape that narrows towards the upper surface of the upper source / drain pattern 150B. In this case, at least a portion of the side surface of the upper contact electrode 191 may not be in contact with the protective pattern 187. In an embodiment, the upper surface of the upper contact electrode 191 may lie on the same plane as the upper surfaces of the capping layer 166 and the gate spacer 164.

[0138] refer to Figure 2 and Figure 4The upper contact electrode 191 can be configured to be recessed into the upper source / drain pattern 150B to a predetermined depth. For example, the upper contact electrode 191 can penetrate a portion of the upper etch stop film 185B located on the upper surface of the lower source / drain pattern 150A or extend to a portion of the upper etch stop film 185B located on the upper surface of the lower source / drain pattern 150A, and can extend to a predetermined depth inside the upper source / drain pattern 150B. In this case, a portion of the side surface and lower surface of the upper contact electrode 191 can contact the upper surface of the upper source / drain pattern 150B.

[0139] The upper contact electrode 191 may include a conductive material. For example, the upper contact electrode 191 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride.

[0140] Although not in Figures 1 to 6 As clearly shown, however, the upper contact electrode 191 can be electrically connected to an external terminal to receive voltage (or current) from or supply voltage (or current) to an external terminal. For example, the upper contact electrode 191 can be electrically connected to a ground terminal or an external input terminal.

[0141] Although not in Figures 1 to 6 As clearly shown, however, the semiconductor device according to the embodiment may also include a lower contact electrode connected to either of the lower source / drain patterns 150A. In this case, the lower contact electrode may penetrate or extend into at least a portion of the dummy semiconductor pattern 143 connected to the lower surface of the lower source / drain pattern 150A.

[0142] A protective pattern 187 may be disposed between the gate structure 160 and the connection electrode 199. The protective pattern 187 may protect the configuration around the connection electrode 199 (e.g., the main gate structure 160M, the gate spacer 164, and the capping layer 166) from damage by etching materials during the process of forming the connection electrode 199.

[0143] The protective pattern 187 may surround at least a portion of the side surface of the connecting electrode 199. (See reference) Figure 2 The protective pattern 187 may surround at least a portion of the side surface of the connection electrode 199 located at a horizontal height above the interface between the main gate structure 160M and the upper channel pattern 140B. (See reference...) Figure 2The protective pattern 187 can be disposed between the main gate structure 160M and the connecting electrode 199. The protective pattern 187 can also be disposed between the gate spacer 164 and the connecting electrode 199. An etch stop film 185B can be located between the protective pattern 187 and one side surface of the gate spacer 164. The protective pattern 187 can also be disposed between the second interlayer insulating layer 173 and the connecting electrode 199. Figure 6 In the cross-sectional view, the protective pattern 187 may surround at least a portion of the side surface of the connecting electrode 199, which is located at a height higher than the upper surface of the upper etch stop film 185B covering the upper surface of the upper source / drain pattern 150B.

[0144] In an embodiment, the protective pattern 187 may include a first protective pattern 187A and a second protective pattern 187B. The second protective pattern 187B may be disposed on the first protective pattern 187A. (See reference...) Figure 2 and Figure 6 The first protective pattern 187A can be disposed between the lower part of the main gate structure 160M and the connecting electrode 199, and the second protective pattern 187B can be disposed between the upper part of the main gate structure 160M and the connecting electrode.

[0145] The protective pattern 187 may extend along a third direction D3. In an embodiment, the lengths by which the first protective pattern 187A and the second protective pattern 187B extend along a third direction D3 may be different from each other. For example, the length of the second protective pattern 187B extending along a third direction D3 may be greater than the length of the first protective pattern 187A extending along a third direction D3. In an embodiment, the ratio of the length of the second protective pattern 187B extending along a third direction D3 to the length of the first protective pattern 187A extending along a third direction D3 may be greater than or equal to approximately 1 and less than or equal to approximately 5.

[0146] In an embodiment, the widths of the first protective pattern 187A and the second protective pattern 187B in the horizontal direction (e.g., the first horizontal direction D1 or the second horizontal direction D2) may be different from each other. In an embodiment, the width of the second protective pattern 187B in the horizontal direction may be greater than the width of the first protective pattern 187A in the horizontal direction. However, this disclosure is not limited to this, and the widths of the first protective pattern 187A and the second protective pattern 187B in the horizontal direction may be substantially the same.

[0147] In an embodiment, the first protective pattern 187A may include a high-k dielectric material. A high-k dielectric material can refer to a material having a higher dielectric constant than, for example, silicon oxide (SiO2). For example, the first protective pattern 187A may include at least one of Al2O3, CaF, Y2O3, ZrO2, HfO2, and / or MgO. In an embodiment, the high-k dielectric material included in the first protective pattern 187A may have lower etch selectivity than the insulating material included in the gate spacer 164, the capping layer 166, and the upper etch stop film 185B. Figure 2 and Figure 6 As shown, when a first protective pattern 187A comprising a high-k dielectric material is disposed between the gate structure 160 and the connection electrode 199, the configuration surrounding the connection electrode 199 (e.g., the main gate structure 160M, the gate spacer 164, and the capping layer 166) is well protected during the process of forming the connection electrode 199, thus preventing damage from the etching material. Furthermore, because the first protective pattern 187A has low etch selectivity, it can be formed with a thinner thickness, and therefore the connection electrode 199 can be formed with a wider width in at least some regions, thereby improving the electrical characteristics of the semiconductor device according to the embodiment.

[0148] In an embodiment, the second protective pattern 187B may include a low-k dielectric material. A low-k dielectric material can refer to, for example, a material having a lower dielectric constant than silicon oxide (SiO2). For example, the second protective pattern 187B may include at least one of SiOCN, SiCN, SiBCN, and BN. When a high-k dielectric material, such as that included in the first protective pattern 187A, is disposed around the connection electrode 199, the parasitic capacitance around the connection electrode 199 may increase, and therefore the electrical characteristics of the semiconductor device according to the embodiment may deteriorate. In the process of manufacturing the semiconductor device according to the embodiment, after the connection electrode 199 is formed, at least a portion of the first protective pattern 187A may be replaced by the second protective pattern 187B. In this case, the parasitic capacitance around the connection electrode 199 is reduced, and therefore the electrical characteristics of the semiconductor device according to the embodiment can be improved.

[0149] refer to Figure 2 and Figure 4 In the semiconductor device according to the embodiment, the protective pattern 187 may also be disposed between the gate structure 160 and the upper contact electrode 191. The specific structure of the protective pattern 187 between the gate structure 160 and the upper contact electrode 191, the materials included in the protective pattern 187, the effect of the protective pattern 187, etc. are similar to those of the protective pattern 187 disposed between the gate structure 160 and the connection electrode 199, therefore, its detailed description will be omitted.

[0150] Figure 7 and Figure 8 This is a diagram used to illustrate a semiconductor device according to some embodiments. Specifically, Figure 7 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram, and Figure 8 yes Figure 7 An enlarged cross-sectional view of region "A" in the image. Because... Figure 7 and Figure 8 The semiconductor device shown has essentially the same features as the semiconductor device in the previous embodiment; therefore, the following description will primarily focus on the differences from the previous embodiment. Specifically, Figure 7 and Figure 8 The semiconductor device shown may differ in part from the foregoing embodiments in that it includes an air gap AG around the connection electrode 199.

[0151] The semiconductor device according to an embodiment may include a first air gap AG and a second air gap AG2. (See reference...) Figure 7 and Figure 8 The first air gap AG1 may surround at least a portion of the side surface of the connecting electrode 199.

[0152] The first air gap AG1 can be located on the first protective pattern 187A. The first air gap AG1 can be disposed between the main gate structure 160M and the connecting electrode 199. The first air gap AG1 can be disposed between the gate spacer 164 and the connecting electrode 199. The upper etch stop film 185B can be located between the first air gap AG1 and one side surface of the gate spacer 164. The first air gap AG1 can also be disposed between the second interlayer insulating layer 173 and the connecting electrode 199.

[0153] The first air gap AG1 can be used as a reference. Figures 1 to 6 At least a portion of the region where the second protective pattern 187B is located in the described semiconductor device. In an embodiment, the width of the first air gap AG1 in the horizontal direction (e.g., the first direction D1 or the second direction D2) may be substantially the same as the width of the first protective pattern 187A in the horizontal direction.

[0154] In the case of the second air gap AG2, the position and effect in the semiconductor device according to the embodiment are similar to the reference. Figures 1 to 6 The location and effect of the air gap AG are similar, so its detailed description will be omitted.

[0155] Figure 9 and Figure 10 This is a diagram used to illustrate a semiconductor device according to some embodiments. Specifically, Figure 9 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram, and Figure 10 yes Figure 9 An enlarged cross-sectional view of region "A" in the image. Because... Figure 9 and Figure 10 The semiconductor device shown has essentially the same features as the semiconductor device in the previous embodiment; therefore, the following description will primarily focus on the differences from the previous embodiment. Specifically, Figure 9 and Figure 10 The semiconductor device shown may differ in part from the foregoing embodiments in that the first protective pattern 187A is not included around the connection electrode 199.

[0156] High-k dielectric material may not be present around the connection electrode 199 of the semiconductor device according to the embodiment. (Reference) Figure 9 and Figure 10 The semiconductor device according to the embodiment may not include a reference. Figures 1 to 6 The first protective pattern described is 187A.

[0157] In the semiconductor device according to the embodiment, in reference Figures 1 to 6 The area in the semiconductor device described where the first protective pattern 187A is disposed can be replaced by the second protective pattern 187B.

[0158] In the process of manufacturing the semiconductor device according to the embodiment, after forming the connection electrode 199, the first protective pattern 187A can be completely etched, and the area where the first protective pattern 187A is located can be filled with the second protective pattern 187B. According to the embodiment, and referenced... Figures 1 to 6 Compared to the described semiconductor device, the parasitic capacitance around the connection electrode 199 can be further reduced, thus improving the electrical characteristics of the semiconductor device.

[0159] Figures 11 to 13 This is a diagram used to illustrate a semiconductor device according to some embodiments. Specifically, Figure 11 It is along Figure 1 A cross-sectional view of the semiconductor device taken by line I1-I1' in the diagram. Figure 12 It is along Figure 1 The cross-sectional view of the semiconductor device taken by line I2-I2' in the diagram, and Figure 13 yes Figure 11 An enlarged cross-sectional view of region "B" in the image. Because... Figures 11 to 13 The semiconductor device shown has essentially the same features as the semiconductor device in the previous embodiment; therefore, the following description will primarily focus on the differences from the previous embodiment. Specifically, Figures 11 to 13 The semiconductor device shown may not include the air gap between the lower source / drain pattern 150A and the upper source / drain pattern 150B, which may be partially different from the foregoing embodiments.

[0160] refer to Figures 11 to 13In the semiconductor device according to the embodiment, a first interlayer insulating layer 171 may be disposed between a lower source / drain pattern 150A and an upper source / drain pattern 150B. The first interlayer insulating layer 171 may also be disposed between two adjacent intermediate insulating patterns 181 along a first direction D1. (See reference...) Figures 11 to 13 The lower etch stop film 185A may be located between the first interlayer insulating layer 171 and the intermediate insulating pattern 181. The lower etch stop film 185A may be located between the first insulating layer 171 and the upper and side surfaces of the lower source / drain pattern 150A.

[0161] In the semiconductor device according to the embodiment, the upper etch stop film 185B may not be disposed on the lower surface of the upper source / drain pattern 150B. In this case, the lower surface of the upper source / drain pattern 150B may be covered by or overlapped with the first interlayer insulating layer 171.

[0162] In one embodiment, the second interlayer insulating layer 173 may not be disposed below the lower surface of the upper source / drain pattern 150B. In another embodiment, the upper etch stop film 185B may not be disposed below the lower surface of the upper source / drain pattern 150B.

[0163] In an embodiment, the first interlayer insulating layer 171 may comprise a low-k dielectric material. For example, the first interlayer insulating layer 171 may comprise at least one of SiOCN, SiCN, SiBCN, and / or BN. However, this disclosure is not limited thereto, and the first interlayer insulating layer 171 may comprise other insulating materials, such as silicon oxide (SiO2).

[0164] Figures 14 to 49 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Figures 14 to 17 , Figures 19 to 21 , Figures 23 to 27 , Figure 29 , Figure 31 , Figure 32 , Figure 34 , Figure 36 and Figures 38 to 49 It is along Figure 1 The cross-sectional view of the region intercepted by the II′ line illustrates a method for manufacturing a semiconductor device according to some embodiments. Figure 18 , Figure 22 , Figure 28 , Figure 30 , Figure 33 , Figure 35 and Figure 37 It is along Figure 1 A cross-sectional view of the region intercepted by the I2-I2′ line in the diagram illustrates a method for manufacturing a semiconductor device according to some embodiments.

[0165] like Figure 14 As shown, a sacrificial layer 120, a plurality of lower channel patterns 140A, an intermediate semiconductor pattern 140S, and a plurality of upper channel patterns 140B can be formed on the substrate 101.

[0166] First, a sacrificial layer 120, a plurality of lower channel patterns 140A, an intermediate semiconductor pattern 140S, and a plurality of upper channel patterns 140B are formed on a substrate 101. The substrate 101 may be silicon-on-insulator (SOI) or bulk silicon. In some embodiments, the substrate 101 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0167] The sacrificial layer 120 may include a lower sacrificial layer 120A, an intermediate sacrificial layer 120B, and an upper sacrificial layer 120C. In an embodiment, the lower sacrificial layer 120A may be stacked alternately with the lower channel pattern 140A, and the upper sacrificial layer 120C may be stacked alternately with the upper channel pattern 140B. The intermediate sacrificial layer 120B may be disposed on the upper and lower surfaces of the intermediate semiconductor pattern 140S.

[0168] Sacrificial layers 120A, 120B, and 120C may be formed of a material having etch selectivity relative to the plurality of lower channel patterns 140A, intermediate semiconductor patterns 140S, and upper channel patterns 140B. The plurality of lower channel patterns 140A, intermediate semiconductor patterns 140S, and upper channel patterns 140B may include materials different from those of sacrificial layers 120A, 120B, and 120C. For example, the plurality of lower channel patterns 140A, intermediate semiconductor patterns 140S, and upper channel patterns 140B may include silicon (Si), and sacrificial layer 120 may include silicon germanium (SiGe). In an embodiment, the intermediate sacrificial layer 120B may have etch selectivity relative to the other sacrificial layers 120A and 120C. In an embodiment, the intermediate sacrificial layer 120B may have a different concentration of germanium (Ge) compared to the lower sacrificial layers 120A and upper sacrificial layers 120C.

[0169] The sacrificial layer 120, multiple lower channel patterns 140A, and multiple upper channel patterns 140B can be formed by performing an epitaxial growth process using the substrate 101 as a seed. The number of multiple lower channel patterns 140A, intermediate semiconductor patterns 140S, and multiple upper channel patterns 140B stacked alternately with the sacrificial layer 120 can be varied in different embodiments.

[0170] Next, portions of the sacrificial layer 120, multiple lower channel patterns 140A, intermediate semiconductor patterns 140S, multiple upper channel patterns 140B, and substrate 101 can be removed to form an active structure, and a field insulating layer 107 can be formed (see [link to documentation]). Figure 4 The active structure may include alternately stacked sacrificial layers 120, a plurality of lower channel patterns 140A, intermediate semiconductor patterns 140S, and a plurality of upper channel patterns 140B. Furthermore, the active structure may also include an active pattern 105, which is formed to protrude from the upper surface of the substrate 101 by removing at least a portion of the substrate 101. The active structure may extend in a first direction D1. The active structures may be configured to be spaced apart from each other in a second direction D2. Therefore, opposing side surfaces of the intermediate sacrificial layers 120B and the intermediate semiconductor patterns 140S may be exposed.

[0171] Field insulation layer 107 (see Figure 4 The active pattern 105 can be formed in at least a portion of the substrate 101 that has been removed. Therefore, the active pattern 105 can be disposed on the side surface of the field insulating layer 107.

[0172] Next, a sacrificial gate structure 210 can be formed on the active structure. The sacrificial gate structure 210 may include a first sacrificial gate electrode 211 and a second sacrificial gate electrode 213 sequentially disposed on a plurality of upper channel patterns 140B, and a preliminary capping layer 215. The first sacrificial gate electrode 211 may include, for example, silicon oxide (SiO2), but is not limited thereto. The second sacrificial gate electrode 213 may include, for example, polysilicon, but is not limited thereto. The preliminary capping layer 215 may include, for example, silicon nitride, but is not limited thereto. Therefore, the opposing side surfaces of a portion of the intermediate sacrificial layer 120B disposed between the sacrificial gate structures 210 and the opposing side surfaces of a portion of the intermediate semiconductor pattern 140S can be exposed.

[0173] Next, as Figure 15 As shown, the intermediate sacrificial layer 120B among multiple sacrificial layers 120 can be selectively removed. The intermediate sacrificial layer 120B can be removed by means of the exposed intermediate sacrificial layer 120B and the opposite side surface of the intermediate semiconductor pattern 140S. Compared with the lower sacrificial layer 120A, the upper sacrificial layer 120C, and the channel patterns 140A and 140B, the process for removing the intermediate sacrificial layer 120B can be performed using an etch material with a higher etch rate than the intermediate sacrificial layer 120B.

[0174] like Figure 16As shown, a first intermediate insulating pattern 181A and a second intermediate insulating pattern 181B can be formed in the region where the intermediate sacrificial layer 120B is removed. In an embodiment, the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B may comprise a material having etch selectivity relative to the intermediate semiconductor pattern 140S. For example, the intermediate insulating patterns 181A and 181B may comprise silicon nitride (SiNX), but are not limited thereto.

[0175] Subsequently, a preliminary gate spacer 217 can be formed to cover or overlap with the opposite side surface of the sacrificial gate structure 210. The preliminary gate spacer 217 can be formed to have a uniform thickness along the upper and side surfaces of the active structure and the sacrificial gate structure 210. First, after forming the preliminary gate spacer 217 to cover or overlap with the entire upper and side surfaces of the sacrificial gate structure 210, a portion of the preliminary gate spacer 217 disposed on the upper surface of the sacrificial gate structure 210 can be etched by a dry etching process.

[0176] Next, as Figure 17 and 18 As shown, a first recess RC1 exposing the intermediate semiconductor pattern 140S can be formed by removing a portion of the upper sacrificial layer 120C and the upper channel pattern 140B. The process for forming the first recess RC1 can be performed using a dry etching process with the sacrificial gate structure 210 as an etching mask. (See reference...) Figure 17 The upper channel pattern 140B and the upper sacrificial layer 120C located between the sacrificial gate structure 210 can be etched in portions of the area spaced apart from each other in the first direction D1, thereby exposing portions of the upper surface of the intermediate semiconductor pattern 140S.

[0177] like Figure 19 As shown, a first barrier pattern 183A can be formed covering or overlapping the side surface of the first recess RC1. The first barrier layer pattern 183A can be formed by conformally depositing an insulating material within the first recess RC1 and on the upper surface of the sacrificial gate structure 210, and then removing the insulating material disposed on the upper surface of the sacrificial gate structure 210 and the lower surface of the first recess RC1 by a dry etching process. The first barrier layer pattern 183A may include a material with etch selectivity relative to the intermediate semiconductor pattern 140S.

[0178] Next, as Figure 20As shown, the intermediate semiconductor pattern 140S can be etched through the area exposed by the first recess RC1. In this case, the sacrificial gate structure 210, the upper channel pattern 140B, and the upper sacrificial layer 120C can be protected by the first barrier layer pattern 183A. Since the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B have etch selectivity relative to the intermediate semiconductor pattern 140S, the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B may not be etched, or may be etched in very small amounts.

[0179] like Figure 21 and Figure 22 As shown, the second recess RC2 and the lower recess PHR can be formed by etching a portion of the first intermediate insulating pattern 181A, the lower sacrificial layer 120A, the lower channel pattern 140A, and the active pattern 105. The process of forming the second recess RC2 and the lower recess PHR can be performed by an anisotropic etching process. In this case, the sacrificial gate structure 210 can be used as a mask. In this case, the upper channel pattern 140B, the upper sacrificial layer 120C, and the second intermediate insulating pattern 181B can be protected from etching by the first barrier layer 183A.

[0180] The processes for forming the second trench RC2 and the lower trench PHR can be performed sequentially. First, a portion of the sacrificial layer 120A and the lower channel pattern 140A can be etched to form the second trench RC2, and then a portion of the active pattern 105 is etched to form the lower trench PHR. In this case, the lower trench PHR can be formed to have a width narrower than the width of the second trench RC2 in the first direction D1. In this case, compared to the process for forming the second trench RC2, the process for forming the lower trench PHR can be controlled to have a higher etching rate relative to the vertical direction.

[0181] Next, as Figure 23 As shown, a dummy semiconductor pattern 143 and a lower source / drain pattern 150A can be formed in the lower groove PHR and the second groove RC2, respectively.

[0182] The dummy semiconductor pattern 143 can be formed by a selective epitaxial growth process that uses the active pattern 105 disposed on the side and bottom surfaces of the lower recess PHR as a seed. Therefore, the side and bottom surfaces of the dummy semiconductor pattern 143 can contact the active pattern 105.

[0183] The lower source / drain pattern 150A can be formed by a selective epitaxial growth process using the upper surface of the dummy semiconductor pattern 143 and multiple lower channel patterns 140A as seeds. The lower source / drain pattern 150A can be formed in the second groove RC2. The side surfaces and lower surface of the lower source / drain pattern 150A can contact the side surfaces of the multiple lower channel patterns 140A and the upper surface of the dummy semiconductor pattern 143, respectively.

[0184] In an embodiment, the lower source / drain pattern 150A and the dummy semiconductor pattern 143 may include silicon germanium (SiGe). In an embodiment, the silicon germanium (SiGe) included in the dummy semiconductor pattern 143 may have a higher germanium (Ge) concentration compared to the lower source / drain pattern 150A. Subsequently, as... Figure 24 As shown, the first blocking pattern 183A can be removed.

[0185] Next, a third intermediate insulation pattern 181S can be formed between the first intermediate insulation pattern 181A and the second intermediate insulation pattern 181B. First, as... Figure 25 As shown, a preliminary third intermediate insulating pattern 181SP can be formed, which covers the upper and side surfaces of the sacrificial gate structure 210, the side surface of the upper channel pattern 140B, the side surface of the upper sacrificial layer 120C, the upper surface of the lower source / drain pattern 150A, and a portion of the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B, or overlaps with the upper and side surfaces of the sacrificial gate structure 210, the side surface of the upper channel pattern 140B, the side surface of the upper sacrificial layer 120C, the upper surface of the lower source / drain pattern 150A, and a portion of the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B. In this case, the third intermediate insulating pattern 181SP can also be formed between the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B. Then, as... Figure 26 As shown, the remaining area of ​​the preliminary third intermediate insulating pattern 181SP, excluding the area located between the first intermediate insulating pattern 181A and the second intermediate insulating pattern 181B, can be etched by an anisotropic etching process to form the third intermediate insulating pattern 181S.

[0186] like Figure 27 and 28 As shown, a down etch stop film 185A can be formed covering the sacrificial gate structure 210 and the lower source / drain pattern 150A, or overlapping with the sacrificial gate structure 210 and the lower source / drain pattern 150A. In an embodiment, the down etch stop film 185A can be conformally formed on the upper and side surfaces of the sacrificial gate structure 210 and the upper and side surfaces of the lower source / drain pattern 150A. (See reference...) Figure 28The lower etch stop film 185A can also be formed on the upper surface of the field insulating layer 107.

[0187] like Figure 29 and Figure 30 As shown, a first interlayer insulating layer 171 can be formed covering the lower source / drain pattern 150A and the field insulating layer 107, or overlapping with the lower source / drain pattern 150A and the field insulating layer 107. The first interlayer insulating layer 171 can be disposed on the upper surface of the field insulating layer 107, the upper surface of the lower source / drain pattern 150A, and the side surface. The first interlayer insulating layer 171 can cover a portion of the lower etch stop film 185A, or overlap with a portion of the lower etch stop film 185A. (See reference...) Figure 30 The first interlayer insulating layer 171 may cover or overlap with the lower etch stop film 185A. The lower etch stop film 185A is conformally formed on the upper surface of the field insulating layer 107, the upper surface of the lower source / drain pattern 150A, and the side surface.

[0188] The first interlayer insulation layer 171 can also be disposed on the side surface of the intermediate insulation pattern 181. (See reference) Figure 29 The first interlayer insulating layer 171 can be formed such that its upper surface is on the same plane as the upper surface of the second intermediate insulating pattern 181B. However, this disclosure is not limited to this, and the upper surface of the first interlayer insulating layer 171 can be disposed at a lower horizontal height than the upper surface of the second intermediate insulating pattern 181B. For example, the upper surface of the first interlayer insulating layer 171 can be disposed between the upper surface of the second intermediate insulating pattern 181B and the lower surface of the first interlayer insulating pattern 181A.

[0189] In this embodiment, the upper surface of the first interlayer insulating layer 171 may not be positioned at a height higher than the upper surface of the second intermediate insulating pattern 181B. The first interlayer insulating layer 171 may be formed so as not to cover the side surfaces of the upper channel pattern 140B and the upper sacrificial layer 120C.

[0190] like Figure 31 As shown, a portion of the lower etch stop film 185A can be etched. In an embodiment, the lower etch stop film 185A can be etched using an etch material that has higher etch selectivity than the first interlayer insulating layer 171 relative to the lower etch stop film 185A. Therefore, as Figure 31As shown, a portion of the lower etch stop film 185A, positioned at a height higher than the upper surface of the first interlayer insulating layer 171, can be removed from the entire area of ​​the lower etch stop film 185A. Therefore, the upper surface of the lower etch stop film 185A can be disposed on the same plane as the upper surface of the first interlayer insulating layer 171. When the lower etch stop film 185A, positioned at a height higher than the upper surface of the first interlayer insulating layer 171, is removed, the side surfaces of the upper channel pattern 140B and the upper sacrificial layer 120C can be exposed.

[0191] and Figure 31 As shown, when the upper surface of the first interlayer insulating layer 171 is disposed between the upper surface of the second intermediate insulating pattern 181B and the lower surface of the first intermediate insulating pattern 181A, a portion of the side surface of the intermediate insulating pattern 181 may be exposed during the process of removing the lower etch stop film 185A. In this case, the lower etch stop film 185A may cover a portion of the side surface of the intermediate insulating pattern 181, or overlap with a portion of the side surface of the intermediate insulating pattern 181. For example, the lower etch stop film 185A may cover the side surface of one or both of the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S, or overlap with the side surface of one or both of the first intermediate insulating pattern 181A, the second intermediate insulating pattern 181B, and the third intermediate insulating pattern 181S. For example, the lower etch stop film 185A may only cover at least a portion of the side surfaces of the first intermediate insulating pattern 181A and the third intermediate insulating pattern 181S, or may only overlap with at least a portion of the side surfaces of the first intermediate insulating pattern 181A and the third intermediate insulating pattern 181S.

[0192] Subsequently, as Figure 32 and Figure 33 As shown, a portion of the first interlayer insulating layer 171 can be etched using a reverse etching process. (Reference) Figure 32 and Figure 33 A portion of the first interlayer insulating layer 171 can be removed. This portion is located at a horizontal height higher than the upper surface of the lower etch stop film 185A covering the upper surface of the lower source / drain pattern 150A. In this embodiment, the first interlayer insulating layer 171 can be sufficiently removed so that an air gap AG can be well formed on the lower source / drain pattern 150A in subsequent processes (see...). Figure 38 ).

[0193] like Figure 34 and Figure 35As shown, an upper source / drain pattern 150B can be formed to fill a portion of the first groove RC1. Specifically, the upper source / drain pattern 150B can be formed on the side surface of the first groove RC1 by using the opposing side surfaces of a plurality of upper channel patterns 140B as seeds. In an embodiment, the upper source / drain pattern 150B may include silicon germanium (SiGe).

[0194] like Figure 36 and 37 As shown, an upper etch stop film 185B can be formed covering the sacrificial gate structure 210 and the upper source / drain pattern 150B, or overlapping with the sacrificial gate structure 210 and the upper source / drain pattern 150B. The upper etch stop film 185B can be formed conformally along the upper surface and side surface of the sacrificial gate structure 210.

[0195] In an embodiment, the upper etch stop film 185B may be formed on the lower surface of the upper source / drain pattern 150B and on portions of the upper and side surfaces of the upper source / drain pattern 150B. (See reference...) Figure 32 and Figure 33 As described, this could be due to the process characteristic that a portion of the first interlayer insulating layer 171 formed on the lower source / drain pattern 150A is removed again by an etch-back process. Figure 37 In a cross-sectional view cut along the second direction D2 and the third direction D3, the upper etch stop film 185B can be conformally formed on the upper surface, lower surface, and entire side surface of the upper source / drain pattern 150B. The upper etch stop film 185B can also be formed on the upper surface of the lower etch stop film 185A covering the upper surface of the first lower source / drain pattern 150A or overlapping the upper surface of the first lower source / drain pattern 150A, and on the upper surface of the interlayer insulating layer 171.

[0196] refer to Figure 36 The upper etch stop film 185B can also be formed on the side surface of the intermediate insulating pattern 181. Specifically, the upper etch stop film 185B can be conformally formed on the side surface of the lower etch stop film 185A covering the side surface of the intermediate insulating pattern 181.

[0197] like Figure 38 As shown, a second interlayer insulating layer 173 can be formed on the upper source / drain pattern 150B. Although not clearly shown, in embodiments, the second interlayer insulating layer 173 may not be formed on the side surface of the upper source / drain pattern 150B (see [reference]). Figure 4 and Figure 6In one embodiment, the second interlayer insulating layer 173 may not fill at least a portion of the region between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B. Therefore, an air gap AG can be formed between the upper surface of the lower source / drain pattern 150A and the lower surface of the upper source / drain pattern 150B, or between the side surfaces of two intermediate insulating patterns 181 facing each other along the first direction D1. Subsequently, the sacrificial gate structure 210 can be removed, and the upper sacrificial layer 120C and the lower sacrificial layer 120A can be removed to form a gate trench 130t between the plurality of channel patterns 140. In some embodiments, the processes of removing the sacrificial gate structure 210, the upper sacrificial layer 120C, and the lower sacrificial layer 120A can be performed simultaneously.

[0198] like Figure 39 As shown, sub-gate insulating films 162A and 162B and main gate insulating film 162M can be formed in the gate trench 130t, sub-gate electrodes 165A and 165B and main gate electrode 165M can be formed, and a capping layer 166 can be formed on the main gate electrode 165M.

[0199] Next, a first protective pattern 187A can be formed on the side surface of the gate spacer 164. First, as... Figure 40 As shown, the first protective pattern 187A can be formed to completely cover the upper surface of the capping layer 166, the upper surface and the side surface of the gate spacer 164, or to completely overlap with the upper surface of the capping layer 166, the upper surface of the gate spacer 164 and the side surface. Subsequently, a portion of the first protective pattern 187A disposed on the upper surface of the capping layer 166, the upper surface of the gate spacer 164 and the upper surface of the upper source / drain pattern 150B can be removed by an anisotropic etching process, thereby forming the first protective pattern 187A on the side surface of the gate spacer 164, as shown. Figure 41 As shown. In an embodiment, the first protective pattern 187A may include a high-k dielectric material. For example, the first protective pattern 187A may include at least one of Al2O3, CaF, Y2O3, ZrO2, HfO2 and / or MgO.

[0200] Next, a connection electrode 199 for connecting the lower source / drain pattern 150A and the upper source / drain pattern 150B can be formed by photolithography and etching processes.

[0201] First, such as Figure 42As shown, a first hard mask HM1 can be formed covering the gate structure 160 and the source / drain pattern 150, or overlapping with the gate structure 160 and the source / drain pattern 150. The first hard mask HM1 can then be patterned to expose the upper surface of the upper source / drain pattern 150B on which the connection electrode 199 will be formed. Subsequently, a third groove RC3 can be formed by an anisotropic etching process, penetrating the upper source / drain pattern 150B in a third direction D3 or extending into the upper source / drain pattern 150B and recessed to a predetermined depth into the lower source / drain pattern 150A. In an embodiment, the first protective pattern 187A can have low etch selectivity relative to the etching material. Therefore, in the process of forming the third groove RC3, the gate spacer 164 and the upper etch stop film 185B disposed on the side surface of the gate spacer 164 can be protected from damage by the etching material. Subsequently, the connection electrode 199 can be formed by filling the third groove RC3 with a conductive material (see [link to documentation]). Figure 43 ).

[0202] Next, as Figure 43 As shown, a second hard mask HM2 can be formed covering the gate structure 160 and the source / drain pattern 150, or overlapping with the gate structure 160 and the source / drain pattern 150. The second hard mask HM2 can then be patterned to expose the upper surface of the upper source / drain pattern 150B on which the upper contact electrode 191 will be formed. Subsequently, a fourth groove RC4 can be formed by an anisotropic etching process to recess to a predetermined depth into the lower source / drain pattern 150A. In the process of forming the fourth groove RC4, the gate spacer 164 and the upper etch stop film 185B disposed on the side surface of the gate spacer 164 can be protected from damage by the etching material.

[0203] Then, as Figure 44 As shown, the fourth groove RC4 can be filled with conductive material to form the upper contact electrode 191.

[0204] Next, as Figure 45 As shown, a portion of the upper contact electrode 191 and the connecting electrode 199 can be re-etched using a back etching process to form the fifth groove RC5. In this case, the upper contact electrode 191 and the connecting electrode 199 can be etched so that their upper surfaces are positioned between the upper and lower surfaces of the main gate structure 160M.

[0205] like Figure 46 As shown, a portion of the first protective pattern 187A can be etched. In this embodiment, compared to the upper contact electrode 191 or the connecting electrode 199, an etching material with higher etching selectivity relative to the first protective pattern 187A can be used to etch the first protective pattern 187A. Therefore, as Figure 46As shown, a portion of the first protective pattern 187A, which is positioned at a height higher than the upper surface of the upper contact electrode 191 or the connecting electrode 199, can be removed from the entire area of ​​the first protective pattern 187A.

[0206] and Figure 46 The difference shown in the figure allows for the complete removal of the first protective pattern 187A. In this case, in the reference... Figure 45 In the process of etching the upper contact electrode 191 and the connecting electrode 199, the upper contact electrode 191 and the connecting electrode 199 can be etched such that their upper surfaces are positioned at a lower horizontal height than the upper surface of the upper etch stop film 185B positioned on the upper surface of the upper source / drain pattern 150B.

[0207] Next, a second protective pattern 187B can be conformally formed on the inner surface of the fifth groove RC5. First, as... Figure 47 As shown, the second protective pattern 187A can be formed to completely cover the upper surface of the capping layer 166, the upper surface and the side surface of the gate spacer 164, or to completely overlap with the upper surface of the capping layer 166, the upper surface of the gate spacer 164, and the side surface of the gate spacer 164. Subsequently, through an anisotropic etching process, a portion of the second protective pattern 187B disposed on the upper surface of the capping layer 166, the upper surface of the gate spacer 164, the upper surface of the upper contact electrode 191, and the upper surface of the connecting electrode 199 can be removed to form the second protective pattern 187B on the inner surface of the fifth groove RC5, as shown. Figure 48 As shown. In an embodiment, the second protective pattern 187B may include a high-k dielectric material. For example, the second protective pattern 187B may include at least one of SiOCN, SiCN, SiBCN, and BN.

[0208] like Figure 49 As shown, the fifth groove RC5 can be filled with a conductive material. In an embodiment, the upper surfaces of the upper contact electrode 191 and the connecting electrode 199 can be disposed on the same plane as the upper surfaces of the cover layer 166 and the gate spacer 164.

[0209] According to an embodiment, at least a portion of the first protective pattern 187A, which includes a high-k dielectric material, can be removed, and a second protective pattern 187B, which includes a low-k dielectric material, can be formed thereon. Therefore, the parasitic capacitance around the connection electrode 199 or the upper contact electrode 191 can be reduced, thereby improving the electrical characteristics of the semiconductor device according to the embodiment.

[0210] Although some embodiments of this disclosure have been described in detail, the scope of this disclosure is not limited to these embodiments. Various changes and modifications made by those skilled in the art using the basic concept of this disclosure as defined in the appended claims should be interpreted as falling within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; A lower trench pattern, wherein the lower trench pattern is located on the surface of the substrate; An upper groove pattern, wherein the upper groove pattern is located on the lower groove pattern; A gate structure extending around the lower channel pattern and the upper channel pattern; Lower source / drain pattern, the lower source / drain pattern being located on the sidewall of the lower channel pattern; Upper source / drain pattern, wherein the upper source / drain pattern is located on the sidewall of the upper channel pattern; A connecting electrode electrically connects the first upper source / drain pattern in the upper source / drain pattern to the first lower source / drain pattern in the lower source / drain pattern; as well as A protective pattern is located between the gate structure and the connection electrode. The protective pattern includes a first protective pattern and a second protective pattern located on the first protective pattern. The second protective pattern includes a second insulating material, which has a second dielectric constant that is less than the first dielectric constant of the first insulating material of the first protective pattern.

2. The semiconductor device according to claim 1, wherein, The first upper source / drain pattern and the first lower source / drain pattern are spaced apart from each other, and The air gap is located between the first upper source / drain pattern and the first lower source / drain pattern.

3. The semiconductor device according to claim 2, further comprising: An intermediate insulating pattern is located between the upper channel pattern and the lower channel pattern. Wherein, the intermediate insulating pattern is located on one side of the connecting electrode, and The air gap is located between the intermediate insulating pattern and the connecting electrode.

4. The semiconductor device according to claim 2, further comprising: A gate spacer, the gate spacer being located on a side surface of the gate structure; as well as An upper etch stop film is provided, the upper etch stop film being located on at least a portion of the gate spacer and on the first upper source / drain pattern. The upper etch stop film is located between the first upper source / drain pattern and the air gap.

5. The semiconductor device according to claim 4, further comprising: A lower etch stop film is provided, which is located on a portion of the first lower source / drain pattern. The upper etch stop film is located between the lower etch stop film and the air gap.

6. The semiconductor device according to claim 1, further comprising: The main gate structure is located on the upper channel pattern. The first protective pattern is located between the lower side of the main gate structure and the connection electrode, and the second protective pattern is located between the upper side of the main gate structure and the connection electrode.

7. The semiconductor device according to claim 1, wherein, The first protective pattern and the second protective pattern extend in a first direction perpendicular to the surface of the substrate, and Wherein, the width of the second protective pattern in the second direction is greater than or equal to the width of the first protective pattern in the second direction, wherein the second direction is parallel to the surface of the substrate and perpendicular to the first direction.

8. The semiconductor device according to claim 7, wherein, The ratio of the length of the second protective pattern extending in the first direction to the length of the first protective pattern extending in the first direction is greater than or equal to 1 and less than or equal to 5.

9. The semiconductor device according to claim 7, wherein, The connecting electrode extends into the first upper source / drain pattern in the first direction, and the end of the connecting electrode contacts the first lower source / drain pattern.

10. The semiconductor device according to claim 7, wherein, The connecting electrode includes: a first portion overlapping the first protective pattern in the second direction, and a second portion overlapping the second protective pattern in the second direction. Wherein, the width of the first part in the second direction is greater than the width of the second part in the second direction.

11. The semiconductor device according to claim 1, further comprising: An upper contact electrode is provided, wherein the upper contact electrode is located on the second upper source / drain pattern in the upper source / drain pattern, and the second upper source / drain pattern is adjacent to the first upper source / drain pattern. The protective pattern is located between the upper contact electrode and the gate structure.

12. The semiconductor device according to claim 1, wherein, The first upper source / drain pattern and the first lower source / drain pattern are spaced apart from each other, and The semiconductor device further includes an interlayer insulating layer located between the first upper source / drain pattern and the first lower source / drain pattern. The interlayer insulating layer includes SiO2, or an insulating material with a dielectric constant less than that of SiO2.

13. The semiconductor device according to claim 1, wherein, The first protective pattern includes at least one of Al2O3, CaF, Y2O3, ZrO2, HfO2, or MgO.

14. The semiconductor device according to claim 1, wherein, The dielectric constant of the second insulating material included in the second protective pattern is smaller than that of SiO2.

15. The semiconductor device according to claim 1, wherein, The second protective pattern includes at least one of SiOC, SiCN, SiBCN, or BN.

16. A semiconductor device, the semiconductor device comprising: Substrate; A lower trench pattern, wherein the lower trench pattern is located on the surface of the substrate; An upper groove pattern, wherein the upper groove pattern is located on the lower groove pattern; A gate structure extending around the lower channel pattern and the upper channel pattern; Lower source / drain pattern, the lower source / drain pattern being located on the sidewall of the lower channel pattern; Upper source / drain pattern, wherein the upper source / drain pattern is located on the sidewall of the upper channel pattern; A connecting electrode electrically connects the first upper source / drain pattern in the upper source / drain pattern to the first lower source / drain pattern in the lower source / drain pattern; as well as A protective pattern is located between a first portion of the side surface of the gate structure and the connection electrode. The first air gap is located between the connecting electrode and the second portion of the side surface of the gate structure.

17. The semiconductor device according to claim 16, wherein, The first upper source / drain pattern and the first lower source / drain pattern are spaced apart from each other, and The second air gap is located between the first upper source / drain pattern and the first lower source / drain pattern.

18. The semiconductor device of claim 16, further comprising: A gate spacer, the gate spacer being located on the side surface of the gate structure; as well as An upper etch stop film is provided, the upper etch stop film being located on at least a portion of the gate spacer and on the first upper source / drain pattern. The upper etch stop film is located between the first upper source / drain pattern and the first air gap.

19. The semiconductor device of claim 16, further comprising: An upper contact electrode is provided, wherein the upper contact electrode is located on the second upper source / drain pattern in the upper source / drain pattern, and the second upper source / drain pattern is adjacent to the first upper source / drain pattern. The protective pattern is located between the upper contact electrode and the gate structure.

20. A semiconductor device, the semiconductor device comprising: Substrate; A lower trench pattern, wherein the lower trench pattern is located on the surface of the substrate; An upper groove pattern, wherein the upper groove pattern is located on the lower groove pattern; An intermediate insulating pattern is located between the upper channel pattern and the lower channel pattern; A gate structure extending around the lower channel pattern and the upper channel pattern; A gate spacer, the gate spacer being located on a portion of the side surface of the gate structure; Lower source / drain pattern, the lower source / drain pattern being located on the sidewall of the lower channel pattern; Upper source / drain pattern, wherein the upper source / drain pattern is located on the sidewall of the upper channel pattern; A connecting electrode extends in a first direction perpendicular to the surface of the substrate into a first upper source / drain pattern in the upper source / drain pattern, and has an end electrically connected to a first lower source / drain pattern in the lower source / drain pattern; An upper contact electrode is located on the upper surface of a second upper source / drain pattern in the upper source / drain pattern, the second upper source / drain pattern being adjacent to the first upper source / drain pattern, wherein the upper contact electrode extends into the second upper source / drain pattern. as well as A protective pattern is provided, wherein the protective pattern is located between the gate spacer and the connection electrode, and between the gate spacer and the upper contact electrode. The protective pattern includes a first protective pattern and a second protective pattern located on the first protective pattern. The second protective pattern includes an insulating material with a dielectric constant lower than that of the first protective pattern.

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