Semiconductor device

Abstract

There is provided a semiconductor device including: a base pattern; a channel pattern on an upper surface of the base pattern; a gate structure on an upper surface of the base pattern; a first source / drain pattern on a first side of the gate structure; a second source / drain pattern on a second side of the gate structure; a first source / drain pad between the first source / drain pattern and the gate structure; a second source / drain pad between the second source / drain pattern and the gate structure; and a backside plug in the base pattern, where the backside plug is electrically connected to the first source / drain pattern, where an upper end of the first source / drain pad is between the first source / drain pattern and the gate structure, and where a lower end of the first source / drain pad is between an upper surface of the base pattern and a lower surface of the base pattern.

Description

Technical Field

[0001] The example implementation involves semiconductor devices. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor is proposed, wherein a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate, and the gate is formed on the surface of the multi-channel active pattern.

[0003] Meanwhile, in order to address the wiring complexity that occurs on the front side of the field-effect transistor and prevent excessive voltage drop, a back-side power distribution network (BSPDN) is introduced, with at least a portion of the back-end process (BEOL) formed on the back side of the field-effect transistor.

[0004] Semiconductor devices may need to be reliably manufactured to meet consumers' demands for superior performance. However, as semiconductor devices become highly integrated, the likelihood of short circuits or leakage currents may increase. Summary of the Invention

[0005] One aspect of the present invention can provide a semiconductor device that reduces (e.g., prevents) a possible short circuit between the gate structure and the back plug by placing a portion of the source / drain region (e.g., a source / drain pad) between the back plug and the gate structure.

[0006] The technical tasks to be achieved by the presented example embodiments are not limited to those described above, and those skilled in the art can infer other technical tasks from the following example embodiments.

[0007] According to one aspect, a semiconductor device is provided, the semiconductor device comprising: a substrate pattern; a channel pattern on a front side of the substrate pattern corresponding to an upper surface of the substrate pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the substrate pattern; a gate structure on the upper surface of the substrate pattern, wherein the gate structure includes a gate insulating film and a gate electrode, and at least a portion of the gate structure is between adjacent channel patterns in the channel pattern; a first source / drain pattern on a first side of the gate structure; a second source / drain pattern on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in a second direction intersecting the first direction, wherein the second direction is parallel to the upper surface of the substrate pattern; and a first source / drain pad in the second direction on the first source. Between the drain pattern and the gate structure; a second source / drain pad, in a second direction between the second source / drain pattern and the gate structure; a back plug in the substrate pattern, wherein the back plug is electrically connected to the first source / drain pattern; and a placeholder in the substrate pattern, wherein the placeholder is inside the second source / drain pad, wherein the upper end of the first source / drain pad is between the first source / drain pattern and the gate structure in a second direction, and the lower end of the first source / drain pad is between the upper surface of the substrate pattern and the back side of the substrate pattern, the back side of the substrate pattern corresponding to the lower surface of the substrate pattern, the lower surface of the substrate pattern corresponding to the upper surface of the substrate pattern in a first direction, wherein the upper end of the first source / drain pad is corresponding to the lower end of the first source / drain pad in a first direction.

[0008] According to one aspect, a semiconductor device is provided, the semiconductor device comprising: a substrate pattern; a channel pattern on a front side of the substrate pattern corresponding to an upper surface of the substrate pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the substrate pattern; a gate structure on the upper surface of the substrate pattern, wherein the gate structure includes a gate insulating film and a gate electrode, and at least a portion of the gate structure is between adjacent channel patterns in the channel pattern; a first source / drain pattern on a first side of the gate structure; a first source / drain pad between the first source / drain pattern and the gate structure in a second direction parallel to the upper surface of the substrate pattern; and a back-side plug between the back side of the substrate pattern and the first source / drain pattern in a first direction, the back side of the substrate pattern corresponding to a lower surface of the substrate pattern, wherein the lower surface of the substrate pattern is opposite to the upper surface of the substrate pattern in the first direction, wherein the back-side plug is electrically connected to the first source / drain pattern, wherein the back-side plug is in contact with the substrate pattern, and wherein the first source / drain pad extends along a sidewall of the gate structure and extends into the substrate pattern in the first direction.

[0009] According to one aspect, a semiconductor device is provided, the semiconductor device comprising: a substrate pattern; a channel pattern on a front side of the substrate pattern corresponding to an upper surface of the substrate pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the substrate pattern; a gate structure on the upper surface of the substrate pattern, wherein the gate structure is between adjacent channel patterns in the channel pattern; a first source / drain pattern on a first side of the gate structure; a second source / drain pattern on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in a second direction parallel to the upper surface of the substrate pattern; a back-side plug below the first source / drain pattern, wherein the back-side plug is electrically connected to the first source / drain pattern; a placeholder below the second source / drain pattern, wherein the placeholder is electrically connected to the second source / drain pattern; a first source / drain pad in a second direction between the first source / drain pattern and the gate structure; and a second source / drain pad in a second direction between the second source / drain pattern and the gate structure, wherein the first source / drain pad overlaps with the back-side plug in the second direction.

[0010] Additional aspects of the exemplary implementations will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of this disclosure.

[0011] According to the example implementation, the possibility of short circuits or current leakage occurring between components of a semiconductor device can be reduced. Attached Figure Description

[0012] These and / or other aspects, features, and advantages of the present invention will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, wherein:

[0013] Figure 1 It is a layout diagram of a semiconductor device according to an example implementation;

[0014] Figure 2 It shows along Figure 1 A diagram of the cross section intercepted by line A-A';

[0015] Figures 3 to 16 This is a diagram illustrating intermediate operations of a method for manufacturing a semiconductor device according to an example embodiment; and

[0016] Figures 17 to 19 This is a diagram illustrating intermediate operations used to explain a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0017] The terms or words used in the specification and claims may not be limited to their dictionary meanings. Terms or words may be interpreted using meanings and concepts consistent with the technical field of this disclosure. The exemplary embodiments described in this specification and the configurations shown in the accompanying drawings are merely exemplary embodiments of this disclosure. Therefore, various equivalents and modifications may exist.

[0018] In the following description, unless the context clearly specifies otherwise, singular expressions include plural expressions. It will be understood that when an element (e.g., a first element) is "(operably or communicatively) coupled" or "(operably or communicatively) connected to" another element (e.g., a second element), the element may be directly coupled to / directly connected to the other element, and an intermediary element (e.g., a third element) may exist between the element and the other element. The terms "have," "may have," "include," "may include," "contain," and "may contain" as used herein indicate the presence of the corresponding feature (e.g., an element such as a numerical value, function, operation, or part), without excluding the presence of additional features. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] The terms "first," "second," etc., can be used to describe various components. However, components are not limited by terminology, and terms can be used to distinguish one component from another. Within the scope of the technical concept of this disclosure, a first component can be named a second component. Similarly, a second component can be named a first component. Furthermore, the shape and size of a component may be exaggerated to emphasize clarity.

[0020] Furthermore, in the following description, terms such as upper side, top, lower side, bottom, side, front side, and rear side may be used based on the orientation shown in the accompanying drawings. If the orientation of the object changes, it may be expressed differently.

[0021] In the following description, exemplary embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0022] Figure 1 This is a layout diagram of the semiconductor device 10 according to an example embodiment. Figure 2 It shows along Figure 1 A diagram of the cross section taken by line A-A'.

[0023] Reference Figure 1 and Figure 2 The semiconductor device 10 may include a first active region AR1, a second active region AR2, and a field region FR.

[0024] According to some example embodiments, a first direction D1 may indicate a direction perpendicular to the front side 20a (e.g., the front surface or the top surface) of the substrate pattern 20. A second direction D2 may indicate a direction intersecting the first direction D1. The second direction D2 may be parallel to the front side 20a (e.g., the front surface or the top surface) of the substrate pattern 20. A third direction D3 may indicate a direction intersecting the first direction D1 and the second direction D2. The third direction D3 may be parallel to the front side 20a (e.g., the front surface or the top surface) of the substrate pattern 20. The first direction D1 and the second direction D2 may be perpendicular to each other, the second direction D2 and the third direction D3 may be perpendicular to each other, and the third direction D3 and the first direction D1 may be perpendicular to each other.

[0025] According to some example implementations, the first active region AR1 and the second active region AR2 may each extend in the second direction D2. The first active region AR1 and the second active region AR2 may be spaced apart from each other in the third direction D3. The first active region AR1 and the second active region AR2 may be separated by a field area FR.

[0026] According to some example embodiments, the field region FR can be placed (on the third direction D3) between the first active region AR1 and the second active region AR2. The field region FR can be adjacent to the first active region AR1 and the second active region AR2. The field region FR can have a shallow trench isolation (STI) structure. However, the example embodiments of this disclosure are not limited thereto. For example, the field region FR can have a deep trench (e.g., it can be defined by a deep trench).

[0027] According to some example embodiments, a device separator (not shown) may be placed around (adjacent to) a first active region AR1 and a second active region AR2. The portion of the device separator between the first active region AR1 and the second active region AR2 may be a field region FR. For example, the portion where the channel region of a transistor (which may be an example of semiconductor device 10) is formed may be designated as the active region, and the portion formed in the active region that separates the channel region of the transistor may be designated as the field region FR. The active region may be a portion forming a fin pattern or nanosheet, which serves as the channel region of the transistor, and the field region FR may be a region where no fin pattern or nanosheet is formed.

[0028] According to some exemplary embodiments, the first active region AR1 and the second active region AR2 can be p-channel metal-oxide-semiconductor (PMOS) formation regions. However, the exemplary embodiments of this disclosure are not limited thereto. For example, the first active region AR1 and the second active region AR2 can be n-channel metal-oxide-semiconductor (NMOS) formation regions. For example, one of the first active region AR1 and the second active region AR2 can be a PMOS formation region and the other can be an NMOS formation region.

[0029] According to some exemplary embodiments, semiconductor device 10 may include fin field-effect transistors and / or nanosheet field-effect transistors, but the exemplary embodiments of this disclosure are not limited thereto. The semiconductor device 10 shown in the figures is merely an exemplary embodiment and is not limited thereto.

[0030] According to some example embodiments, semiconductor device 10 may include, for example, tunneling transistors (tunneling field-effect transistors (FETs)), three-dimensional transistors, and / or vertical transistors (vertical FETs). In some embodiments, semiconductor device 10 may include planar transistors. Semiconductor device 10 may be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures. Semiconductor device 10 according to examples may include bipolar junction transistors and / or lateral double-diffused transistors (LDMOS).

[0031] Semiconductor device 10 according to some example embodiments may include a substrate pattern 20, a plurality of channel patterns CH, a gate structure GS, a first source / drain pattern 110, a second source / drain pattern 210, a front plug (front wiring path 82 and front contact 83), a back plug 60, a front wiring pattern 41 and a back wiring pattern 30.

[0032] According to some example implementations, the substrate pattern 20 may be placed on the back-side wiring pattern 30. The substrate pattern 20 may be placed (in the first direction D1) between the back-side wiring pattern 30 and the gate structure GS.

[0033] According to some example embodiments, the substrate pattern 20 may include a semiconductor material. For example, the substrate pattern 20 may include silicon or silicon-on-insulator (SOI). In some embodiments, the substrate pattern 20 may include, but is not limited to, silicon-germanium, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide. For example, the substrate pattern 20 may include silicon oxide, silicon nitride, silicon carbide, silicon nitride, and / or low-k materials.

[0034] According to some exemplary embodiments, the substrate pattern 20 may extend in a second direction D2. A device insulator may be disposed between two substrate patterns 20 spaced apart along a third direction D3. The substrate pattern 20 may have a pin shape. According to some exemplary embodiments, the substrate pattern 20 and the device insulator may contain the same insulating material. In this case, the boundary between the substrate pattern 20 and the device insulator may be indistinguishable, and the substrate pattern 20 and the device insulator may be considered as a single insulating layer. For example, the substrate pattern 20 and the device insulator may be joined to form an integrated (monolithic) structure.

[0035] According to some example embodiments, a plurality of channel patterns CH can be placed on a substrate pattern 20 (front side, front surface, or upper surface). The plurality of channel patterns CH can be spaced apart from the substrate pattern 20 in a first direction D1. The plurality of channel patterns CH can be arranged on the front side 20a (e.g., front surface or upper surface) of the substrate pattern 20. The channel patterns CH in the plurality of channel patterns CH can be spaced apart from each other in the first direction D1.

[0036] The accompanying drawings illustrate a plurality of channel patterns CH comprising four nanosheets; however, the drawings are for illustrative purposes only, and exemplary embodiments of this disclosure are not limited thereto. For example, the plurality of channel patterns CH may comprise one, two, three, or more than four nanosheets.

[0037] According to some example embodiments, a plurality of channel patterns CH may have a gate electrode 71 and a gate insulating film 72 disposed between adjacent channel patterns CH in the channel patterns CH. For example, the gate electrode 71 and the gate insulating film 72 may be (in the first direction D1) between adjacent channel patterns CH in the plurality of channel patterns CH. Although not shown, the gate insulating film 72 may be placed on the uppermost channel pattern CH among the plurality of channel patterns CH. The gate electrode 71 may be on the uppermost channel pattern CH among the plurality of channel patterns CH. The gate spacer 423 may be on the uppermost channel pattern CH among the plurality of channel patterns CH. The gate spacer 423 may extend around (e.g., at least partially around) the uppermost gate electrode 71 among the gate electrodes 71. For example, the gate spacer 423 may be on the lower surface and side surface of the uppermost gate electrode 71 among the gate electrodes 71.

[0038] According to some example embodiments, the multiple channel patterns CH may include elemental semiconductor materials such as silicon or germanium. In some embodiments, the multiple channel patterns CH may include compound semiconductors. For example, the multiple channel patterns CH may include group IV-IV compound semiconductors and / or group III-V compound semiconductors. For example, group IV-IV compound semiconductors may be binary compounds, ternary compounds, or compounds doped with group IV elements including, for example, carbon, silicon, germanium, and / or tin. For example, group III-V compound semiconductors may be binary compounds, ternary compounds, or quaternary compounds formed by combining, for example, aluminum, gallium, and / or indium, which are group III elements, with, for example, phosphorus, arsenic, and / or antimony, which are group V elements.

[0039] According to some example embodiments, the gate structure GS may be placed on the front side 20a (e.g., the front surface or the top surface) of the substrate pattern 20. The semiconductor device 10 may include a plurality of gate structures GS. Each of the plurality of gate structures GS may extend in a third direction D3. The gate structure GS may be placed on a first active pattern AP1 and a second active pattern AP2. For example, the plurality of gate structures GS may be positioned to intersect with the first active pattern AP1 and the second active pattern AP2 (overlapping in a first direction D1).

[0040] According to some example embodiments, the gate electrode 71 may be arranged to extend in the third direction D3. The gate electrode 71 may be positioned (in the second direction D2) between the first source / drain pattern 110 and the second source / drain pattern 210. Adjacent gate electrodes 71 may be arranged spaced apart from each other in the second direction D2.

[0041] According to some example embodiments, the gate electrode 71 may be (electrically) connected to the gate contact 81. The gate electrode 71 may include a conductive material. In this disclosure, the conductive material may include, for example, a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. For example, the conductive material may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride. (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), and / or vanadium (V). However, this disclosure is not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidized forms of the above substances, but this disclosure is not limited thereto.

[0042] According to some example embodiments, the gate electrode 71 may be placed on both sides of the first source / drain pattern 110 (e.g., opposite sides in the second direction D2) and may be placed on both sides of the second source / drain pattern 210 (e.g., opposite sides in the second direction D2). At least one of the gate electrodes 71 may be a gate electrode 71 used as the gate of a transistor. In some embodiments, some of the gate electrodes 71 may be dummy electrodes.

[0043] According to some example embodiments, the gate insulating film 72 may extend around at least a portion of the gate electrode 71 (e.g., cover at least a portion of the gate electrode 71). The gate insulating film 72 may include an insulating material. In this disclosure, the insulating material may include, for example, silicon oxide, silicon germanium oxide, germanium oxide, silicon nitride, silicon nitride, high-k materials having a dielectric constant greater (higher) than silicon oxide and / or low-k materials having a dielectric constant smaller (lower) than silicon oxide. High-k materials may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. However, high-k materials are not limited thereto. Low-k materials can include, for example, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonil silazane (TOSZ), fluorosilicate glass (FSG), and / or polyimide nanofoams such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, and / or mesoporous silica. However, low-k materials are not limited to these.

[0044] According to some example embodiments, the gate insulating film 72 may include different insulating materials. For example, the figures show the gate insulating film 72 as a single film, but this is merely for illustrative purposes, and the gate insulating film 72 may include multiple films. Although the figures show a single-layer gate insulating film 72, the gate structure GS may include spacers (not shown) located on the side (e.g., side surface) of the gate structure GS.

[0045] According to some exemplary embodiments, the first source / drain pattern 110 and the second source / drain pattern 210 may be disposed on opposite sides of the gate structure GS (e.g., one of the gate structures GS). For example, the first source / drain pattern 110 may be disposed on a first side of the gate structure GS, and the second source / drain pattern 210 may be disposed on a second side of the gate structure GS (in the second direction D2) opposite to the first side. For example, at least one of the gate structures GS may be disposed between the first source / drain pattern 110 and the second source / drain pattern 210 in the second direction D2.

[0046] According to some exemplary embodiments, the first source / drain pattern 110 and the second source / drain pattern 210 may have the same conductivity type. For example, the first source / drain pattern 110 and the second source / drain pattern 210 may be N-type or P-type. In exemplary embodiments, the first source / drain pattern 110 and the second source / drain pattern 210 may have different conductivity types. For example, the first source / drain pattern 110 or the second source / drain pattern 210 may be N-type, while the other may be P-type. In exemplary embodiments, each of the first source / drain pattern 110 and the second source / drain pattern 210 may include an impurity, and the impurity may vary depending on the conductivity type. For example, N-type may include N-type dopants, which are impurities such as phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi), and P-type may include P-type dopants, which are impurities such as boron (B) and / or gallium (Ga).

[0047] According to some example implementations, the semiconductor device 10 may include a front-side interlayer insulating film 50, a front-side plug (front-side wiring path 82 and front-side contact 83) and a gate contact 81.

[0048] According to some example embodiments, the front interlayer insulating film 50 may include a first front interlayer insulating film 51, a second front interlayer insulating film 52, a third front interlayer insulating film 53, and a gate capping layer 54. The first front interlayer insulating film 51 may be formed on a first source / drain pattern 110 and a second source / drain pattern 210, and the gate capping layer 54 may be formed on the gate structure GS. The second front interlayer insulating film 52 and the third front interlayer insulating film 53 may be sequentially formed on the first front interlayer insulating film 51 and / or the gate capping layer 54. The first front interlayer insulating film 51, the second front interlayer insulating film 52, the third front interlayer insulating film 53, and the gate capping layer 54 may include, for example, a silicon oxide layer and / or a silicon nitride layer (e.g., may be formed of a silicon oxide layer and / or a silicon nitride layer). Each of the first front interlayer insulating film 51, the second front interlayer insulating film 52, the third front interlayer insulating film 53, and the gate cap layer 54 may include the same material (e.g., may be formed of the same material) or may include different materials (e.g., may be formed of the same material).

[0049] According to some example embodiments, the front plug (front wiring path 82 and front contact 83) may be formed in the first front interlayer insulating film 51 and the second front interlayer insulating film 52. For example, the front wiring path 82 may be in the second front interlayer insulating film 52 (and may extend into the second front interlayer insulating film 52). For example, the front contact 83 may be in the first front interlayer insulating film 51 (and may extend into the first front interlayer insulating film 51).

[0050] According to some example embodiments, the front plug (front wiring path 82 and front contact 83) may include front wiring path 82 and front contact 83. The front plug (front wiring path 82 and front contact 83) may be electrically connected to the second source / drain pattern 210. The front contact 83 may contact the second source / drain pattern 210. The front wiring path 82 may be formed on the front contact 83. The front contact 83 and the front wiring path 82 may include a metallic material. In some embodiments, the front plug (e.g., the front contact 83) may be in the first front interlayer insulating film 51 and the second source / drain pattern 210 (extending into the first front interlayer insulating film 51 and the second source / drain pattern 210).

[0051] According to some example embodiments, the front wiring pattern 41 may be on the front plug (front wiring path 82 and front contact 83). For example, the front wiring pattern 41 may be in the third front interlayer insulating film 53 (e.g., it may extend into the third front interlayer insulating film 53). The front plug (front wiring path 82 and front contact 83) may be (electrically) connected to the front wiring pattern 41. Specifically, the front wiring pattern 41 may be connected to (contact) the front wiring path 82. The front wiring pattern 41 may be one of the signal lines that transmit electrical signals to the semiconductor device 10.

[0052] According to some example embodiments, the gate contact 81 may be formed in (within) the gate capping layer 54 and the second front side interlayer insulating film 52. For example, the gate contact 81 may extend into the gate capping layer 54 and the second front side interlayer insulating film 52.

[0053] According to some example embodiments, the gate contact 81 may be (electrically) connected to the gate electrode 71. For example, the gate contact 81 may be connected to the gate electrode 71 (e.g., the uppermost gate electrode 71) by extending into (e.g., penetrating) a portion of the front interlayer insulating film 50 (e.g., the gate cap layer 54 and the second front interlayer insulating film 52). The gate contact 81 may include a metallic material. The gate contact 81 may be (electrically) connected to the gate wiring pattern 42. The gate wiring pattern 42 may be on the gate contact 81. For example, the gate wiring pattern 42 may be (e.g., extending into) a third front interlayer insulating film 53.

[0054] According to some example embodiments, the back-side wiring pattern 30 may be one of the power lines supplying power to the semiconductor device 10. The back-side wiring pattern 30 may extend in a second direction D2. The back-side wiring pattern 30 may have a width in a third direction D3.

[0055] According to some exemplary embodiments, the back-side wiring pattern 30 may be placed on the back side 20b (e.g., the back surface or lower surface) of the substrate pattern 20. The back-side wiring pattern 30 may be (electrically) connected to the first source / drain pattern 110 via a back-side plug 60. In the figures, the back-side wiring pattern 30 is shown as a single film, but exemplary embodiments of the invention are not limited thereto. For example, the back-side wiring pattern 30 may include a multilayer structure comprising a barrier film and a filler film.

[0056] According to some example embodiments, the back-side wiring pattern 30 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), and titanium carbide (TiC). Tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof. However, the backside wiring pattern 30 is not limited to these.

[0057] According to some example embodiments, the semiconductor device 10 may include a back-side plug 60. The back-side plug 60 may extend into a substrate pattern 20 (e.g., from the back side 20b of the substrate pattern 20 toward a first source / drain pattern 110) to be (electrically) connected to the first source / drain pattern 110. The back-side plug 60 may include a metallic material. The back-side plug 60 may be (electrically) connected to a back-side wiring pattern 30. The back-side wiring pattern 30 may be electrically connected to the first source / drain pattern 110 via the back-side plug 60.

[0058] According to some exemplary embodiments, the back-side plug 60 may include a power path 61 and a back-side contact 62 (on the upper surface of the power path 61). The power path 61 may be (electrically) connected to the back-side wiring pattern 30. The power path 61 may abut (contact) the back-side wiring pattern 30. The width of the power path 61 in the second direction D2 may be greater than the width of the back-side contact 62 in the second direction D2.

[0059] According to some exemplary embodiments, the back contact 62 may protrude from the upper surface of the power path 61. The back contact 62 may be electrically connected to the power path 61. The back contact 62 may be electrically connected to the first source / drain pattern 110. At least a portion of the back contact 62 may contact the first source / drain pattern 110.

[0060] According to some exemplary embodiments, the power path 61 and the back-side contact 62 may comprise a metallic material. In some embodiments, the power path 61 and the back-side contact 62 may comprise different metallic materials. For example, the resistivity of the back-side contact 62 may be less than the resistivity of the power path 61. Because the resistivity of the back-side contact 62 in contact with the first source / drain pattern 110 is small (e.g., less than the resistivity of the power path 61), the voltage drop can be reduced and the power loss can be reduced. The performance of the semiconductor device 10 can be improved by increasing the current transport efficiency from the back-side wiring pattern 30 to the first source / drain pattern 110. However, this is merely an exemplary embodiment, and the characteristics of the metallic materials contained in the power path 61 and the back-side contact 62 are not limited thereto.

[0061] According to some example embodiments, the back contact 62 may include a first contact region 62a and a second contact region 62b (which is the region other than the first contact region 62a). The second contact region 62b may be (electrically) connected to a power path 61 (may be in contact with the power path 61). The first contact region 62a may be positioned (in a first direction D1) between the second contact region 62b and the first source / drain pattern 110. In some embodiments, the first contact region 62a may protrude from the second contact region 62b toward the first source / drain pattern 110 in the first direction D1.

[0062] According to some exemplary embodiments, the first source / drain pattern 110 may extend around (e.g., at least partially surround) the first contact region 62a. Since the first contact region 62a is (at least partially) surrounded by the first source / drain pattern 110, the contact area between the back-side plug 60 and the first source / drain pattern 110 can be increased. As the contact area between the back-side plug 60 and the first source / drain pattern 110 increases, the contact resistance between the back-side plug 60 and the first source / drain pattern 110 can be reduced. This can improve the current transfer efficiency from the back-side wiring pattern 30 to the first source / drain pattern 110, thereby improving the performance of the semiconductor device 10.

[0063] According to some exemplary embodiments, the first source / drain pad 120, which will be described later, may extend around (e.g., at least partially surround) the second contact region 62b. The second contact region 62b may be surrounded laterally by the first source / drain pad 120 and underside by a power path 61. For example, the power path 61 may be on the underside of the second contact region 62b (e.g., in contact with the underside of the second contact region 62b), and the first source / drain pad 120 may be on the sideside of the second contact region 62b (e.g., in contact with the sideside of the second contact region 62b).

[0064] According to some example embodiments, the semiconductor device 10 may include a first source / drain pad 120. At least a portion of the first source / drain pad 120 may be disposed (in the second direction D2) between a first source / drain pattern 110 and a (adjacent) gate structure GS, and (in the second direction D2) between the first source / drain pattern 110 and a plurality of (adjacent) channel patterns CH. A portion (e.g., the remainder) of the first source / drain pad 120 may be in a substrate pattern 20 (e.g., may extend into the substrate pattern 20). The first source / drain pad 120 may extend around the first source / drain pattern 110 (e.g., at least partially around the first source / drain pattern 110). The first source / drain pad 120 may be placed on the side surface (e.g., side surface) of the channel pattern CH. The first source / drain pad 120 may be on the side surface of the first source / drain pattern 110. The first source / drain pad 120 may include, for example, silicon (Si) and / or silicon germanium (SiGe), but is not limited thereto.

[0065] According to some example implementations, at least a portion of the first source / drain pad 120 may be conformally arranged relative to the sides (e.g., side surfaces) of the plurality of channel patterns CH. For example, the boundary between the first source / drain pad 120 and the first source / drain pattern 110 may be (substantially) parallel to the boundary between the first source / drain pad 120 and the plurality of channel patterns CH.

[0066] According to some example embodiments, the outer surfaces of the first source / drain pad 120 and the first source / drain pattern 110 can have various shapes. For example, the outer surface of the first source / drain pad 120 can have a rhomboid shape, a circular shape, or a rectangular shape. For example, the outer surface of the first source / drain pattern 110 can have a rhomboid shape, a circular shape, or a rectangular shape.

[0067] According to some example embodiments, the first source / drain pad 120 may have the same conductivity type as the first source / drain pattern 110. The first source / drain pad 120 may include impurities of the same type as the first source / drain pattern 110. If the first source / drain pattern 110 is P-type, then the first source / drain pad 120 may also be P-type. When the first source / drain pattern 110 is N-type, the first source / drain pad 120 may also be N-type. However, the type and conductivity type of the boundary between the first source / drain pattern 110 and the first source / drain pad 120 are not limited thereto.

[0068] The first source / drain pad 120 may have a different composition than the first source / drain pattern 110. For example, the impurity concentration of the first source / drain pad 120 may be less than (lower than) the impurity concentration of the first source / drain pattern 110.

[0069] According to some example embodiments, one end 120a (e.g., upper end 120a) of the first source / drain pad 120 (in the first direction D1) may contact the front interlayer insulating film 50 (e.g., the first front interlayer insulating film 51). One end 120a of the first source / drain pad 120 may be disposed between adjacent channel patterns CH in the second direction D2. One end 120a of the first source / drain pad 120 may be positioned further away from the back side 20b of the substrate pattern 20 in the first direction D1 than the other end 120b (e.g., lower end 120b) of the first source / drain pad 120. The other end 120b of the first source / drain pad 120 may be in the substrate pattern 20. The other end 120b of the first source / drain pad 120 may be on the upper surface of the power path 61 (e.g., may contact the upper surface of the power path 61).

[0070] According to some exemplary embodiments, one end 120a of the first source / drain pad 120 may be disposed on the same plane as one end of the first source / drain pattern 110. For example, one end 120a of the first source / drain pad 120 (e.g., upper surface or upper end) may be coplanar with one end (e.g., upper surface or upper end) of the first source / drain pattern 110. Furthermore, one end 120a of the first source / drain pad 120 may be disposed on the same plane (e.g., lower side or lower surface) as one side of the front interlayer insulating film 50 (e.g., the first front interlayer insulating film 51). One end 120a of the first source / drain pad 120 may be located (in the second direction D2) between the first source / drain pattern 110 and the (adjacent) gate structure GS.

[0071] When the distance between the back-side plug 60 and the (corresponding) gate structure GS (e.g., adjacent gate structure GS) is close or there is no blocking member, this increases the possibility of short circuit or current leakage. Therefore, the first source / drain pad 120 can be placed between the (corresponding) gate structure GS (e.g., adjacent gate structure GS) and the back-side plug 60. However, this disclosure is not limited to this, and blocking members such as insulating materials can be further placed between the (corresponding) gate structure GS (e.g., adjacent gate structure GS) and the back-side plug 60.

[0072] According to some example embodiments, the other end 120b of the first source / drain pad 120 may be positioned within the substrate pattern 20. The first source / drain pad 120 may be placed between the substrate pattern 20 and the back plug 60. For example, the other end 120b of the first source / drain pad 120 may be between the substrate pattern 20 and the back plug 60. The other end 120b of the first source / drain pad 120 may be located between the front side 20a and the back side 20b of the substrate pattern 20. For example, the other end 120b of the first source / drain pad 120 may be on (contact with) the upper surface of the back plug 60 (e.g., power path 61).

[0073] According to some example embodiments, the other end 120b of the first source / drain pad 120 may be positioned closer to the back side 20b of the substrate pattern 20 than the (corresponding) gate structure GS (e.g., an adjacent gate structure GS). The distance between the other end 120b of the first source / drain pad 120 and the back side 20b of the substrate pattern 20 (in the first direction D1) may be less than the distance between the (corresponding) gate structure GS (e.g., an adjacent gate structure GS) and the back side 20b of the substrate pattern 20 (in the first direction D1). The distance between the other end 120b of the first source / drain pad 120 and the back side 20b of the substrate pattern 20 (in the first direction D1) may be less than the width (thickness) of the substrate pattern 20 in the first direction D1.

[0074] According to some exemplary embodiments, the other end 120b of the first source / drain pad 120 may be located between the (corresponding) gate structure GS (e.g., adjacent gate structure GS) and the power path 61 in the first direction D1. The other end 120b of the first source / drain pad 120 may be placed between the gate insulating film 72 at the lowest portion of the (corresponding) gate structure GS (e.g., adjacent gate structure GS) and one side of the power path 61. For example, the other end 120b of the first source / drain pad 120 may be located (in the first direction D1) between the lowermost gate insulating film 72 and the power path 61. The other end 120b of the first source / drain pad 120 may be located in the middle region (e.g., midpoint) of the back contact 62 in the first direction D1. However, the shape and arrangement of the first source / drain pad 120 are not limited thereto.

[0075] According to some exemplary embodiments, a first source / drain pad 120 may be disposed on one side of the first source / drain pattern 110 and on one side of the back contact 62. The first source / drain pad 120 may overlap with the first source / drain pattern 110 and the back contact 62 in a second direction D2. The first source / drain pad 120 may overlap with the first contact region 62a and the second contact region 62b in the second direction D2. The other end 120b of the first source / drain pad 120 may be (substantially) coplanar with the lower surface (e.g., the bottom) of the back contact 62 in a first direction D1.

[0076] According to some example embodiments, the semiconductor device 10 may include a second source / drain pad 220. At least a portion of the second source / drain pad 220 may be located (in the second direction D2) between the second source / drain pattern 210 and the (corresponding) gate structure GS (e.g., an adjacent gate structure GS), and (in the second direction D2) between the second source / drain pattern 210 and a plurality of channel patterns CH. Another portion of the second source / drain pad 220 may be located in (within) the substrate pattern 20. The second source / drain pad 220 may extend around (e.g., at least partially around) the second source / drain pattern 210. The second source / drain pad 220 may be disposed on the side surface (e.g., side surface) of the channel pattern CH. The second source / drain pad 220 may include, for example, silicon (Si) and / or silicon germanium (SiGe), but the second source / drain pad 220 is not limited thereto.

[0077] According to some example implementations, at least a portion of the second source / drain pad 220 may be conformally arranged relative to the sides (e.g., side surfaces) of the plurality of channel patterns CH. The boundary between the second source / drain pad 220 and the second source / drain pattern 210 may be (substantially) parallel to the boundary between the second source / drain pad 220 and the plurality of channel patterns CH.

[0078] According to some example embodiments, the outer surface of the second source / drain pad 220 and the outer surface of the second source / drain pattern 210 can have various shapes. For example, the outer surface of the second source / drain pad 220 can have a rhomboid shape, a circular shape, or a rectangular shape. For example, the outer surface of the second source / drain pattern 210 can have a rhomboid shape, a circular shape, or a rectangular shape.

[0079] According to some exemplary embodiments, the second source / drain pad 220 may have the same conductivity type as the second source / drain pattern 210. The second source / drain pad 220 may include impurities of the same type as the second source / drain pattern 210. When the second source / drain pattern 210 is P-type, the second source / drain pad 220 may also be P-type. When the second source / drain pattern 210 is N-type, the second source / drain pad 220 may also be N-type. However, the type and conductivity type of the boundary between the second source / drain pattern 210 and the second source / drain pad 220 are not limited thereto.

[0080] The second source / drain pad 220 may have a different composition than the second source / drain pattern 210. For example, the impurity concentration of the second source / drain pad 220 may be less than (lower than) the impurity concentration of the second source / drain pattern 210.

[0081] According to some exemplary embodiments, one end 221 (e.g., upper end or upper surface) of the second source / drain pad 220 (in the first direction D1) may contact the front interlayer insulating film 50 (e.g., the first front interlayer insulating film 51). One end 221 of the second source / drain pad 220 may be disposed between a plurality of adjacent channel patterns CH in the second direction D2. One end 221 of the second source / drain pad 220 may be positioned (in the first direction D1) further away from the back side 20b of the substrate pattern 20 than the other end 222 (e.g., lower end or lower surface) of the second source / drain pad 220.

[0082] According to some example embodiments, the other end 222 (e.g., the lower end or lower surface) of the second source / drain pad 220 may face the back side 20b of the substrate pattern 20. The other end 222 of the second source / drain pad 220 may be disposed on the opposite side (in the first direction D1) of one end 221 (e.g., the upper end or upper surface) of the second source / drain pad 220. The other end 222 of the second source / drain pad 220 may include the portion of the second source / drain pad 220 closest to the back side 20b of the substrate pattern 20.

[0083] According to some example embodiments, the second source / drain pad 220 may be located on the side surface (e.g., side surface) of the second source / drain pattern 210 and the side surface (e.g., side surface) of the second occupant 320, as will be described in detail below. The second source / drain pad 220 may be on the lower surface (e.g., lower end) of the second occupant 320 (e.g., covering or overlapping the lower surface of the second occupant 320). The second source / drain pad 220 may extend around the second source / drain pattern 210 and the second occupant 320 (e.g., at least partially surrounding the second source / drain pattern 210 and the second occupant 320). The second source / drain pad 220 may overlap with the second source / drain pattern 210 and the second occupant 320 in a second direction D2. The second source / drain pad 220 may overlap with the second source / drain pattern 210 and the second occupant 320 in a first direction D1. The second source / drain pad 220 may overlap with the back plug 60 in the second direction D2. The second source / drain pad 220 may overlap with the first contact region 62a, the second contact region 62b and the power path 61 in the second direction D2.

[0084] According to some exemplary embodiments, the first source / drain pad 120 and the second source / drain pad 220 may have the same conductivity type. For example, the first source / drain pad 120 and the second source / drain pad 220 may be N-type or P-type. In exemplary embodiments, the first source / drain pad 120 and the second source / drain pad 220 may have different conductivity types. For example, one of the first source / drain pad 120 and the second source / drain pad 220 may be N-type and the other may be P-type. In exemplary embodiments, the first source / drain pad 120 and the second source / drain pad 220 may each include impurities, and the impurities may vary depending on the conductivity type. For example, N-type may include N-type dopants, which are impurities including, for example, phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi), and P-type may include P-type dopants, which are impurities including, for example, boron (B) and / or gallium (Ga).

[0085] According to some example embodiments, the semiconductor device 10 may include a second berth 320. The second berth 320 may be placed inside the second source / drain pad 220. The second berth 320 may be (electrically) connected to the second source / drain pattern 210. For example, the second source / drain pattern 210 may be on the upper surface of the second berth 320.

[0086] According to some example embodiments, at least a portion of the second occupant 320 may be surrounded by the second source / drain pattern 210 and the second source / drain pad 220. The second occupant 320 may be positioned below the second source / drain pattern 210. The second source / drain pad 220 may be positioned between the second occupant 320 and the (corresponding) gate structure GS (e.g., an adjacent gate structure).

[0087] According to some example embodiments, the second occupier 320 may include impurities. The second occupier 320 may include silicon (Si) and / or silicon germanium (SiGe), but the second occupier 320 may not be limited to these.

[0088] According to some exemplary embodiments, the impurity concentration of the second source / drain pattern 210 may differ from the impurity concentration of the second source / drain pad 220 and the impurity concentration of the second occupant 320, and the impurity concentration of the second source / drain pad 220 may differ from the impurity concentration of the second occupant 320. According to some exemplary embodiments, the impurity concentration of the second occupant 320 may be less than (lower than) the impurity concentration of the second source / drain pattern 210. The impurity concentration of the second occupant 320 may be greater than (higher than) the impurity concentration of the second source / drain pad 220.

[0089] Figures 3 to 16 This is a diagram illustrating intermediate operations used to explain a method for manufacturing a semiconductor device according to an example embodiment. Regarding... Figures 3 to 16 This can be briefly explained or omitted. Figure 2 The same configuration description.

[0090] Reference Figure 3 The substrate pattern 20 may have a front side 20a (e.g., upper side 20a or upper surface 20a) and a back side 20b (e.g., lower side 20b or lower surface 20b). The substrate pattern 20 may be a substrate, an insulating layer, or an insulating substrate.

[0091] According to some exemplary embodiments, a semiconductor stack pattern STC can be formed by alternately stacking a first semiconductor layer 431 and a second semiconductor layer 432 on a substrate pattern 20. The first semiconductor layer 431 may be a sacrificial semiconductor layer, and the second semiconductor layer 432 may be a channel (e.g., ...). Figure 2 The semiconductor layer has multiple channel patterns (CH). Although four first semiconductor layers 431 and four second semiconductor layers 432 are shown, this disclosure is not limited thereto.

[0092] According to some exemplary embodiments, a semiconductor stack pattern STC can be formed on the front side of a substrate (e.g., substrate pattern 20). A first semiconductor layer 431 and a second semiconductor layer 432 can be formed by an epitaxial growth method. The first semiconductor layer 431 and the second semiconductor layer 432 can comprise different semiconductor materials. For example, the first semiconductor layer 431 can comprise silicon germanium (SiGe), and the second semiconductor layer 432 can comprise silicon (Si). However, this disclosure is not limited thereto.

[0093] According to some example embodiments, during the manufacturing process of the semiconductor device 10, mask patterns 420 spaced apart from each other (in the second direction D2) can be formed on a semiconductor stack pattern STC. A first opening 411 and a second opening 412 can be formed between adjacent mask patterns 420. The mask pattern 420 may include a dummy gate pattern 421 on the semiconductor stack pattern STC and a cover pattern 422 on the dummy gate pattern 421. In some embodiments, a pre-gate spacer 323 may be formed on the side surface of the mask pattern 420. In some embodiments, the cover pattern 422 may be on the upper surface of the dummy gate pattern 421. The pre-gate spacer 323 may extend around the mask pattern 420 (e.g., at least partially around the mask pattern 420). For example, the pre-gate spacer 323 may overlap with the dummy gate pattern 421 and the cover pattern 422 in the second direction D2 and / or the third direction D3.

[0094] Reference Figure 4 The semiconductor stack pattern STC and the substrate pattern 20 can be etched using the mask pattern 420 as an etching mask. As the semiconductor stack pattern STC is etched, multiple semiconductor patterns stacked along the first direction D1 can be formed.

[0095] According to some example embodiments, as the semiconductor stack pattern STC and the substrate pattern 20 are etched, a first source / drain opening 441 connected to the first opening 411 and a second source / drain opening 442 connected to the second opening 412 can be formed. The first source / drain opening 441 and the second source / drain opening 442 can be formed below the front side 20a of the substrate pattern 20. Here, the first opening 411 and the second opening 412 can be in the mask pattern 420 (e.g., they can overlap with the mask pattern 420 in the second direction D2 and / or the third direction D3), and the first source / drain opening 441 and the second source / drain opening 442 can be in the semiconductor stack pattern STC and the substrate pattern 20 (e.g., they can overlap with the semiconductor stack pattern STC and the substrate pattern 20 in the second direction D2 and / or the third direction D3).

[0096] Reference Figure 5A pre-first source / drain pad 450 may be formed in the first source / drain opening 441, and a second source / drain pad 220 may be formed in the second source / drain opening 442. In the following text, the term "pre" may refer to an intermediate structure prior to its formation as the final structure.

[0097] According to some example embodiments, the pre-first source / drain pad 450 can be grown via epitaxial growth. The second source / drain pad 220 can be grown via epitaxial growth. The pre-first source / drain pad 450 and the second source / drain pad 220 can be grown separately or simultaneously.

[0098] According to some example embodiments, the pre-first source / drain pad 450 may be an epitaxial layer having a predetermined thickness from the edge of the first source / drain opening 441. At least a portion of the pre-first source / drain pad 450 may contact the substrate pattern 20. The pre-first source / drain pad 450 may be formed to have a predetermined thickness from the edge of the first source / drain opening 441.

[0099] According to some exemplary embodiments, the second source / drain pad 220 may be an epitaxial layer having a predetermined thickness from the edge of the second source / drain opening 442. At least a portion of the second source / drain pad 220 may contact the substrate pattern 20. The second source / drain pad 220 may be formed to have a predetermined thickness from the edge of the second source / drain opening 442.

[0100] According to some example implementations, the pre-first source / drain pad 450 and the second source / drain pad 220 may include silicon (Si) and / or silicon germanium (SiGe). However, the pre-first source / drain pad 450 and the second source / drain pad 220 are not limited thereto.

[0101] exist Figure 5 After the manufacturing process, selective execution is possible. Figure 6 and Figure 7 Any one of the manufacturing processes.

[0102] Reference Figure 6 A first occupant 310 may be formed in the lower portion of the first source / drain opening 441. A second occupant 320 may be formed in the lower portion of the second source / drain opening 442. At least a portion of the first occupant 310 and at least a portion of the second occupant 320 may be formed in the substrate pattern 20.

[0103] According to some example implementations, the first occupant 310 can be formed by selectively epitaxially growing semiconductor material in some regions within the first source / drain opening 441, and the second occupant 320 can be formed by selectively epitaxially growing semiconductor material in some regions within the second source / drain opening 442.

[0104] Reference Figure 7 A first occupant 310 may be formed in the first source / drain opening 441. A second occupant 320 may be formed in the second source / drain opening 442. At least a portion of the first occupant 310 and at least a portion of the second occupant 320 may be formed inside the substrate pattern 20 and the semiconductor stack pattern STC. For example, the first occupant 310 and the second occupant 320 may overlap with the substrate pattern 20 and the semiconductor pattern STC in the second direction D2 and / or the third direction D3.

[0105] Reference Figure 8 ,exist Figure 6 or Figure 7 After the process, a first source / drain pattern 110 can be formed in the first source / drain opening 441, and a second source / drain pattern 210 can be formed in the second source / drain opening 442. The first source / drain pattern 110 can be on the upper surface of the first occupier 310, and the second source / drain pattern 210 can be on the upper surface of the second occupier 320. When selected Figure 7 During the process, a portion (e.g., the upper portion) of the first occupier 310 and a portion (e.g., the upper portion) of the second occupier 320 can be removed before the first source / drain pattern 110 and the second source / drain pattern 210 are formed thereon, respectively.

[0106] According to some example embodiments, a first source / drain pad 450, a first occupant 310, and a first source / drain pattern 110 may be formed below (inside or inside) the first source / drain opening 441. A second source / drain pad 220, a second occupant 320, and a second source / drain pattern 210 may be formed below (inside or inside) the second source / drain opening 442. The first source / drain pattern 110 and the second source / drain pattern 210 may be formed on the occupant (e.g., on the first occupant 310 and the second occupant 320, respectively).

[0107] Reference Figure 9Multiple channel patterns CH, spaced apart from each other (in the first direction D1), can be formed by selectively removing the first semiconductor layer 431 and the dummy gate pattern 421 of the semiconductor stack pattern STC. Openings 471 and 472 can be formed on the uppermost channel pattern CH and between adjacent channel patterns CH, respectively. Openings 471 and 472 can be spaces from which the dummy gate pattern 421 and the first semiconductor layer 431 of the semiconductor stack pattern STC have been removed, respectively.

[0108] Reference Figure 10 A gate insulating film 72 and a gate electrode 71 can be formed in openings 471 and 472. For example, the gate electrode 71 can be formed in openings 471 and 472 between adjacent channel patterns CH in a plurality of channel patterns CH, and in openings 471 and 472 on the uppermost channel pattern CH in a plurality of channel patterns CH. The gate insulating film 72 can be formed between the plurality of channel patterns CH (adjacent channel patterns CH) and the gate electrode 71.

[0109] Reference Figure 11 A pre-first front-side interlayer insulating film 51a can be formed on the first source / drain pattern 110 and the second source / drain pattern 210. During the formation of the pre-gate capping layer 54a and the gate spacer 423, at least a portion of the capping pattern 422 and at least a portion of the pre-gate spacer 323 can be removed (e.g., etched). The gate structure GS may include a gate electrode 71, a gate insulating film 72, and a gate spacer 423. The pre-gate capping layer 54a may be on the gate structure GS.

[0110] refer to Figure 12 A portion of the pre-first front interlayer insulating film 51a can be removed (e.g., etched) to form the first front interlayer insulating film 51, and a portion of the pre-gate capping layer 54a can be removed (e.g., etched) to form the gate capping layer 54. A portion of the first front interlayer insulating film 51 can form an opening exposing the second source / drain pattern 210 for a front plug (e.g., front wiring path 82 and front contact 83). The front contact 83 can be formed in (within) the opening for the front plug. The front contact 83 can be electrically connected to the second source / drain pattern 210.

[0111] According to some example embodiments, a second front-side interlayer insulating film 52 may be formed on the first front-side interlayer insulating film 51 and the gate capping layer 54. A front-side wiring path 82 may be formed to extend into (e.g., penetrate) the second front-side interlayer insulating film 52. A gate contact 81 may be formed to extend into (e.g., penetrate) the gate capping layer 54 and the second front-side interlayer insulating film 52.

[0112] According to some example embodiments, a third front interlayer insulating film 53 may be formed on the second front interlayer insulating film 52. Within the third front interlayer insulating film 53, a gate wiring pattern 42 electrically connected to the gate contact 81 and a front wiring pattern 41 electrically connected to the front plug (front wiring path 82 and front contact 83) may be formed. The gate wiring pattern 42 may be electrically connected via the gate contact 81 to the gate electrode 71 of the gate structure GS (the uppermost gate electrode 71).

[0113] exist Figures 13 to 16 The middle and below, although not shown, can be seen in the following: Figure 12 The manufacturing process is carried out after the structure is flipped 180 degrees.

[0114] Reference Figure 13 A portion of the substrate pattern 20, a portion of the first occupant 310, and a portion of the pre-first source / drain pad 450 may be removed (e.g., etched) to form the first source / drain pad 120 and the first via 473 for the power path 61.

[0115] According to some example implementations, the first hole 473 for the power path 61 may expose the first occupant 310 and the first source / drain pad 120. The lower end of the first hole 473 for the power path 61 may be located on the same plane as the back side 20b of the substrate pattern 20 (may be coplanar with the back side 20b of the substrate pattern 20).

[0116] Reference Figure 14 It can be removed (e.g., etched away) in Figure 13 The remaining first occupier 310 after the process is used to form a second hole 474 for the second contact region 62b. The lower end of the second hole 474 for the second contact region 62b can be arranged on the same plane as (can be coplanar with) the upper end of the first hole 473 for the power path 61. The second hole 474 for the second contact region 62b can expose the first source / drain pattern 110.

[0117] Reference Figure 15 A third hole 475 for the first contact region 62a can be formed by removing (e.g., etching) a portion of the first source / drain pattern 110 exposed by the second hole 474 for the second contact region 62b. The lower end of the third hole 475 for the first contact region 62a can be disposed on the same plane as (can be coplanar with) a portion of the upper end of the second hole 474 for the second contact region 62b. Figure 14 Compared to the previous case, the third hole 475 used for the first contact region 62a can increase the exposed area of ​​the first source / drain pattern 110.

[0118] Reference Figure 16 A back-side plug 60 may be formed in the third hole 475, the second hole 474, and the first hole 473. The back-side plug 60 may include a metal layer (e.g., it may be formed of a metal layer). The back-side plug 60 may include an integrally connected power path 61 and a back-side contact 62 to form a monolithic structure.

[0119] According to some example embodiments, a first contact region 62a may be formed in a third hole 475. A second contact region 62b may be formed in a second hole 474. A power path 61 may be formed in a first hole 473. The power path 61, the second contact region 62b, and the first contact region 62a may extend in a first direction D1 (from the back side 20b of the substrate pattern 20 toward the first source / drain pattern 110).

[0120] According to some example embodiments, the back contact 62 and the power path 61 may comprise different metallic materials. However, this disclosure is not limited thereto. The back contact 62 and the power path 61 may be formed simultaneously and may have the same material.

[0121] According to some example implementations, refer to Figure 2 A back-side wiring pattern 30 can be formed on the back side 20b of the base pattern 20 and the back-side plug 60.

[0122] Figures 17 to 19 This is a diagram illustrating intermediate operations used to explain a method of manufacturing a semiconductor device 10a according to some example embodiments. Semiconductor device 10a may (substantially) resemble semiconductor device 10. Descriptions may be brief or omitted. Figure 2 The same configuration of semiconductor device 10 in the description.

[0123] refer to Figure 17 ,exist Figure 4 Following the process, a pre-first source / drain pad 450a can be formed on at least a portion of the edge (e.g., inner surface) of the first source / drain opening 441. A second source / drain pad 220a can be formed on at least a portion of the edge (e.g., inner surface) of the second source / drain opening 442. For example, this can be achieved by... Figure 5 After the process, portions of the pre-first source / drain pad 450, the second source / drain pad 220, and at least a portion of the substrate pattern 20 are removed (e.g., etched) in the first direction D1 to form the pre-first source / drain pad 450a and the second source / drain pad 220a, as well as the first source / drain opening 441a and the second source / drain opening 442a.

[0124] According to some example implementations, it can be achieved by... Figure 4Following the process, semiconductor material is deposited on at least a portion of the edge (e.g., inner surface) of the first source / drain opening 441 to form a pre-first source / drain pad 450a. In some embodiments, in Figure 5 Following the process, the pre-first source / drain pad 450a can be formed by removing (e.g., etching) the lower portion (e.g., the bottom) of the pre-first source / drain pad 450, and the first source / drain opening 441a can be formed by removing at least a portion of the substrate pattern 20. The second source / drain pad 220a can be formed in a similar manner to the pre-first source / drain pad 450a (e.g., in the same manner). For example, the second source / drain pad 220a can be formed by removing (e.g., etching). Figure 5 The second source / drain pad 220 is formed at the lower part (e.g., the bottom) of the substrate, and the second source / drain opening 442a can be formed by removing (e.g., etching) at least a portion of the substrate pattern 20.

[0125] According to some example embodiments, the pre-first source / drain pad 450a may be formed only on the sidewall of the first source / drain opening 441a. For example, the lower end (and lower sidewall) of the first source / drain opening 441a may be exposed. The second source / drain pad 220a may be formed only on the sidewall of the second source / drain opening 442a. For example, the lower end (and lower sidewall) of the second source / drain opening 442a may be exposed.

[0126] According to some example implementations, an opening may be formed on one side (e.g., the lower portion) of the pre-first source / drain pad 450a to expose a portion of the substrate pattern 20. An opening may also be formed at the end (e.g., the lower end) of the pre-first source / drain pad 450a.

[0127] According to some example embodiments, an opening may be formed on one side (e.g., the lower portion) of the second source / drain pad 220a to expose a portion of the substrate pattern 20. An opening may also be formed at the end (e.g., the lower end) of the second source / drain pad 220a. Figure 17 After the process shown, it is possible to Figure 18 The process shown is performed before and Figures 6 to 12 The process shown is (basically) the same process.

[0128] Reference Figure 18The first source / drain pad 120 can be formed by removing (e.g., etching) at least a portion of the pre-first source / drain pad 450a. A third hole 475 for the first contact region 62a, a second hole 474 for the second contact region 62b, and a first hole 473 for the power path 61 can be formed by removing (e.g., etching) a portion of the pre-first source / drain pattern 450a and the first occupant 310.

[0129] According to some example embodiments, a second occupant 320a may be formed in the second source / drain opening 442a. The second occupant 320a may be formed through an opening formed at the end (e.g., the lower end) of the second source / drain pad 220a. The second occupant 320a may include a protrusion 321a in the opening. The protrusion 321a may protrude lower than the lower end (e.g., the bottom) of the second source / drain pad 220a in a first direction D1. For example, the lower end of the protrusion 321a may be lower than the lower end of the second source / drain pad 220a. At least a portion of the protrusion 321a of the second occupant 320a may contact the substrate pattern 20.

[0130] According to some example embodiments, a second source / drain pattern 210 may be formed on the upper surface (e.g., top) of the second berth 320a. The second source / drain pattern 210 may also be formed inside the second source / drain pad 220a. The second source / drain pattern 210 may be electrically connected to the front plug (front wiring path 82 and front contact 83).

[0131] Reference Figure 19 The back-side plug 60 can be formed in the third hole 475, the second hole 474, and the first hole 473. For example, the first contact region 62a can be in the third hole 475, the second contact region 62b can be in the second hole 474, and the power path 61 can be in the first hole 473. In some embodiments, the back-side plug 60 can be electrically connected by contacting the first source / drain pattern 110. The back-side wiring pattern 30 can be formed on the back side 20b of the substrate pattern 20 and the back-side plug 60.

[0132] At the start of the previously described method for manufacturing the semiconductor device 10, the substrate pattern 20 may comprise a semiconductor material (e.g., may be formed from a semiconductor material). For example, the substrate pattern 20 may comprise silicon and / or silicon germanium. After forming the source / drain pads 120, 220, 120a, 220a, placeholders 320, 320a, and source / drain patterns 110, 210, the semiconductor material forming the substrate pattern 20 may be removed (via etching), and an insulating material may be formed in the areas where the semiconductor material has been removed. For example, in Figure 12Following this process, the semiconductor material of the substrate pattern 20 can be replaced with an insulating material. This process can be similarly applied to… Figures 17 to 19 Example implementation.

[0133] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

[0134] Cross-references to related applications

[0135] This application claims the benefit of Korean Patent Application No. 10-2024-0164491, filed on November 18, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Base pattern; A channel pattern on the front side of the base pattern corresponding to the upper surface of the base pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the base pattern. A gate structure on the upper surface of the substrate pattern, wherein the gate structure includes a gate insulating film and a gate electrode, and at least a portion of the gate structure is between adjacent channel patterns in the channel pattern; A first source / drain pattern is located on the first side of the gate structure. A second source / drain pattern is provided on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in a second direction intersecting the first direction, wherein the second direction is parallel to the upper surface of the substrate pattern; A first source / drain pad is located in the second direction between the first source / drain pattern and the gate structure; A second source / drain pad is located in the second direction between the second source / drain pattern and the gate structure; A back-side plug in the substrate pattern, wherein the back-side plug is electrically connected to the first source / drain pattern; as well as The placeholder in the substrate pattern, wherein the placeholder is inside the second source / drain pad, Wherein, the upper end of the first source / drain pad lies between the first source / drain pattern and the gate structure in the second direction, and the lower end of the first source / drain pad lies between the upper surface of the substrate pattern and the back side of the substrate pattern, the back side of the substrate pattern corresponding to the lower surface of the substrate pattern, and the lower surface of the substrate pattern opposite to the upper surface of the substrate pattern in the first direction. Wherein, the upper end of the first source / drain pad is opposite to the lower end of the first source / drain pad in the first direction.

2. The semiconductor device according to claim 1, wherein, The placeholder is in contact with the second source / drain pattern.

3. The semiconductor device according to claim 2, wherein, The lower end of the second source / drain pattern is in the substrate pattern.

4. The semiconductor device according to claim 3, wherein, The second source / drain pattern, the second source / drain pad, and the placeholder include corresponding impurities having a first impurity concentration, a second impurity concentration, and a third impurity concentration. Wherein, the concentration of the first impurity is different from the concentration of the second impurity and the concentration of the third impurity, and The concentration of the second impurity is different from the concentration of the third impurity.

5. The semiconductor device according to claim 1, wherein, At least a portion of the occupant is in contact with the base pattern.

6. The semiconductor device according to claim 5, wherein, The lower end of the occupant is closer to the lower surface of the substrate pattern than the second source / drain pad.

7. The semiconductor device according to claim 1, wherein, The lower end of the first source / drain pad is closer to the lower surface of the substrate pattern than the gate structure.

8. The semiconductor device according to claim 1, wherein, The back-side plug includes: A power path extends in the first direction from the lower surface of the substrate pattern toward the upper surface of the substrate pattern; and The back contact extends from the upper surface of the power path toward the first source / drain pattern and is electrically connected to the first source / drain pattern.

9. The semiconductor device according to claim 8, wherein, The lower end of the first source / drain pad contacts the upper surface of the power path.

10. The semiconductor device according to claim 8, wherein, The back contact includes: A first contact region, wherein the first source / drain pattern extends around the first contact region; and The second contact area is the area of ​​the back contact other than the first contact area, wherein the second contact area is in contact with the first source / drain pad.

11. The semiconductor device according to claim 8, wherein, The back contact has a lower resistivity than the power path.

12. The semiconductor device according to claim 8, wherein, The power path has a first width in the second direction. Wherein, the back contact has a second width in the second direction, and Wherein, the first width is greater than the second width.

13. The semiconductor device according to claim 1, wherein, The first source / drain pattern and the first source / drain pad respectively include impurities of a first impurity concentration and impurities of a second impurity concentration, and Wherein, the concentration of the first impurity is greater than the concentration of the second impurity.

14. A semiconductor device, comprising: Base pattern; A channel pattern on the front side of the base pattern corresponding to the upper surface of the base pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the base pattern. A gate structure on the upper surface of the substrate pattern, wherein the gate structure includes a gate insulating film and a gate electrode, and at least a portion of the gate structure is between adjacent channel patterns in the channel pattern; A first source / drain pattern is located on the first side of the gate structure. A first source / drain pad is located between the first source / drain pattern and the gate structure in a second direction parallel to the upper surface of the substrate pattern; as well as A back-side plug, located in the first direction between the back side of the substrate pattern and the first source / drain pattern, wherein the back side of the substrate pattern corresponds to the lower surface of the substrate pattern. Wherein, the lower surface of the base pattern is opposite to the upper surface of the base pattern in the first direction. The back-side plug is electrically connected to the first source / drain pattern. Wherein, the back-side plug contacts the substrate pattern, and The first source / drain pad extends along the sidewall of the gate structure and into the substrate pattern in the first direction.

15. The semiconductor device of claim 14, further comprising an interlayer insulating film on the first source / drain pattern. in, The upper end of the first source / drain pad contacts the interlayer insulating film, and The lower end of the first source / drain pad is in the substrate pattern.

16. The semiconductor device of claim 14, further comprising: A second source / drain pattern is provided on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in the second direction; A second source / drain pad is located in the second direction between the second source / drain pattern and the gate structure; as well as The placeholder in the substrate pattern, wherein the placeholder is inside the second source / drain pad and is electrically connected to the second source / drain pattern.

17. The semiconductor device according to claim 16, wherein, The second source / drain pattern, the second source / drain pad, and the placeholder respectively include impurities having a first impurity concentration, a second impurity concentration, and a third impurity concentration, and The concentration of the third impurity is less than the concentration of the first impurity and greater than the concentration of the second impurity.

18. The semiconductor device according to claim 14, wherein, The back-side plug includes: A power path extends in the first direction from the lower surface of the substrate pattern toward the upper surface of the substrate pattern; and The back contact protrudes from the upper surface of the power path toward the first source / drain pattern and is electrically connected to the first source / drain pattern. The lower end of the first source / drain pad is in contact with the upper surface of the power path.

19. The semiconductor device according to claim 18, wherein, The back contact includes: A first contact region, wherein the first source / drain pattern extends around the first contact region; and The second contact area is the area of ​​the back contact other than the first contact area, wherein the second contact area is in contact with the first source / drain pad.

20. A semiconductor device, comprising: Base pattern; A channel pattern on the front side of the base pattern corresponding to the upper surface of the base pattern, wherein the channel patterns are spaced apart from each other in a first direction perpendicular to the upper surface of the base pattern. A gate structure on the upper surface of the substrate pattern, wherein the gate structure is between adjacent channel patterns in the channel pattern; A first source / drain pattern is located on the first side of the gate structure. A second source / drain pattern is provided on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure in a second direction parallel to the upper surface of the substrate pattern; A back plug below the first source / drain pattern, wherein the back plug is electrically connected to the first source / drain pattern; A placeholder below the second source / drain pattern, wherein the placeholder is electrically connected to the second source / drain pattern; A first source / drain pad is located in the second direction between the first source / drain pattern and the gate structure; as well as The second source / drain pad is located in the second direction between the second source / drain pattern and the gate structure. The first source / drain pad overlaps with the back plug in the second direction.

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