Multifunctional photoelectric logic device based on two-dimensional SnS2 / WS2 Van der Waals heterojunction

Abstract

The invention provides a multifunctional photoelectric logic device based on a two-dimensional SnS2 / WS2 Van der Waals heterojunction, and belongs to the technical field of two-dimensional nano materials, the multifunctional photoelectric logic device comprises a substrate, a WS2 layer prepared on the substrate, a SnS2 layer forming a vertical stacking Van der Waals heterostructure with the WS2 layer, and a source electrode and a drain electrode respectively arranged in non-overlapping areas of the SnS2 layer and the WS2 layer; according to the multifunctional photoelectric logic device based on the two-dimensional SnS2 / WS2 Van der Waals heterojunction, through cooperative modulation of gate voltage and bias voltage, positive, negative and zero light current three-state regulation and control are achieved, and seven basic logic gates and a suppression gate are integrated in a single device; the anti-interference bipolar non-return-to-zero coding communication is realized by utilizing the bidirectional light current characteristic; efficient information encryption is achieved based on XOR logic symmetry, the device has the advantages of being simple in structure, high in integration degree, rich in function and the like, and a new scheme is provided for development of an intelligent photoelectric system.

Description

Technical Field

[0001] This invention relates to the field of two-dimensional nanomaterials technology, and more specifically, to a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction. Background Technology

[0002] In recent years, the rapid development of artificial intelligence and the Internet of Things (IoT) technologies has placed higher demands on the integration, functional density, and energy efficiency of digital information systems. Traditional silicon-based logic devices rely on multiple transistors to achieve a single logic function; for example, an XOR gate typically requires 12 transistors, resulting in low logic integration density and high power consumption. Simultaneously, as device feature sizes approach physical limits, the short-channel effect becomes increasingly significant, and performance improvements in traditional devices have encountered a clear bottleneck. Optoelectronic logic devices, through the synergistic control of photons and electrons, offer a feasible path to overcome the inherent limitations of traditional electronic devices.

[0003] Against this backdrop, multifunctional devices with reconfigurable logic functions and information encryption capabilities have become a research hotspot. However, most semiconductor devices only exhibit unidirectional photoresponse, severely limiting their reconfigurability and multifunctional expansion. Therefore, there is an urgent need to develop multifunctional optoelectronic logic devices with multiple photoresponse modes to improve the functional flexibility and integration level of systems. Two-dimensional materials, with their excellent electrical tunability, strong light-matter interaction, and efficient heterogeneous integration compatibility, provide important support for the construction of high-performance optoelectronic logic devices. Among them, SnS2, as an n-type semiconductor, has a visible light bandgap of 2.2 eV and strong light absorption characteristics, showing excellent photoelectric conversion potential. WS2, also an n-type semiconductor, has a bandgap of approximately 1.43 eV, possessing not only good carrier transport performance but also a Fermi level that is highly sensitive to gate voltage. By constructing WS2 and SnS2 into a van der Waals heterojunction, thanks to their bandgap matching and the built-in electric field at the interface, it is expected to achieve dynamic control of the polarity and amplitude of photocurrent, providing a new technical solution for multifunctional integration of single devices and the construction of intelligent optoelectronic systems. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a multifunctional optoelectronic logic device and its fabrication method based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, thereby solving the problem that existing technologies fail to achieve multifunctional integration of reconfigurable logic gates, bipolar non-return-to-zero coded communication, and information symmetric encryption in a single device.

[0005] This invention is implemented as follows: This invention provides a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, comprising: Substrate; A WS2 layer is prepared on the substrate; A SnS2 layer is prepared on the WS2 layer, and the SnS2 layer and the WS2 layer form a vertically stacked van der Waals heterostructure. A source electrode and a drain electrode are fabricated on the substrate; the source electrode is partially covered by a SnS2 layer, and the drain electrode is partially covered by a WS2 layer; The regions where the source electrode covers the SnS2 layer and the regions where the drain electrode covers the WS2 layer are both far from the vertically overlapping regions of the van der Waals heterostructure.

[0006] Preferably, the substrate is a silicon substrate with a SiO2 insulating layer on its surface; The silicon substrate forms the gate electrode of the device; The WS2 layer, SnS2 layer, source electrode, and drain electrode are all located on the upper side of the SiO2 insulating layer.

[0007] Preferably, the thickness of the WS2 layer is 5nm-10nm, and the thickness of the SnS2 layer is 20nm-30nm.

[0008] Preferably, both the drain electrode and the source electrode are metal electrodes, selected from at least one of Cr, Au, In, Pd and Ag.

[0009] Preferably, the thickness of both the source electrode and the drain electrode is 10-100 nm.

[0010] This invention also provides a method for fabricating a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, comprising the following steps: S1: Clean and dry the substrate; S2: Mechanically peel off the WS2 crystal to transfer the two-dimensional semiconductor WS2 onto polydimethylsiloxane (PDMS) to prepare the WS2 layer; S3: The prepared WS2 layer is transferred from polydimethylsiloxane to the substrate surface using a dry transfer method via a micro / nano material mechanical transfer platform to form the bottom functional layer; S4: Mechanically peel off the SnS2 crystal to transfer the two-dimensional semiconductor SnS2 onto polydimethylsiloxane to prepare the SnS2 layer; S5: Repeat the dry transfer in S3 to transfer the SnS2 layer to a portion of the WS2 layer, forming a van der Waals heterostructure in which the SnS2 layer and the WS2 layer are stacked vertically. S6: Fabricate a metal source electrode and a metal drain electrode on the substrate, ensuring that the metal source electrode and the metal drain electrode are arranged in the non-overlapping region of the SnS2 layer and the WS2 layer, to obtain a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction.

[0011] Preferably, in S6 above, the electrode pattern is defined using electron beam lithography or maskless lithography, and the metal source electrode and metal drain electrode are prepared by thermal evaporation and lift-off processes.

[0012] Preferably, in S1 above, the substrate is ultrasonically cleaned sequentially with deionized water, acetone, anhydrous ethanol and deionized water, and then dried with nitrogen gas. In S2 above, blue film tape is used to mechanically peel off the WS2 crystal; In S4 above, blue film tape is used to mechanically peel off the SnS2 crystal.

[0013] Preferably, in S2 above, the heating temperature for the dry transfer is 85°C, and the temperature is maintained for 10 minutes to ensure that the WS2 layer is completely detached from the substrate.

[0014] Preferably, in S6 above, the metal source electrode and the metal drain electrode are transferred to the non-overlapping regions of the SnS2 layer and WS2 layer respectively by a polyvinyl alcohol (PVA) assisted method or a polystyrene (PS) assisted method.

[0015] The beneficial effects of this invention are: (1) The two-dimensional SnS2 / WS2 van der Waals heterojunction multifunctional optoelectronic logic device of the present invention realizes the bidirectional photocurrent characteristics of gate voltage regulation. Through the coordinated modulation of gate voltage and bias voltage, the polarity and amplitude of photocurrent can be dynamically regulated. Seven basic logic gates are successfully integrated in a single device, reducing the number of transistors required for logic gates.

[0016] (2) This invention utilizes the bidirectional photocurrent characteristics with controllable gate voltage to realize bipolar non-return-to-zero coding optoelectronic communication. Compared with the traditional unipolar return-to-zero coding scheme, this method distinguishes the signal state "0" and "1" through the significant positive and negative polarity difference of the photocurrent, thereby effectively improving the anti-interference capability of communication.

[0017] (3) This invention achieves photocurrent cancellation by controlling the competition effect between the built-in electric field and the applied electric field of the heterojunction, thereby realizing the XOR logic gate function; and utilizes the reflexivity of the XOR logic itself to realize the encryption and decryption of optical information, providing a simple and efficient symmetric encryption scheme to ensure information security.

[0018] (4) Based on the free switching of three-state photocurrent, this invention integrates the three core functions of logic operation, optoelectronic communication and information encryption into a single device, achieving high functional density integration. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 is a schematic diagram of the structure of the present invention.

[0021] Figure 2 is an optical microscope image of the present invention.

[0022] Figure 3(a) shows the time-resolved optical response of the present invention under 532nm illumination as a function of gate voltage. Figure 3 (b) is the time-resolved optical response at different optical powers.

[0023] Figure 4 The current mapping diagrams of the present invention for implementing different logic functions under 532nm illumination are shown: (a) OR, (b) AND, (c) Inhibit, (d) NOR, (e) NAND, (f) XNOR and (g) NOT logic.

[0024] Figure 5(a) is a comparison diagram of the signal waveforms of bipolar non-return-to-zero coding and unipolar return-to-zero coding, and Figure 5(b) is a waveform diagram of bipolar non-return-to-zero coding communication of the present invention.

[0025] Figure 6(a) shows the XOR logic gate implemented based on zero photocurrent in this invention; Figure 6(b) is the truth table of the XOR logic; Figure 6(c) shows the mechanism analysis corresponding to the four current states; Figure 6(d) and Figure 6 (e) are illustrations showing the effects of image encryption and decryption using XOR logic.

[0026] In the figure: 1. Substrate; 2. WS2 layer; 3. SnS2 layer; 4. Source electrode; 5. Drain electrode. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All components in the present invention, unless otherwise specified, are components known in the prior art. Specific embodiments of the present invention are given below. It should be noted that the present invention is not limited to the following specific embodiments, and all equivalent modifications made based on the technical solutions of this application fall within the protection scope of the present invention.

[0028] Example 1 This embodiment presents a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, comprising: Substrate 1; WS2 layer 2 is fabricated on substrate 1; SnS2 layer 3 is prepared on WS2 layer 2, and SnS2 layer 3 and WS2 layer 2 form a vertically overlapping van der Waals heterostructure. Source electrode 4 and drain electrode 5 are fabricated on substrate 1; The source electrode 4 is partially covered by SnS2 layer 3, and the drain electrode 5 is partially covered by WS2 layer 2; The area of ​​the source electrode 4 covering the SnS2 layer 3 is far away from the overlapping area of ​​the heterostructure, and the area of ​​the drain electrode 5 covering the WS2 layer 2 is far away from the overlapping area of ​​the heterostructure; the electrode arrangement is designed to ensure that the electrodes do not make direct contact, thereby avoiding short circuits.

[0029] A multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction is disclosed. Specifically, from bottom to top, it includes: a substrate 1, a WS2 layer 2, a SnS2 layer 3, a metal source electrode 4, and a metal drain electrode 5. One end of the SnS2 layer 3 is connected to the metal source electrode 4, and the other end is connected to one end of the WS2 layer 2. The other end of the WS2 layer 2 is connected to the metal drain electrode 5. Here, by fixing SnS2 and WS2 of a certain thickness together, a SnS2 / WS2 van der Waals heterojunction is constructed, aiming to realize a multifunctional two-dimensional optoelectronic logic device by utilizing the tunability of the two materials.

[0030] This invention provides a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction. By constructing a van der Waals heterojunction using mechanically peeled WS2 and SnS2 nanosheets, a multifunctional optoelectronic device integrating reconfigurable logic gates, optoelectronic communication, and information encryption is realized. This provides a practical solution to overcome the problems of simple logic functions and low integration of individual devices in the prior art.

[0031] As a preferred embodiment: The substrate 1 is a silicon substrate with a SiO2 insulating layer on its surface; The SiO2 insulating layer is 300nm, and there are no special requirements for the thickness of the underlying silicon substrate. The WS2 layer 2, SnS2 layer 3, source electrode 4, and drain electrode 5 are all located on the upper side of the SiO2 insulating layer; The thickness of the WS2 layer 2 is 5nm-10nm, and the thickness of the SnS2 layer 3 is 20nm-30nm.

[0032] As a preferred embodiment, both the drain electrode 5 and the source electrode 4 are metal electrodes, selected from one or more of Cr, Au, In, Pd and Ag.

[0033] As a preferred embodiment, the source electrode 4 and the drain electrode 5 are Au single metal layers with a thickness of 60 nm.

[0034] Example 2 A method for fabricating a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction includes the following steps: S1: Clean and dry substrate 1; S2: Mechanically peel off the WS2 crystal to transfer the two-dimensional semiconductor WS2 onto polydimethylsiloxane to prepare WS2 layer 2; S3: The prepared WS2 layer is transferred from polydimethylsiloxane to the substrate surface using a dry transfer method via a micro / nano material mechanical transfer platform to form the bottom functional layer; S4: Mechanically peel off the SnS2 crystal to transfer the two-dimensional semiconductor SnS2 onto polydimethylsiloxane to prepare SnS2 layer 3; S5: Repeat the dry transfer in S3 to transfer the SnS2 layer to a portion of the WS2 layer, forming a van der Waals heterostructure in which SnS2 layer 3 and WS2 layer 2 are stacked vertically. S6: Prepare a metal source electrode 4 and a metal drain electrode 5 on the substrate 1, ensuring that the metal source electrode 4 and the metal drain electrode 5 are arranged in the non-overlapping region of the SnS2 layer 3 and the WS2 layer 2, to obtain a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction.

[0035] In this embodiment, the thickness of WS2 layer 2 is approximately 5.8 nm, and the thickness of SnS2 layer 3 is approximately 27.6 nm. In the multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction fabricated in this embodiment, substrate 1 is a silicon substrate with a silicon dioxide insulating layer on its surface; source electrode 4 and drain electrode 5 are 60 nm thick Au electrodes. The specific steps are as follows: Step 1: Take a piece approximately 1cm in size 2 The silicon substrate (with a silicon dioxide insulating layer on its surface) was sequentially placed in deionized water, acetone, anhydrous ethanol and deionized water for ultrasonic cleaning. After ultrasonic cleaning, it was dried with high-purity nitrogen and sealed for storage.

[0036] Step 2: Cut a polydimethylsiloxane film of appropriate size and attach it to a clean glass slide. Place a WS2 single crystal on a blue film tape, fold the tape in half and peel it off repeatedly until a thin film of the target thickness is obtained. Then attach the blue film tape to the adhesive side of the polydimethylsiloxane film and let it stand for 10 minutes to allow the WS2 to transfer to the surface of the polydimethylsiloxane. Under an optical microscope, select WS2 thin films of appropriate thickness and mark their positions for subsequent transfer.

[0037] Step 3: Fix the polydimethylsiloxane / glass slide assembly carrying WS2 onto the micro / nano material mechanical transfer platform with the polydimethylsiloxane side facing down. Place the silicon substrate cleaned in Step 1 on the stage below the platform. Locate the marked WS2 area using an optical microscope. Slowly adjust the height of the glass slide to bring the WS2 into contact with the substrate. Then heat to about 85°C and hold for 10 minutes to allow the WS2 to completely desorb and firmly adhere to the substrate surface, forming the bottom functional layer.

[0038] Step 4: Mechanically peel off the SnS2 crystal using the same method as in Step 2. Place the SnS2 single crystal on the blue film tape and peel it off repeatedly before transferring it to the polydimethylsiloxane film. Select SnS2 slices of suitable thickness under an optical microscope and mark their positions for later use.

[0039] Step 5: Install the polydimethylsiloxane / glass slide assembly containing SnS2 onto the transfer platform with the SnS2 side facing down, and place the silicon substrate with transferred WS2 below it; simultaneously observe the target areas of SnS2 and WS2 using an optical microscope, finely adjust the platform knob to achieve precise alignment of the two, then make partial areas of SnS2 and WS2 vertically overlap and make them in close contact, heat to 85°C and hold for 10 minutes to complete the dry transfer of SnS2 to the surface of WS2, forming a SnS2 / WS2 van der Waals heterostructure.

[0040] Step Six: On the cleaned substrate, spin-coat polymethyl methacrylate (PMMA) or AZ5214E ​​photoresist using a spin coater. After spin coating, bake at 130°C for 3 minutes, followed by exposure using electron beam lithography or maskless lithography. The defined source and drain electrode patterns are drawn using AutoCAD software. Then, develop and fix the electrode, dry it with nitrogen, and store it in the dark. Finally, deposit a 60nm thick Au metal layer using a thermal evaporation process, and remove excess metal using a lift-off process, i.e., immerse the electrode in acetone at 60°C for 60 minutes to remove the metal from the unexposed areas, forming source electrode 4 and drain electrode 5.

[0041] The prepared source electrode 4 and drain electrode 5 are picked up using a PVA stamp or spin-coated PS film. Then, a polyvinyl alcohol (PVA) stamp or polystyrene (PS) film with electrodes is attached to a polydimethylsiloxane film. The PS film needs to be baked at 130°C for 5 minutes after spin-coating. Using the transfer method in step five, the electrodes are precisely transferred to the non-overlapping area of ​​SnS2 layer 3 and WS2 layer 2. Subsequently, the PVA stamp or PS film remains on the substrate. The PVA stamp is removed by immersion in 80°C deionized water for 60 minutes, or the PS film is removed by immersion in 80°C toluene for 30 minutes. Finally, the source electrode 4 / drain electrode 5 forms reliable contact with the non-overlapping area of ​​SnS2 layer 3 and WS2 layer 2, respectively, thus obtaining a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, such as... Figure 2 As shown.

[0042] Photoelectric performance testing of the multifunctional optoelectronic logic device based on the two-dimensional SnS2 / WS2 van der Waals heterojunction: The multifunctional optoelectronic logic device based on the two-dimensional SnS2 / WS2 van der Waals heterojunction of this embodiment was irradiated with a 532nm laser to test its photoelectric performance.

[0043] Figure 3(a) shows the bias voltage V ds = 0V, the photocurrent of the SnS2 / WS2 heterojunction device exhibits a significant polarity reversal characteristic as the gate voltage changes. When the gate voltage V g A forward photocurrent (PPC) is generated at ≥-40V. g A negative photocurrent (NPC) is generated at <-40V; such as Figure 3 As shown in (b), in V g = 50V and V ds Under the condition of -0.4 V, as the optical power increases, the negative photocurrent first gradually decreases to a low level, approaching the zero photocurrent level (ZPC), and then the positive photocurrent gradually increases as the polarity reverses.

[0044] Based on the adjustable gate voltage optical response characteristics of the aforementioned devices, they can be applied to reconfigurable optical logic gates, such as... Figure 4 As shown in (ag), with V g and V ds As the input signal, it is defined as input logic "0" for larger voltages and input logic "1" for smaller voltages; the output current is used as the output signal, with a threshold of |10nA|, I ds >10nA or I dsWhen the voltage is less than -10nA, it is defined as the output logic "1", and when it is between -10nA and 10nA, it is defined as the output logic "0". By testing the output response under different input combinations, all logic gate functions are completely matched with the truth table, proving the device's reconfigurable logic capability. Through the coordinated modulation of gate voltage and bias voltage, the polarity and amplitude of photocurrent can be dynamically controlled. Seven basic logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and one inhibitor gate are successfully integrated in a single device, reducing the number of transistors required for logic gates.

[0045] Figure 5(a) compares the waveforms of bipolar non-return-to-zero (NRZ) coding and traditional unipolar return-to-zero (RZ) coding. The former has a significant positive-to-negative difference and stronger anti-interference capability. As shown in Figure 5(b), a bipolar non-return-to-zero coding communication system is constructed using the bidirectional photocurrent characteristics of the device. The polarity of the photocurrent is modulated by the gate voltage, and finally the signal sequence is decoded into the ASCII code corresponding to the letters "SNNU". Under illumination, the input gate voltage pulse sequence is "01010011", "01001110", "01001110", "01010101", where V g =-60V and V g = 0V corresponds to input states "1" and "0" respectively; V g Output current I at -60V ds <0, V g Output current I at 0V ds >0, where I ds When I > 0nA, the output state is "0". ds When <0nA, the output state is "1", thus obtaining the output signal sequence. The corresponding letter can be obtained by referring to the ASCII code table. It should be noted that the letter "SNNU" is just an example. In principle, any letter or number information can be transmitted by using the device based on the ASCII code.

[0046] Figure 6(a) shows the XOR logic gate implemented based on ZPC, Figure 6(b) shows the truth table of the XOR logic, and Figure 6(c) shows the built-in electric field (E) corresponding to the four current states. bi ) and applied electric field (E) extThe competition mechanism between the two is as follows: "0,0": under low bias voltage and no illumination, the dark current driven by the external electric field is weak; "0,1": under low bias voltage and illumination, the built-in electric field dominates, generating a strong photocurrent; "1,0": under high bias voltage and no illumination, the external electric field significantly enhances the dark current; "1,1": under high bias voltage and illumination, the external electric field weakens the built-in electric field, and the photocurrent originally driven by the built-in electric field is suppressed to a low level; Figures 6(d) and 6(e) respectively show the image encryption / decryption effect, with the original optical information and electrical information key as input, and processed by... The device outputs ciphertext of the photocurrent. The original information can be recovered by performing an XOR operation on the ciphertext and the same key. The original image becomes an unrecognizable scrambled image after encryption, but can be completely recovered after decryption, verifying the effectiveness of the encryption system. By controlling the competition effect between the built-in electric field and the applied electric field of the heterojunction, photocurrent cancellation (i.e., zero photocurrent) is achieved, thereby realizing the function of the XOR logic gate. Furthermore, by utilizing the reflexivity of the XOR logic itself, the encryption and decryption of optical information are realized, providing a simple and efficient symmetric encryption scheme to ensure information security.

[0047] In summary, this invention integrates three core functions—logic operation, optoelectronic communication, and information encryption—into a single device based on the free switching of three-state photocurrents (positive, negative, and zero photocurrent), achieving high functional density integration.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction, characterized in that, include: Substrate (1); A WS2 layer (2) is prepared on the substrate; A SnS2 layer (3) is prepared on the WS2 layer (2), and the SnS2 layer (3) and the WS2 layer (2) form a vertically stacked van der Waals heterostructure; A source electrode (4) and a drain electrode (5) are fabricated on the substrate (1); the source electrode (4) is partially covered by a SnS2 layer (3), and the drain electrode (5) is partially covered by a WS2 layer (2). The regions where the source electrode (4) covers the SnS2 layer (3) and the regions where the drain electrode (5) covers the WS2 layer (2) are both far from the vertically overlapping regions of the van der Waals heterostructure.

2. The multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction according to claim 1, characterized in that, The substrate (1) is a silicon substrate with a SiO2 insulating layer on its surface; The silicon substrate forms the gate electrode of the device; The WS2 layer (2), SnS2 layer (3), source electrode (4) and drain electrode (5) are all located on the upper side of the SiO2 insulating layer.

3. A multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction according to claim 2, characterized in that, The thickness of the WS2 layer (2) is 5nm-10nm, and the thickness of the SnS2 layer (3) is 20nm-30nm.

4. A multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction according to claim 1, characterized in that, Both the drain electrode (5) and the source electrode (4) are metal electrodes selected from at least one of Cr, Au, In, Pd and Ag.

5. A multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction according to claim 1, characterized in that, The thickness of both the source electrode (4) and the drain electrode (5) is 10-100 nm.

6. A method for fabricating a multifunctional optoelectronic logic device based on a two-dimensional SnS2 / WS2 van der Waals heterojunction according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1: Clean and dry the substrate (1); S2: Mechanically peel off the WS2 crystal to transfer the two-dimensional semiconductor WS2 onto polydimethylsiloxane to prepare the WS2 layer (2). S3: The prepared WS2 layer (2) is transferred from polydimethylsiloxane to the surface of the substrate (1) by dry transfer using a micro-nano material mechanical transfer platform to form the bottom functional layer; S4: Mechanically peel off the SnS2 crystal to transfer the two-dimensional semiconductor SnS2 onto polydimethylsiloxane to prepare the SnS2 layer (3). S5: Repeat the dry transfer in S3 to transfer SnS2 layer (3) to a portion of the WS2 layer (2) to form a van der Waals heterostructure in which SnS2 layer (3) and WS2 layer (2) are stacked vertically. S6: Prepare a metal source electrode (4) and a metal drain electrode (5) on the substrate, ensuring that the metal source electrode (4) and the metal drain electrode (5) are arranged in the non-overlapping area of ​​the SnS2 layer (3) and the WS2 layer (2).

7. The preparation method according to claim 6, characterized in that, In the above S6, the electrode pattern is defined by electron beam lithography or maskless photolithography, and the metal source electrode (4) and metal drain electrode (5) are prepared by thermal evaporation and stripping processes.

8. The preparation method according to claim 6, characterized in that, In S1 above, the substrate (1) is ultrasonically cleaned sequentially with deionized water, acetone, anhydrous ethanol and deionized water, and then dried with nitrogen gas. In S2 above, blue film tape is used to mechanically peel off the WS2 crystal; In S4 above, blue film tape is used to mechanically peel off the SnS2 crystal.

9. The preparation method according to claim 6, characterized in that, In S2 above, the heating temperature for the dry transfer is 85°C, and the temperature is maintained for 10 minutes.

10. The preparation method according to claim 6, characterized in that, In the above S6, the metal source electrode (4) and the metal drain electrode (5) are transferred to the non-overlapping regions of the SnS2 layer (3) and the WS2 layer (2) by a polyvinyl alcohol-assisted method or a polystyrene-assisted method, respectively.

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