LED element, manufacturing method thereof and LED light source comprising LED element

Abstract

The present invention relates to an LED element, a method for manufacturing the same, and an LED light source comprising the same, according to which a larger number of LED elements with smaller chip sizes can be obtained from a single wafer, and dead volumes caused by surface defects generated in a wafer dry etching process and dangling bonds generated in a wet etching process can be reduced to the greatest extent, thereby improving the yield of the LED element. Each obtained LED element shows high-efficiency physical properties, so that the LED element can be widely applied to manufacturing of light sources with high resolution and high brightness characteristics.

Description

Technical Field

[0001] This invention relates to a method for manufacturing an LED element, and more specifically, to a method for manufacturing a high-efficiency LED element, an LED element manufactured by the method, and an LED light source or other product containing the element. Background Technology

[0002] Micro-LEDs (μLEDs) are attracting widespread attention as next-generation display elements. Micro-LED displays offer high performance, extremely long theoretical lifespan, and high efficiency. However, developing displays with 8K resolution requires at least one micro-LED on each of nearly 100 million sub-pixels. Therefore, the pick-and-place technology used to manufacture micro-LED displays suffers from high unit cost, high defect rate, and low productivity. Furthermore, there is a declining yield of usable chips when producing individual micro-LEDs from wafers, and the current large size of micro-LEDs limits the number of chips that can be manufactured per wafer, resulting in extremely high production costs.

[0003] Accordingly, in recent years, a method has been proposed to transfer RGB micro-LEDs to sub-pixel positions using laser lift-off (LLO) to manufacture micro-LED displays.

[0004] However, in the case of laser lift-off (LLO), the efficiency is reduced due to the applied laser shock, making it unsuitable for transfer processes. Furthermore, the inhomogeneity of the wafer in this method is directly reflected in the micro-LED elements, leading to uneven brightness in the resulting display.

[0005] To address these issues, a method for realizing displays by shrinking the size of micro-LEDs to below 10 μm has been proposed in recent years. This aims to significantly increase the number of micro-LED chips that can be obtained from a single wafer while reducing efficiency deviations between pixels. However, when manufacturing LED chips with dimensions smaller than 10 μm, not only is there a significant problem of decreased efficiency for each chip, but when using LED chips smaller than 10 μm to realize displays via laser lift-off, the applied laser shock causes an even greater decrease in chip efficiency.

[0006] Accordingly, an alternative solution has been proposed in recent years, which is to realize a display screen by separating multiple individual LED chips with a size of less than 10 μm through fluid assembly. However, even with this alternative solution, the fundamental problem of significantly reduced external quantum efficiency caused by manufacturing micro-LEDs with a size of less than 10 μm from wafers has not been solved.

[0007] Especially when manufacturing micro LED chips from wafers using dry etching, the dead volume caused by surface defects increases significantly depending on the chip size. For example, when the chip length, width, and thickness are 92 μm, the dead volume from the surface inward is about 4.69%; while when the length, width, and thickness are reduced to 52 μm or 12 μm, the dead volume from the surface inward increases to about 8.3% or 36%, respectively. Therefore, even if the number of LED chips that can be obtained from a single wafer increases, the efficiency of each LED chip decreases significantly.

[0008] Furthermore, wet etching can be considered to remove the dead volume formed by the accumulation of surface defects as described above. However, when surface defects have accumulated and formed a large dead volume, wet etching can only remove part of the surface defects. Moreover, for GaN wafers manufactured along the c-plane direction, wet etching increases the dangling bonds on the surface, which leads to an increase in surface strain and non-radiative recombination. Therefore, the efficiency reduction effect caused by dangling bonds is relatively greater than the efficiency improvement effect of wet etching, resulting in a relatively small increase in the efficiency of LED chips.

[0009] Therefore, there is an urgent need to develop a method for manufacturing small, efficient LED chips to enable light sources such as high-resolution, high-brightness displays. Summary of the Invention

[0010] The technical problem to be solved The present invention is proposed to solve the above problems. Its purpose is to provide an LED element manufacturing method and an LED element manufactured by the method, which reduces the dead volume caused by surface defects in the wafer dry etching process when reducing the chip size to separate from a single wafer and obtain a greater number of micro LED elements, so as to obtain small-sized and high-efficiency LED elements.

[0011] Furthermore, the present invention aims to provide an LED light source such as a high-resolution, high-brightness display screen using small-sized, high-efficiency LED elements, an LED ink composition suitable for realizing LED light sources through various assembly processes, and an LED assembly for transfer, such as an interposer or a light-emitting element substrate in which LEDs are arranged at fixed intervals.

[0012] Technical solutions to solve technical problems To address the aforementioned technical problems, this invention provides a method for manufacturing LED components, which involves separating and obtaining components from a wafer with a thickness of less than 10 μm and a cross-sectional area of ​​100 μm perpendicular to the thickness direction. 2 The following LED element includes the following steps: (1) a dry etching step, in which a predetermined pattern is dry etched from the top of the wafer toward the lower side in the thickness direction to create a plurality of structures spaced apart from each other, wherein the angle formed between the side of the structure serving as the etching surface and the bottom surface of the structure connected to the wafer is 84° or less; and (2) a first recovery step, in which wet etching is performed to remove surface defects on the side of the structure caused by dry etching.

[0013] According to one embodiment of the present invention, step (1) can be performed to make the included angle between the side surface of the structure etched by wet etching and the bottom surface of the structure connected to the wafer 60~84°.

[0014] In addition, the dry etching in step (1) can be performed by inductively coupled plasma-reactive ion etching (ICP-RIE) at an etching rate of less than 200 nm / min.

[0015] In addition, the inductively coupled plasma-reactive ion etching may include 0~100 sccm of BCl3 and 0~100 sccm of Cl2 chlorine gas as process gases, and be carried out at a process pressure of 1~100 mT.

[0016] Furthermore, the average afterglow time of the LED structure measured at 300 K after performing step (1) and before performing step (2) can be longer than the average afterglow time measured at 10 K.

[0017] Furthermore, the side Raman spectroscopy analysis results of the LED structure after performing step (1) were obtained at 687 cm⁻¹. -1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The ratio of the peak area of ​​GaN Al(LO) mode at that location can be less than 15%.

[0018] In addition, step (2) can be performed to make the angle between the side surface of the wet-etched structure and the bottom surface of the structure connected to the wafer greater than 85°.

[0019] In addition, the structure has a first conductive semiconductor layer, a photoactive layer and a second conductive semiconductor layer of gallium nitride (GaN) semiconductor. According to the Ga 3d bonding analysis results of XPS spectrum, the ratio of Ga-O bonding as a defect in Ga-N and Ga-O bonding can vary by less than ±30% relative to the Ga-O bonding ratio of the wafer itself.

[0020] Furthermore, after performing step (2), the average afterglow time of the LED structure measured at 300 K can be longer than the average afterglow time measured at 10 K.

[0021] Furthermore, the average afterglow time of the LED structure after performing step (2) can be longer at 300 K than that of the LED structure before performing step (2).

[0022] Furthermore, the side Raman spectroscopy analysis results of the LED structure after step (2) were obtained at 687 cm⁻¹. -1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The ratio of the peak area of ​​GaN Al(LO) mode at that location can be below 8%.

[0023] In addition, a second recovery step of irradiating the LED structure with UV can be performed as step (3) after step (2).

[0024] In addition, the UV wavelength of the irradiation in step (3) can be 250~400 nm, the irradiation intensity can be 1 mW~100 W, and the irradiation time can be 0.1~48 hours.

[0025] In addition, step (3) can irradiate water molecules (H2O) in the chemical form of -OH and -H onto the dangling bonds on the surface to alleviate the strain caused by the dangling bonds, and re-trapping electrons trapped in the shallow trap and deep trap back into the conduction band to participate in luminescence, thereby improving the luminescence efficiency.

[0026] Furthermore, after performing step (3), the average afterglow time of the LED structure measured at 300 K can be longer than the average afterglow time measured at 10 K.

[0027] Furthermore, the average afterglow time of the LED structure after performing step (3) can be longer at 300 K than that of the LED structure before performing step (3).

[0028] Furthermore, the internal quantum efficiency of the manufactured LED element can be 70 to 130% of the intrinsic quantum efficiency of the wafer itself.

[0029] Furthermore, the present invention provides an LED element obtained by etching a wafer along the thickness direction and then separating the etched structure from the wafer, wherein the thickness is less than 10 μm and the cross-sectional area perpendicular to the thickness direction is less than 100 μm², wherein the average decay time measured at 300K is equal to or greater than the average decay time measured at 10K.

[0030] According to one embodiment of the invention, the average afterglow time measured at 300 K can be longer than the average afterglow time measured at 10 K.

[0031] Furthermore, the average afterglow time measured at 300 K can be more than 15% longer than the average afterglow time measured at 10 K.

[0032] Furthermore, in the luminescence measured at 300 K, delayed luminescence caused by shallow and deep traps can contribute more to the luminescence than the luminescence within the band gap.

[0033] Furthermore, in the luminescence measured at 300 K, the contribution of delayed luminescence caused by shallow and deep traps can be more than twice as large as the contribution of bandgap luminescence.

[0034] In addition, Raman spectroscopy analysis results, 687 cm⁻¹ -1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The ratio of the GaN Al(LO) mode peak area can be less than 8%, for example, less than 6%.

[0035] In addition, it may have a first conductive semiconductor layer, a photoactive layer, and a second conductive semiconductor layer, all of which are based on gallium nitride (GaN) semiconductors.

[0036] Furthermore, based on XPS spectral analysis of Ga 3d bonding on the side of LED components, the proportion of Ga-O bonds that are defects in Ga-N and Ga-O bonds can vary by less than ±30% relative to the proportion of Ga-O bonds on the wafer itself.

[0037] Furthermore, the LED element can be an LED element manufactured according to the manufacturing method of the present invention.

[0038] Furthermore, the present invention also provides an LED ink composition comprising an LED element according to the present invention.

[0039] Furthermore, an LED assembly for transfer is provided, comprising: a substrate for transfer; and a plurality of LED elements according to the invention, the LED elements being arranged at predetermined intervals on the substrate for transfer.

[0040] Furthermore, the present invention provides an LED light source having a plurality of LED elements according to the present invention, the LED elements being electrically connected and drivable.

[0041] The terms used in this invention are defined below.

[0042] In the description of the embodiments of the present invention, when it is stated that each layer, region, line or substrate is formed on, above, under, or below, the terms on, above, under, below, and below all include the meanings of "directly" and "indirectly".

[0043] On the other hand, this invention statement was made with the support of the following national scientific research and development projects.

[0044] [Project Unique Number] 1711199993 [Project Number] 00281346 (A2024-0127) [Responsible Department] Ministry of Science, Technology and Information [Name of the organization responsible for project management (professional)] Korea Research Foundation [Research Project Title] Nanomaterials Technology Development Project (Strategic) [Research Topic Title] Development of 300 ppi High-Resolution Inorganic Light Emitting Diode Display Materials and Processing Technology with Inherent Tensile Strength Exceeding 30% [Project Implementing Organization] Hongik University Industry-University-Research Cooperation Foundation [Research Period] August 1, 2023 - December 31, 2027 [Project Unique Number] 1711192466 [Project Number] 2021R1A2C2009521 (A2023-0130) [Responsible Department] Ministry of Science, Technology and Information [Name of the organization responsible for project management (professional)] Korea Research Foundation [Research Project Title] Personal Basic Research (Information and Communication Technology Department) [Research Topic Title] Development of Dot Matrix LED Materials and Display Light Sources / Application Technologies [Name of the Institution Conducting the Project] Kookmin University [Research Period] March 1, 2021 - February 28, 2026 Invention Effects The LED element manufacturing method according to the present invention can obtain smaller and more numerous LED elements from a single wafer, while minimizing surface defects in each LED element caused by dry etching of the wafer and dead volume of each LED element caused by dangling bonds generated during wet etching. Furthermore, the wet etching process used to remove surface defects during LED element manufacturing actually results in dangling bonds on the sides of the element. An additional recovery process involving UV irradiation of these dangling bonds to adsorb water molecules minimizes surface strain in the LED element, thereby achieving higher efficiency properties. Moreover, light sources using small, high-efficiency LED elements can exhibit high resolution and high brightness, enabling their widespread use in various industries that utilize LED elements. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of a method for manufacturing an LED element according to an embodiment of the present invention.

[0046] Figure 2a This is a pair of execution schematic diagrams and cross-sectional SEM images of each step in an LED element manufacturing method according to an embodiment of the present invention, wherein the execution schematic diagram and cross-sectional SEM image on the left is related to step (1), and the execution schematic diagram and cross-sectional SEM image on the right is related to step (2).

[0047] Figure 2b The images are a pair of execution schematic diagrams and cross-sectional SEM photographs of each step in the LED element manufacturing method according to a comparative example of the present invention, wherein the execution schematic diagram and cross-sectional SEM photograph on the left are related to step (1), and the execution schematic diagram and cross-sectional SEM photograph on the right are related to step (2).

[0048] Figure 3 TEM photograph (left), high-resolution TEM photograph (middle), and diffraction pattern photograph (right) of an LED element manufactured by performing only step (I) of the LED element manufacturing method according to an embodiment of the present invention.

[0049] Figure 4 TEM photograph (left), high-resolution TEM photograph (middle), and diffraction pattern photograph (right) of an LED element manufactured by performing only step (I) of the LED element manufacturing method according to the comparative example of the present invention.

[0050] Figure 5 Raman spectra of the side surface (i.e., etched surface) of an LED element manufactured according to an embodiment and comparative example of the present invention.

[0051] Figure 6 XPS spectrum of the side surface (i.e., etched surface) of an LED element manufactured according to an embodiment and comparative example of the present invention.

[0052] Figure 7 In order to be in Figure 6 The Ga 3d binding peak spectrum shown separates the Ga-O, Ga-Ga, and Ga-N spectra and presents a graph that quantitatively represents the relative amounts of each bond, which is shown in a bar chart.

[0053] Figure 8 and Figure 9 The photoluminescence (PL) curves of an LED device manufactured according to an embodiment and a comparative example of the present invention were measured at 300 K and 10 K, respectively.

[0054] Figure 10 To utilize Figure 8 and Figure 9 The results show the internal quantum efficiency curves at different temperatures. In the table, "Pristine" refers to the wafer itself, "HDDE" refers to Comparative Example 1, "LDDE" refers to Comparative Example 1, "HDDE / SWE" refers to Comparative Example 1, and "LDDE / SWE" refers to Example 1.

[0055] Figure 11 This is a graph showing the afterglow time of an LED element manufactured according to an embodiment and a comparative example of the present invention. In the graph, "original" in the table represents the wafer itself, "HDDE" represents Comparative Preparation Example 1, "LDDE" represents Preparation Example 1, "HDDE / SWE" represents Comparative Example 1, and "LDDE / SWE" represents Example 1.

[0056] Figure 12 This is a schematic diagram illustrating the light emission mechanism of the recoverable-low-damage dry etching (right side) included in the present invention and the restrictive-high-damage dry etching (left side) that deviates from the present invention.

[0057] Figure 13 and Figure 14 The PL emission curve was measured by changing the UV irradiation time as a second recovery step when manufacturing an LED element according to an embodiment and comparative example of the present invention.

[0058] Figure 15 This is a graph showing the internal quantum efficiency of an LED element manufactured according to an embodiment and a comparative embodiment of the present invention after UV irradiation following the second recovery step. The internal quantum efficiency utilizes... Figure 8 and Figure 9The results (PL changes at different temperatures) were calculated.

[0059] Figure 16 and Figure 17 The images show the afterglow time curves of LED elements manufactured according to an embodiment and a comparative embodiment of the present invention, after UV irradiation following the second recovery step.

[0060] Figure 18 This is a schematic diagram illustrating the light emission mechanism of the delayed PL phenomenon in an LED element manufactured after UV irradiation following a second recovery step in an LED manufacturing method according to an embodiment of the present invention.

[0061] Figure 19 This is a schematic diagram of the manufacturing process of an LED electrode assembly and a cross-sectional SEM image of the manufactured LED electrode assembly, which corresponds to an electroluminescent element manufactured for measuring the external quantum efficiency of the obtained LED element.

[0062] Figure 20 and Figure 21 The graphs show the brightness and external quantum efficiency measured by changing the current density through LED electrode assemblies, wherein the LED electrode assemblies are LED elements manufactured according to embodiments and comparative examples of the present invention that have undergone UV irradiation with a second recovery step. Detailed Implementation

[0063] The embodiments of the present invention will now be described in detail to enable those skilled in the art to readily implement the invention. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0064] According to an embodiment of the LED element manufacturing method of the present invention, an LED element with a thickness of less than 10 μm and a cross-sectional area of ​​100 μm perpendicular to the thickness direction is separated and obtained from a wafer. 2 The following LED components may include the following steps: (1) a dry etching step, in which a predetermined pattern is dry etched from the top of the wafer toward the lower side in the thickness direction to create a plurality of structures spaced apart from each other, wherein the angle formed between the side of the structure serving as the etching surface and the bottom surface of the structure connected to the wafer is 84° or less; and (2) a first recovery step, in which wet etching is performed to remove surface defects on the side of the structure caused by dry etching.

[0065] First, step (1) of the present invention will be described, namely, the step of dry etching a wafer with a predetermined pattern downward along the thickness direction to manufacture a plurality of structures.

[0066] refer to Figure 1The wafer 100a prepared in step (1) can be any commercially available wafer, without limitation. As an example, the wafer 100a may include a substrate 1, a first conductive semiconductor layer 10, a photoactive layer 20, and a second conductive semiconductor layer 30 as the most basic structure. In this case, the first conductive semiconductor layer 10 may be an n-type conductive semiconductor layer, and the second conductive semiconductor layer 30 may be a p-type conductive semiconductor layer. The n-type and p-type conductive semiconductor layers may be any known conductive semiconductor layers used for light-emitting diodes, without limitation. For example, the n-type and p-type conductive semiconductor layers may include III-V semiconductors known as III-N nitride materials, especially binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen.

[0067] Specifically, the first conductive semiconductor layer 10 (i.e., the n-type conductive semiconductor layer) can be selected from a semiconductor material having an InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) structure, such as at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. More specifically, it may include gallium nitride (GaN), and may be doped with a first conductive dopant (e.g., Si, Ge, Sn, etc.). Furthermore, for example, the thickness of the first conductive semiconductor layer 10 within the wafer may be 100 nm to 20 μm.

[0068] Furthermore, the second conductive semiconductor layer 30 (i.e., the p-type conductive semiconductor layer) can be selected from a semiconductor material having the InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) structure, such as at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, InN, etc. Specifically, it can include gallium nitride (GaN), and can be doped with a second conductive dopant (e.g., Mg). According to a preferred embodiment of the present invention, the thickness of the second conductive semiconductor layer 30 can be 50~150nm, but is not limited thereto.

[0069] Furthermore, the photoactive layer 20 located between the first conductive semiconductor layer 10 and the second conductive semiconductor layer 30 can be formed as a single quantum well or multiple quantum well structure. The photoactive layer 20 can be any photoactive layer found in conventional LED elements used in lighting, displays, etc., and is not limited thereto. A cladding layer (not shown) doped with conductive dopant can be formed above and / or below the photoactive layer 20, and the cladding layer can be implemented as an AlGaN layer or an InAlGaN layer. Other materials such as AlGaN and AlInGaN can also be used as the photoactive layer 20. When an electric field is applied to the element, electrons and holes from the conductive semiconductor layers located above and below the photoactive layer 20 move towards the photoactive layer, where electron-hole pair bonding occurs, thereby generating light emission. According to a preferred embodiment of the present invention, the thickness of the photoactive layer 20 can be 50~200 nm, but is not limited thereto.

[0070] Furthermore, each layer within the wafer 100a can have a c-plane crystal structure. Additionally, the wafer 100a can undergo a cleaning process, which can appropriately employ conventional wafer cleaning solutions and processes; therefore, this invention does not impose any particular limitations on this. The cleaning solution can be, for example, isopropanol, acetone, and hydrochloric acid, but is not limited to these.

[0071] Simultaneously, an electrode layer 40 can be further formed on the second conductive semiconductor layer 30 of the aforementioned wafer 100a. Figure 1 (b)). The electrode layer 40 can be an electrode layer included in conventional LED elements used in lighting, displays, etc., and is not limited thereto. The electrode layer 40 can be a single layer formed from one of Cr, Ti, Al, Au, Ni, ITO and their oxides or alloys, or a single layer formed from a mixture of two or more materials, or a composite layer composed of layers formed from two or more materials respectively. The electrode layer 40 can be formed using conventional methods for forming electrode layers on semiconductor layers, for example, by sputtering deposition. Furthermore, the thickness of the electrode layer 40 can be 10~500 nm, but is not limited thereto. In addition, the electrode layer 40 can be further subjected to a rapid thermal annealing process after deposition. For example, the rapid thermal annealing process can be carried out at 600°C for 10 minutes; however, it can be appropriately adjusted according to factors such as the thickness and material of the electrode layer, and therefore the present invention does not impose any particular limitation on this.

[0072] After that, for the prepared wafers ( Figure 1(a) 100a, the upper part of wafer 100a is patterned with a predetermined pattern on a plane perpendicular to the thickness direction (i.e., the direction of each layer stacking in the final realized single LED element 101) (Figures 1(b) to (f)), so that it has a target shape and 100 μm 2 The following dimensions. Specifically, assuming an additional electrode layer 40 is formed on wafer 100a, a mask pattern layer can be formed on the upper surface of the electrode layer 40. The mask pattern layer can be formed using methods and materials commonly used in wafer etching, and the pattern of the pattern layer can be formed by appropriately applying conventional photolithography or nanoimprinting processes.

[0073] For example, such as Figure 1 As shown in (d), the mask pattern layer can be a stacked structure of a first mask layer 2, a second mask layer 3, and a resin pattern layer 4' with a predetermined pattern formed on the electrode layer 40. A brief description of the method for forming the mask pattern layer is provided. For example, the first mask layer 2 and the second mask layer 3 are formed by deposition on the electrode layer 40. Figure 1 (b)), and a patterned resin layer 4 is formed on the second mask layer 3. Figure 1 (c) serves as the base for the resin pattern layer 4'. Residual resin portions 4a of the resin layer 4 are removed using conventional methods such as RIE (reactive ion etching) to form the resin pattern layer 4'. Figure 1 (d)), and then the second mask layer 3, the first mask layer 2 and the electrode layer 40 are etched sequentially according to the pattern. Figure 1 (e) and (f)). In this case, the first mask layer 2 can be formed of, for example, silicon dioxide, and the second mask layer 3 can be a metal layer such as aluminum or nickel, and can be etched using RIE (reactive ion etching) and ICP (inductively coupled plasma), respectively. Simultaneously, during the etching of the first mask layer 2, the resin pattern layer 4' can also be removed (see reference). Figure 12 (f)

[0074] Furthermore, the patterned resin layer 4, which forms the basis of the resin pattern layer 4', can be formed by known methods such as nanoimprinting, photolithography using photosensitive materials, laser interference lithography, or electron beam lithography, and the present invention does not impose any particular limitation on this.

[0075] After that, as Figure 1 As shown in (f), a wafer 100g is obtained by dry etching from the top of the wafer 100a downward along the thickness direction according to a predetermined pattern on the second conductive semiconductor layer 30. This wafer 100g has a plurality of structures 101a spaced apart from each other on its sides. Figure 1As shown in (g). At this time, at least a portion of the thickness of the first conductive semiconductor layer 10 in wafer 100a can be dry etched, and can be appropriately controlled according to the thickness of the first conductive semiconductor layer in the LED element to be manufactured and the thickness of the first conductive semiconductor layer 10 in the wafer.

[0076] The dry etching can be performed using inductively coupled plasma-reactive ion etching (ICP-RIE). Preferably, when performing ICP-RIE, chemical etching is allowed to dominate compared to physical etching. Furthermore, preferably, dry etching is performed using ICP-RIE, making chemical etching more dominant than physical etching, and the included angle θ formed between the side surface ss of structure 101a (i.e., the etched surface after dry etching) and the bottom surface ls of the structure connected to the wafer is less than 84°, preferably 60° to 84°. Such an included angle on the side surface of the structure after dry etching can reduce the number of surface defects generated, and at the same time, the generated surface defects can be recovered by the step (2) described later, i.e., the first recovery step, and the recoverability can be further improved. This can ultimately significantly improve the internal quantum efficiency and external quantum efficiency of the obtained LED element 101.

[0077] refer to Figure 2a and 2b This will be explained further. Depending on whether physical or chemical etching dominates in dry etching using ICP-RIE, the angle between the etched surface and the main wafer surface will vary. Specifically, for example... Figure 2b As shown, when using ICP-RIE for dry etching, if physical etching is more dominant than chemical etching, the etched surface can be etched at an angle of over 85°, almost approaching 90°, relative to the main wafer surface. However, as... Figure 2a As shown, when dry etching using ICP-RIE makes chemical etching more dominant than physical etching, the etched surface can be etched at an angle, forming a cone shape rather than perpendicular to the bottom surface of the structure (or the main surface of the wafer).

[0078] Therefore, the manufacturing method of this invention employs ICP-RIE for dry etching, with chemical etching dominating over physical etching. This results in a cone-shaped etched surface after dry etching, and the degree to which chemical etching is superior to physical etching is such that the angle θ between the side surface ss of structure 101a (i.e., the etched surface after dry etching) and the bottom surface ls of the structure connected to the wafer is less than 84°. If physical etching dominates when using ICP-RIE for dry etching (see reference...), Figure 2bEven if chemical etching is dominant, if the angle θ between the side surface ss (i.e. the etched surface) of structure 101a and the bottom surface ls of structure connected to the wafer is greater than 84°, restrictive (unrecoverable or low-recovery) high-damage dry etching will occur, resulting in a large dead volume. Even if the amorphous structure surface on the side surface ss of structure 101a after dry etching is removed by performing the first recovery step (2) described later, there are still a large number of surface defects of various types, resulting in a negligible improvement in luminous efficiency.

[0079] In the following description, when the dry etching morphology is dominated by physical etching rather than chemical etching, specifically when the etched surface is etched at an angle of 85° or greater or close to 90° relative to the main surface of the wafer, it is referred to as restricted-high-damage dry etching or high-damage dry etching. Furthermore, when the dry etching morphology is dominated by chemical etching rather than physical etching, and the included angle θ between the side surface ss (i.e., the etched surface) of structure 101a and the bottom surface ls of the structure connected to the wafer is less than 84°, it is referred to as recoverable-low-damage dry etching or low-damage dry etching.

[0080] The surface defects generated by dry etching in step (1) above can include amorphous regions generated near the surface of the etched surface and defects caused by group III element vacancies (e.g., Ga vacancies). Figure 3 and Figure 4 As shown, the diffraction pattern (overlaid on the right side of the image) confirms that the LED structure was achieved using a restricted-high-damage dry etching method. Figure 4 ) and LED structures achieved using recoverable-low-damage dry etching ( Figure 3 Both maintained their crystal structure with almost no change. However, compared with the high-resolution TEM image (background image), the LED structure etched by the restrictive-high-damage dry etching method had a larger dark spot area caused by defects compared with the recoverable-low-damage LED structure, which corresponds to the dead volume of surface and internal defects. Therefore, it can be inferred that the high-damage dry etching method produces more surface defects than the low-damage dry etching method.

[0081] In addition, refer to Figure 5 It can be seen that in the restricted-high-damage dry etching process, at 687 cm⁻¹ -1 Defect peaks originating from Ga vacancies were observed near the wavenumber, and a small number of Ga vacancy defects were also observed during recoverable-low-damage dry etching. These results indicate that defects generated by dry etching include not only... Figure 3 and Figure 4The crystal structures shown to have increased defects also include group III element vacancies, such as Ga vacancies. However, regarding the number of group III element vacancies generated, such as Ga vacancies, the number of Ga vacancies generated in conventional vertical dry etching, i.e., restricted-high-damage dry etching, is greater, while the number of Ga vacancies observed in recoverable-low-damage dry etching is very small. This confirms that there is a significant difference in the number of defects after dry etching.

[0082] In addition, refer to Figure 6 and Figure 7 By measuring the Ga 3d peak in XPS spectra and performing bond separation spectra, it was confirmed that, in addition to Ga-N defects, Ga-Ga and Ga-O bonds also exist in both recoverable-low-damage dry etching and restricted-high-damage dry etching processes. However, by quantifying the relative amounts of each bond by measuring the Ga 3d peak in XPS spectra and performing bond separation spectra, it was confirmed that the Ga-O bond ratio in structures etched using the restricted-high-damage dry etching process reached 21% after dry etching. This represents an increase of approximately 90.1% compared to the wafer's own Ga-O bond ratio of 11%, and the Ga-Ga bond ratio also increased from 9% on the wafer itself to 23%, an increase of approximately 155.5%. Conversely, structures etched using the recoverable-low-damage dry etching method exhibited 10% Ga-O bonding after dry etching, a reduction of approximately 9.1% compared to the wafer's inherent Ga-O bonding of 11%. This confirms that the recoverable-low-damage dry etching method reduces Ga-O bonding, or more precisely, reduces the wafer's inherent Ga-O bonding, compared to the restrictive-high-damage dry etching method. These results indicate that both etching methods lead to Ga-O bonding (and / or Ga-Ga bonding) that constitutes the main surface defects after dry etching, but the number of defects generated by the two methods differs significantly, with the recoverable-low-damage dry etching method producing very few or no defects.

[0083] Furthermore, it is worth noting that even for the same type of defect, the degree of defect recovery in subsequent recovery processes can vary significantly depending on the dry etching conditions performed. For example... Figure 5 As shown, for structures etched using restricted-high-damage dry etching, the peak value caused by Ga vacancy defects only decreases slightly and remains almost unchanged even after the first recovery step of subsequent wet etching due to the presence of a large number of Ga vacancy defects. In contrast, for structures etched using recoverable-low-damage dry etching, Ga vacancy defects are hardly observed after the first recovery step of subsequent wet etching.

[0084] Simultaneously, Raman spectroscopy analysis was performed on the side surface of the LED structure after the recovery-low-damage dry etching step (1), at 687 cm⁻¹.-1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The ratio of the GaN Al(LO) mode peak area can be less than 15%. Furthermore, Raman spectroscopy analysis was performed on the side of the LED structure after the first recovery step (i.e., step (2)) of wet etching following the recoverable-low-damage dry etching step (1), at 687 cm⁻¹. -1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The ratio of the peak area of ​​GaN Al(LO) mode at that location can be below 8%.

[0085] Specifically, such as Figure 5 As shown, 687 cm -1 The mode peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The peak area ratio of GaN Al(LO) mode at the site was 23.5% after restrictive-high-damage dry etching, while the peak area ratio was only 10.6% after recoverable-low-damage dry etching, which confirms a significant reduction in the generation of Ga vacancy defects.

[0086] Meanwhile, quantum efficiency calculations also confirm that even after the first recovery step of wet etching, the defect recovery of structures etched using the restricted-high-damage dry etching method is negligible.

[0087] Specifically, such as Figure 8 As shown, at low temperatures (10 K), all samples exhibited similar PL intensities regardless of the etching method used. These results indicate that as the temperature decreases, the yellow luminescence and nonradiative recombination caused by surface defects are quenched and almost disappear because the surface defects no longer trap excited electrons. Instead, most excitons between the conduction band and valence band participate in radiative recombination, thus increasing the blue luminescence intensity, and most samples become similar in luminescence intensity.

[0088] However, as Figure 9 As shown, when PL was measured at room temperature (300 K), the restricted-high-damage dry-etched sample produced a large number of surface defects after dry etching. Even if the amorphous structure was removed by wet etching, a large number of surface defects would still remain. Therefore, although the blue luminescence intensity was restored to some extent, it did not achieve the expected enhancement effect.

[0089] In addition, such as Figure 10 As shown, the internal quantum efficiency calculated after confined-high-damage dry etching is 1.48%, reaching 14.0% after the first recovery step of subsequent wet etching. Although the first recovery step improves the internal quantum efficiency by about 10 times, the absolute value is still low. In contrast, the internal quantum efficiency of the recoverable-low-damage dry-etched sample reaches 40.4% even without the first recovery step. This confirms that using only recoverable-low-damage dry etching does not significantly reduce the internal quantum efficiency, which reaches 54.8% after the first recovery step of subsequent wet etching. The achieved internal quantum efficiency is very high, 3.9 times that of wet etching after confined-high-damage dry etching.

[0090] In addition, reference will be made Figure 11 This study investigates whether the efficiency differences in LED devices obtained using the aforementioned etching methods are caused by surface defect characteristics. In the recoverable-low-damage dry etching samples, the PL decay time was 106.9 ns after dry etching and extended to 204.3 ns after wet etching. In contrast, in the restricted-high-damage dry etching samples, the PL decay time was only 3.1 ns after dry etching and only 25.4 ns after wet etching, indicating that even after the first recovery step, the decay time remained relatively short. These results suggest that for LED devices achieved using restricted-high-damage dry etching, electrons generated by UV excitation after dry etching are trapped by energy levels caused by surface defects. Most of these electrons participate in non-radiative decay at the surface defect sites, while only a small portion emits yellow light and participates in radiative decay. Therefore, the decay time of blue emission is inevitably shortened. Therefore, the afterglow time of LED devices obtained by restrictive-high-damage dry etching is extremely short. Although it can be slightly extended by the first recovery step of wet etching, the afterglow time is still short even after the first recovery step. This result indicates that the absolute number of surface defects generated by dry etching is large, and although the number of surface defects is large, only a small number of defects can be removed, which are surface defects with limited recovery.

[0091] Conversely, the afterglow time of the recoverable-low-damage dry etched LED device is 106.9 ns, which is longer than that of the restrictive-high-damage dry etched LED device. Furthermore, after the first recovery step, the afterglow time is further extended to 204.3 ns. This result indicates that the absolute number of surface defects generated by dry etching is small, and most of these defects can be removed through the recovery process, making them recoverable surface defects.

[0092] Furthermore, structures etched using recoverable-low-damage dry etching may exhibit different average afterglow characteristics compared to structures etched using restrictive-high-damage dry etching. Specifically, prior to the first recovery step of wet etching (described later), the average afterglow time of structures etched using recoverable-low-damage dry etching, measured at 300 K, can be longer than that measured at 10 K. However, the average afterglow time of structures etched using restrictive-high-damage dry etching, measured at 300 K, can be shorter than that measured at 10 K.

[0093] Therefore, in conclusion Figures 5 to 11 As a result, structures generated using restrictive-high-damage dry etching produce an extremely large absolute number of defects, and the recovery ability of these surface defects is limited, with very low or no recovery. Conversely, structures generated using recoverable-low-damage dry etching produce a small absolute number of defects, and the recovery ability of these surface defects is very high, reaching the defect level inherent in the wafer before dry etching. Furthermore, it can be seen that, in addition to the execution of the recovery step, the method of executing the preceding dry etching also significantly affects the physical properties of the realized LED device.

[0094] At the same time, will refer to Figure 12 Specifically, the PL luminescence mechanism based on the dry etching method is explained. For restricted-high-damage dry etching, even though the surface defects are reduced by the first recovery step of wet etching in step (2) described later, as mentioned above, a large number of surface defects that cannot be removed still exist. This causes UV-excited electrons to be trapped by the defects. These defect-trapped electrons cause some yellow defect luminescence, and most of the electrons are lost due to non-radiative recombination by thermal (IR), thus reducing blue band-to-band luminescence. Conversely, for recoverable-low-damage dry etching, the surface defect density is significantly reduced after the first recovery step. Therefore, although the yellow defect luminescence is only slightly reduced, the loss caused by thermal or infrared (IR) non-radiative recombination is significantly reduced, and blue band-to-band luminescence is significantly enhanced.

[0095] According to one embodiment of the present invention, the etching rate of the recoverable-low-damage dry etching performed by the above-described ICP-RIE can be set such that the included angle θ formed between the side surface ss of structure 101a (i.e., the etched surface after dry etching) and the bottom surface ls of the structure connected to the wafer is 84° or less, preferably 60° to 84°. For example, the etching rate can be set to 200 nm / min or less, preferably 150 nm / min or less, and more preferably 10 to 100 nm / min, thereby reducing the number of surface defects generated and significantly improving the recoverability of surface defects. If the etching rate is less than 10 nm / min, the large etching depth will lead to difficulty in successful etching or excessive etching time. Furthermore, if the etching rate exceeds 200 nm / min, physical etching will dominate, resulting in a structure obtained by restrictive-high-damage dry etching.

[0096] Furthermore, the specific conditions for ICP-RIE used in recoverable-low-damage dry etching can vary depending on the specific device used. For example, the ICP power can be 50 to 350 W and the Rf power can be 10 to 100 W. More preferably, the ICP power can be 50 to 200 W and the Rf power can be 10 to 100 W.

[0097] Furthermore, as an additional condition for ICP-RIE, a chlorine-based gas containing BCl3 and Cl2 can be used as the process gas. In this case, the process gas flow rate can be 0-100 sccm for BCl3, or for example, 0-60 sccm for Cl2 and 0-100 sccm for Cl2, or for example, 0-60 sccm for Cl2. This is more conducive to achieving the objectives of the present invention. Simultaneously, when the chlorine-based gas contains both BCl3 and Cl2, the lower limit can be 0 sccm or more, except when both flow rates are 0 sccm. In addition to the chlorine-based gas, the process gas may also contain nitrogen, in which case the nitrogen flow rate can be 2-6 sccm. On the other hand, in one example, an inert gas (such as argon) may not be used as the process gas. Furthermore, the process pressure can be 1-100 mT, and the process can be performed at a DC bias voltage of 100-200 V, which is beneficial to achieving the objectives of the present invention. At the same time, it should be noted that the additional conditions required by the ICP-RIE, such as ICP power, Rf power and DC bias voltage, can be adjusted according to the specific ICP-RIE device to achieve the same effect.

[0098] Subsequently, according to step (2) of the present invention, a first recovery step of wet etching is performed to remove surface defects on the side of the structure caused by dry etching.

[0099] As described in step (1), during dry etching, the surface near the etched surface may contain various types of defects, such as amorphous regions, group III element vacancies (e.g., Ga vacancies), Ga-O and / or Ga-Ga bonds, etc. These surface defects can significantly reduce the luminous efficiency of the obtained LED device. Even if the recoverable-low-damage etching of the preferred step (1) is performed, the defect level may still be significantly higher than the inherent defects of the wafer itself. Therefore, according to step (2) of the present invention, a first recovery step of wet etching is performed on the dry-etched wafer 100g to remove the dead volume on the dry-etched structure 101a, thereby obtaining the first recovered wafer 100h. In addition, as Figure 3 As shown, even when the etching surface is an inclined cone shape and not perpendicular to the main surface of the wafer during the dry etching process, the angle formed by the lower part and the side (i.e. the etching surface) of the structure by wet etching can be etched to be close to perpendicular in the subsequent step (2).

[0100] Preferably, step (2) is performed such that the included angle θ between the side surface ss of the structure etched by wet etching and the bottom surface ls of the structure connected to the wafer is 85° or higher. The conditions for wet etching are not limited, as long as this angle can be formed. For example, the wet etching can be performed by immersing the structure in a wet etching solution containing ammonium salts or potassium with hydroxyl groups at a temperature of 60-100°C for 5-30 minutes, which can help achieve the purpose of this invention.

[0101] Furthermore, according to an embodiment of the present invention, Raman spectral analysis of the side surface (i.e., etched surface) of the LED structure after step (2) showed that at 687 cm⁻¹ -1 The peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The percentage of the GaN Al(LO) mode peak area can be below 8%, thereby significantly reducing surface defects. Specifically, such as Figure 5 As shown, after the first recovery step of wet etching following restrictive-high-damage dry etching, the peak area percentage of the Ga vacancy-related defect mode is approximately 11%. Conversely, after the first recovery step of wet etching following recoverable-low-damage dry etching, it can be confirmed that the peak area percentage of the Ga vacancy-related defect mode is reduced to approximately 4.8%. The number of Ga vacancy defects inherent on the side surface of the LED device is significantly reduced after recovery, ultimately resulting in an LED device with higher luminous efficiency.

[0102] Furthermore, XPS spectral analysis of Ga 3d bonding on the side surface (i.e., the etched surface) of the LED shows that the Ga-O bonding ratio is less than ±30% compared to the original Ga-O bonding ratio of the wafer. In other words, for recoverable-low-damage dry etching, the Ga-O bonds generated by dry etching can be restored to the level of inherent defects in the wafer before dry etching through the first recovery step of subsequent wet etching, and may even be improved. (Reference) Figure 6 and Figure 7 For recoverable-low-damage dry etching, the proportion of Ga-O bonding defects was confirmed to be reduced to 9%, lower than the 11% inherent to the wafer itself, representing an improvement compared to wafer-level defects. On the other hand, for restrictive-high-damage dry etching, the Ga-O bonding proportion decreased from 22% after the first recovery step of wet etching to 16%. However, this represents only a recovery of about 16% compared to the wafer's inherent Ga-O bonding proportion of 11% (an increase of 45.5% compared to the wafer itself), indicating a significant decrease in the physical properties of the obtained LED device.

[0103] In addition, refer to Figure 6 and Figure 7 Defects other than Ga-O bonding, namely Ga-Ga bonding, recovered to 12% after the first recovery step following recoverable-low-damage dry etching, slightly higher than the wafer's inherent proportion of 9%. This indicates that the defect recovery level is similar to or slightly increased compared to the pre-etching wafer defect level. Conversely, after the first recovery step following restrictive-high-damage dry etching, the Ga-Ga bonding proportion was confirmed to be 23%, a significant increase compared to the wafer's inherent proportion of 9%, making it difficult to achieve LED devices with wafer-level defects.

[0104] Meanwhile, as mentioned above, after the recoverable-low-damage dry etching in step (1) and the first recovery step in step (2), defects can be significantly removed and recovered. However, some defects may not be recovered to the level inherent to the wafer itself. In addition, the increase in dangling bonds increases the risk of strain on the side surfaces (i.e., the etched surfaces).

[0105] Therefore, according to an embodiment of the present invention, as step (3), after the first recovery step in step (2), the wet-etched structure can also be subjected to further processing ( ). Figure 1 The second recovery step of UV irradiation (100h) Figure 1 (i) can be used to recover residual defects and dangling bonds, so that the internal quantum efficiency can reach the internal quantum efficiency of the wafer itself before etching.

[0106] Specifically, refer to Figure 13For structures that have undergone a first recovery step of wet etching following recoverable-low-damage dry etching, UV irradiation can passivate residual defects and dangling bonds. Therefore, it can be confirmed that the emission peak intensity increases steadily with increasing UV irradiation time. Furthermore, due to the passivation of residual defects and dangling bonds, the increase in PL emission peak intensity can continue for a long time until passivation is complete; for example, defect passivation can reach saturation after approximately 12 hours of irradiation.

[0107] Furthermore, UV irradiation in the second recovery step cannot restore residual defects or dangling bonds on all dry-etched surfaces subjected to different conditions. That is, for structures subjected to the aforementioned restrictive-high-damage dry etching, even if a second recovery step involving UV irradiation is performed after the first recovery step of wet etching, the defects may be almost impossible to recover.

[0108] Specifically, refer to Figure 14 It can be confirmed that for structures that have undergone a first recovery step after restrictive-high-damage dry etching, their luminescence properties remain almost unchanged even after UV irradiation. Conversely, refer to... Figure 13 It can be confirmed that for structures that have undergone a first recovery step after recoverable-low-damage dry etching, the luminescence properties are improved by performing a second recovery step through UV irradiation.

[0109] In addition, refer to Figure 15 It can be seen that for LED devices obtained after performing the second recovery step under UV irradiation, when the internal quantum efficiency is calculated by measuring the low-temperature (10 K) PL and room-temperature (300 K) PL respectively, the internal quantum efficiency of LED devices obtained by restrictive-high-damage dry etching and wet etching after UV irradiation is 15.8%, which is slightly lower than or close to the level before UV irradiation. Conversely, the internal quantum efficiency of LED devices obtained by recoverable-low-damage dry etching and wet etching after UV irradiation is 71.1%, which is about 30% higher than the 54.8% before UV irradiation. It can be confirmed that its internal quantum efficiency is close to the internal quantum efficiency value of the wafer used before etching.

[0110] On the other hand, depending on the dry etching method, UV irradiation in the second recovery step may induce additional defects in some defects already recovered in the first recovery step. In other words, some defects generated during restrictive-high-damage dry etching may, even after the second recovery step, actually increase the level of defects already recovered in the first recovery step, thus reducing the total recovery amount after both steps. Conversely, some defects generated during recoverable-low-damage dry etching may maintain their recovered defect level even if the second recovery step fails to restore them to the level recovered in the first recovery step.

[0111] Furthermore, according to an embodiment of the present invention, Raman spectral analysis of the side surface (i.e., etched surface) of the LED structure after step (3) showed that at 687 cm⁻¹ -1 The peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The percentage of the GaN Al(LO) mode peak area can be below 8%, which is the same as that of the LED structure that has undergone step (2). This prevents the reduction of the total recovery due to additional defects caused by step (3), thereby reducing the improvement effect of physical properties.

[0112] Specifically, refer to Figure 5 During the first recovery step of wet etching following restricted-high-damage dry etching, the Raman spectrum at 687 cm⁻¹... -1 The peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The percentage of the GaN Al(LO) mode peak area at 11.0% increased to 13.8% after the second recovery step with UV irradiation. However, after the first recovery step with wet etching following recoverable-low-damage dry etching, the 687 cm⁻¹ peak area in the Raman spectrum... -1 The peak area of ​​the Ga vacancy-related defect mode at 746.62 cm⁻¹ is relative to the peak area at 746.62 cm⁻¹. -1 The percentage of the GaN Al(LO) mode peak area was 4.8%, which remained at 4.8% after the second recovery step of UV irradiation, preventing a decrease in recovery.

[0113] also, Figure 6 and Figure 7 The results also support this interpretation. Specifically, by measuring the Ga 3d peak in the XPS spectrum and separating the spectrum into Ga-N, Ga-Ga, and Ga-O bonds, and quantifying the relative amount of each bond, it can be seen that the Ga-O bond ratio of the structure achieved by restricted-high-damage dry etching is 19% after the first and second recovery steps, which is an increase of about 72.7% compared to the wafer's own Ga-O bond ratio of 11%. The Ga-Ga bond ratio also increased by about 133.3% from the wafer's own bonding ratio of 9% to 21%. Conversely, for structures etched using recoverable-low-damage dry etching, after the first and second recovery steps following dry etching, the Ga-O bonding ratio remains unchanged at 11%, compared to the wafer's own 11%. Therefore, it can be confirmed that, compared to the case of restrictive-high-damage dry etching followed by the first and second recovery steps, Ga-O bonding can be restored to the wafer level under the recoverable-low-damage dry etching followed by the first and second recovery steps. This indicates that Ga-O bonding is also one of the main causes of surface defects.

[0114] In addition, such as Figure 16 As shown, the average decay time of the LED element obtained after recoverable low-damage dry etching (step (1)), the first recovery step of wet etching, and the second recovery step of UV irradiation can remain unchanged or be longer as the temperature increases, preferably longer. For example, the average decay time measured at room temperature (300 K) can be longer than the average decay time measured at a low temperature (10 K). More preferably, the average decay time measured at 300 K is at least 30% longer than the average decay time measured at 10 K, thereby obtaining excellent luminous efficiency. In addition, the average decay time of the LED structure after performing step (2) can be longer at 300 K than that of the LED structure before performing step (2).

[0115] Conversely, such as Figure 17 As shown, the LED element obtained by the first recovery step of restricted-high-damage dry etching, wet etching, and UV irradiation, despite undergoing two recovery steps, has a shortened average afterglow time as the temperature rises from low temperature (10 K) to room temperature (300 K) due to the influence of high-density defects. This characteristic is consistent with the luminescence mechanism of typical high-defect luminescent materials.

[0116] Figure 16 and Figure 17 The results shown above are due to the passivation of surface defects by prolonged UV irradiation, forming shallow non-quenching traps. These traps induce delayed luminescence through multiple carrier trapping and release processes. While the significant reduction in defect levels through recoverable low-damage dry etching and wet etching is also a factor, the reversal of afterglow time with temperature indicates that UV passivation reduces residual defects and dangling bonds, transforming them into non-quenching traps.

[0117] Specifically, such as Figure 18As shown, prolonged UV irradiation passivates surface defects, reducing defect-induced radiative and non-radiative recombination and releasing electrons back into the conduction band. In this case, some UV-excited electrons emit light rapidly through pre-existing Eh recombination, resulting in a peak with a short afterglow time. Furthermore, some or all of the remaining UV-excited electrons are repeatedly captured and released by shallow and deep non-quenching traps. Some or all of the excited electrons returning to the conduction band emit light slowly, thus the delayed emission peak with prolonged afterglow time and the aforementioned peak with short afterglow time can coexist, ultimately leading to a prolonged afterglow time. Finally, compared to low temperature (10 K), the average afterglow time at room temperature (300 K) is longer. This phenomenon confirms that the second recovery step of UV irradiation passivates surface defects caused by dangling bonds into non-quenching traps, allowing the capture-release process to proceed smoothly at room temperature.

[0118] On the other hand, the UV irradiation in step (3) will adsorb water molecules (H2O) in the chemical form of -OH and -H onto the dangling bonds on the etched side surface, thereby relieving the strain caused by the dangling bonds and re-trapping the electrons trapped in the shallow and deep traps back to the conduction band, so that they can participate in luminescence to improve luminescence efficiency.

[0119] In addition, the UV wavelength of the irradiation in step (3) can be 250~400 nm, the irradiation intensity can be 1 mW~100 W, and the irradiation time can be 0.1~48 hours, which can be more conducive to achieving the purpose of the present invention.

[0120] Subsequently, the structure exposed to UV radiation can undergo a further step of forming a protective film 80. Figure 1 (j) and (k)), to protect the surface where dead volume is removed and residual defects are passivated. The protective film 80 can be formed by performing the following steps: First, a protective film material is deposited on the wafer on which the structure 101a has been formed after UV irradiation, forming a protective film 80a that surrounds the exposed surface of each structure 101a with a specified thickness. Figure 1 (j)); then, the protective film deposited on the upper surface S1 of the first conductive semiconductor layer 10 between adjacent structures 101a and the protective film formed above the electrode layer 40 are removed, thereby exposing the upper surface S1 of the first conductive semiconductor layer 10 between structures 101a and the electrode layer 40 to the outside (j) Figure 1The protective film material may include at least one selected from, for example, silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), scandium oxide (Sc2O3), titanium dioxide (TiO2), aluminum nitride (AlN), and gallium nitride (GaN). Furthermore, the thickness of the protective film 80 formed by depositing the protective film material may be 5 to 100 nm, more preferably 30 to 100 nm.

[0121] Then, the step of separating multiple structures from the wafer can be performed.

[0122] The plurality of structures can be separated from the wafer using known methods, and the present invention does not impose any particular limitation thereto. For example, the plurality of structures 101a can be separated from the wafer by removing a sacrificial layer or a separation layer on the wafer. Alternatively, according to Korean Patent Publication No. 2021-0132920 disclosed by the inventors of the present invention, the plurality of structures 101a can be separated by using a dicing tool or an adhesive film for separation after performing lateral etching along a direction parallel to the main surface of the wafer using wet etching. Alternatively, the plurality of structures 101a can be separated from the wafer by applying physical force (e.g., ultrasound) after lateral etching. Alternatively, according to Korean Patent Publication No. 2022-0096608 disclosed by the inventors of this invention, multiple pores are formed on the upper surface S1 of the first conductive semiconductor layer 10 between structures 101a and on the lower side of the first conductive semiconductor layer 10 connected thereto by an electrochemical method; then, the wafer is immersed in a bubble forming solution and ultrasonic waves are applied. The energy generated when the generated and grown bubbles burst in the pores is used to collapse the pores by utilizing the sonochemical mechanism, thereby separating the multiple structures 101a from the first conductive semiconductor layer 10 that forms the multiple pores, thereby obtaining an LED element assembly 100 having multiple LED elements 101 separated into individual LED elements.

[0123] In addition to the separation method proposed by the inventors of this invention, known methods such as laser lift-off, chemical lift-off, and mechanical lift-off can also be used to separate multiple structures from a wafer. This invention does not impose any particular limitations on the method used to separate LED structures with an area of ​​less than 100 μm².

[0124] The LED element 101 obtained by the above manufacturing method exhibits an afterglow time measured at 300 K that is the same as, and preferably even longer than, the afterglow time measured at 10 K. This characteristic stems from the fact that surface defects generated during the dry etching process are substantially removed, while residual defects and dangling bonds are passivated, thus enabling a successful capture-release process at room temperature. This indirectly proves that the internal quantum efficiency of the separately realized LED element 101 is almost equal to the internal quantum efficiency of the wafer 101a, which forms the basis of the LED element 101.

[0125] Furthermore, in the LED element 101, in the light emission measured at 300 K, the contribution of delayed light emission caused by shallow traps and deep traps may be greater than the contribution of bandgap light emission, more preferably more than twice, which can explain the efficiency improvement brought about by delayed light emission.

[0126] The thickness of the implemented LED element 101 can be less than 10 μm, for example, it can be 0.5~5 μm or 0.5~2.0 μm. Furthermore, the area of ​​the surface perpendicular to the thickness direction can be less than 100 μm² or less than 10 μm², but is not limited thereto. Additionally, the shape of the surface perpendicular to the thickness direction can be a polygon (e.g., a triangle, square, or rectangle) or a closed curve (e.g., a circle or ellipse), and the present invention does not impose any particular limitations on this.

[0127] Furthermore, the thickness of the first conductive semiconductor layer 10 in the LED element 101 can be 0.5~9.0 μm, but is not limited to this.

[0128] Furthermore, the LED element 101 implemented in one embodiment of the present invention, after being implemented as an LED electrode assembly, has a measured maximum external quantum efficiency of 5% to 20%, for example, according to reference... Figure 19 It can be confirmed that their efficiencies reached 7.02% and 13.76%, respectively.

[0129] Furthermore, the present invention also includes an ink composition comprising the aforementioned LED element 101. The ink composition may further comprise other components depending on the apparatus using the ink composition. For example, if the apparatus is an inkjet printer, the ink composition may also contain dispersion media and other additives found in ink compositions for inkjet printers; the present invention does not impose any particular limitation in this regard.

[0130] Furthermore, the present invention also includes an LED interposer or LED substrate containing a plurality of LED elements arranged at fixed intervals according to an embodiment of the present invention.

[0131] The LED interposer or LED substrate can be formed by arranging LED elements, which are separated by methods such as laser lift-off, chemical lift-off, or mechanical lift-off, at fixed intervals. Furthermore, the remaining components and manufacturing methods used to realize the LED interposer or LED substrate, other than the LED elements, can appropriately employ known components and manufacturing methods for LED interposers or LED substrates, and the present invention does not impose any particular limitations on this.

[0132] Furthermore, the present invention also includes a light source in which the aforementioned LED elements are electrically connected to be driven. The light source may be, for example, various indoor / outdoor LED lighting for homes / vehicles, displays, medical devices, beauty devices, various optical devices, or components thereof.

[0133] The invention will be described in more detail by way of the following embodiments; however, these embodiments are not intended to limit the scope of the invention, but should be understood as being intended to aid in the understanding of the invention.

[0134] <Example 1> Preparation Example 1 A conventional LED wafer (Epistar) is prepared by sequentially stacking an undoped n-type III nitride semiconductor layer, a silicon-doped n-type III nitride semiconductor layer (4 µm thick), a photoactive layer (0.15 µm thick), and a p-type III nitride semiconductor layer (0.05 µm thick) on a substrate. On the prepared LED wafer, ITO (0.15 µm thick) as an electrode layer, SiO2 (1.2 µm thick) as a first mask layer, and Ni (80.6 nm thick) as a second mask layer are sequentially deposited. Then, a SOG resin layer with a rectangular pattern is transferred onto the second mask layer using a nanoimprint lithography (NIRT) device. Subsequently, the SOG resin layer is cured using RIE, and residual resin is removed by RIE etching to form a resin pattern layer. The second mask layer is then etched using ICP according to the pattern, and the first mask layer is etched using RIE. Subsequently, using ICP-RIE, dry etching was performed on the first electrode layer, the p-type III nitride semiconductor layer, and the photoactive layer according to the process gas, process pressure, ICP power, Rf power, DC bias voltage, and etching rate shown in Table 1. Then, the doped n-type III nitride semiconductor layer was dry etched to a thickness of 0.5 μm, forming multiple spaced-apart structures. At this point, the angle between the side surface (i.e., the etched surface) of the dry-etched structure and the bottom surface of the structure was 80°.

[0135] Preparation Example 2 The wafer with multiple structures prepared in Example 1 was immersed in an ammonium salt etching solution containing hydroxyl groups for 13 minutes to perform the first recovery step of wet etching, thereby obtaining a wafer with the mask pattern layer removed and multiple structures (4 μm long side, 700 nm short side, and 950 nm high) formed.

[0136] <Example 2> The same steps as in Example 1 were used, but the dry etching conditions using ICP-RIE were adjusted as shown in Table 1 below to obtain a wafer with multiple structures. After dry etching according to the adjusted dry etching conditions, the angle between the side surface (i.e., the etched surface) and the bottom surface of the structure was 83°.

[0137] <Example 3> The same steps as in Example 1 were used, but the dry etching conditions using ICP-RIE were adjusted as shown in Table 1 below to obtain a wafer with multiple structures. After dry etching according to the adjusted dry etching conditions, the angle between the side surface (i.e., the etched surface) of the structure and the bottom surface of the structure was 82°.

[0138] <Comparative Example 1> Comparative Preparation Example 1 The same steps as in Preparation Example 1 of Example 1 were used, but the dry etching conditions using ICP-RIE were adjusted as shown in Table 1 below. After dry etching, the angle between the side surface of the structure (i.e., the etched surface) and the bottom surface of the structure was 88°.

[0139] Comparative Preparation Example 2 The wafer with multiple structures formed in Comparative Preparation Example 1 was subjected to wet etching using the same method as Preparation Example 2 of Example 1 to obtain the wafer with multiple structures.

[0140] <Example 4> Following the same steps as in Example 1, after performing the first recovery steps of dry etching and wet etching, the wafer was subjected to UV irradiation at a wavelength of 265 nm and an intensity of 3.3 mW for 24 hours to perform the second recovery step, thereby obtaining a wafer with multiple structures.

[0141] <Comparative Example 2> Following the same steps as Comparative Example 1, after performing the first recovery steps of dry etching and wet etching as in Preparation Examples 1-2, a second recovery step was performed by UV irradiation at a wavelength of 265 nm and an intensity of 3.3 mW for 24 hours, resulting in a wafer with multiple structures.

[0142] <Manufacturing Example> The separation method described in Korean Patent Publication No. 2022-0096608 disclosed by the inventors is used to separate multiple structures from a prepared wafer in which multiple structures are formed. Specifically, an Al2O3 temporary protective film (72 nm thick, based on the side of the structure) is deposited on the wafer in which the structures are formed. Then, the temporary protective film material formed between the multiple structures is removed by RIE to expose the upper surface of the doped n-type III nitride semiconductor layer between the structures.

[0143] Next, the LED wafer with a temporary protective film was immersed in an electrolyte solution of 0.3 M oxalic acid and connected to the anode terminal of the power supply. Simultaneously, a platinum electrode immersed in the electrolyte was connected to the cathode terminal, and a voltage of 15 V was applied for 5 minutes to form numerous pores along the thickness direction on the surface of the doped n-type III nitride semiconductor layer between the structures. Then, the temporary protective film was removed by ICP, and a 60 nm thick SiO2 protective film was deposited with the side of the LED structure as a reference. Subsequently, the spin-coating induced film material formed between the LED structures was removed by RIE to expose the upper surface of the doped n-type III nitride semiconductor layer between the structures. The wafer was then immersed in a 100% γ-butyrolactone foaming solution and irradiated with ultrasound at 160 W and 40 kHz for 10 minutes. The generated bubbles caused the pores formed in the doped n-type III nitride semiconductor layer to collapse, thereby obtaining multiple LED elements separated from the wafer.

[0144] [Table 1]

[0145] <Experimental Example 1> The following physical property measurements were performed on the wafers with multiple structures obtained according to Examples 1-4 and Comparative Examples 1-2.

[0146] 1. SEM photo taking SEM images were taken of each structure formed on the wafers obtained by Preparation Example 1 and Example 1, as well as Comparative Preparation Example 1 and Comparative Example 1. The results are as follows: Figure 2a (Left: Preparation Example 1, Right: Example 1) and Figure 2b (Left: Comparison of Example 1, Right: Comparison of Example 1) As shown.

[0147] refer to Figure 2a and 2b It can be seen that, In dry etching using ICP-RIE, if physical etching dominates over chemical etching, then... Figure 2bAs shown in the schematic diagram and photograph on the left, the etched surface is etched at an angle of 88° relative to the main surface of the wafer, almost 90°; however, when dry etching using ICP-RIE makes chemical etching more dominant than physical etching, then as... Figure 2a As shown in the schematic diagram and photograph on the left, the etched surface is etched at an angle, forming a cone shape.

[0148] On the other hand, after wet etching, such as Figure 2a and 2b As shown in the schematic diagram and photograph on the right, the etched surface forms an angle of nearly 90° with respect to the main surface of the wafer.

[0149] 2. TEM Photograph Acquisition and Analysis For the wafers with multiple structures obtained according to Preparation Example 1 of Example 1 and Comparative Preparation Example 1 of Comparative Example 1, TEM images were taken of the side surface (etched surface) of any one of the structures, and the results are as follows. Figure 3 (Example 1) and Figure 4 (As shown in Example 1 for comparison).

[0150] refer to Figure 3 and 4 It can be seen that, Whether comparing the structure etched using the restricted-high-damage dry etching method in Preparation Example 1 or the structure etched using the recoverable-low-damage dry etching method in Example 1, the diffraction patterns (refer to the upper right corner of each figure) confirm that the crystal structure is well preserved with minimal changes.

[0151] However, observation of high-resolution TEM images reveals that, compared to the structure etched using the recoverable-low-damage dry etching method in Preparation Example 1, the structure etched using the restrictive-high-damage dry etching method in Preparation Example 1 exhibits a larger dark spot area caused by defects, i.e., a dead volume. Therefore, it can be inferred that the restrictive-high-damage dry etching method produces more surface defects than the recoverable-low-damage dry etching method.

[0152] 3. Raman spectroscopy and XPS analysis Raman spectroscopy measurements were performed on wafers identical to those used in Example 1, as well as wafers with multiple structures obtained according to Preparation Example 1, Example 1, Example 4, Comparative Preparation Example 1, Comparative Example 1, and Comparative Example 2. The spectral results at different wavelengths are as follows: Figure 5 As shown. Furthermore, Figure 6 The spectrum of Ga 3d bonding peaks obtained from XPS analysis is shown. Furthermore, using... Figure 6The results showed that Ga-O, Ga-Ga, and Ga-N spectra were separated, and their relative quantities were quantified using a Gaussian function, as shown in the figure. Figure 7 As shown.

[0153] refer to Figure 5 It can be seen that, Comparative preparation 1 for restricted-high-damage dry etching was performed at 687 cm⁻¹ -1 Defect peaks originating from Ga vacancies were observed near the wavenumber, and a small number of Ga vacancy defects were also observed in Preparation Example 1, which underwent recoverable-low-damage dry etching.

[0154] Furthermore, in Comparative Example 1, which underwent a first recovery step via wet etching after restricted-high-damage dry etching, its 687 cm⁻¹… -1 The peak area of ​​the Ga vacancy-related defect mode relative to 746.62 cm⁻¹ -1 The percentage of the GaN Al(LO) mode peak area is approximately 11.0%. Conversely, in Example 1, which involves a first recovery step of wet etching after recoverable-low-damage dry etching, it was confirmed that the percentage of the Ga vacancy-related defect mode peak area decreased to approximately 4.8%. This indicates that the number of Ga vacancy defects inherent on the side surface of the LED element is significantly reduced after recovery, ultimately resulting in an LED element with superior luminous efficiency.

[0155] Furthermore, in Comparative Example 2, which involved a first recovery step of restricted-high-damage dry etching, a second recovery step of wet etching, and a second recovery step of UV irradiation, at 687 cm⁻¹... -1 Defect peaks originating from Ga vacancies were observed near the wavenumber. However, in Example 4, which involved a first recovery step of recoverable-low-damage dry etching, wet etching, and a second recovery step of UV irradiation, very few Ga vacancy defects were observed, thus confirming that the defects were significantly recovered.

[0156] In addition, refer to Figure 6 and Figure 7 It can be seen that, In the structure of Comparative Preparation Example 1 obtained by restricted-high-damage dry etching, the Ga-O bonding increased from 11% to 21% of the wafer itself after dry etching, an increase of approximately 90.1%; and the Ga-Ga bonding also increased from 9% to 23% of the wafer itself, an increase of approximately 156%. On the other hand, in the structure obtained by Preparation Example 1 using recoverable low-damage dry etching, the Ga-O bonding ratio decreased from 11% to 10% after dry etching, a decrease of approximately 9.1%, while the Ga-Ga bonding ratio increased from 9% to 20%, an increase of approximately 122%. This indicates that compared to Comparative Preparation Example 1, the Ga-O bonding was reduced, and the increase in Ga-Ga bonding was also smaller.

[0157] Furthermore, in Example 1, which involved a first recovery step of wet etching following recoverable-low-damage dry etching, the Ga-O bonds generated by dry etching were significantly reduced, recovering to 9%, an improvement compared to the wafer's inherent Ga-O bond ratio of 11% before dry etching. The Ga-Ga bonds also recovered to 12%, slightly higher than the wafer's inherent Ga-Ga bond ratio of 9%. However, in Comparative Example 1, which involved a first recovery step of wet etching following restrictive-high-damage dry etching, even after the first recovery step, the Ga-Ga bonds generated by dry etching were not removed, reaching a Ga-Ga bond ratio of 23%, significantly higher than the final wafer's inherent Ga-Ga bond ratio of 9%. Moreover, in Comparative Example 1, due to the first recovery step, the Ga-O bond ratio generated by dry etching decreased from 21% to 16%, but this was still significantly higher than the wafer's inherent Ga-O bond ratio of 11%, confirming that the recovery was minimal compared to Comparative Example 1.

[0158] Furthermore, in Comparative Example 2, after restrictive-high-damage dry etching, a first recovery step involving wet etching and a second recovery step involving UV irradiation were performed. Despite these two recovery steps, the Ga-O bonding ratio ultimately reached 19%, an increase of approximately 72.7% compared to the wafer's own Ga-O bonding ratio of 11%. Moreover, after the first recovery step following restrictive-high-damage dry etching, the Ga-O bonding ratio recovered from 21% to 16%. However, after the second recovery step, the Ga-O bonding ratio increased to 19%, indicating that the Ga-O bonding did not recover further in the second recovery step but instead increased.

[0159] Furthermore, in Comparative Example 2, despite the first and second recovery steps, the Ga-Ga bonding ratio still increased from 9% of the wafer itself to 21%, an increase of approximately 133.3%. The Ga-Ga bonding ratio after the first recovery step was the same as that after dry etching, both being 23%, indicating that the first recovery step in Comparative Example 2 failed to recover Ga-Ga bonds, or recovered very little.

[0160] Conversely, in Example 4, the structure of Preparation Example 1, which was prepared using recoverable-low-damage dry etching, underwent a first recovery step and a second recovery step. The Ga-O bonding ratio decreased from 11% of the wafer itself to 10%, and the Ga-O bonding defects were restored to the wafer state before dry etching, or even to a better level. Furthermore, in Example 4, the Ga-Ga bonding ratio was 11%, which, although slightly higher than the wafer's own 9% (an increase of approximately 22% compared to the wafer itself), can be assessed as having been restored to a level close to the wafer state before dry etching. Moreover, it can be assessed that the degree of Ga-Ga bonding defect recovery in Example 4 is significantly superior to that in Comparative Example 2.

[0161] 4. Evaluation of PL and internal quantum efficiency at different temperatures Photoluminescence (PL) was measured at 300 K and 10 K for wafers identical to those used in Example 1, and wafers with multiple structures obtained according to Preparation Example 1, Example 1, Example 4, Comparative Preparation Example 1, Comparative Example 1, and Comparative Example 2. The results are as follows: Figure 8 and Figure 9 As shown.

[0162] Furthermore, using the measured PL changes at different temperatures, the internal quantum efficiency was calculated using the following formula 1, and the results are as follows: Figure 10 As shown.

[0163] [Formula 1] η IQE =IPL(300K) / IPL(10K) In Formula 1, IPL(A) represents the integral value of the PL intensity measured at absolute temperature AK.

[0164] In addition, refer to Figures 8 to 10 It can be seen that, exist Figure 9 At the low temperature (10 K) shown, the PL intensity of the examples and comparative examples was almost the same regardless of the etching method used. This can be explained by the fact that as the temperature decreases, the yellow luminescence and nonradiative recombination caused by the defects are quenched and almost disappear because the surface defects no longer trap the excited electrons, while most of the excitons between the conduction band and the valence band participate in radiative recombination, thus increasing the blue luminescence intensity, and the luminescence intensity of most samples becomes similar.

[0165] However, reference Figure 8It can be seen that when PL was measured at room temperature (300 K), Comparative Preparation Example 1, after restrictive-high-damage dry etching, generated a large number of surface defects after dry etching. Even after removing the amorphous surface structure by wet etching (Comparative Example 1), a large number of surface defects remained, resulting in some recovery of blue light intensity, but not achieving the expected enhancement effect. However, in Examples 1 and 2, the blue light intensity was significantly enhanced because the surface defects formed by dry etching were recovered.

[0166] On the other hand, reference Figure 10 It can be seen that the internal quantum efficiency of Comparative Example 1 after restrictive-high-damage dry etching is 1.48%, while the internal quantum efficiency of Comparative Example 1 after the first recovery step of subsequent wet etching reaches 14.0%. Therefore, it can be confirmed that after the first recovery step, the internal quantum efficiency of Comparative Example 1 is about 10 times higher than that of Comparative Example 1, but the absolute value is still low. On the other hand, in the preparation example 1 after recoverable-low-damage dry etching, even without the first recovery step, its internal quantum efficiency reaches 40.4%; while the internal quantum efficiency of Example 1 after the first recovery step of wet etching reaches 54.8%. Therefore, it can be determined that even if only recoverable-low-damage dry etching is used, the internal quantum efficiency will not decrease significantly, and the internal quantum efficiency of Example 1 is about 3.9 times that of Comparative Example 1.

[0167] 5. Afterglow Time Assessment 1 For wafers identical to those used in Example 1, and wafers with multiple structures obtained according to Preparation Example 1, Example 1, Comparative Preparation Example 1, and Comparative Example 1, the afterglow time was measured using time-correlated single-photon counting (TCSPC), and the results are as follows: Figure 11 As shown.

[0168] refer to Figure 11 It can be seen that, The PL afterglow time of the sample in Preparation Example 1 after recoverable-low-damage dry etching was 106.9 ns, while the afterglow time of the sample after the first recovery step of subsequent wet etching, i.e. Example 1, was extended to 204.3 ns.

[0169] Conversely, the afterglow time of Comparative Preparation Example 1 after restrictive-high-damage dry etching was 3.1 ns, while the afterglow time of the sample after the first recovery step of subsequent wet etching, i.e. Comparative Example 1, was extended to 25.4 ns, but was still significantly shorter than that of Preparation Example 1 and Example 1.

[0170] 6. PL luminescence characteristics and internal quantum efficiency based on UV irradiation time For the wafers with multiple structures obtained by changing the UV irradiation time in the second recovery step in Examples 4 and Comparative Example 2, PL luminescence was measured, and the results are as follows: Figure 13 (Example 4) and Figure 14 As shown in (Comparative Example 2).

[0171] Furthermore, photoluminescence (PL) was measured at 300 K and 10 K. Using the measured PL changes at different temperatures, the internal quantum efficiency was calculated using Equation 1 above, and the results are as follows: Figure 15 As shown.

[0172] refer to Figure 13 and 14 It can be seen that, In Example 4, after recoverable-low-damage dry etching, a first recovery step of wet etching and a second recovery step of UV irradiation were performed. Since the defects were passivated by moisture, the intensity of the emission peak continued to increase with the extension of UV irradiation time.

[0173] However, Comparative Example 2 underwent a first recovery step of wet etching and a second recovery step of UV irradiation after restrictive-high-damage dry etching. Even though UV irradiation was performed in the second recovery step, its luminescence properties remained almost unchanged.

[0174] 7. Afterglow Time Assessment 2 The afterglow times of Example 4 and Comparative Example 2 were measured using the same method as in Experimental Example 1, and the results are as follows: Figure 16 (Example 4) and Figure 17 (Comparative Example 2) is shown. In this case, the LED elements corresponding to Example 4 and Comparative Example 2 were irradiated with UV for 24 hours.

[0175] refer to Figure 16 and Figure 17 It can be seen that, Example 4 underwent a first recovery step of recoverable-low-damage dry etching and wet etching, followed by a second recovery step of UV irradiation. The afterglow time of the LED device corresponding to Example 4, measured at room temperature (300 K), was longer than that measured at a low temperature (10 K). Conversely, Comparative Example 2 underwent a first recovery step of restrictive-high-damage dry etching and wet etching, followed by a second recovery step of UV irradiation. Although the LED device corresponding to Comparative Example 2 underwent two recovery steps, the afterglow time showed a decreasing trend as the temperature increased from low temperature (10 K) to room temperature (300 K), exhibiting typical luminescence mechanism characteristics of high-defect luminescent materials.

[0176] 8. External quantum efficiency assessment For a wafer with multiple structures formed according to Examples 1, 4, and Comparative Example 1, the multiple structures are separated from the wafer according to the above manufacturing example to obtain LED elements. Subsequently, each obtained LED element is processed according to... Figure 19 As shown, the LEDs are mounted on spaced-apart lower electrodes on a substrate, and an upper electrode is formed above the mounted LED element to form an LED electrode assembly. In this case, the LED element corresponding to Example 2 was irradiated with UV light for 24 hours.

[0177] Specifically, a first lower electrode and a second lower electrode extending along a first direction are formed on a 500 μm thick quartz substrate. The first and second lower electrodes are alternately arranged at 3 μm intervals along a second direction perpendicular to the first direction to form a lower electrode line. At this time, both the first and second lower electrodes have a width of 10 μm and a thickness of 0.2 μm, are made of gold, and the mounting area of ​​the LED element in the lower electrode line is set to 1 mm². Then, the prepared LED element is mixed with acetone to prepare a solution. Two 9 μm thick solutions are added dropwise to the mounting area. A 10 kHz, 40 Vpp sinusoidal AC power supply, serving as a combined power source, is then applied to the first and second lower electrodes. The ultrathin sheet-like LED element is mounted onto the lower electrode by dielectrophoresis.

[0178] Subsequently, a 100 nm thick SiO2 passivation material was deposited using a PECVD process for the first planarization treatment. Then, SU-8 photoresist was applied to the mounting area of ​​the LED element to a thickness corresponding to the LED element's thickness. After etching to expose the upper surface of the LED element, multiple upper electrodes (10 μm wide, 0.2 μm thick, 3 μm electrode spacing, TCO material) extending in a second direction perpendicular to the first direction and spaced apart from each other along the first direction were formed on the top surface of the mounted LED element, thereby forming the LED electrode assembly.

[0179] Next, a driving power supply was applied to the upper and lower electrodes of the LED electrode assembly, and the current density was changed to make it emit light. The brightness was then measured, and the results are as follows: Figure 20 As shown. Furthermore, utilizing... Figure 8 and Figure 9 The calculated external quantum efficiency is as follows Figure 21 As shown.

[0180] refer to Figure 20 and Figure 21 It can be seen that, The maximum external quantum efficiency (EQ) of the LED electrode assembly equipped with the LED element of Comparative Example 1 is only 2.65%, while the maximum external quantum efficiency of the LED electrode assembly equipped with the LED element of Example 1 reaches 7.02%, and the external quantum efficiency of the LED electrode assembly equipped with the LED element of Example 2 reaches 13.76%.

[0181] Furthermore, based on the current density of the applied power supply, the brightness of the LED electrode assembly equipped with the LED element of Comparative Example 1 was measured to be 1024 cd / m² at 112 mA / m², while the brightness of the LED electrode assembly equipped with the LED element of Example 1 reached 2637 cd / m² at 110 mA / m², and the brightness of the LED electrode assembly equipped with the LED element of Example 4 reached 3747 cd / m² at 110 mA / m².

[0182] In summary, the LED element of Embodiment 4 of the present invention restores the etched surface defects and dangling bonds, exhibiting excellent luminous efficiency. Furthermore, when the element is used to manufacture an LED electrode assembly as an electroluminescent element, it can achieve significantly superior external quantum efficiency and brightness enhancement.

[0183] Although an embodiment of the present invention has been described above, the technical concept of the present invention is not limited to the embodiment presented in this specification. Those skilled in the art who understand the technical concept of the present invention can easily propose other embodiments by adding, modifying, deleting or adding components within the same technical concept, and such embodiments will also be considered to fall within the technical concept of the present invention.

Claims

1. A method for manufacturing an LED element, comprising separating and obtaining an LED element with a thickness of less than 10 μm and a cross-sectional area of ​​100 μm perpendicular to the thickness direction from a wafer. 2 The following LED components include the following steps: (1) Dry etching step: Dry etching is performed from the top of the wafer toward the lower side in the thickness direction according to a predetermined pattern to create multiple structures spaced apart between the side surfaces, wherein, The angle formed between the side surface of the structure that serves as the etching surface and the bottom surface of the structure connected to the wafer is less than 84°. as well as (2) The first recovery step is to perform wet etching to remove surface defects on the side of the structure caused by dry etching.

2. The LED element manufacturing method according to claim 1, wherein, The dry etching in step (1) is performed by inductively coupled plasma-reactive ion etching (ICP-RIE) at an etching rate of less than 200 nm / min.

3. The LED element manufacturing method according to claim 2, wherein, The inductively coupled plasma-reactive ion etching process uses 0-100 sccm of BCl3 and 0-100 sccm of Cl2 chlorine gas as process gases and is carried out at a process pressure of 1-100 mT.

4. The LED element manufacturing method according to claim 1, wherein, The average afterglow time of the LED structure after performing step (1) and before performing step (2) was longer at 300 K than the average afterglow time measured at 10 K.

5. The LED element manufacturing method according to claim 1, wherein, The Raman spectral analysis results of the LED structure after step (1) were obtained at 687 cm⁻¹. -1 The peak area of ​​the nearby Ga vacancy-related defect mode relative to 746.62 cm⁻¹ -1 The ratio of the peak area of ​​the nearby GaN Al(LO) mode is less than 15%.

6. The LED element manufacturing method according to claim 1, wherein, Perform step (2) to make the angle between the side surface of the structure etched by wet etching and the bottom surface of the structure connected to the wafer greater than 85°.

7. The LED element manufacturing method according to claim 1, wherein, The structure has a first conductive semiconductor layer, a photoactive layer, and a second conductive semiconductor layer, all based on gallium nitride (GaN) semiconductors. According to the Ga 3d bonding analysis results of XPS spectrum, the proportion of Ga-O bonds that are defects in Ga-N and Ga-O bonds on the side of the LED structure that has undergone step (2) varies by less than ±30% relative to the Ga-O bond proportion of the wafer itself.

8. The LED element manufacturing method according to claim 1, wherein, After performing step (2), the average afterglow time of the LED structure measured at 300 K was longer than the average afterglow time measured at 10 K.

9. The LED element manufacturing method according to claim 1, wherein, After performing step (2), the average afterglow time of the LED structure measured at 300K is longer than that of the LED structure before performing step (2).

10. The LED element manufacturing method according to claim 1, wherein, After performing step (2), the following steps are also included: (3) Second recovery step: Irradiate the LED structure with UV light.

11. The LED element manufacturing method according to claim 1, wherein, The internal quantum efficiency of the manufactured LED element is 70 to 130% of the internal quantum efficiency of the wafer.

12. An LED element obtained by etching a wafer along its thickness direction and then separating the etched structure from the wafer, wherein the thickness is less than 10 μm and the cross-sectional area perpendicular to the thickness direction is less than 100 μm², wherein... Furthermore, the average decay time measured at 300K is equal to or greater than the average decay time measured at 10K.

13. The LED element according to claim 12, characterized in that, In the luminescence measured at 300 K, delayed luminescence caused by shallow and deep traps contributed more to the luminescence than the luminescence within the band gap.

14. The LED element according to claim 13, characterized in that, In the luminescence measured at 300 K, the contribution of delayed luminescence caused by shallow and deep traps was more than twice that of the contribution of bandgap luminescence.

15. The LED element according to claim 12, wherein, The average afterglow time measured at 300 K was more than 15% longer than the average afterglow time measured at 10 K.

16. The LED element according to claim 12, wherein, It has a first conductive semiconductor layer, a photoactive layer, and a second conductive semiconductor layer, all based on gallium nitride (GaN) semiconductors. For the Ga 3d bonding analysis results based on XPS spectra on the side of the LED element, the proportion of Ga-O bonds that are defects in Ga-N and Ga-O bonds varies by less than ±30% relative to the proportion of Ga-O bonds on the wafer itself.

17. The LED element according to claim 12, wherein, Raman spectroscopy analysis results, 687 cm⁻¹ -1 The peak area of ​​the nearby Ga vacancy-related defect mode relative to 746.62 cm⁻¹ -1 The ratio of the peak area of ​​the nearby GaN Al(LO) mode is less than 8%.

18. The LED element according to claim 12, wherein, Water molecules are adsorbed on the dangling bonds on the side surface of the LED element.

19. An LED assembly for transfer, wherein, include: Substrate used for transfer; as well as A plurality of LED elements according to any one of claims 12 to 18, the LED elements being arranged at predetermined intervals on the substrate for transfer.

20. An LED light source comprising a plurality of LED elements according to any one of claims 12 to 18, the LED elements being drivable by electrical connection.

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