Display semiconductor device and preparation method thereof

Abstract

The invention provides a display semiconductor device and a preparation method thereof. The display semiconductor device comprises a driving substrate, a pixel unit and a metal bonding layer. The driving substrate is provided with a first contact; the pixel units are located above the driving substrate, and the transverse size is at least partially increased from bottom to top; the metal bonding layers are arranged on the surface of the driving substrate, are electrically connected with the first contacts, extend to the side walls of the pixel units and are electrically connected with the first semiconductor layers in a large area, and the metal bonding layers of the adjacent pixel units are mutually isolated. Through large-area contact between the metal bonding layer and the first semiconductor layer, the contact resistance is reduced, and the luminous efficiency is improved. And large-area medium-free continuous metal layer bonding is adopted, and compared with mixed bonding or salient point bonding, the difficulty of the bonding process is remarkably reduced. The metal bonding layer extends to the side wall, the heat dissipation area is increased, a three-dimensional heat diffusion path is formed, heat accumulation in the device is effectively reduced, thermal stress generated by difference of thermal expansion coefficients is reduced, the interface stripping risk is restrained, and reliability is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor light-emitting devices and their integration technology manufacturing, and relates to a display semiconductor device and its preparation method. Background Technology

[0002] Taking the field of Micro-LED micro-displays as an example, device size designs are typically within 100 micrometers, and with technological advancements, they are gradually shrinking to 1μm~5μm, and even evolving towards the nanometer scale. Existing technologies commonly employ inverted trapezoidal structures and rely on metal contacts at the bottom of the pixel unit to bond with the driving substrate.

[0003] However, the aforementioned inverted trapezoidal structure still presents the following problems in practical applications: 1) High manufacturing difficulty: The metal contacts are located at the bottom of the pixel unit and their size decreases as the pixel size shrinks, leading to increased contact processing difficulty, higher requirements for bonding alignment process conditions, and increased process complexity and manufacturing costs. 2) Degraded device performance: The reduced contact size limits the contact area, increases contact resistance, and consequently increases the overall resistance of the LED, reducing luminous efficiency and hindering low-power applications. 3) Reliability issues: The thermal expansion coefficients of the metal contacts and the surrounding passivation layer are mismatched, and the small contact size and narrow heat dissipation path make it difficult for heat to dissipate during LED operation, easily leading to heat accumulation, device performance degradation, or even failure.

[0004] Therefore, how to effectively overcome the problems of high difficulty in processing metal contact size, high device resistance and poor heat dissipation caused by pixel miniaturization, and achieve synergistic optimization of optical and electrical performance, has become a technical problem that urgently needs to be solved in this field.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a display semiconductor device and its preparation method, which aims to effectively reduce the light emission scattering angle and improve brightness, while overcoming the problems of high difficulty in processing metal contact size, high device resistance and poor heat dissipation performance caused by pixel miniaturization.

[0007] To achieve the above and other related objectives, the present invention provides a display semiconductor device, the display semiconductor device comprising:

[0008] A display semiconductor device, characterized in that it comprises:

[0009] The driving substrate is provided with a first contact.

[0010] A pixel unit, located above the driving substrate, includes a first semiconductor layer, an active layer, and a second semiconductor layer disposed from bottom to top; wherein, in the vertical direction away from the driving substrate, the lateral dimension of the pixel unit increases in at least a portion of the range.

[0011] A metal bonding layer is disposed on the surface of the driving substrate and contacts the first contact surface to achieve electrical connection; the metal bonding layer extends to at least a portion of the sidewall of the pixel unit and is electrically connected to the first semiconductor layer, but has no direct contact with the active layer and the second semiconductor layer;

[0012] The metal bonding layers of adjacent pixel units are isolated from each other.

[0013] Optionally, the lateral dimension of the bonding surface of the metal bonding layer is greater than or equal to the maximum lateral dimension of the pixel unit.

[0014] Optionally, the portion of the pixel unit with increased lateral size includes at least one first portion and at least one second portion that are sequentially connected along the vertical direction; wherein the lateral size of the first portion gradually increases along the vertical direction.

[0015] Optionally, it may also include an isolation structure located between adjacent pixel units.

[0016] Optionally, the isolation structure includes a trench and a second passivation layer, the second passivation layer at least covering the sidewalls of the trench.

[0017] Optionally, it also includes a first passivation layer, wherein the sidewall of the pixel unit has a turning point, and the turning point is the position where the lateral dimension of the pixel unit is the largest.

[0018] Optionally, the second passivation layer covers the sidewall above the inflection point of the pixel unit, and the first passivation layer covers at least the sidewall below the inflection point.

[0019] Optionally, below the inflection point, the lateral dimension of the pixel unit remains monotonically constant along the vertical direction; above the inflection point, the lateral dimension of the pixel unit remains monotonically constant along the vertical direction.

[0020] Optionally, the inflection point corresponds to the active layer or the second semiconductor layer.

[0021] Optionally, above the inflection point, at least a portion of the sidewalls of the second semiconductor layer and / or the active layer are substantially vertical.

[0022] Optionally, when the inflection point is located at the top of the pixel unit, the second passivation layer is adjacent to the inflection point, and the first passivation layer covers the sidewall of the pixel unit.

[0023] Optionally, the first passivation layer has at least one opening located on the sidewall and / or bottom of the first passivation layer to expose at least one area for electrical connection with the first semiconductor layer, through which the metal bonding layer is electrically connected to the first semiconductor layer.

[0024] Optionally, the first passivation layer comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

[0025] Optionally, it also includes a pixel fence located on both sides of the pixel unit, including a first end and a second end opposite to each other. The sidewall and top of the first end are covered by the second passivation layer; one sidewall of the second end is in contact with the metal bonding layer; and the remaining sidewall of the second end is covered by the second passivation layer.

[0026] Optionally, the sidewall of the trench forms an angle with the vertical direction, the angle ranging from 0 to 45°.

[0027] Optionally, the second passivation layer comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

[0028] Optionally, a metal structure is provided within the trench.

[0029] Optionally, the metal structure is an isolation fence, and the second passivation layer at least covers the sidewalls of the isolation fence.

[0030] Optionally, the driving substrate is further provided with a second contact, the second contact having the opposite polarity to the first contact, and the second contact being electrically connected to the metal structure.

[0031] Optionally, it further includes a transparent common electrode layer, which is located on the surface of the pixel unit and the isolation structure and is electrically connected to the second semiconductor layer.

[0032] Optionally, a second ohmic contact layer is provided between the second semiconductor layer and the transparent common electrode layer; and / or, a first ohmic contact layer is provided between the first semiconductor layer and the metal bonding layer.

[0033] Optionally, the first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor.

[0034] Optionally, the thickness of the P-type semiconductor layer is less than the thickness of the N-type semiconductor.

[0035] Optionally, the metal bonding layer includes a first metal layer and a second metal layer; the first metal layer extends along the sidewall of the pixel unit and is electrically connected to the first semiconductor layer; the second metal layer is disposed on the driving substrate and is electrically connected to the first contact.

[0036] Optionally, the metal bonding layer comprises a single-layer or multi-layer structure formed by at least one metal selected from Cr, Al, Ag, Pt, Ni, Ti, Sn, Cu, Au, and Rh.

[0037] This application also proposes a method for fabricating a display semiconductor device, characterized by comprising the following steps:

[0038] A carrier substrate is provided, on which a second semiconductor layer, an active layer and a first semiconductor layer are sequentially disposed from bottom to top, wherein the second semiconductor layer, the active layer and the first semiconductor layer constitute an epitaxial layer;

[0039] On the surface of the carrier substrate, an array of mesa structures is formed by etching the epitaxial layer. The mesa structure includes a second semiconductor layer, an active layer, and a first semiconductor layer stacked from bottom to top, with at least the active layer exposed between adjacent mesa structures. In the direction perpendicular to the carrier substrate, the lateral dimension of the mesa structure increases in at least a certain range.

[0040] A first metal layer is formed on the surface of the carrier substrate, the first metal layer extending to at least a portion of the sidewall of the mesa structure and being electrically connected to the first semiconductor layer;

[0041] A driving substrate is provided, wherein a first contact is provided on the driving substrate, and a second metal layer is formed on the driving substrate; the first metal layer and the second metal layer are bonded together to form a metal bonding layer, and the metal bonding layer is electrically connected to the first contact;

[0042] Remove the carrier substrate to expose the second semiconductor layer;

[0043] An isolation structure is formed between adjacent mesa structures, the isolation structure dividing the metal bonding layer into multiple electrically isolated regions, each region corresponding to a pixel unit.

[0044] Optionally, the formation of the isolation structure includes:

[0045] Grooves are formed between the platform structures to expose the drive substrate;

[0046] A second passivation layer is formed within the trench, the second passivation layer at least covering the sidewalls of the trench.

[0047] Optionally, it also includes forming a metal structure inside the trench.

[0048] Optionally, the metal structure is an isolation fence, and the second passivation layer at least covers the sidewalls of the isolation fence.

[0049] Optionally, the driving substrate is further provided with a second contact, the second contact having the opposite polarity to the first contact, and the second contact being electrically connected to the metal structure.

[0050] Optionally, it also includes:

[0051] Before depositing the first metal layer

[0052] A patterned first passivation layer is deposited on the surface of the platform structure;

[0053] The first passivation layer has at least one opening located on the surface and / or sidewall of the first passivation layer to expose at least one area for electrical connection with the first semiconductor layer;

[0054] The first metal layer is electrically connected to the first semiconductor layer through the opening.

[0055] Optionally, the first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor.

[0056] Optionally, a transparent common electrode layer is formed on the surface of the pixel unit and the isolation structure, and the transparent common electrode layer is electrically connected to the second semiconductor layer.

[0057] Optionally, a second ohmic contact layer is formed between the second semiconductor layer and the transparent common electrode layer; and / or, a first ohmic contact layer is formed between the first semiconductor layer and the first metal layer.

[0058] Optionally, the carrier substrate is an epitaxial substrate, and the second semiconductor layer, the active layer, and the first semiconductor layer are formed by sequential deposition on the epitaxial substrate.

[0059] Optionally, it also includes:

[0060] An epitaxial substrate is provided, on which the second semiconductor layer, the active layer, and the first semiconductor layer are sequentially deposited;

[0061] A temporary substrate is provided, wherein a first temporary bonding layer is provided on the surface of the temporary substrate;

[0062] The epitaxial layer is bonded to the temporary substrate through the first temporary bonding layer, and the epitaxial substrate is removed;

[0063] A carrier substrate is provided, wherein a second temporary bonding layer is disposed on the surface of the carrier substrate;

[0064] The epitaxial layer on the temporary substrate is bonded to the carrier substrate, and the temporary substrate is removed;

[0065] Wherein, the size of the carrier substrate is greater than or equal to the size of the temporary substrate:

[0066] If the two are of equal size, a wafer-level bonding process is used;

[0067] If the carrier substrate is larger, the epitaxial layer and the substrate on which it is located are cut together before the epitaxial layer is bonded to the carrier substrate to form an array of chip units.

[0068] Optionally, when the size of the carrier substrate is larger than the size of the temporary substrate, the size of the carrier substrate is greater than or equal to 8 inches.

[0069] As described above, the present invention provides a display semiconductor device and its fabrication method, comprising a driving substrate, a pixel unit, and a metal bonding layer. A first contact is provided on the surface of the driving substrate; the pixel unit is located above the driving substrate, and its lateral dimension increases at least partially in the direction away from the driving substrate; the metal bonding layer is disposed on the surface of the driving substrate, making contact with the first contact surface to achieve electrical connection, and extending to at least a portion of the sidewalls of the pixel unit, forming a large-area electrical contact with the first semiconductor layer. This application replaces the tiny metal contacts at the bottom of the traditional pixel with a large-area metal bonding layer, increasing the contact area between the metal bonding layer and the driving substrate, fundamentally avoiding the bottlenecks of high processing difficulty for small-sized contacts and bonding alignment processes; simultaneously, by increasing the contact surface with the first semiconductor layer, the contact resistance is significantly reduced, improving current injection efficiency and luminous brightness; secondly, the metal bonding layer also serves as a highly efficient heat diffusion layer, allowing heat to diffuse uniformly laterally before being conducted to the driving substrate, avoiding localized heat accumulation in traditional structures, significantly improving heat dissipation performance and device reliability. It further suppresses the risk of peeling due to thermal mismatch. Furthermore, the isolation structure can block the lateral leakage current path, eliminate electrical crosstalk, and can be equipped with a metal structure to optimize the light emission angle and reduce optical crosstalk, thereby improving display contrast and color purity. Attached Figure Description

[0070] Figures 1-13 The diagram shown is a schematic representation of the semiconductor device in Embodiment 1.

[0071] Figure 1 This is the basic structure of the display semiconductor device in Embodiment 1 of the present invention;

[0072] Figure 2 In Embodiment 1 of the present invention Figure 1 Based on this, a first ohmic contact layer and a second ohmic contact layer are provided, the isolation structure is provided with a metal structure, and the metal bonding layer is composed of a first metal layer and a second metal layer;

[0073] Figure 3 In Embodiment 1 of the present invention Figure 1 Based on this, the first passivation layer has multiple openings corresponding to the metal bonding layer;

[0074] Figure 4 In Embodiment 1 of the present invention, the sidewall of the first semiconductor layer is a vertical sidewall, the sidewalls of the active layer and the second semiconductor layer are inclined sidewalls, and the isolation structure is provided with a second passivation layer and a filling metal pillar.

[0075] Figure 5 In Embodiment 1 of the present invention, the lateral dimension of the active layer is a vertical sidewall, and the lateral dimensions of the second semiconductor layer and the first semiconductor layer gradually increase.

[0076] Figure 6 In Embodiment 1 of the present invention, the second semiconductor layer has the largest lateral dimension and its sidewalls are vertical surfaces;

[0077] Figure 7 In Embodiment 1 of the present invention, the second semiconductor layer and the active layer have the largest lateral dimensions and the sidewalls are vertical surfaces.

[0078] Figure 8 In Embodiment 1 of the present invention, the second semiconductor layer has the largest lateral dimension and the sidewalls are vertical, and a pixel fence is provided around the pixel;

[0079] Figure 9 In Embodiment 1 of the present invention, the trench sidewall of the isolation structure is an inclined structure;

[0080] Figure 10 An isolation fence is installed in the trench of the isolation structure in Embodiment 1 of the present invention;

[0081] Figure 11 In Embodiment 1 of the present invention, the turning point of the pixel unit is located in the second semiconductor layer, and the trench sidewall is an inclined sidewall;

[0082] Figure 12In Embodiment 1 of the present invention, the turning point of the pixel unit is located in the active layer, and the trench sidewall is an inclined sidewall.

[0083] Figure 13 In Embodiment 1 of the present invention, a pixel fence is set for the pixel unit, and the trench sidewall is an inclined sidewall.

[0084] Figure 14 This is a schematic diagram of the process structure for forming a display semiconductor device in Embodiment 2 of the present invention.

[0085] Figure 15 This is a schematic diagram of the structure after an epitaxial layer is formed on an epitaxial substrate in Embodiment 2 of the present invention.

[0086] Figure 16 This is a schematic diagram of the structure after the epitaxial layer is transferred to the temporary substrate in Embodiment 2 of the present invention.

[0087] Figure 17 This is a schematic diagram of the structure after the epitaxial layer is divided into chip units in Embodiment 2 of the present invention.

[0088] Figure 18 This is a schematic diagram of the structure after the epitaxial layer is bonded to the carrier substrate in Embodiment 2 of the present invention.

[0089] Figure 19 This is a schematic diagram of the structure when removing the temporary substrate in Embodiment 2 of the present invention.

[0090] Figure 20 This is a schematic diagram of the structure after an epitaxial layer is formed on the carrier substrate in Embodiment 2 of the present invention.

[0091] Figure 21 This is a schematic diagram of the structure after etching to form a mesa structure in Embodiment 2 of the present invention, wherein the mesa structure exposes the second semiconductor layer.

[0092] Figure 22 This is a schematic diagram of the structure after etching to form a mesa structure in Embodiment 2 of the present invention, wherein the mesa structure exposes the active layer.

[0093] Figure 23 This is a schematic diagram of the structure after the formation of the first passivation layer in Embodiment 2 of the present invention, wherein the first passivation layer has an opening.

[0094] Figure 24 This is a schematic diagram of the structure after the formation of the first passivation layer in Embodiment 2 of the present invention. The first passivation layer exposes the sidewalls and top of the first semiconductor layer and forms the first ohmic contact layer.

[0095] Figure 25 This is a schematic diagram of the structure after the formation of the first passivation layer in Embodiment 2 of the present invention. The first passivation layer has three openings, including those located on the sidewall and the top, and forms a first ohmic contact layer.

[0096] Figure 26 This is a schematic diagram of the structure after the first metal layer is formed in Embodiment 2 of the present invention.

[0097] Figure 27 This is a schematic diagram of the structure after providing the driving substrate in Embodiment 2 of the present invention.

[0098] Figure 28 This is a schematic diagram of the structure after the driving substrate and the pixel unit are bonded in Embodiment 2 of the present invention.

[0099] Figure 29 This is a schematic diagram of the structure when removing the carrier substrate in Embodiment 2 of the present invention.

[0100] Figure 30 This is a schematic diagram of the structure after the carrier substrate is removed and the second semiconductor layer is planarized in Embodiment 2 of the present invention.

[0101] Figure 31 This is a schematic diagram of the structure after the trench is formed in Embodiment 2 of the present invention.

[0102] Figure 32 This is a schematic diagram of the structure after filling the second passivation layer in Embodiment 2 of the present invention.

[0103] Figure 33 This is a schematic diagram of the structure after the second passivation layer covers the sidewall of the trench in Embodiment 2 of the present invention.

[0104] Figure 34 This is a schematic diagram of the structure after a metal reflective layer is formed in the trench in Embodiment 2 of the present invention.

[0105] Figure 35 This is a schematic diagram of the structure after the transparent common electrode layer is formed in Embodiment 2 of the present invention.

[0106] Figure 36 This is a schematic diagram of the exposed portion of the second semiconductor layer in the mesa structure of Embodiment 2 of the present invention, after which bonding is performed.

[0107] Figure 37 This is a schematic diagram of the structure after etching the second semiconductor layer to form a turning point in Embodiment 2 of the present invention.

[0108] Figure 38 This is a schematic diagram of the structure in Embodiment 2 of the present invention, showing the second passivation layer covering the sidewall of the trench and the sidewall above the turning point.

[0109] Figure 39 This is a schematic diagram of the structure after the second semiconductor layer is exposed in the mesa structure of Embodiment 2 of the present invention.

[0110] Figure 40 This is a schematic diagram of the structure after etching the second semiconductor layer in Embodiment 2 of the present invention.

[0111] Figure 41 This is a schematic diagram of the structure after the patterned mask layer is formed in Embodiment 2 of the present invention.

[0112] Figure 42 This is a schematic diagram of the structure after forming a pixel fence in Embodiment 2 of the present invention.

[0113] Figure 43 This is a schematic diagram of the structure after removing the mask layer in Embodiment 2 of the present invention.

[0114] Figure 44 This is a schematic diagram of the structure after the second passivation layer is formed in Embodiment 2 of the present invention.

[0115] Explanation of reference numerals in the attached figures

[0116] 100 carrier substrate 101 Epitaxial substrate 102 temporary substrate 103 First temporary bonding layer 104 Second temporary bonding layer 105 Chip unit 110 Second semiconductor layer 111 Second Ohmic Contact Layer 120 Active layer 130 First semiconductor layer 131 First Ohmic Contact Layer 132 Opening 140 First passivation layer 150 First metal layer 151 Pixel fence 152 conductive metal layer 153 First reflective layer 160 Metal bonding layer 200 drive substrate 210 First contact point 220 Second contact point 230 Second metal layer 300 isolation structure 310 trench 320 Second passivation layer 330 Metal reflective layer 340 isolation fence 400 transparent common electrode layer 510 mask layer Detailed Implementation

[0117] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0118] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0119] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0120] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be changed at will, and the layout of the components may also be more complex.

[0121] This invention provides an integration scheme suitable for vertical semiconductor light-emitting devices. Its core lies in forming a large-area electrical connection and heat diffusion channel with the driving substrate through a metal bonding layer. Simultaneously, the metal bonding layer extends to the sidewall of the pixel unit, increasing the contact area with the first semiconductor layer and reducing contact resistance. Furthermore, a passivation layer and isolation structure are used to protect the pixel unit and achieve electrical and optical isolation.

[0122] This solution is versatile and applicable to various vertically structured semiconductor devices that require integration with driving circuits, including but not limited to micro-LEDs, micro-lasers (especially vertical-cavity surface-emitting lasers, VCSELs), and other optoelectronic devices (such as photodetector arrays). Their common feature is that the first semiconductor layer, the active layer, and the second semiconductor layer form a vertically stacked structure (e.g., in Micro-LEDs, an N-type layer, a multi-quantum-well emission region, and a P-type layer; in VCSELs, an N-type DBR mirror, a multi-quantum-well active region, and a P-type DBR mirror).

[0123] It should be noted that, in this application, the compound semiconductor layer refers to a layer structure with a certain thickness prepared from compound semiconductor materials. Compound semiconductors generally refer to compounds formed from two or more elements, including crystalline inorganic compounds (such as III-V and II-VI compound semiconductors) and oxide semiconductors. The compound semiconductors involved in this application are mainly epitaxial materials for light-emitting diodes, such as InGaN ternary material systems or AlGaInP quaternary material systems, whose emission wavelengths can cover the entire spectrum from ultraviolet, visible, and infrared light. Their substrate materials can be GaN, SiC, Sapphire, InP, etc.

[0124] Taking the Micro-LED field as an example, some compound semiconductor materials involved in this application are shown in Table 1. In some practical applications, the film layers of compound semiconductors are more complex, or there are cases where materials are used in combination:

[0125] Table 1. Material Table of Film Layers for Compound Semiconductors

[0126] Layer name Material Material Material Material Material Material Material P contact layer GaP GaAs GaAs GaAs AlGaN GaN GaN Barrier layer, confinement layer, or waveguide layer AlInP AlGaAs AlGaAs AlGaAs AlGaN AlGaN AlGaN MQW active quantum well AlGaInP AlGaInP InGaAs AlGaAs InGaN InGaN InGaN Barrier layer, confinement layer, or waveguide layer AlInP AlGaInP AlGaAs GaAs AlGaN GaN GaN N contact layer GaAs AlGaAs AlGaAs GaAs GaN GaN GaN Buffer layer or cutoff layer AlGaInP AlGaAs AlGaAs GaInP InGaN AlN AlN substrate GaAs GaAs GaAs GaAs GaN Si Sapphire

[0127] In this context, R, G, and B represent red, green, and blue, respectively. Subpixels that emit light in red, green, and blue colors are referred to as red subpixels, green subpixels, and blue subpixels, respectively. In Table 1, "R compound" indicates the compound semiconductor layer used to prepare red subpixels, and "R\G\B compound" indicates the compound semiconductor layer used to prepare red, green, and blue subpixels. The same material can be used to prepare the compound semiconductor layer for red, green, or blue subpixels. The different wavelengths of light are achieved by adjusting the doping elements, such as the ratio of In / Al, which results in different emitted colors.

[0128] The structure of the display semiconductor device of this application will be further described below with reference to the following specific embodiments.

[0129] Example 1

[0130] The following will combine Figures 1-13 The relevant structure of the display semiconductor device in this embodiment will be further described.

[0131] This invention provides a display semiconductor device, see below. Figure 1 It includes a driving substrate 200, a pixel unit, and a metal bonding layer 160.

[0132] The driving substrate 200 is provided with a first contact 210;

[0133] The pixel unit is located above the driving substrate 200 and includes a first semiconductor layer 130, an active layer 120 and a second semiconductor layer 110 disposed from bottom to top; wherein, in the vertical direction away from the driving substrate 200, the lateral dimension of the pixel unit increases in at least a portion of the range.

[0134] The metal bonding layer 160 is disposed on the surface of the driving substrate 200 and is in contact with the first contact 210 and electrically connected thereto; the metal bonding layer 160 extends to at least a portion of the sidewall of the pixel unit and is electrically connected to the first semiconductor layer 130, but has no direct contact with the active layer 120 and the second semiconductor layer 110; wherein the metal bonding layers 160 of adjacent pixel units are isolated from each other.

[0135] In this invention, the term "lateral dimension" refers to the horizontal cross-sectional dimension of the layer at any height. Because the pixel units of this invention increase in size within at least a certain range, the lateral dimension changes monotonically with height within this range. Furthermore, the lateral dimension either increases regularly and monotonically from the bottom to the top of this range, or increases with a certain gradient, to change the emission angle and improve light extraction efficiency.

[0136] Specifically, the driving substrate 200 has a driving circuit, on which the first contact 210 and a common contact are provided. The metal bonding layer 160 is electrically connected to the first contact 210 and forms an electrical connection with the first semiconductor layer 130. Current flows into the first semiconductor layer 130 through the metal bonding layer 160, driving the active layer 120 to emit light; then, the current is collected through the electrode structure at the other end and transmitted back to the common contact of the driving substrate 200 through a conductive structure (subsequent metal structure or peripheral circuit of pixel unit), forming a complete circuit, thereby realizing independent driving of each pixel unit.

[0137] In this structure, see Figures 1-4 By expanding the area of ​​the metal bonding layer 160 to be much larger than the size of the first contact, the current is fully laterally expanded within the large area of ​​the metal bonding layer 160 before reaching the first contact 210, significantly reducing the current contraction effect. The metal bonding layer 160 and the first semiconductor layer 130 are electrically connected over a large area, which further significantly reduces the contact resistance, reduces power consumption, and improves luminous efficiency. At the same time, it replaces the tiny contact at the bottom of the traditional pixel unit, avoiding the bottleneck of high processing difficulty and high alignment bonding process requirements for small-sized contact, and significantly reducing the bonding process difficulty and manufacturing cost.

[0138] As an example, see Figures 4-6 The portion of the pixel unit with increased lateral size includes at least one first portion and at least one second portion connected sequentially in the vertical direction; wherein, see reference Figure 4 A step is formed between the first semiconductor layer 130 and the active layer 120, and the active layer 120 and the second semiconductor layer 110 gradually increase in size. The active layer 120 and the second semiconductor layer 110 respectively constitute the first part and the second part, and their changing trends are consistent. In another embodiment, see [reference needed]. Figure 6 Both the first and second portions are located on the sidewalls of the first semiconductor layer 130. The first portion at the bottom has a gradually increasing lateral dimension along the vertical direction, forming a stepped structure; the second portion is located above the first portion, with a significant abrupt change in lateral dimension between them. Alternatively, in other embodiments, the first portion corresponds to the first semiconductor layer 130, and its lateral dimension continuously increases along the vertical direction; the second portion corresponds to the active layer 120, and its sidewall slope changes relative to the first portion, for example, becoming steeper or gentler (see [reference]). Figure 5 ).

[0139] It should be noted that the specific shapes (such as size, slope, step height, etc.) of the first and second parts can be flexibly adjusted according to actual needs to achieve flexible control over the light emission direction or current expansion. The specific types and situations of the sidewalls of the pixel units and their relationship with the passivation layer will be detailed in subsequent chapters.

[0140] As an example, the lateral dimension of the bonding surface of the metal bonding layer 160 is greater than or equal to the maximum lateral dimension of the pixel unit. Specifically, the metal bonding layer 160 extends to at least a portion of the sidewall of the pixel unit, thereby forming a three-dimensional contact structure with the pixel unit. On the one hand, the metal bonding layer 160 contacts the sidewall of the pixel unit, increasing the contact area by tens to hundreds of times, significantly reducing contact resistance, breaking through the current injection bottleneck of traditional microdisplays, and improving current injection efficiency and luminous brightness. On the other hand, this structure constructs a three-dimensional heat dissipation network from the pixel unit to the driving substrate 200, effectively suppressing heat accumulation and improving device reliability. More importantly, this solution avoids dependence on the precision of the bonding equipment from the structural and process design level. In the alignment bonding process, the bonding precision only needs to be less than the center-to-center distance (pitch) of adjacent pixel units. Subsequently, adjacent pixel units are isolated by photolithographic alignment and etching (the photolithographic alignment precision in the prior art is much greater than the alignment precision of existing bonding equipment). Compared to conventional hybrid bonding and bump bonding, this invention does not require precise alignment of pixel units with specific points, further improving efficiency and yield in the manufacturing process. Furthermore, the inverted trapezoidal sidewall morphology of the pixel units enhances the coverage and adhesion of the metal bonding layer 160, effectively preventing metal peeling during subsequent thermal cycling and further improving device stability.

[0141] See Figures 1-5 In one embodiment, when the lateral dimension is greater than the maximum lateral dimension of the pixel unit, the metal bonding layer 160 completely covers the bottom of the pixel unit and surrounds the sidewalls of the pixel unit, maximizing the electrical connection area and thermal diffusion range. In another embodiment, see primarily... Figures 6-7 When the lateral dimension is equal to the maximum lateral dimension of the pixel unit, the metal bonding layer 160 is precisely aligned with the bottom edge of the pixel unit, which helps to achieve a more compact pixel layout while maintaining the advantage of large-area contact.

[0142] As an example, see Figures 2-5 The metal bonding layer 160 further includes a first metal layer 150 and a second metal layer 230; the second metal layer 230 is disposed on the driving substrate 200 and electrically connected to the first contact 210; the first metal layer 150 extends along the sidewall of the pixel unit and is electrically connected to the first semiconductor layer 130.

[0143] In one specific embodiment, see Figure 2In the metal-to-metal bonding process, the large-area first metal layer 150 can be directly bonded to the second metal layer 230 deposited on the driving substrate 200, simplifying interface matching. The second metal layer 230 can be deposited with metal material through deposition processes such as PVD, and then planarized through CMP or polishing processes to obtain a smooth bonding interface. Compared with traditional hybrid bonding processes and bump bonding processes, this bonding method significantly reduces the bonding process difficulty and manufacturing cost. Preferably, the first metal layer 150 and the second metal layer 230 can be made of the same metal material, expanding and contracting synchronously during thermal cycling, fundamentally eliminating interface thermal stress. The first metal layer 150 and the second metal layer 230 serve as heat diffusion layers, allowing heat to diffuse uniformly laterally before being conducted to the driving substrate 200, avoiding local heat accumulation in traditional small contacts, alleviating thermal stress caused by the mismatch of thermal expansion coefficients of different materials, thereby suppressing the risk of interface delamination and improving heat dissipation performance and device reliability.

[0144] As an example, the metal bonding layer 160 comprises a single-layer or multi-layer structure formed of at least one metal selected from Cr, Al, Ag, Pt, Ni, Ti, Sn, Cu, Au, and Rh.

[0145] Specifically, in the multilayer structure, the reflective layer can be made of Al, Ag, or Rh to reflect light from the sidewalls of the pixel units, improving light extraction efficiency and suppressing optical crosstalk. The bonding layer can be made of metals or alloys such as Cu, Ti, Al, and Au to form metal-metal bonds with the driving substrate 200, achieving reliable electrical connection and mechanical fixation. The remaining layers (such as adhesive layers, barrier layers, conductive layers, etc.) can be flexibly combined as needed to achieve synergistic optimization of adhesion, oxidation resistance, bonding strength, and resistivity, meeting different process conditions and performance requirements.

[0146] Furthermore, in some other embodiments, see [reference] Figure 2The first metal layer 150 also has a reflective function. Its surface facing the pixel unit has high reflectivity, used to reflect lateral light generated inside the pixel unit back to the light-emitting direction, suppressing light absorption and optical crosstalk between pixels, and improving luminous efficiency. In this case, the first metal layer 150 can be made of high-reflectivity metal materials such as Ag, Al, or Rh, or adopt a multi-layer structure, where the sub-layer facing the pixel unit is a high-reflectivity metal, and the sub-layer facing away from the pixel unit is a low-resistance conductive metal (such as Cu), used for subsequent bonding. In this embodiment, the first metal layer 150 consists of a first reflective layer 153 and a conductive metal layer 152, with the first reflective layer 153 close to the sidewall of the pixel unit. Of course, in another embodiment, the metal bonding layer 160 can also use a single metal (such as Al or Ti) as the material of the metal bonding layer 160, and the metal bonding layer 160 has both reflective and bonding functions. The structure of the metal bonding layer 160 is not limited to this, and will not be described in detail here.

[0147] As an example, the driving substrate 200 may include, but is not limited to, a CMOS driving substrate, or may also be a TFT glass substrate or other types of semiconductor driving circuit substrate, as long as it can provide driving signals to realize independent control and light emission driving of pixel units.

[0148] See Figure 1 The first contact 210 can serve as an anode contact, allowing the bottom of the pixel unit to be electrically connected to the anode of the driving substrate 200. The structure also includes a transparent common electrode layer 400 located on the surface of the pixel unit. In this embodiment, the transparent common electrode layer 400 can be connected to a common contact of the driving substrate 200 to achieve a cathode connection.

[0149] Of course, the first contact 210 can also be used as a cathode contact, and the corresponding transparent common electrode layer 400 is set accordingly.

[0150] As an example, see Figure 2 The driving substrate 200 also includes a second contact 220, the potential of which is opposite to that of the first contact 210. The transparent common electrode layer 400 can be connected to the second contact 220 to form a circuit loop. The polarities of the first contact 210 and the second contact 220 are interchangeable; in one embodiment, the first contact 210 is the anode and the second contact 220 is the cathode. In another embodiment, the opposite is true. Accordingly, the type (P-type or N-type) of the first semiconductor layer 130 matches the polarity of the first contact 210, and so does the polarity of the second semiconductor layer 110.

[0151] As an example, see Figures 2-5A first ohmic contact layer 131 is provided between the first semiconductor layer 130 and the metal bonding layer 160.

[0152] Specifically, the material and structure of the first ohmic contact layer 131 are adapted to the conductivity type of the first semiconductor layer 130. When the first semiconductor layer 130 is a P-type semiconductor, the first ohmic contact layer 131 adopts a high work function metal material system. Specifically, the first ohmic contact layer 131 is selected from at least one of Ni / Au, Pd / Au, Pt / Au, Ni / Pd / Au, AuZn, Al / Ti / Si, or uses transparent conductive oxides such as AZO (aluminum-doped zinc oxide). After annealing, the above materials form a low-barrier ohmic contact with the P-type semiconductor interface.

[0153] When the first semiconductor layer 130 is an N-type semiconductor, the first ohmic contact layer 131 is made of a low work function metal or alloy material. Specifically, the first ohmic contact layer 131 is selected from at least one of Ti / Al-based stacks (such as Ti / Al / Ni / Au, Ti / Al / Ti / Au, Ti / Al / Mo / Au), AuGe-based alloys (such as AuGe, AuGeNi), Ni / Au, Cr / Au, Mo / Au, and Pd / Au. Among them, the Ti / Al-based system generates TiN or Ti-Si compounds through the reaction of Ti with the semiconductor, forming a high-concentration N-type doped interface to achieve a low-resistance ohmic contact; Ge in the AuGe-based alloy acts as an N-type dopant, which can form a heavily doped layer at the interface, reducing the barrier width.

[0154] In this example, the first semiconductor layer 130 and the second semiconductor layer 110 have opposite conductivity types, for example, one is P-type and the other is N-type. By setting this, the barrier height of the metal-semiconductor interface can be effectively reduced, achieving linear or quasi-linear current-voltage characteristics, significantly reducing contact resistance and on-state voltage, thereby improving current injection efficiency, reducing power consumption, and improving the uniformity and reliability of the device under high current density.

[0155] As an example, the structure also includes an isolation structure 300 located between adjacent pixel units.

[0156] For details, please refer to Figures 1-13 The isolation structure 300 extends vertically, with its bottom contacting the driving substrate 200 and its top not lower than the light-emitting surface of the pixel unit or flush with the top of the pixel unit. It is used to form physical separation and electrical isolation between adjacent pixel units and to make the metal bonding layer 160 of each pixel unit independent of each other.

[0157] As an example, see Figures 1-13The isolation structure 300 includes a trench 310 and a second passivation layer 320, the second passivation layer 320 at least covering the sidewall of the trench 310. Of course, in this invention, the isolation structure 300 is not limited to a trench or a passivation layer; any structure capable of achieving electrical isolation is acceptable. For details, please refer to... Figure 1 or Figure 2 The trench 310 is formed between adjacent pixel units and extends in a vertical direction. Its bottom can expose the surface of the driving substrate 200, and its top is not lower than the light-emitting surface of the pixel unit or flush with the top of the pixel unit.

[0158] As an example, the sidewalls of the trench 310 can form a certain angle θ (e.g., 0~45°) with the vertical direction to facilitate the stepped coverage of the second passivation layer 320 and adapt to the sidewall morphology of the pixel unit, avoiding poor coverage or stress concentration at corners. See also Figures 1-8 When θ = 0°, the groove 310 has a rectangular cross-section, and the lateral opening size remains unchanged along the vertical direction. (See also...) Figures 9-13 When θ>0°, the groove 310 has a trapezoidal cross-section that is narrow at the bottom and wide at the top, and its lateral opening size gradually increases along the vertical direction. Preferably, the value of θ is in the range of 0~30°, so as to facilitate the continuous coverage of the second passivation layer 320 on the sidewall, and to coordinate with the tilt angle of the sidewall below the pixel unit turning point to optimize the overall optical path.

[0159] The second passivation layer 320 at least covers the sidewalls of the trench 310, as described in some embodiments, see [reference]. Figure 1 and Figures 9-10 The second passivation layer 320 further covers the bottom of the trench 310, forming a continuous insulating protective layer. The second passivation layer 320 provides electrical isolation between adjacent pixel units, preventing leakage between pixels. Simultaneously, the second passivation layer 320 and the trench 310 together constitute the physical isolation structure 300, isolating the metal bonding layers 160 of each pixel unit from each other and preventing short circuits. Furthermore, when the second passivation layer 320 is made of a material with light-absorbing properties, it can also suppress optical crosstalk between adjacent pixel units, improving display contrast. Additionally, a metal structure may be optionally disposed within the trench 310, which will be described in detail later.

[0160] As an example, the second passivation layer 320 comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

[0161] Among them, single-layer structures can meet basic insulation protection requirements, and the process is simple and the cost is controllable; while multilayer structures can achieve comprehensive performance such as high density, low stress, high dielectric constant or optical refractive index control by combining different materials.

[0162] As an example, the transparent common electrode layer 400 is located on the surface of the pixel unit and the isolation structure 300, and is electrically connected to the second semiconductor layer 110.

[0163] Specifically, the transparent common electrode layer 400 covers the entire surface and is electrically connected to the second semiconductor layer 110 of each pixel unit, serving as a common electrode to achieve uniform current injection and lateral distribution. (See also...) Figure 10 and Figure 11 When the sidewall of the trench 310 is inclined, the transparent common electrode layer 400 can also cover the trench 310 in accordance with its shape, so that the transparent common electrode layer 400 forms a continuous coverage on the sidewall of the trench 310, thereby ensuring the continuity of the common electrode of each pixel unit, while avoiding weak or broken coverage caused by the steps of the trench 310, and improving electrode reliability.

[0164] As an example, see Figure 2 A second ohmic contact layer 111 is provided between the second semiconductor layer 110 and the transparent common electrode layer 400.

[0165] For details, please refer to Figure 2The second ohmic contact layer 111 is used to form a low-resistance ohmic contact, optimizing current injection efficiency. The material and structure of the second ohmic contact layer 111 are adapted to the conductivity type of the second semiconductor layer 110. When the second semiconductor layer is a P-type semiconductor, the second ohmic contact layer 111 uses a high work function metal material system. Specifically, the second ohmic contact layer 111 is selected from at least one of Ni / Au, Pd / Au, Pt / Au, Ni / Pd / Au, AuZn, or Al / Ti / Si, or uses a transparent conductive oxide such as AZO (aluminum-doped zinc oxide). After annealing, the above materials form a low-barrier ohmic contact with the P-type semiconductor interface. When the second semiconductor layer is an N-type semiconductor, the second ohmic contact layer 111 uses a low work function metal or alloy material. Specifically, the second ohmic contact layer 111 is selected from at least one of Ti / Al-based stacks (such as Ti / Al / Ni / Au, Ti / Al / Ti / Au, Ti / Al / Mo / Au), AuGe-based alloys (such as AuGe, AuGeNi), Ni / Au, Cr / Au, Mo / Au, and Pd / Au. In the Ti / Al-based system, Ti reacts with the semiconductor to generate TiN or Ti-Si compounds, forming a high-concentration N-type doped interface to achieve a low-resistance ohmic contact. In the AuGe-based alloy, Ge acts as an N-type dopant, forming a heavily doped layer at the interface and reducing the barrier width. In this example, the first semiconductor layer 130 and the second semiconductor layer 110 have opposite conductivity types; for example, one is P-type and the other is N-type. Correspondingly, the materials of the first ohmic contact layer 131 and the second ohmic contact layer 111 are also set according to the rule of "P-type with high work function and N-type with low work function". By setting a barrier height that can effectively reduce the metal-semiconductor interface, linear or quasi-linear current-voltage characteristics can be achieved, significantly reducing contact resistance and on-state voltage, thereby improving current injection efficiency, reducing power consumption, and improving the uniformity and reliability of the device under high current density. It should be noted that this layer is not mandatory and may be omitted in some embodiments; see [reference needed]. Figure 1 and Figure 3 This allows the transparent common electrode layer 400 to directly contact the second semiconductor layer 110, thereby reducing light shading and improving luminous efficiency.

[0166] As an example, see Figures 1-13 The structure also includes a first passivation layer 140, and the sidewall of the pixel unit has a turning point, which is the position where the lateral dimension of the pixel unit is the largest.

[0167] Specifically, the first passivation layer 140 covers at least the sidewall region below the inflection point, serving to protect the pixel unit during the process and forming electrical isolation between the metal bonding layer 160 and the second semiconductor layer 110 and the active layer 120 of the pixel unit. The inflection point can serve as a stop marker for the etching process, facilitating precise control of the coverage boundary between the first passivation layer 140 and the subsequent second passivation layer 320 on the sidewall.

[0168] It should be noted that, in this application, "inflection point" refers to the location in the sidewall contour of a pixel unit where the lateral dimension reaches its maximum value. Above this location may be a vertical sidewall, an inward-reducing sidewall, or no sidewall (i.e., the top of the pixel unit). That is, below the inflection point, the lateral dimension increases vertically (monotonically increasing and at least partially increasing); above the inflection point, the lateral dimension remains unchanged vertically (vertical) or monotonically decreases (inward-reducing), or there is no sidewall (i.e., the inflection point is located at the top of the pixel unit). The different cases of sidewalls above and below the inflection point will be explained later.

[0169] As an example, see Figures 1-3 The first passivation layer 140 has at least one opening 132 located on the sidewall and / or bottom of the first passivation layer 140 to expose at least one area for electrical connection with the first semiconductor layer 130, and the metal bonding layer 160 is electrically connected to the first semiconductor layer 130 through the opening 132.

[0170] Specifically, the method of forming the opening 132 on the first passivation layer 140 can be flexibly selected according to design requirements. For example, see [reference needed]. Figures 1-3 The opening 132 can be formed on the bottom surface of the first passivation layer 140 using photolithography etching to expose a predetermined area of ​​the first semiconductor layer 130; as an alternative, see [reference needed]. Figure 1 and Figure 2 The first passivation layer 140 only covers the bottom and part of the sidewalls of the first semiconductor layer 130, leaving the remaining sidewalls directly exposed, thus eliminating the need for additional openings. In a further embodiment, exposed areas can be provided on both the bottom and sidewalls to increase the contact area. In one embodiment, the sidewalls of the first semiconductor layer 130 are sloping sidewalls, see [reference needed]. Figure 3The number of openings 132 can be three. By adjusting the number, position, and distribution of the openings 132, the contact resistance can be effectively controlled to meet the design requirements of different pixel sizes and driving currents. This diverse configuration of the openings 132 provides process flexibility for optimizing device performance. In this embodiment, regardless of the form of the openings 132 used, the metal bonding layer 160 forms a large-area electrical contact with the first semiconductor layer 130 through the openings 132, thereby achieving a low-resistance electrical connection.

[0171] As an example, the first passivation layer 140 comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

[0172] Specifically, the first passivation layer 140 is made of the aforementioned dielectric material with equal resistivity, achieving reliable insulation through a single-layer or multi-layer structure. Its excellent step coverage capability can form uniform protection on inclined sidewalls, preventing thin film at sharp corners. This can be achieved through refractive index modulation (such as SiO2). 2 / The TiO2 stack optimizes the sidewall optical matching and provides a smooth substrate for the metal bonding layer 160 (which can also serve as a reflective layer), improving light extraction efficiency. Simultaneously, the stack design with matched thermal expansion coefficients and complementary stress effectively buffers thermal stress, balancing electrical performance, optical output, and mechanical reliability.

[0173] The following section describes the relative positions of the pixel unit sidewall structure and the metal bonding layer 160, taking the sidewall morphology of the pixel unit as a starting point and combining the partitioning coverage of the passivation layer.

[0174] The sidewall shape corresponding to the position with the largest lateral dimension can be controlled by the etching process. For example, anisotropic dry etching can form a vertical sidewall, while adjusting the etching parameters or using wet etching can form an inclined sidewall. Based on this sidewall shape, the present invention has made differentiated designs on the coverage areas of the first passivation layer 140 and the second passivation layer 320.

[0175] As an example, the second passivation layer 320 covers the sidewall above the inflection point of the pixel unit, and the first passivation layer 140 covers at least the sidewall below the inflection point.

[0176] As an example, below the inflection point, the lateral dimension of the pixel unit monotonically does not decrease along the vertical direction; above the inflection point, the lateral dimension of the pixel unit monotonically does not increase along the vertical direction. The inflection point corresponds to the active layer 120 or the second semiconductor layer 110.

[0177] In the first sub-in embodiment, the inflection point is located in the second semiconductor layer 110.

[0178] Specifically, in the first sub-implementation embodiment, see [link to relevant documentation]. Figure 6 The turning point is located in the middle of the pixel unit. It corresponds to the bottom of the second semiconductor layer 110, but it can also be located in the middle or at other positions.

[0179] Above the inflection point, the sidewalls of the second semiconductor layer 110 are vertical surfaces and are covered by the second passivation layer 320; the sidewalls of the active layer 120 and the first semiconductor layer 130 are inclined surfaces with increasing lateral dimensions from bottom to top, covered by the first passivation layer 140. The first passivation layer 140 continuously covers the inclined sidewalls below the inflection point, forming a smooth insulating substrate, facilitating uniform coverage of the metal bonding layer 160, and serving as a support interface for the metal bonding layer 160, improving the sidewall reflection efficiency. The second passivation layer 320 separately covers the vertical sidewalls of the second semiconductor layer 110, avoiding the intersection of the two passivation layers on the vertical sidewalls, simplifying the process and improving reliability. The sidewalls of the first semiconductor layer 130 are continuous inclined surfaces or stepped inclined surfaces, with a surface area larger than the vertical sidewalls, providing a larger optional area for the opening 132 of the first passivation layer 140. Optionally, by providing the openings 132 on the sidewalls and bottom of the first semiconductor layer 130, the metal bonding layer 160 can achieve a larger area of ​​electrical contact, thereby reducing contact resistance and making it suitable for designs with high light extraction efficiency requirements (such as large-size displays).

[0180] In the second embodiment, the inflection point is located in the active layer 120.

[0181] In the second sub-implementation embodiment, see Figure 7 The inflection point is located in the middle of the active layer 120 (or anywhere else). Above the inflection point, a portion of the sidewalls of the second semiconductor layer 110 and the active layer 120 are vertical and flush, covered by the second passivation layer 320, avoiding passivation layer overlap and simplifying the process. Continuous vertical sidewalls help reduce pixel unit size and increase integration density, making them suitable for high-resolution displays or designs sensitive to process costs. Below the inflection point, the sidewalls are inverted trapezoidal inclined sidewalls, which can be formed individually using different material selection ratios or step-by-step etching. Their inflection angle can be set according to actual needs. The inflection angle range is 15°~85°; preferably 30°~65°; more preferably 45°.

[0182] Third embodiment, see Figures 11-13 Above the inflection point, the horizontal dimension decreases monotonically along the vertical direction.

[0183] As a third sub-implementation, if the inflection point corresponds to the second semiconductor layer 110; above the inflection point, the lateral dimension of the second semiconductor layer 110 monotonically decreases and is covered by the second passivation layer 320; below the inflection point, the lateral dimension of the pixel unit increases vertically and is covered by the first passivation layer 140; if the inflection point is located in the active layer 120, the passivation layer coverage principle still follows the aforementioned rule that "the second passivation layer 320 covers the sidewall above the inflection point, and the first passivation layer 140 covers the sidewall below the inflection point." In this embodiment, Figure 11 The inflection point is shown to be located in the middle of the second semiconductor layer 110; Figures 12-13 The inflection point is shown to be located in the middle of the active layer 120.

[0184] In such embodiments, the sidewalls of the trench 310 of the isolation structure 300 can be tilted at an angle so that the second passivation layer 320 continuously covers and extends to the sidewalls of the trench 310, forming an integrated insulating isolation layer and simplifying the process. Preferably, the tilt angle of the sidewalls of the trench 310 and the sidewall angle below the inflection point can be set collaboratively to optimize the optical path and suppress crosstalk. The sidewall below the inflection point reflects lateral light upwards, improving light extraction efficiency; the sidewall above the inflection point narrows and collimates the upward light, reducing optical crosstalk. Both act on different stages of light propagation, forming an optical path control of "first reflection and collection, then collimation and shaping," achieving a synergistic improvement in light extraction efficiency and display contrast.

[0185] Of course, in the above embodiments, the sidewall below the turning point is an inverted trapezoidal inclined sidewall (its lateral dimension remains monotonically constant along the vertical direction), which can be formed separately using different material selection ratios or step-by-step etching. Its inclination angle can be set according to actual needs. This sidewall can be a continuous inclined surface, a segmented inclined surface, or a stepped structure. There are no limitations here.

[0186] It should be noted that the inflection point divides the sidewall of the pixel unit into upper and lower regions; see [reference needed]. Figures 6-8 as well as Figure 11 or Figure 13Below the inflection point, the metal bonding layer 160 forms a large-area electrical contact with the first semiconductor layer 130 through the opening 132 of the first passivation layer 140, undertaking the functions of low-resistance electrical connection and heat absorption. Above the inflection point, the metal bonding layer 160 is separated from the pixel unit by the second passivation layer 320 and does not participate in the electrical connection. At the same time, the inflection point serves as an etching stop marker, which can precisely control the position of the second passivation layer 320, ensuring accurate alignment and reliable contact between the metal bonding layer 160 and the first semiconductor layer 130. The sidewall morphology above the inflection point (such as a vertical surface or an inwardly inclined surface) is independently responsible for optimizing the emission angle and suppressing optical crosstalk, complementing the efficient conductivity and heat dissipation of the metal bonding layer 160 below the inflection point. It can also perform secondary direction adjustment for light propagating at different angles, jointly achieving synergistic optimization of efficient electrical injection, efficient light extraction, and efficient heat dissipation.

[0187] Furthermore, this design achieves joint coverage by the first passivation layer 140 and the second passivation layer 320. Its ingenuity lies in achieving complementary advantages of the two passivation layers through functional partitioning: the first passivation layer 140 is dedicated to covering the bottom sloping sidewall, providing a flat insulating substrate for the metal bonding layer 160 and preventing short circuits between it and the active region 120; the second passivation layer 320 not only performs an isolation function by wrapping the vertical sidewall but also provides a smooth interface for subsequent deposition of metal structures such as isolation fences or filling metal pillars, facilitating deposition and thus improving light extraction efficiency. The first passivation layer 140 and the second passivation layer 320 cooperate and divide their functions, eliminating the interface reliability risks caused by the junction of different passivation layers on the vertical sidewall and expanding the process window. Meanwhile, the metal bonding layers 160 of adjacent pixel units are isolated from each other, and together with the first passivation layer 140 and the second passivation layer 320, they form complete electrical isolation and physical protection for the sidewalls and bottom of the pixel units, effectively suppressing current crosstalk and optical crosstalk, while blocking external water and oxygen erosion, thus comprehensively ensuring the electrical performance and long-term reliability of the metal bonding layer 160, and further improving the stability and reliability of the device.

[0188] As an example, see Figures 1-5 When the inflection point is located at the top of the pixel unit, there is no sidewall above the part with the largest horizontal dimension. The second passivation layer 320 is adjacent to the inflection point, and the first passivation layer 140 covers the sidewall of the pixel unit.

[0189] Specifically, the second passivation layer 320 does not need to cover the sidewalls of the pixel unit; it only intersects with the first passivation layer 140 to protect the top edge. The first passivation layer 140 completely covers the entire sidewall of the pixel unit, simplifying the partitioned coverage structure of the passivation layer. See, for example... Figures 2-5The overall size of the pixel unit remains monotonically constant along the vertical direction, and the sidewalls of the pixel unit are covered by the first passivation layer 140.

[0190] Specifically, in this configuration, the sidewalls do not require the second passivation layer 320. This structure simplifies the passivation layer process while maintaining a large-area electrical contact between the metal bonding layer 160 and the first semiconductor layer 130, making it suitable for display devices that are sensitive to process costs or have high integration. "Monotonically increasing" includes gradually increasing from bottom to top, step-like increasing, or a combination of the above.

[0191] As a preferred example of an inclined sidewall, see [reference]. Figures 1-3 The sidewalls of each pixel unit collectively form a continuously extending inclined surface from bottom to top. This structure eliminates interlayer steps and sharp corners, facilitating continuous coverage of the first passivation layer 140 and the metal bonding layer 160. This allows the metal bonding layer 160 to extend as a continuous metallic body, maximizing both the electrical contact area and the thermal diffusion area. This significantly improves heat dissipation efficiency while reducing contact resistance, achieving synergistic optimization of electrical and thermal performance. Furthermore, the metal bonding layer 160 can function as a reflector, maximizing sidewall reflection efficiency and improving insulation reliability and device stability.

[0192] Based on the above structure, the inclination of the sidewalls can be combined in different ways according to design requirements. For example, see [reference needed]. Figure 6 The first semiconductor layer 130 and the active layer 120 have inclined sidewalls, while the second semiconductor layer 110 has a vertical sidewall; or the first semiconductor layer 130 has an inclined sidewall, and the second semiconductor layer 110 and the active layer 120 have vertical sidewalls. Through differentiated design, the light extraction direction, current distribution, and passivation layer coverage effect can be flexibly adjusted to adapt to different pixel sizes and light extraction efficiency requirements.

[0193] The polarity, material, and thickness configuration of the semiconductor layer will be explained next.

[0194] As an example, the first semiconductor layer 130 is a P-type semiconductor layer, and the second semiconductor layer 110 is an N-type semiconductor layer. As another example, the first semiconductor layer 130 is an N-type semiconductor layer, and the second semiconductor layer 110 is a P-type semiconductor layer. Regardless of the polarity configuration, the metal bonding layer 160 forms a large-area electrical contact with the bottom first semiconductor layer 130.

[0195] As a preferred embodiment, see [reference] Figure 1The common anode structure is adopted, that is, the first semiconductor layer 130 is N-type and the second semiconductor layer 110 is P-type (bottom layer N-type, top layer P-type). This polarity configuration, together with the large-area metal bonding layer 160 and the inverted trapezoidal sidewall of the present invention, forms a triple synergy, which has significant advantages in electrical, optical and thermal aspects.

[0196] In some embodiments, when the first semiconductor layer 130 is P-type, its material includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, and p-AlGaN. When the second semiconductor layer 110 is N-type, its material includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, and n-AlGaN. In other embodiments, when the first semiconductor layer 130 is N-type, its material may be selected from at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, and n-AlGaN; and when the second semiconductor layer 110 is P-type, its material may be selected from at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, and p-AlGaN.

[0197] Furthermore, the active layer 120 can be configured as a single-well, multi-well, quantum well, multiple quantum well (MQW), quantum dot, or quantum wire structure. As a preferred example, the active layer 120 adopts a multiple quantum well (MQW) structure, including alternating well layers and barrier layers, such as a combination of InGaN well layers and GaN barrier layers. Embodiments of this disclosure are not limited thereto.

[0198] As an example, see Figure 7In a common anode embodiment where the first semiconductor layer 130 is N-type and the second semiconductor layer 110 is P-type, the thickness of the P-type semiconductor layer is less than the thickness of the N-type semiconductor layer. In a specific embodiment, the thickness of the P-type semiconductor layer ranges from 50 nm to 150 nm, the thickness of the active layer 120 ranges from 50 nm to 400 nm, and the thickness of the N-type semiconductor layer ranges from 500 nm to 3 μm. This thickness configuration allows the P-type semiconductor layer to directly form a low-resistance contact with the transparent common electrode layer 400, significantly reducing the forward operating voltage; the bottom N-type semiconductor layer forms a large-area contact with the metal bonding layer 160, utilizing the high electron mobility of the N-type material to achieve uniform current spread, further reducing contact resistance. Simultaneously, the thinner P-type semiconductor layer allows the active layer 120 to be closer to the light-emitting surface, shortening the light emission path and reducing light absorption loss within the semiconductor layer. Secondly, combined with the inverted trapezoidal sidewall structure, the lateral dimension of the active layer 120 increases along the light direction, expanding the light-emitting area. Simultaneously, the inverted trapezoidal sidewalls emit lateral light upwards, improving light extraction efficiency. Furthermore, the thicker N-type semiconductor layer provides reliable mechanical support for subsequent metal bonding or substrate transfer processes, preventing warping or breakage during bonding. The above are exemplary configurations of semiconductor layer polarity, material, and thickness.

[0199] Based on the aforementioned isolation structure 300, a metal structure may be further provided within the trench 310. Further details will be provided here.

[0200] As an example, the metal structure is a filled metal pillar; the second passivation layer 320 at least covers the sidewalls of the filled metal pillars, preventing unintended electrical contact between the metal layer and the sidewalls of the pixel units. See also Figure 2 or Figures 4-8 and Figure 12 The filling metal pillars can be a metal reflective layer 330. Of course, the filling metal pillars can be made of highly conductive metals such as Cu, Al, and W, and are formed inside the trench 310 through deposition and etch-back processes to achieve potential connection between adjacent pixel units. In some embodiments, the filling metal pillars are multilayer structures, such as Al / Cu / Al, Ti / Cu / Ti, or Ag / Cu / Ag stacked designs, to optimize reflectivity, conductivity, and anti-diffusion performance. The metal structure may include a reflective layer and a filling layer, whose main functions include reflecting and isolating optical crosstalk between pixels, and enhancing the electrical transport extension capability of the common electrode.

[0201] As an example, see Figure 10An isolation fence can also be disposed within the trench 310; the second passivation layer 320 at least covers the sidewalls of the isolation fence, making it completely insulated from the metal bonding layer 160 and the sidewalls of the pixel unit. The isolation fence may contact or be spaced from the sidewalls of the trench 310, extending along the periphery of the pixel unit in a ring or strip structure to enhance the mechanical strength of the isolation structure 300. The isolation fence can be formed simultaneously by etching during the formation of the trench 310, simplifying the process and reducing manufacturing costs.

[0202] In other embodiments, the metal structure within the trench 310 is not limited to the examples of metal structures described above. See also... Figure 11 The surface of the sidewall of the trench 310 (e.g., at a 15° angle to the vertical direction) may be sequentially covered with the second passivation layer 320, the transparent common electrode layer 400, and the metal reflective layer 330 to reduce light loss and suppress crosstalk. Alternatively, the surface of the sidewall of the trench 310 may also be sequentially covered with the second passivation layer 320, the metal reflective layer 330, and the transparent common electrode layer 400.

[0203] As an example, in an embodiment where the driving substrate 200 also provides a second contact 220, the second contact 220 is electrically connected to the metal structure such as the isolation fence or the filling metal pillar. For details, see [link to relevant documentation]. Figure 2 The second contact 220 can serve as a common cathode (or common anode) contact, making the metal structure (the isolation fence or filled metal pillar) an extension of the common electrode of the pixel unit. This distributes the reference potential evenly around each pixel unit, improving the integrity of the current loop and simultaneously serving as an electrostatic discharge path, enhancing the device's anti-static capability. In one embodiment, the second contact 220 and the metal structure are electrically connected through a redistribution layer on the surface of the driving substrate 200, simplifying the peripheral circuit design.

[0204] As an example, the display semiconductor device also includes a pixel fence 151 located on both sides of the pixel unit, including a first end and a second end opposite to each other. The sidewalls and top of the first end are covered by the second passivation layer 320; one sidewall of the second end is in contact with the metal bonding layer 160; and the remaining sidewalls of the second end are covered by the second passivation layer 320.

[0205] Specifically, such as Figure 8 or Figure 13As shown, the second passivation layer 320 has a three-dimensional structure with bends. The sidewall of the pixel fence 151 is in direct contact with the metal bonding layer 160 to form a vertical conductive interface to reduce contact resistance. The first end and top of the pixel fence 151 are covered by the second passivation layer 320 to protect the top of the fence and prevent short circuits of the transparent electrode. At the same time, the columnar structure formed by the pixel fence 151 around the pixel unit can serve as an optical resonant cavity, reflecting the side-emitted light beam multiple times and confining the light energy within the cavity, significantly improving the luminous efficiency. Figure 8 In this embodiment, when the groove 310 is basically vertical, the corresponding structure of the pixel fence 151 is as follows; Figure 13 This is the structure of the pixel fence 151 in this embodiment when the groove 310 has a certain tilt angle.

[0206] It should be noted that the isolation fence (described in detail below) differs fundamentally from the pixel fence 151 described here in structure and function. The pixel fence 151 is located on both sides of the pixel unit, with one sidewall of its second end directly contacting the metal bonding layer 160 to form a vertical conductive interface, serving both conductive and optical resonance functions. Its first sidewall and top are covered by the second passivation layer 320, protecting the top of the fence and preventing short circuits with the transparent electrode. The isolation fence is disposed within the trench 310, completely separated from the metal bonding layer 160 by the second passivation layer 320, with no direct electrical contact. It extends along the periphery of the pixel unit in a ring or strip structure, enhancing the mechanical strength of the isolation structure 300. In some embodiments, the isolation fence is also electrically connected to the second contact 220 on the driving substrate 200, serving as an extension of the common electrode to evenly distribute the reference potential to each pixel unit, while also acting as an electrostatic discharge path to improve antistatic capabilities.

[0207] As another embodiment of the present invention, the above structure is also applicable to the integration of vertical-cavity surface-emitting laser (VCSEL) arrays. The first semiconductor layer 130 can be an N-type DBR mirror, the active layer 120 can be a multi-quantum-well active region, and the second semiconductor layer 110 can be a P-type DBR mirror. By integrating the VCSEL unit with the driving substrate 200 through the metal bonding layer 160, circuit driving and thermal management of a high-density laser array can be achieved. All equivalent transformations in the field of VCSEL arrays based on the ideas of this invention should fall within the protection scope of this invention.

[0208] In this embodiment, the structure achieves comprehensive optimization of electrical, optical, and thermal aspects through the collaborative design of the driving substrate, pixel unit, and metal bonding layer. First, the metal bonding layer contacts the first contact surface of the driving substrate and extends along the sidewall of the pixel unit to the first semiconductor layer, upgrading the traditional two-dimensional planar contact to a three-dimensional contact. Compared to the traditional solution with only bottom contact, the contact area is increased by tens to hundreds of times, resulting in a reduction in contact resistance and an order-of-magnitude increase in heat dissipation capacity. This significantly reduces power consumption and improves device reliability, while avoiding the bottlenecks of difficult alignment and stringent bonding requirements in traditional micro-contact processes, effectively reducing manufacturing costs and process complexity. Second, in the vertical direction away from the driving substrate, the lateral dimension of the pixel unit monotonically increases within at least a certain range. Combined with the partitioned coverage of the sidewall passivation layer, the sidewall morphology can be flexibly adjusted to optimize the light emission angle and improve light extraction efficiency. Third, the metal bonding layer combines conductivity, heat dissipation, and reflection functions. Furthermore, the metal bonding layers of adjacent pixel units are isolated from each other. With the addition of the first passivation layer and the second passivation layer, complete electrical isolation and physical protection can be formed for the sidewalls and bottom of the pixel units, effectively suppressing current crosstalk between adjacent pixels and blocking external water and oxygen erosion, thereby further improving the stability and reliability of the device.

[0209] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, without departing from the concept of the present invention, the technical features described in each embodiment (such as sidewall morphology, passivation layer coverage method, structure of the metal bonding layer, configuration of the isolation structure, polarity and thickness of the semiconductor layer, etc.) can be arbitrarily arranged and combined according to actual design requirements, and the resulting technical solutions all fall within the scope of protection of the present invention.

[0210] Example 2

[0211] This embodiment uses the display semiconductor device of Embodiment 1 to illustrate its fabrication method. Of course, the structure of Embodiment 1 can also be fabricated using other similar methods. In this embodiment, the second metal layer is first deposited on the driving substrate, and then the pixel units are bonded to the second metal layer through the first metal layer. The following will refer to the appendix to the specification... Figures 14-44 This section details the fabrication method of display semiconductor devices, including the following steps:

[0212] First, refer to Figure 14 and Figure 20 In step S1, a carrier substrate 100 is provided, on which a second semiconductor layer 110, an active layer 120, and a first semiconductor layer 130 are deposited sequentially from bottom to top; the second semiconductor layer 110, the active layer 120, and the first semiconductor layer 130 constitute an epitaxial layer. The first semiconductor layer 130 has an opposite conductivity type to the second semiconductor layer 110.

[0213] As an example, see Figure 20 The carrier substrate 100 is an epitaxial growth substrate, and the second semiconductor layer 110, the active layer 120 and the first semiconductor layer 130 are formed by sequential deposition on the carrier substrate 100.

[0214] Specifically, the carrier substrate 100 may be one of sapphire, silicon, or silicon carbide, and the second semiconductor layer 110, the active layer 120, and the first semiconductor layer 130 are grown using metal-organic chemical vapor deposition or molecular beam epitaxy. In this application, the carrier substrate 100 is removed after subsequent transfer bonding to the driving substrate. The corresponding driving substrate is used to ultimately support the pixel unit and provide electrical connection.

[0215] Furthermore, as an example, the first semiconductor layer 130 is an N-type semiconductor and the second semiconductor layer 110 is a P-type semiconductor; or the first semiconductor layer 130 is a P-type semiconductor and the second semiconductor layer 110 is an N-type semiconductor. The structure and materials of the P-type or N-type semiconductor can be found in Embodiment 1, and will not be repeated here.

[0216] In another embodiment, the epitaxial layer on the carrier substrate 100 is obtained by transfer. That is, before step S1, the method further includes:

[0217] Execute steps S1~1, see below. Figure 15 An epitaxial substrate 101 is provided, wherein the second semiconductor layer 110, the active layer 120 and the first semiconductor layer 130 are sequentially deposited on the epitaxial substrate 101 to form the epitaxial layer.

[0218] Execute steps S1~2, see below. Figure 16 A temporary substrate 102 is provided, and a first temporary bonding layer 103 is provided on the surface of the temporary substrate 102. As an example, the first temporary bonding layer 103 includes at least one of an organic adhesive, a photosensitive adhesive, or an inorganic temporary bonding material; it can be subsequently released by mechanical peeling, thermal sliding, laser debonding, or vapor phase etching. The temporary substrate 102 can be a glass substrate or a semiconductor substrate to support the first temporary bonding layer 103. When released by vapor phase etching, the first temporary bonding layer 103 can be an inorganic dielectric material such as SiO2, which has high bonding strength, good temperature resistance, and excellent reliability.

[0219] Execute steps S1~3, see below. Figure 16 The epitaxial layer is bonded to the temporary substrate 102 through the first temporary bonding layer 103, and the epitaxial substrate 101 is removed.

[0220] Execute steps S1~4, see below. Figure 18 A target carrier substrate 100 is provided, and a second temporary bonding layer 104 is disposed on the surface of the carrier substrate 100. The carrier substrate 100 may be a silicon wafer or a glass wafer, and is used to support the subsequent chip unit 105. The material of the second temporary bonding layer 104 is the same as that of the first temporary bonding layer 103.

[0221] Execute steps S1~5, see below. Figures 19-20 The epitaxial layer on the temporary substrate 102 is bonded to the carrier substrate 100, and the temporary substrate 102 is then removed. The specific transfer method is determined according to the substrate size.

[0222] If the size of the carrier substrate 100 is equal to the size of the temporary substrate 102, a wafer-level bonding process is used; this can improve the morphological characteristics such as wafer warp, bow, and total thickness deviation (TTV), thereby reducing the difficulty of subsequent bonding and processing.

[0223] If the size of the carrier substrate 100 is larger than the size of the temporary substrate 102, the epitaxial layer and the substrate on which it is located are cut together before bonding to form the chip units 105 arranged in an array.

[0224] In one specific embodiment, see Figure 17 First, the temporary substrate 102 and the epitaxial layer are cut together to form the chip units 105 arranged in an array. Specifically, laser scribing and / or dry etching processes can be used for cutting. The chip units 105 are relatively large, and each chip unit 105 contains multiple sub-pixel units. Subsequently, the cut chip units 105 are bonded to the carrier substrate 100, and the temporary substrate 102 is removed.

[0225] The above configuration facilitates the integration of multiple chip units 105 onto the same carrier substrate 100, achieving large-scale heterogeneous integration. Of course, in other embodiments, the chip units 105 can also be obtained by segmentation on the epitaxial substrate 101; this is not a limitation.

[0226] As an example, the carrier substrate 100 has a size of ≥8 inches, preferably 12 inches, to match the mainstream semiconductor manufacturing linewidth and achieve efficient wafer-level bonding with the subsequent driving substrate.

[0227] This completes the fabrication or integration of the epitaxial layer on the carrier substrate 100, providing a material basis for subsequent etching to form the mesa structure.

[0228] In another embodiment, the polarity of the epitaxial layer can be reversed in a single transfer. Specifically, the epitaxial layer is directly bonded from the epitaxial substrate 101 to the carrier substrate 100, and the polarity is reversed by flipping the substrate during the bonding process, eliminating the need for two transfers. It should be noted that the polarity order of the epitaxial layer is not limited to the above example. Those skilled in the art will understand that the specific polarity configuration of the epitaxial layer does not affect the implementation of the core structure of the present invention, and therefore will not be elaborated further.

[0229] Next, refer to Figure 14 and Figures 20-22 In step S2, an epitaxial layer is etched on the surface of the carrier substrate 100 to form an array of mesa structures. The mesa structures include a second semiconductor layer 110, an active layer 120, and a first semiconductor layer 130 stacked from bottom to top, with at least the active layer 120 exposed between adjacent mesa structures. In the vertical direction toward the carrier substrate 100, the lateral dimension of the mesa structure increases in at least a portion of the range.

[0230] Specifically, Figure 20 The carrier structure after removing the temporary substrate 102. (For easy reference) Figure 20 In subsequent processes, the second temporary bonding layer 104 is omitted from the carrier structure shown in the attached drawings. The etching depth and sidewall morphology can be flexibly adjusted according to design requirements. In one embodiment, see [reference needed]. Figure 21 The etching depth between adjacent mesa structures stops at the surface of the second semiconductor layer 110 or extends into its interior to increase the subsequent metal contact area or optimize current spread; at this time, the sidewalls of the first semiconductor layer 130, the active layer 120 and the second semiconductor layer 110 are all inclined sidewalls.

[0231] In another embodiment, see Figure 22 The sidewalls of the active layer 120 are exposed between adjacent mesa structures, and the sidewalls of the second semiconductor layer 110 can be determined according to the sidewall angle of the trench 310 formed subsequently. This combined design provides a flat interface for the first passivation layer 140 and allows the subsequent metal bonding layer 160 to directly cover the inclined sidewalls of the active layer 120, reducing optical waveguide loss and increasing the light extraction efficiency while increasing the light-emitting area. Of course, the mesa can also be stepped; this is not a limitation.

[0232] In one specific embodiment, see Figures 23-25 Prior to the formation of the first metal layer 150, a patterned first passivation layer 140 is deposited on the surface of the mesa structure.

[0233] As an example, see Figure 23The first passivation layer 140 has at least one opening 132, the opening 132 being located on the surface and / or sidewalls of the first passivation layer 140 to expose at least one area for electrical connection with the first semiconductor layer 130; as an example, see [reference needed]. Figure 24 The opening 132 can be formed at the bottom of the first passivation layer 140 using photolithography etching to expose a predetermined area of ​​the first semiconductor layer 130; or the first passivation layer 140 can be made to cover only part of the sidewalls of the first semiconductor layer 130, with the remaining sidewalls and bottom directly exposed, thus eliminating the need for additional openings; alternatively, exposed areas can be provided at both the bottom and sidewalls to increase the contact area. Furthermore, see [reference needed]. Figure 25 The number of openings 132 is three; of course, the number, position, and distribution of the openings 132 can be flexibly adjusted according to design requirements to effectively control contact resistance and meet the requirements of different pixel sizes and drive currents. This diverse configuration of the openings 132 provides process flexibility for optimizing device performance.

[0234] Next, refer to Figure 14 and Figure 26 Step S3 is executed, in which a first metal layer 150 is formed on the surface of the carrier substrate 100. The first metal layer 150 extends to at least a portion of the sidewall of the mesa and is electrically connected to the first semiconductor layer 130.

[0235] The material of the first metal layer 150 can be selected from at least one of Cr, Al, Ag, Pt, Ni, Ti, Sn, Cu, Au, and Rh, or it can be formed by stacking two or more of the above metals in sequence. Through the stacked design, different functions can be optimized synergistically. In some embodiments, the first metal layer 150 can be selected from high reflectivity metal materials such as Ag, Al, and Rh, or adopt a multilayer structure, wherein the sublayer facing the pixel unit is a high reflectivity metal, and the sublayer facing away from the pixel unit is a low-resistance conductive metal (such as Cu).

[0236] As an example, the first ohmic contact layer 131 may also be disposed between the first semiconductor layer 130 and the first metal layer 150.

[0237] For details, please refer to Figure 24 or Figure 25 The first ohmic contact layer 131 is used to form an ohmic contact between the subsequently formed first metal layer 150 and the first semiconductor layer 130, reducing contact resistance and improving current injection efficiency. In an embodiment where the first passivation layer 140 is formed, the first ohmic contact layer 131 is located between the first semiconductor layer 130 and the first passivation layer 140. The opening 132 exposes at least a portion of the first ohmic contact layer 131.

[0238] See Figure 26 The first metal layer 150 can be formed on the surface of the mesa structure and the first passivation layer 140 (if present) using a deposition process, and is electrically connected to the first semiconductor layer 130 or the first ohmic contact layer 131 through the opening 132 or by direct contact. Subsequent planarization using grinding or CMP processes can be performed to make the upper surface of the first metal layer 150 higher than the upper surface of the first semiconductor layer 130. The material and structure of the first metal layer 150 are the same as in Embodiment 1, and will not be described in detail here.

[0239] Next, refer to Figure 14 and Figures 27-28 In step S4, the driving substrate 200 is provided, the driving substrate 200 is provided with the first contact 210, and the second metal layer 230 is formed on the driving substrate 200; the first metal layer 150 and the second metal layer 230 are bonded together to form the metal bonding layer 160, and the metal bonding layer 160 is electrically connected to the first contact 210.

[0240] Specifically, the material of the second metal layer 230 can be selected from at least one of Cr, Al, Ag, Pt, Ni, Ti, Sn, Cu, Au, and Rh, and is used to form a reliable metal-metal bonding interface with the first metal layer 150. Preferably, the second metal layer 230 and the first metal layer 150 are made of the same material, which can effectively reduce the bonding process difficulty, improve the process window and bonding yield, and enhance the reliability of electrical connections; at the same time, as a heat conduction medium, it can efficiently conduct the heat generated by the pixel unit to the driving substrate 200, further improving the thermal management performance of the device.

[0241] This bonding process, through the fault-tolerant design of the large-area metal bonding layer 160, relaxes the alignment requirements of the bonding process from the sub-micron level to the micron level in traditional processes, and avoids the accumulation of errors from multiple alignments by adopting a "bonding first, then grooving" sequence. Therefore, the overall process difficulty and manufacturing cost are significantly lower than traditional hybrid bonding or bump bonding schemes. At the same time, it avoids the strict surface flatness requirements of traditional hybrid bonding and the high alignment requirements of bump bonding. This process is significantly simplified, greatly reducing process complexity and cost.

[0242] In one embodiment, reference may be made to Embodiment 1. Figure 2 The driving substrate 200 is further provided with a second contact 220, the potential of the second contact 220 being opposite to the potential of the first contact 210, so as to facilitate the formation of a circuit between the metal structure formed in the subsequent trench 310 and the subsequent transparent common electrode layer 400.

[0243] Next, refer to Figure 14 and Figures 29-30 Step S5 is executed to remove the carrier substrate 100 and expose the second semiconductor layer 110.

[0244] Specifically, depending on the material properties of the carrier substrate 100, it can be removed by laser lift-off, mechanical grinding combined with chemical mechanical polishing, wet chemical etching, or dry etching. In actual production, a combination of processes is often used, such as first grinding to thin the substrate and then wet etching the residue, to efficiently and with low damage expose a smooth surface of the second semiconductor layer 110. In one specific embodiment, the carrier substrate 100 is removed by laser lift-off, and then the second semiconductor layer 110 is planarized by grinding or CMP thinning until the first passivation layer 140 is exposed. In other embodiments, the second semiconductor layer 110 may not be planarized; see [reference needed]. Figure 36 The structure is such that, subsequently, a portion of the sidewalls of the second semiconductor layer 110 are etched to form the structure above the inflection point; this will be described in detail later. Figure 38 Structure preparation process.

[0245] Next, refer to Figure 14 and Figures 31-34 In step S6, an isolation structure 300 is formed between adjacent mesa structures. The isolation structure 300 divides the metal bonding layer 160 into multiple electrically isolated regions, each region corresponding to a pixel unit.

[0246] As an example, the formation process of the isolation structure 300 includes: forming a trench 310 between the platform structures to expose the drive substrate 200; forming a second passivation layer 320 in the trench 310, the second passivation layer 320 at least covering the sidewall of the trench 310.

[0247] For details, please refer to Figure 31 The trench 310 is formed by etching between adjacent pixel units, and the second passivation layer 320 is formed by deposition (e.g., ALD process) on the sidewalls of the trench 310. Figure 32 The excess second passivation layer 320 at the bottom can be removed by a back etching process. Figure 33 ); as an example, see Figure 38 The sidewalls of the trench 310 may form a certain angle (e.g., 0~45°) with the vertical direction to facilitate the stepped coverage of the second passivation layer 320 and adapt to the sidewall shape of the pixel unit, avoiding poor coverage or stress concentration at corners. In one embodiment, the second passivation layer 320 is retained on the sidewalls of the trench 310, as shown in Embodiment 1. Figure 2 This exposes the bottom of the trench 310 for subsequent electrode lead-out or metal filling. In another embodiment, refer to Embodiment 1. Figure 3 The second passivation layer 320 fills the trench 310 as an insulating layer for isolation. In other embodiments, refer to Embodiment 1. Figure 10 A metal structure may be provided in the trench 310, and the second passivation layer 320 may also cover the sidewall of the metal structure.

[0248] As an example, see Embodiment 1. Figure 2 or Figures 10-11 The metal structure is simultaneously formed within the trench 310; when the second contact 220 is provided on the driving substrate 200, the second contact 220 is electrically connected to the metal structure. The metal structure can enhance the electrical isolation effect between adjacent pixels, and can also serve as an auxiliary heat dissipation channel or reflective structure to improve device performance.

[0249] Furthermore, in an embodiment with the second contact 220, in order to expose the second contact 220 within the subsequent trench 310, the second contact 220 on the surface of the driving substrate 200 has been precisely positioned using a front-end CMOS process and has alignment marks during manufacturing. In the photolithography step of forming the trench 310, the photolithography machine identifies the alignment marks on the driving substrate 200 and precisely overlays the pattern of the trench 310 with the position of the second contact 220, thereby achieving lateral alignment between the trench 310 and the second contact 220.

[0250] As an example, see Embodiment 1. Figure 10 The metal structure is an isolation fence 340, and the second passivation layer 320 at least covers the sidewalls of the isolation fence 340. Specifically, during the formation of the trench 310, a patterned etching process can be used to retain part of the metal bonding layer 160 within the trench 310 to form the isolation fence 340. That is, the trench 310 and the isolation fence 340 are defined synchronously in the same etching step, without the need for additional deposition. This integrated process simplifies the process, reduces costs, and ensures structural consistency. The isolation fence 340 extends along the periphery of the pixel unit in a ring or strip shape to enhance the mechanical strength of the isolation structure 300. In one embodiment, as previously described in Embodiment 1... Figure 11 The transparent common electrode layer 400 covers the pixel unit and further covers the sidewalls of the trench 310 and the isolation fence 340, so that the isolation fence 340 is electrically connected to the transparent common electrode layer 400 and can serve as an extension of the common electrode.

[0251] As an example, the metal structure is a filled metal pillar, and the second passivation layer 320 at least covers the sidewalls of the filled metal pillar. Specifically, the filled metal pillar can be used to fill the trench 310 using electroplating or chemical plating processes. The filled metal pillar can serve as a grounding wire, shielding layer, or heat dissipation channel, further optimizing the electrical performance and thermal management capabilities of the pixel array. In some embodiments, see [reference needed]. Figures 34-35 The filling metal pillars can serve as a metal reflective layer 330, which is surrounded by the second passivation layer 320 and electrically connected to the transparent common electrode layer 400. Of course, the structural design and materials of the metal structure are not limited to this; please refer to Embodiment 1 for details, which will not be elaborated here.

[0252] As an example, see Figure 35 A transparent common electrode layer 400 is formed on the surface of the pixel unit and the isolation structure 300, and the transparent common electrode layer 400 is electrically connected to the second semiconductor layer 110. Specifically, the transparent common electrode layer 400 covers the entire surface of each pixel unit, serving as a common electrode to achieve uniform current injection. The material of the transparent common electrode layer 400 is selected from at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), antimony-doped tin oxide (ATO), and fluorine-doped tin oxide (FTO). In an embodiment structure having the isolation fence 340 within the trench 310, refer to Embodiment 1. Figure 10 The transparent common electrode layer 400 forms a continuous cover on the sidewall of the trench 310, thereby ensuring the continuity of the common electrode of each pixel unit, while avoiding weak or broken coverage caused by the steps of the trench 310, thus improving electrode reliability.

[0253] As an example, see Figure 35 Before forming the transparent common electrode layer 400, a second ohmic contact layer 111 is formed on the surface of the second semiconductor layer 110 to further reduce contact resistance. Specifically, the second ohmic contact layer 111 can be a metal stack such as Ni / Au, Ni / Ag, or Ni / Pt, formed by deposition and rapid thermal annealing processes, so that a low-resistance ohmic contact is formed between the second semiconductor layer 110 and the transparent common electrode layer 400, thereby reducing the device's forward operating voltage and improving current injection efficiency. The above describes the fabrication method of the semiconductor device shown in this embodiment.

[0254] In this embodiment, a further explanation of the preparation method of the inflection point structure in Embodiment 1 is provided.

[0255] In step S6 of this embodiment, the degree of etching of the mesa structure determines the position of the turning point in embodiment one. Figure 24This is shown as the mesa structure exposing the second semiconductor layer 110 during the etching process. Figure 24 Based on this, after depositing the first metal layer 150, the desired result is obtained. Figure 36 The intermediate structure; next, refer to Figure 37 The exposed portion of the second semiconductor layer 110 is etched to obtain the second semiconductor layer 110 with a certain tilt angle; then, refer to... Figure 38 The groove is further etched using an etching process, and the sidewalls of the groove 310 are inclined sidewalls. Further details can be found in the following section. Figure 38 The second passivation layer 320 is deposited within the trench 310. Thus, the second passivation layer 320 and the first passivation layer 140 cooperate to isolate the pixel units, and the corresponding pixel units of the metal bonding layer 160 are independent of each other.

[0256] Of course, in the process of forming the isolation structure 300 in this embodiment, if the semiconductor layer in the pixel unit has not been completely etched and divided, the isolation structure 300 can also be formed by first etching the pixel unit and then etching the metal bonding layer 160 with an ion beam.

[0257] As one optional embodiment, refer to Embodiment 1. Figure 8 Taking a pixel unit with the sidewall of the second semiconductor layer 110 as a vertical plane as an example, see [reference]. Figures 39-44 The formation process of the pixel fence 151 is further explained.

[0258] First, refer to Figure 39 The pixel unit structure is bonded to the driving substrate 200; then, refer to... Figure 40 The second semiconductor layer 110 is etched to expose the first passivation layer 140. Next, refer to... Figure 41 A mask layer 510 is provided to cover the top and sidewalls of the second semiconductor layer 110, wherein the active layer 120 and the sidewalls of the first semiconductor layer 130 are protected by the first passivation layer 140; then, refer to Figure 42 The metal bonding layer 160 is patterned using an ion beam etching process, causing metal atoms to be back-sputtered and deposited on the sidewalls of the pixel unit, forming the pixel fence 151. In this embodiment, the mask layer 510 is a photoresist layer. (See also...) Figures 43-44The second passivation layer 320 is deposited on both sides of the pixel fence 151 and within the trench 310 by removing the photoresist layer 510. Alternatively, in another embodiment, the mask layer 510 can be made of an inorganic material, such as, but not limited to, silicon oxide and silicon nitride. After the pixel fence 151 is formed, only the portion of the mask layer 510 covering the top of the second semiconductor layer 110 needs to be removed; the remaining inorganic material, together with the subsequently deposited passivation layer, constitutes the second passivation layer 320.

[0259] Furthermore, the bottom of the pixel fence 151 contacts the sidewall of the metal bonding layer 160, and the upper part is spaced apart from the second semiconductor layer 110 or the active layer 120, forming an optical resonant cavity for the pixel unit. This structure is suitable for the aforementioned pixel units with a turning point, where the lateral dimension of the pixel unit above the turning point remains unchanged or gradually decreases along the vertical direction. For example, below the turning point, the sidewall of the first semiconductor layer 130 is inclined, and the sidewalls of the second semiconductor layer 110 and the active layer 120 are perpendicular or recessed; or, the sidewalls of the first semiconductor layer 130 and the active layer 120 are inclined, and the sidewall of the second semiconductor layer 110 is perpendicular or recessed. In this embodiment, the turning point can be located at any position of the second semiconductor layer 110 or the active layer 120, and the formation of the pixel fence 151 enhances the light field confinement and improves the luminous efficiency.

[0260] In summary, the present invention provides a display semiconductor device and a method for fabricating the same, comprising a driving substrate, a pixel unit, and a metal bonding layer. A first contact is provided on the surface of the driving substrate; the pixel unit is located above the driving substrate, and its lateral dimension increases at least partially in the direction away from the driving substrate; the metal bonding layer is disposed on the surface of the driving substrate, making contact with the first contact surface to achieve electrical connection, and extends to at least a portion of the sidewalls of the pixel unit, forming a large-area electrical contact with the first semiconductor layer 130.

[0261] This application replaces the tiny metal contacts at the bottom of traditional pixels with a large-area metal bonding layer, increasing the contact area between the metal bonding layer and the driving substrate. This fundamentally avoids the bottlenecks of high processing difficulty and stringent alignment requirements of small-sized contacts. Simultaneously, by expanding the area of ​​the metal bonding layer to be much larger than the size of the first contact, the current is fully laterally spread within the large-area metal bonding layer before reaching the first contact, significantly reducing the current constriction effect. Furthermore, the large-area contact between the metal bonding layer and the first semiconductor layer further reduces contact resistance, thereby effectively improving current injection efficiency and luminous brightness. Secondly, this metal bonding layer also serves as a highly efficient heat diffusion layer, extending laterally to the sidewalls of the pixel unit. This allows heat to diffuse uniformly laterally before being conducted to the driving substrate, significantly reducing junction temperature and heat accumulation during device operation. This alleviates thermal stress caused by the mismatch of thermal expansion coefficients of different materials, thereby suppressing the risk of interface delamination and improving heat dissipation performance and device reliability. Additionally, by using a large-area, dielectric-free continuous metal layer for bonding, the bonding process difficulty is significantly reduced compared to hybrid bonding or bump bonding. Furthermore, the metal bonding layers of adjacent pixel units are isolated from each other. Combined with the first and second passivation layers, this provides complete electrical isolation and physical protection for the sidewalls and bottom of the pixel units, effectively suppressing current crosstalk between adjacent pixels and preventing external water and oxygen erosion, further improving the stability and reliability of the device. This invention offers significant synergistic advantages in simultaneously simplifying alignment processes, reducing resistance, improving heat dissipation, suppressing crosstalk, and enhancing reliability while continuously miniaturizing pixel dimensions.

[0262] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A display semiconductor device, characterized in that, include: The driving substrate is provided with a first contact. A pixel unit, located above the driving substrate, includes a first semiconductor layer, an active layer, and a second semiconductor layer disposed from bottom to top; wherein, in the vertical direction away from the driving substrate, the lateral dimension of the pixel unit increases in at least a portion of the range. A metal bonding layer is disposed on the surface of the driving substrate and contacts the first contact surface to achieve electrical connection; the metal bonding layer extends to at least a portion of the sidewall of the pixel unit and is electrically connected to the first semiconductor layer, but has no direct contact with the active layer and the second semiconductor layer; The metal bonding layers of adjacent pixel units are isolated from each other.

2. The display semiconductor device according to claim 1, characterized in that: The lateral dimension of the bonding surface of the metal bonding layer is greater than or equal to the maximum lateral dimension of the pixel unit.

3. The display semiconductor device according to claim 1, characterized in that: The portion of the pixel unit whose lateral size increases includes at least one first portion and at least one second portion that are sequentially connected along the vertical direction; wherein the lateral size of the first portion gradually increases along the vertical direction.

4. The display semiconductor device according to claim 1, characterized in that: It also includes isolation structures located between adjacent pixel units.

5. The display semiconductor device according to claim 4, characterized in that: The isolation structure includes a trench and a second passivation layer, the second passivation layer at least covering the sidewalls of the trench.

6. The display semiconductor device according to claim 5, characterized in that: It also includes a first passivation layer, and the sidewall of the pixel unit has a turning point, which is the position where the lateral dimension of the pixel unit is the largest.

7. The display semiconductor device according to claim 6, characterized in that: The second passivation layer covers the sidewall above the inflection point of the pixel unit, and the first passivation layer covers at least the sidewall below the inflection point.

8. The display semiconductor device according to claim 7, characterized in that: Below the inflection point, the lateral dimension of the pixel unit remains monotonically constant along the vertical direction; above the inflection point, the lateral dimension of the pixel unit remains monotonically constant along the vertical direction.

9. The display semiconductor device according to claim 7, characterized in that: The inflection point corresponds to the active layer or the second semiconductor layer.

10. The display semiconductor device according to any one of claims 7 to 9, characterized in that: Above the inflection point, at least a portion of the sidewalls of the second semiconductor layer and / or the active layer are substantially vertical.

11. The display semiconductor device according to claim 6, characterized in that: When the inflection point is located at the top of the pixel unit, the second passivation layer is adjacent to the inflection point, and the first passivation layer covers the sidewall of the pixel unit.

12. The display semiconductor device according to claim 6, characterized in that: The first passivation layer has at least one opening located on the sidewall and / or bottom of the first passivation layer to expose at least one area for electrical connection with the first semiconductor layer, through which the metal bonding layer is electrically connected to the first semiconductor layer.

13. The display semiconductor device according to claim 6, characterized in that: The first passivation layer comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

14. The display semiconductor device according to claim 5, characterized in that: It also includes a pixel fence, which is located on both sides of the pixel unit and includes a first end and a second end opposite to each other. The sidewall and top of the first end are covered by the second passivation layer; one sidewall of the second end is in contact with the metal bonding layer; and the remaining sidewall of the second end is covered by the second passivation layer.

15. The display semiconductor device according to claim 5, characterized in that: The sidewall of the trench forms an angle with the vertical direction, and the angle ranges from 0 to 45°.

16. The display semiconductor device according to claim 5, characterized in that: The second passivation layer comprises a single layer formed of at least one material selected from SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2, or a stack formed of two or more of the above materials.

17. The display semiconductor device according to claim 5, characterized in that: A metal structure is installed inside the trench.

18. The display semiconductor device according to claim 17, characterized in that: The metal structure is an isolation fence, and the second passivation layer at least covers the sidewalls of the isolation fence.

19. The display semiconductor device according to claim 17, characterized in that: The driving substrate is further provided with a second contact, which has the opposite polarity to the first contact and is electrically connected to the metal structure.

20. The display semiconductor device according to claim 4, characterized in that: It also includes a transparent common electrode layer, which is located on the surface of the pixel unit and the isolation structure and is electrically connected to the second semiconductor layer.

21. The display semiconductor device according to claim 20, characterized in that: A second ohmic contact layer is disposed between the second semiconductor layer and the transparent common electrode layer; and / or, a first ohmic contact layer is disposed between the first semiconductor layer and the metal bonding layer.

22. The display semiconductor device according to claim 1, characterized in that: The first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor.

23. The display semiconductor device according to claim 22, characterized in that: The thickness of the P-type semiconductor layer is less than the thickness of the N-type semiconductor.

24. The display semiconductor device according to claim 1, characterized in that: The metal bonding layer includes a first metal layer and a second metal layer; the first metal layer extends along the sidewall of the pixel unit and is electrically connected to the first semiconductor layer; the second metal layer is disposed on the driving substrate and is electrically connected to the first contact.

25. The display semiconductor device according to claim 1, characterized in that: The metal bonding layer comprises a single-layer or multi-layer structure formed by at least one metal selected from Cr, Al, Ag, Pt, Ni, Ti, Sn, Cu, Au, and Rh.

26. A method for fabricating a display semiconductor device, characterized in that, Includes the following steps: A carrier substrate is provided, on which a second semiconductor layer, an active layer and a first semiconductor layer are sequentially disposed from bottom to top, wherein the second semiconductor layer, the active layer and the first semiconductor layer constitute an epitaxial layer; On the surface of the carrier substrate, an array of mesa structures is formed by etching the epitaxial layer. The mesa structure includes a second semiconductor layer, an active layer, and a first semiconductor layer stacked from bottom to top, with at least the active layer exposed between adjacent mesa structures. In the direction perpendicular to the carrier substrate, the lateral dimension of the mesa structure increases in at least a certain range. A first metal layer is formed on the surface of the carrier substrate, the first metal layer extending to at least a portion of the sidewall of the mesa structure and being electrically connected to the first semiconductor layer; A driving substrate is provided, wherein a first contact is provided on the driving substrate, and a second metal layer is formed on the driving substrate; the first metal layer and the second metal layer are bonded together to form a metal bonding layer, and the metal bonding layer is electrically connected to the first contact; Remove the carrier substrate to expose the second semiconductor layer; An isolation structure is formed between adjacent mesa structures, the isolation structure dividing the metal bonding layer into multiple electrically isolated regions, each region corresponding to a pixel unit.

27. The method for fabricating a display semiconductor device according to claim 26, characterized in that, The formation of the isolation structure includes: Grooves are formed between the platform structures to expose the drive substrate; A second passivation layer is formed within the trench, the second passivation layer at least covering the sidewalls of the trench.

28. The method for fabricating a display semiconductor device according to claim 27, characterized in that, Also includes: A metal structure is formed inside the trench.

29. The method for fabricating a display semiconductor device according to claim 28, characterized in that: The metal structure is an isolation fence, and the second passivation layer at least covers the sidewalls of the isolation fence.

30. The method for fabricating a display semiconductor device according to claim 28, characterized in that: The driving substrate is further provided with a second contact, which has the opposite polarity to the first contact, and is electrically connected to the metal structure.

31. The method for fabricating a display semiconductor device according to claim 26, characterized in that, Also includes: Before depositing the first metal layer A patterned first passivation layer is deposited on the surface of the platform structure; The first passivation layer has at least one opening located on the surface and / or sidewall of the first passivation layer to expose at least one area for electrical connection with the first semiconductor layer; The first metal layer is electrically connected to the first semiconductor layer through the opening.

32. The method for fabricating a display semiconductor device according to claim 26, characterized in that: The first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor.

33. The method for fabricating a display semiconductor device according to claim 26, characterized in that, Also includes: A transparent common electrode layer is formed on the surface of the pixel unit and the isolation structure, and the transparent common electrode layer is electrically connected to the second semiconductor layer.

34. The method for fabricating a display semiconductor device according to claim 26, characterized in that: A second ohmic contact layer is formed between the second semiconductor layer and the transparent common electrode layer; and / or, a first ohmic contact layer is formed between the first semiconductor layer and the first metal layer.

35. The method for fabricating a display semiconductor device according to claim 26, characterized in that: The carrier substrate is an epitaxial substrate, and the second semiconductor layer, the active layer and the first semiconductor layer are formed by sequential deposition on the epitaxial substrate.

36. The method for fabricating a display semiconductor device according to claim 26, characterized in that, The epitaxial layer on the carrier substrate is formed by the following transfer process, including: An epitaxial substrate is provided, on which the second semiconductor layer, the active layer, and the first semiconductor layer are sequentially deposited; A temporary substrate is provided, wherein a first temporary bonding layer is provided on the surface of the temporary substrate; The epitaxial layer is bonded to the temporary substrate through the first temporary bonding layer, and the epitaxial substrate is removed. A carrier substrate is provided, wherein a second temporary bonding layer is disposed on the surface of the carrier substrate; The epitaxial layer on the temporary substrate is bonded to the carrier substrate, and the temporary substrate is removed. Wherein, the size of the carrier substrate is greater than or equal to the size of the temporary substrate. If the two are of equal size, a wafer-level bonding process is used; If the carrier substrate is larger, the epitaxial layer and the substrate on which it is located are cut together before the epitaxial layer is bonded to the carrier substrate to form an array of chip units.

37. The method for fabricating a display semiconductor device according to claim 36, characterized in that: When the size of the carrier substrate is larger than the size of the temporary substrate, the size of the carrier substrate is greater than or equal to 8 inches.

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