Method and device for checking chip sorting accuracy, electronic equipment and storage medium

Abstract

The invention discloses a method and device for checking chip sorting accuracy, electronic equipment and a storage medium, and belongs to the technical field of semiconductors, and the method comprises the steps: building a checking model which is equal to a wafer object in proportion according to the actual sizes of wafers and chips and the distance between the chips; reading CP data of the chip; displaying the position of each chip in the test model according to the chip coordinate information, and displaying a Bin Code character at the corresponding coordinate position according to the chip Bin Code; setting visual parameters of the inspection model, wherein the visual parameters comprise configuration of different display colors according to Bin Code types and setting of transparency of the inspection model; a wafer object image is obtained through an electron microscope, and the lens magnification of the electron microscope is adjusted, so that the wafer object image and the inspection model have the same size; and carrying out overlapping comparison on the adjusted wafer object image and the inspection model, and inspecting the accuracy of chip sorting through a comparison result. The technical effects that the efficiency can be improved, the cost is reduced, and errors are not prone to occurring are achieved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method, apparatus, electronic device, and storage medium for verifying the accuracy of chip sorting. Background Technology

[0002] In actual manufacturing, the performance of individual chips on the same wafer varies, and these electrical performance differences are randomly distributed across the wafer. After electrical performance testing, the entire wafer needs to be graded according to the distribution of chip electrical performance, i.e., assigned different Bin Codes. Chips with the same Bin Code are then selected by a sorting machine and reconstructed into a new wafer for subsequent chip mounting processes. This is to meet the requirements of power modules that use a multi-chip parallel structure to achieve high current and high power levels. For automotive-grade power modules, not only chip sorting is required, but the data of each chip must also be completely traced back to its initial CP data. For wafers that are conventionally directly mounted, defective chips are removed by ink spot removal before continuing with subsequent processes. For wafers awaiting sorting, any modification to the physical wafer will cause a mismatch between the CP data and the actual wafer, affecting the quantity verification after chip sorting. Currently, existing technologies typically involve manually counting the rows and columns of defective chips on the wafer and correcting their coordinates in the chip alignment (CP). However, this is extremely difficult, prone to misidentifying rows or columns, affecting the overall sorting accuracy, heavily reliant on operator skill, and is not only inefficient but also highly susceptible to introducing new errors due to human error. Alternatively, a method can be used that reads the chip mapping diagram and automatically identifies the location of defective chips to modify the CP and mapping diagram. However, this requires expensive equipment and integration with automated optical inspection equipment, and the high investment cost limits its widespread application and adoption.

[0003] Therefore, it is necessary to provide a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0004] The technical problem to be solved by this invention is the low efficiency, high cost, and susceptibility to errors before and during chip sorting.

[0005] To address the aforementioned technical problems, this invention provides a method for verifying the accuracy of chip sorting. The method includes: establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and chips, and the spacing between chips; reading the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying the Bin Code character at the corresponding coordinate position according to the chip Bin Code; setting visualization parameters for the inspection model, including configuring different display colors according to Bin Code type and setting the transparency of the inspection model; acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope to make the image of the actual wafer the same size as the inspection model; and overlaying and comparing the adjusted image of the actual wafer with the inspection model to verify the accuracy of chip sorting through the comparison results.

[0006] Optionally, the step of overlaying and comparing the adjusted wafer image with the inspection model includes, during the inspection process before chip sorting, when a defective chip appearance is identified, clicking the corresponding position in the inspection model on the imaging window to correct the test results of the chip in the CP data, so that the CP data is consistent with the wafer.

[0007] Optionally, the step of overlaying and comparing the adjusted wafer image with the inspection model includes, during the chip sorting process, after one Bin Code is sorted, matching the wafer image with the inspection model to confirm whether the position of the Bin Code in the inspection model completely overlaps with the chip position of the Bin Code that has been removed from the wafer; if so, the sorting is qualified; if not, the sorting is unqualified.

[0008] Optionally, the step of overlaying and comparing the adjusted wafer image with the inspection model includes stopping the sorting process when an abnormality occurs during chip sorting, such as misalignment, missed pick-up, or accidental pick-up. The location of the abnormality is then determined by overlaying and comparing the inspection model with the wafer image.

[0009] Optionally, the step of comparing the adjusted wafer image with the inspection model includes, after all chip sorting is completed, using the imaging function of the electron microscope to verify whether all remaining chips are defective wafers that do not need to be sorted by completely overlapping the wafer image with the inspection model.

[0010] Optionally, reading the CP data of the chip includes, after reading the CP data, selecting the chip coordinate information and the coordinate origin position, so that the coordinate system of the test model is consistent with the coordinate system of the CP data, wherein the chip coordinate information includes chip coordinate X information and chip coordinate Y information.

[0011] Optionally, configuring different display colors according to Bin Code type includes allocating the display colors of different Bin Codes through automatic generation or manual adjustment.

[0012] According to another aspect of the present invention, the present invention also provides an apparatus for verifying the accuracy of chip sorting. The apparatus includes a model building module for establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and the chip, and the spacing between the chips; a data reading module for reading the chip's CP data, the CP data including wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; a coordinate setting module for displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying Bin Code characters at the corresponding coordinate positions according to the chip Bin Code; a model setting module for setting the visualization parameters of the inspection model, the visualization parameters including configuring different display colors according to Bin Code type, and setting the transparency of the inspection model; an imaging module for acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope so that the image of the actual wafer has the same size as the inspection model; and an inspection module for overlaying and comparing the adjusted image of the actual wafer with the inspection model, and verifying the accuracy of chip sorting through the comparison results.

[0013] According to another aspect of the present invention, an electronic device for verifying the accuracy of chip sorting is also provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it performs the following steps: establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and the chip, and the spacing between the chips; reading the chip's CP data, the CP data including wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying Bin Code characters at the corresponding coordinate positions according to the chip Bin Code; setting visualization parameters of the inspection model, the visualization parameters including configuring different display colors according to Bin Code type, and setting the transparency of the inspection model; acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope so that the image of the actual wafer has the same size as the inspection model; and overlaying and comparing the adjusted image of the actual wafer with the inspection model, verifying the accuracy of chip sorting through the comparison results.

[0014] According to another aspect of the present invention, a computer-readable storage medium for verifying the accuracy of chip sorting is also provided, having stored thereon a computer program that, when executed by a processor, performs the following steps: establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and the chip, and the spacing between the chips; reading the chip's CP data, the CP data including wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying Bin Code characters at the corresponding coordinate positions according to the chip Bin Code; setting visualization parameters of the inspection model, the visualization parameters including configuring different display colors according to Bin Code type, and setting the transparency of the inspection model; acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope so that the image of the actual wafer has the same size as the inspection model; and overlaying and comparing the adjusted image of the actual wafer with the inspection model, verifying the accuracy of chip sorting through the comparison results.

[0015] Beneficial effects: This invention provides a method for verifying the accuracy of chip sorting. The method involves establishing a verification model proportional to the actual wafer size based on the actual dimensions of the wafer and chips, as well as the spacing between chips. The method reads the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results. Then, the method displays the position of each chip in the verification model according to the chip coordinate information, and displays the Bin Code character at the corresponding coordinate position. The method sets visualization parameters for the verification model, including configuring different display colors according to Bin Code type and setting the transparency of the verification model. An image of the actual wafer is acquired using an electron microscope, and the lens magnification of the electron microscope is adjusted so that the image of the actual wafer is the same size as the verification model. The adjusted image of the actual wafer is then overlaid and compared with the verification model, and the accuracy of chip sorting is verified by comparing the results. By establishing an inspection model scaled to the physical wafer, the chip information in the CP data is visualized, creating an intuitive chip distribution view. This allows operators to directly observe the spatial distribution of the CP data before chip sorting. Simultaneously, by acquiring images of the physical wafer using an electron microscope and adjusting them to the same size as the inspection model, the images are overlaid and compared, enabling direct comparison between the CP data and the physical wafer. This allows any inconsistencies to be immediately detected, facilitating timely identification and resolution of anomalies. Furthermore, in the preparation stage before chip sorting, the consistency between CP data and the physical wafer can be updated efficiently and cost-effectively, improving efficiency, avoiding errors, and reducing costs. During chip sorting, anomalies can be detected promptly, reducing the time and effort required for anomaly localization and improving efficiency. Thus, the technical effects of improved efficiency, reduced costs, and reduced errors are achieved both before and during chip sorting. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a method for verifying the accuracy of chip sorting, as provided in an embodiment of the present invention.

[0018] Figure 2 This is a structural block diagram of a device for verifying the accuracy of chip sorting, provided in an embodiment of the present invention.

[0019] Figure 3 This is a structural diagram of an electronic device for verifying the accuracy of chip sorting, provided as an embodiment of the present invention.

[0020] Figure 4 This is a structural diagram of a computer-readable storage medium for verifying the accuracy of chip sorting, provided as an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention. The keyword "and / or" involved in this embodiment indicates two situations: and or. In other words, A and / or B mentioned in the embodiments of the present invention indicates two situations: A and B, or A or B. It describes three states of A and B. For example, A and / or B means: only A is included but not B; only B is included but not A; and A and B are included.

[0022] It should be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Therefore, without departing from the teachings of the exemplary embodiments, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. Spatially related terms, such as “below,” “above,” etc., may be used herein to facilitate the description of the relationship between one element or feature and another element or feature. It is understood that, in addition to the orientations shown in the figures, spatially related terms also include different orientations of the device in use or operation. For example, if the device in the figures is flipped, then an element or feature described as “below” will be oriented to be “above” other elements or features. Therefore, the exemplary term “below” may include both above and below orientations. The device may be oriented (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein are interpreted accordingly.

[0023] Furthermore, in embodiments of the present invention, it should be understood that the at least one controller disclosed herein may include various microprocessors, integrated circuits, storage devices (e.g., flash memory, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or other suitable variations), and software that cooperates to perform the operations disclosed herein. In addition, the at least one controller disclosed herein utilizes one or more microprocessors to execute a computer program contained in a non-transitory computer-readable medium, the computer program being programmed to perform any number of the disclosed functions. Furthermore, the controller provided herein includes a housing and various numbers of microprocessors, integrated circuits, and storage devices (e.g., flash memory, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) located within the housing. The disclosed controller also includes hardware-based inputs and outputs for receiving data from and sending data to other hardware-based devices discussed herein, respectively.

[0024] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for verifying chip sorting accuracy according to an embodiment of the present invention. The method for verifying chip sorting accuracy according to an embodiment of the present invention includes the following steps: Step S100: Based on the actual dimensions of the wafer and the chip, and the spacing between the chips, establish an inspection model that is proportional to the actual wafer. Specifically, establishing a verification model proportional to the actual wafer refers to constructing a digital model on the wafer using computer software, based on the wafer's diameter (e.g., 8 inches or 12 inches) and the actual dimensions of the chips on the wafer (e.g., chip length and width, and chip spacing, such as scribe line width). This model accurately reflects the spatial distribution of chips on the wafer, including the precise location, size, and relative relationships of each chip. The process of establishing the verification model may involve first obtaining the wafer's specifications, including its diameter and thickness; then obtaining the chip design dimensions, such as the length and width of a single chip; and finally obtaining the chip spacing data, i.e., the scribe line width. Based on these parameters, computer-aided design software is then used to construct a two-dimensional or three-dimensional wafer verification model that accurately reflects the spatial distribution of chips on the wafer. In practical applications, the verification model can be implemented based on different software platforms, such as general software or professional semiconductor design software. By using the verification model as a digital reference system, it can be accurately matched with the actual wafer, enabling intuitive comparison between CP data and physical wafers. This allows operators to quickly identify inconsistencies between the data and the actual wafer in a more intuitive and efficient manner.

[0025] Step S110: Read the CP data of the chip, wherein the CP data includes wafer batch information, chip coordinate information, chip Bin Code and chip-level electrical characteristic test results; The process of reading the chip's CP data includes reading the CP data, selecting the chip coordinate information and the coordinate origin position, so that the coordinate system of the test model is consistent with the coordinate system of the CP data. The chip coordinate information includes chip coordinate X information and chip coordinate Y information.

[0026] Specifically, CP data refers to the data set obtained after performing electrical performance tests on each chip on a wafer during the wafer testing phase. The process of reading CP data may include first extracting the CP data of the current wafer from the CP testing system's database or data file, then parsing the CP data file to extract wafer batch information, such as wafer ID and batch number, as well as chip coordinate information, such as the X and Y coordinates of each chip on the wafer, the chip Bin Code (which can represent the classification code of the chip test results, such as good products or different types of defective products), and chip-level electrical characteristic test results, such as measured values ​​of voltage, current, and frequency parameters. The parsed CP data is then imported into the inspection system to prepare for subsequent processing. After reading the CP data, coordinate system alignment is required, i.e., selecting the chip coordinate information and the origin position to ensure that the coordinate system of the inspection model is consistent with the coordinate system of the CP data, thus avoiding incorrect mapping of chip positions. Coordinate system alignment can include setting the origin of the coordinate system in the CP data, such as the wafer center, setting the direction of the coordinate axes, such as the positive directions of the X and Y axes, and performing coordinate transformations as needed, such as translation or rotation, so that the coordinate system of the verification model corresponds completely with the coordinate system of the CP data. Chip coordinate information includes chip X coordinates and chip Y coordinates, such as (3,5) representing the 3rd position in the X direction and the 5th position in the Y direction, so that there is a one-to-one correspondence between the coordinate values ​​and the physical position of the chip on the wafer, that is, the position of each chip on the wafer can be uniquely determined by the coordinate information.

[0027] Step S120: In the inspection model, the position of each chip is displayed according to the chip coordinate information, and the Bin Code character is displayed at the corresponding coordinate position according to the chip Bin Code; Specifically, using the inspection model established in steps S100 and S110 and the read CP data, the chip location information and Bin Code information from the CP data are visualized in the inspection model. The process of displaying the chip location and Bin Code in the inspection model can include first obtaining the location of each chip in the inspection model based on the chip coordinate information in the CP data, such as X and Y coordinates; then drawing the chip's outline or boundary at the obtained location to indicate its presence; and finally, displaying the corresponding Bin Code character at the chip location based on the Bin Code value corresponding to each chip, for example, using "1" to represent a good product and "0" to represent a defective product. Furthermore, when displaying the Bin Code character, an appropriate font size and position can be selected based on the chip size and display area limitations to ensure that the Bin Code character is clearly visible and does not overlap.

[0028] Step S130: Set the visualization parameters of the inspection model. The visualization parameters include configuring different display colors according to the type of Bin Code and setting the transparency of the inspection model. The configuration of different display colors according to Bin Code type includes allocating the display colors of different Bin Codes through automatic generation or manual adjustment.

[0029] Specifically, to improve visualization, different display methods can be used, such as using different colors to represent different Bin Codes, or using different graphic symbols to replace text characters, thereby improving recognition efficiency. By transforming abstract CP data into an intuitive visual representation, operators can quickly identify the distribution of chips on the wafer and test results. Furthermore, through visualization, operators can directly observe the distribution patterns of chips with different Bin Codes on the wafer, which is beneficial for discovering potential process problems or defect distribution patterns. This provides a visual reference for subsequent comparison with physical wafers, making the comparison process more intuitive and efficient, and ultimately improving work efficiency.

[0030] It's important to note that configuring different display colors according to Bin Code type means assigning different colors to different Bin Code values. This allows operators to visually distinguish different types of chips through color. For example, good chips (Bin Code "1") can be displayed in green, while defective chips (Bin Code "0") of a certain type can be displayed in red. Using color coding allows operators to quickly identify different types of chips without having to carefully read the Bin Code characters on each chip. Furthermore, color configuration can be done automatically or manually. Automatic generation means the system automatically generates a set of highly distinguishable colors based on the number of Bin Code types and assigns these colors to different Bin Codes. Manual adjustment means operators can manually select and assign colors to each Bin Code according to their habits and needs. The specific method can be chosen based on the actual situation and the operator's preferences. Setting the transparency of the inspection model refers to adjusting the transparency of the entire inspection model or some elements so that the content of both the inspection model and the physical wafer image can be seen simultaneously during subsequent overlay comparison. The transparency can be adjusted as needed. For example, when it is necessary to focus on the content of the inspection model, the transparency can be reduced, i.e., the opacity can be increased. When it is necessary to focus on the content of the physical image, the transparency can be increased, making the comparison process clearer and more intuitive.

[0031] Step S140: Obtain a physical image of the wafer using an electron microscope, and adjust the magnification of the electron microscope lens so that the physical image of the wafer has the same size as the inspection model; Specifically, the process of acquiring and resizing a wafer image using an electron microscope can include first placing the wafer to be inspected on the stage of an electron or optical microscope to ensure accurate positioning; then starting the microscope, adjusting the focus and other parameters to acquire a clear image; and finally adjusting the lens magnification to ensure the acquired wafer image matches the size of the inspection model. The adjusted image is then imported into the inspection system for subsequent overlay comparison. Adjusting the electron microscope's lens magnification ensures the wafer image and the inspection model are the same size, achieving accurate overlay comparison. Magnification adjustment can be performed through the electron microscope's control system; for example, the operator can adjust the magnification based on the size of the inspection model until the image perfectly matches the model's dimensions.

[0032] Step S150: Overlap and compare the adjusted physical image of the wafer with the inspection model, and verify the accuracy of chip sorting by comparing the results.

[0033] The method of overlaying and comparing the adjusted wafer image with the inspection model includes, during the inspection process before chip sorting, when a defective chip appearance is identified, clicking the corresponding position in the inspection model on the imaging window to correct the test results of the chip in the CP data, so that the CP data is consistent with the wafer.

[0034] The step of overlaying and comparing the adjusted wafer image with the inspection model includes the following steps during the chip sorting process: after one Bin Code is sorted, the wafer image is completely matched with the inspection model, and it is confirmed one by one whether the position of the Bin Code in the inspection model completely coincides with the chip position of the Bin Code that has been removed from the wafer; if so, the sorting is qualified; if not, the sorting is unqualified.

[0035] The step of overlaying and comparing the adjusted physical wafer image with the inspection model includes stopping the sorting process when an abnormality occurs during chip sorting, such as misalignment, missed pick-up, or accidental pick-up. The location of the abnormality is then determined by overlaying and comparing the inspection model with the physical wafer image.

[0036] The step of comparing the adjusted wafer image with the inspection model includes, after all chip sorting is completed, using the imaging function of the electron microscope to verify whether all remaining chips are defective wafers that do not need to be sorted by completely overlapping the wafer image with the inspection model.

[0037] Specifically, during the pre-sorting inspection process, when an electron microscope reveals a defect in a chip's appearance, such as scratches or contamination, the operator can click on the corresponding location in the inspection model within the imaging window. The system will automatically identify the chip at that location and correct the test results for that chip in the CP data, ensuring consistency between the CP data and the actual wafer. This avoids incorrect sorting due to appearance defects that were not detected during CP testing. During chip sorting, after sorting chips with a specific Bin Code, the operator can perfectly correlate the actual wafer image with the inspection model, verifying that the chip location for that Bin Code in the inspection model completely overlaps with the location of the removed chips on the actual wafer. If the locations perfectly overlap, the sorting operation is accurate and can be considered successful. If there is a misalignment, an error has occurred during the sorting process, requiring further inspection and processing. During chip sorting, if any abnormalities occur such as misalignment, missed pick-up, or accidental pick-up, operators can immediately stop the sorting process. By comparing the inspection model with the actual wafer image, the location of the abnormality can be pinpointed, quickly identifying the problem and improving the efficiency and accuracy of the inspection process. After all chip sorting is complete, operators can use the imaging function of an electron microscope to completely overlay and compare the actual wafer image with the inspection model to verify that all remaining chips are defective wafers that do not need sorting. This ensures that no chips that should be sorted have been missed, improving the completeness and accuracy of the sorting process.

[0038] To provide a detailed explanation of the device for verifying chip sorting accuracy provided by the present invention, the above embodiments have described in detail a method for verifying chip sorting accuracy. Based on the same inventive concept, this application also provides a device for verifying chip sorting accuracy.

[0039] Please see Figure 2 , Figure 2This is a structural block diagram of a device for verifying the accuracy of chip sorting according to an embodiment of the present invention. The device includes a model building module 200, a data reading module 210, a coordinate setting module 220, a model setting module 230, an imaging module 240, and an inspection module 250. The model building module 200 is used to build an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and the chip, and the spacing between the chips. The data reading module 210 is used to read the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results. The coordinate setting module 220 is used to display the position of each chip in the inspection model according to the chip coordinate information, and to display the Bin Code character at the corresponding coordinate position according to the chip Bin Code. The model setting module 230 is used to set the visualization parameters of the inspection model, including parameters based on Bin Code. The code type is configured with different display colors, and the transparency of the inspection model is set; the imaging module 240 is used to acquire a physical image of the wafer through an electron microscope, and adjust the lens magnification of the electron microscope so that the physical image of the wafer and the inspection model have the same size; the inspection module 250 is used to overlap and compare the adjusted physical image of the wafer with the inspection model, and verify the accuracy of chip sorting by comparing the results.

[0040] This invention provides an apparatus for verifying the accuracy of chip sorting. A model building module 200 establishes a verification model proportional to the actual wafer size and chip spacing based on the actual dimensions of the wafer and chips. A data reading module 210 reads the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results. A coordinate setting module 220 displays the position of each chip in the verification model according to the chip coordinate information and displays the Bin Code character at the corresponding coordinate position. A model setting module 230 sets the visualization parameters of the verification model, including configuring different display colors according to Bin Code type and setting the transparency of the verification model. An imaging module 240 acquires an image of the actual wafer using an electron microscope and adjusts the lens magnification of the electron microscope to make the image of the actual wafer the same size as the verification model. An verification module 250 overlays and compares the adjusted image of the actual wafer with the verification model, verifying the accuracy of chip sorting through the comparison results. By establishing an inspection model scaled to the physical wafer, the chip information in the CP data is visualized, creating an intuitive chip distribution view. This allows operators to directly observe the spatial distribution of the CP data before chip sorting. Simultaneously, by acquiring images of the physical wafer using an electron microscope and adjusting them to the same size as the inspection model, the images are overlaid and compared, enabling direct comparison between the CP data and the physical wafer. This allows any inconsistencies to be immediately detected, facilitating timely identification and resolution of anomalies. Furthermore, in the preparation stage before chip sorting, the consistency between CP data and the physical wafer can be updated efficiently and cost-effectively, improving efficiency, avoiding errors, and reducing costs. During chip sorting, anomalies can be detected promptly, reducing the time and effort required for anomaly localization and improving efficiency. Thus, the technical effects of improved efficiency, reduced costs, and reduced errors are achieved both before and during chip sorting.

[0041] To provide a detailed explanation of the electronic device for verifying chip sorting accuracy provided by the present invention, the above embodiments have described in detail a method for verifying chip sorting accuracy. Based on the same inventive concept, this application also provides an electronic device for verifying chip sorting accuracy.

[0042] Please see Figure 3 , Figure 3This is a structural diagram of an electronic device for verifying the accuracy of chip sorting, provided in an embodiment of the present invention. This invention provides an electronic device for verifying the accuracy of chip sorting, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor 320. When the processor 320 executes the program, it performs the following steps: establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and chips, and the spacing between chips; reading the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying Bin Code characters at the corresponding coordinate positions according to the chip Bin Code; setting visualization parameters for the inspection model, including configuring different display colors according to Bin Code type and setting the transparency of the inspection model; acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope to make the image of the actual wafer the same size as the inspection model; and overlaying and comparing the adjusted image of the actual wafer with the inspection model to verify the accuracy of chip sorting through the comparison results.

[0043] This invention provides an electronic device for verifying the accuracy of chip sorting. It establishes a verification model proportional to the actual wafer size based on the actual dimensions of the wafer and chips, as well as the spacing between chips. The device reads the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results. Then, it displays the position of each chip in the verification model according to the chip coordinate information, and displays the Bin Code character at the corresponding coordinate position. The device sets visualization parameters for the verification model, including configuring different display colors according to Bin Code type and setting the transparency of the verification model. It acquires an image of the actual wafer using an electron microscope, adjusting the microscope lens magnification to ensure the image of the actual wafer is the same size as the verification model. The adjusted image of the actual wafer is then overlaid and compared with the verification model to verify the accuracy of chip sorting. By establishing an inspection model scaled to the physical wafer, the chip information in the CP data is visualized, creating an intuitive chip distribution view. This allows operators to directly observe the spatial distribution of the CP data before chip sorting. Simultaneously, by acquiring images of the physical wafer using an electron microscope and adjusting them to the same size as the inspection model, the images are overlaid and compared, enabling direct comparison between the CP data and the physical wafer. This allows any inconsistencies to be immediately detected, facilitating timely identification and resolution of anomalies. Furthermore, in the preparation stage before chip sorting, the consistency between CP data and the physical wafer can be updated efficiently and cost-effectively, improving efficiency, avoiding errors, and reducing costs. During chip sorting, anomalies can be detected promptly, reducing the time and effort required for anomaly localization and improving efficiency. Thus, the technical effects of improved efficiency, reduced costs, and reduced errors are achieved both before and during chip sorting.

[0044] To provide a detailed explanation of the computer-readable storage medium for verifying chip sorting accuracy provided by the present invention, the above embodiments have described in detail a method for verifying chip sorting accuracy. Based on the same inventive concept, this application also provides a computer-readable storage medium for verifying chip sorting accuracy.

[0045] Please see Figure 4 , Figure 4This is a structural diagram of a computer-readable storage medium for verifying the accuracy of chip sorting, provided in an embodiment of the present invention. The embodiment of the present invention provides a computer-readable storage medium for verifying the accuracy of chip sorting, which stores a computer program 41. When executed by a processor 320, this program performs the following steps: establishing an inspection model proportional to the actual wafer based on the actual dimensions of the wafer and the chip, and the spacing between the chips; reading the chip's CP data, the CP data including wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; displaying the position of each chip in the inspection model according to the chip coordinate information, and displaying Bin Code characters at the corresponding coordinate positions according to the chip Bin Code; setting the visualization parameters of the inspection model, the visualization parameters including configuring different display colors according to Bin Code type, and setting the transparency of the inspection model; acquiring an image of the actual wafer using an electron microscope, adjusting the lens magnification of the electron microscope so that the image of the actual wafer has the same size as the inspection model; and overlaying and comparing the adjusted image of the actual wafer with the inspection model, verifying the accuracy of chip sorting through the comparison results.

[0046] This invention provides a computer-readable storage medium for verifying the accuracy of chip sorting. It establishes a verification model proportional to the actual wafer size based on the actual dimensions of the wafer and chips, as well as the spacing between chips. The CP data of the chips is read, including wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results. Then, the position of each chip is displayed in the verification model according to the chip coordinate information, and the Bin Code character is displayed at the corresponding coordinate position. Visualization parameters of the verification model are set, including configuring different display colors according to Bin Code type and setting the transparency of the verification model. An image of the actual wafer is acquired using an electron microscope, and the lens magnification of the electron microscope is adjusted so that the image of the actual wafer is the same size as the verification model. The adjusted image of the actual wafer is overlaid and compared with the verification model, and the accuracy of chip sorting is verified by the comparison results. By establishing an inspection model scaled to the physical wafer, the chip information in the CP data is visualized, creating an intuitive chip distribution view. This allows operators to directly observe the spatial distribution of the CP data before chip sorting. Simultaneously, by acquiring images of the physical wafer using an electron microscope and adjusting them to the same size as the inspection model, the images are overlaid and compared, enabling direct comparison between the CP data and the physical wafer. This allows any inconsistencies to be immediately detected, facilitating timely identification and resolution of anomalies. Furthermore, in the preparation stage before chip sorting, the consistency between CP data and the physical wafer can be updated efficiently and cost-effectively, improving efficiency, avoiding errors, and reducing costs. During chip sorting, anomalies can be detected promptly, reducing the time and effort required for anomaly localization and improving efficiency. Thus, the technical effects of improved efficiency, reduced costs, and reduced errors are achieved both before and during chip sorting.

[0047] In some embodiments, the apparatus provided in this disclosure may also have functions or included modules that can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here. The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor 320 to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for verifying the accuracy of chip sorting, characterized in that, The method includes Based on the actual dimensions of the wafers and chips, and the spacing between the chips, an inspection model proportional to the actual wafer is established. Read the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; In the inspection model, the position of each chip is displayed according to the chip coordinate information, and the Bin Code character is displayed at the corresponding coordinate position according to the chip Bin Code; The visualization parameters of the inspection model are set, including configuring different display colors according to the type of Bin Code and setting the transparency of the inspection model; A physical image of the wafer is acquired using an electron microscope, and the magnification of the electron microscope lens is adjusted so that the physical image of the wafer has the same size as the inspection model; The adjusted physical image of the wafer is overlaid and compared with the inspection model, and the accuracy of chip sorting is verified by the comparison results.

2. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The step of overlaying and comparing the adjusted wafer image with the inspection model includes, during the inspection process before chip sorting, when a defective chip appearance is identified, clicking the corresponding position in the inspection model on the imaging window to correct the test results of the chip in the CP data, so that the CP data is consistent with the wafer.

3. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The step of overlaying and comparing the adjusted wafer image with the inspection model includes the following steps during the chip sorting process: after one Bin Code is sorted, the wafer image is completely matched with the inspection model, and it is confirmed one by one whether the position of the Bin Code in the inspection model completely coincides with the chip position of the Bin Code that has been removed from the wafer; if so, the sorting is qualified; if not, the sorting is unqualified.

4. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The step of overlaying and comparing the adjusted physical wafer image with the inspection model includes stopping the sorting process when an abnormality occurs during chip sorting, such as misalignment, missed pick-up, or accidental pick-up. The location of the abnormality is then determined by overlaying and comparing the inspection model with the physical wafer image.

5. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The step of comparing the adjusted wafer image with the inspection model includes, after all chip sorting is completed, using the imaging function of the electron microscope to verify whether all remaining chips are defective wafers that do not need to be sorted by completely overlapping the wafer image with the inspection model.

6. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The process of reading the chip's CP data includes reading the CP data, selecting the chip coordinate information and the coordinate origin position, so that the coordinate system of the test model is consistent with the coordinate system of the CP data. The chip coordinate information includes chip coordinate X information and chip coordinate Y information.

7. The method for verifying the accuracy of chip sorting according to claim 1, characterized in that, The configuration of different display colors according to Bin Code type includes allocating the display colors of different Bin Codes through automatic generation or manual adjustment.

8. A device for verifying the accuracy of chip sorting, characterized in that, The device includes The model building module is used to build a verification model that is proportional to the actual wafer based on the actual size of the wafer and chip, as well as the spacing between the chips. The data reading module is used to read the CP data of the chip, which includes wafer batch information, chip coordinate information, chip Bin Code and chip-level electrical characteristic test results; The coordinate setting module is used to display the position of each chip in the inspection model according to the chip coordinate information, and to display the Bin Code character at the corresponding coordinate position according to the chip Bin Code; The model settings module is used to set the visualization parameters of the testing model. The visualization parameters include configuring different display colors according to the BinCode type and setting the transparency of the testing model. An imaging module is used to acquire physical images of the wafer using an electron microscope, and to adjust the magnification of the electron microscope lens so that the physical image of the wafer has the same size as the inspection model; The inspection module is used to overlay and compare the adjusted physical image of the wafer with the inspection model, and to verify the accuracy of chip sorting by comparing the results.

9. An electronic device for verifying the accuracy of chip sorting, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it performs the following steps: Based on the actual dimensions of the wafers and chips, and the spacing between the chips, an inspection model proportional to the actual wafer is established. Read the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; In the inspection model, the position of each chip is displayed according to the chip coordinate information, and the Bin Code character is displayed at the corresponding coordinate position according to the chip Bin Code; The visualization parameters of the inspection model are set, including configuring different display colors according to the type of Bin Code and setting the transparency of the inspection model; A physical image of the wafer is acquired using an electron microscope, and the magnification of the electron microscope lens is adjusted so that the physical image of the wafer has the same size as the inspection model; The adjusted physical image of the wafer is overlaid and compared with the inspection model, and the accuracy of chip sorting is verified by the comparison results.

10. A computer-readable storage medium for verifying the accuracy of chip sorting, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it performs the following steps: Based on the actual dimensions of the wafers and chips, and the spacing between the chips, an inspection model proportional to the actual wafer is established. Read the chip's CP data, which includes wafer batch information, chip coordinate information, chip Bin Code, and chip-level electrical characteristic test results; In the inspection model, the position of each chip is displayed according to the chip coordinate information, and the Bin Code character is displayed at the corresponding coordinate position according to the chip Bin Code; The visualization parameters of the inspection model are set, including configuring different display colors according to the type of Bin Code and setting the transparency of the inspection model; A physical image of the wafer is acquired using an electron microscope, and the magnification of the electron microscope lens is adjusted so that the physical image of the wafer has the same size as the inspection model; The adjusted physical image of the wafer is overlaid and compared with the inspection model, and the accuracy of chip sorting is verified by the comparison results.

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