Slave circuit charging over single wire bus

Abstract

Charging from a circuit through a single wire bus including a single wire is described in the present disclosure. Herein, the master circuit is configured to communicate a plurality of bus telegrams with the slave circuit over the single wire bus. Each of the bus telegrams starts in a sequence start (SOS) sequence. The main circuit is configured to signal a start of the SOS sequence by asserting a higher voltage on the single wire bus. Thus, the slave circuit may detect the SOS sequence in each of the bus telegrams and perform certain tasks (e.g., timing synchronization and charging) during the SOS sequence. By indicating the start of the SOS sequence with a higher bus voltage, the slave circuit can collect more power with a miniaturized power collection circuit, so that the slave circuit can drive a high power device, such as a micro-electro-mechanical system (MEMS) switch.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 589,479, filed October 11, 2023, the disclosure of which is hereby incorporated in its entirety by reference. Technical Field

[0003] The technology disclosed herein generally relates to charging a slave circuit via a single-wire communication bus in an electronic device. Background Technology

[0004] Mobile communication devices have become increasingly prevalent in today's society. This widespread use is partly driven by the many features now available on such devices. The increased processing power in these devices means that they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0005] To provide a redefined user experience, existing wireless communication devices (e.g., smartphones) are equipped with various circuits to support diverse applications and achieve various user experiences. Furthermore, wireless communication devices employ various communication buses to enable inter-circuit and intra-circuit communication. For example, a two-wire radio frequency front-end (RFFE) bus allows transceiver circuitry to communicate with power amplifier circuitry, power management circuitry, and / or antenna circuitry; a high-bandwidth memory bus enables time-critical direct access to memory circuitry; and a multi-wire general-purpose input / output (GPIO) bus bridges communication to external peripheral devices.

[0006] However, not all communication requires a multi-wire bus like the RFFE bus, memory bus, and GPIO bus. In some cases, a single-wire serial bus may be sufficient or even desirable for low-speed and / or low-bandwidth communication between certain types of circuits, such as antenna tuners, sensors, and switches. Summary of the Invention

[0007] The aspects disclosed in the detailed description relate to charging a slave circuit via a single-wire bus comprising a single wire. Herein, a master circuit is configured to communicate with the slave circuit via multiple bus telegrams through the single-wire bus. Each of the bus telegrams begins with a Sequence Start (SOS) sequence. The master circuit is configured to signal the start of the SOS sequence by asserting a higher voltage on the single-wire bus. Therefore, the slave circuit can detect the SOS sequence in each of the bus telegrams and perform certain tasks (e.g., timing synchronization and charging) during the SOS sequence. By indicating the start of the SOS sequence with a higher bus voltage, the slave circuit can harvest more power using miniaturized power acquisition circuitry, thereby enabling the slave circuit to drive high-power devices such as microelectromechanical systems (MEMS) switches.

[0008] In one aspect, a single-wire bus device is provided. The single-wire bus device includes a master circuit. The master circuit is coupled to a single-wire bus consisting of a single wire to transmit multiple bus telegrams, each bus telegram beginning with an SOS sequence and ending with a pause period. The master circuit is configured to assert a bus voltage on the single-wire bus at a high voltage level during the pause period in any of the multiple bus telegrams. The master circuit is also configured to increase the bus voltage above the high voltage level and then decrease the bus voltage below the high voltage level, thereby indicating an SOS sequence in the next consecutive bus telegram among the multiple bus telegrams. The single-wire bus device also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits is configured to detect an SOS sequence in each of the multiple bus telegrams in response to detecting a change in the bus voltage.

[0009] On the other hand, a wireless device is provided. The wireless device includes a single-wire bus device. The single-wire bus device includes a master circuit. The master circuit is coupled to a single-wire bus consisting of a single wire to transmit multiple bus messages, each bus message beginning with an SOS sequence and ending with a pause period. The master circuit is configured to assert a bus voltage on the single-wire bus at a high voltage level during the pause period in any of the multiple bus messages. The master circuit is also configured to increase the bus voltage above the high voltage level and then decrease the bus voltage below the high voltage level, thereby indicating an SOS sequence in the next bus message of the multiple bus messages. The single-wire bus device also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits is configured to detect an SOS sequence in each of the multiple bus messages in response to a detected change in the bus voltage.

[0010] In another aspect, a method is provided for charging any one of a plurality of slave circuits via a single-wire bus. The method includes asserting a bus voltage on the single-wire bus at a high voltage level during a pause period in any of the plurality of bus telegrams, each bus telegram beginning with an SOS sequence and ending with the pause period. The method further includes increasing the bus voltage above the high voltage level and then decreasing the bus voltage below the high voltage level to indicate an SOS sequence in the next consecutive bus telegram of the plurality of bus telegrams. The method further includes detecting an SOS sequence in each of the plurality of bus telegrams in response to detecting a change in the bus voltage.

[0011] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and recognize its additional aspects. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0013] Figure 1A This is a schematic diagram of an exemplary conventional single-wire bus device in which the master circuit is configured to communicate with the slave circuit via a single-wire bus;

[0014] Figure 1B It provides access through Figure 1A A schematic diagram illustrating an exemplary single-wire bus transmitting one or more bus telegrams from the master circuit to the slave circuit;

[0015] Figure 1C It provides access through Figure 1AA schematic diagram illustrating an exemplary single-wire bus transmitting one or more bus telegrams from a slave circuit to a master circuit;

[0016] Figure 1D This is a schematic diagram illustrating an exemplary illustration of a bus symbol modulated to represent a voltage PWM value of one (“1”) based on voltage pulse width modulation (PWM);

[0017] Figure 1E This is a schematic diagram illustrating an exemplary illustration of a bus symbol modulated based on voltage PWM to represent a voltage PWM value of zero (“0”);

[0018] Figure 1F It provides Figure 1B and 1C A schematic diagram illustrating an exemplary sequence of the Start of Sequence (SOS) sequence preceding each bus telegram;

[0019] Figure 1G It provides Figure 1A A schematic diagram illustrating an exemplary circuit;

[0020] Figure 2 This is a schematic diagram of an exemplary single-wire bus device, wherein the main circuitry may be configured, according to embodiments of the present disclosure, to indicate the start of an SOS sequence by asserting a higher voltage on the single-wire bus;

[0021] Figure 3 It provides Figure 2 A schematic diagram illustrating an exemplary SOS sequence;

[0022] Figure 4 yes Figure 2 A schematic diagram of an exemplary slave control circuit in a slave circuit, the slave control circuit being configured to detect an SOS sequence by detecting a higher voltage asserted on a single-wire bus;

[0023] Figure 5 This is a schematic diagram of an exemplary communication device, in which the following can be provided Figure 2 Single-wire bus devices; and

[0024] Figure 6 It is used to pass Figure 2 A flowchart illustrating an exemplary process of charging multiple slave circuits via a single-wire bus in a single-wire bus device. Detailed Implementation

[0025] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0026] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly located on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on top of another element" or "extending directly over another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0028] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formal sense.

[0031] The aspects disclosed in the detailed description relate to charging a slave circuit via a single-wire bus comprising a single wire. Herein, a master circuit is configured to communicate with the slave circuit via multiple bus telegrams through the single-wire bus. Each of the bus telegrams begins with a Sequence Start (SOS) sequence. The master circuit is configured to signal the start of the SOS sequence by asserting a higher voltage on the single-wire bus. Therefore, the slave circuit can detect the SOS sequence in each of the bus telegrams and perform certain tasks (e.g., timing synchronization and charging) during the SOS sequence. By indicating the start of the SOS sequence with a higher bus voltage, the slave circuit can harvest more power using miniaturized power acquisition circuitry, thereby enabling the slave circuit to drive high-power devices such as microelectromechanical systems (MEMS) switches.

[0032] From Figure 2 Before discussing the single-wire bus device of this disclosure, first refer to Figure 1A-1G This document provides a brief overview of conventional single-wire bus devices to help understand the basic operation of a conventional single-wire bus and the technical issues addressed in this article.

[0033] In this regard, Figure 1A This is a schematic diagram of an exemplary conventional single-wire bus device 10 in which the master circuit 12 is configured to communicate with a plurality of slave circuits 14(1)-14(M) via a single-wire bus 16 coupled to the master control port 18. Thus, the master circuit 12 and the slave circuits 14(1)-14(M) can communicate with each other only in an alternating manner (e.g., time-division manner).

[0034] The master circuit 12 is configured to always initiate bus telegraph communication on the single-wire bus 16 by transmitting bus telegraphs to one or more slave circuits among the slave circuits 14(1)-14(M). Thus, the conventional single-wire bus device 10 is also referred to as a “master-slave bus architecture”. The slave circuits 14(1)-14(M) can provide a data payload to the master circuit 12 via the single-wire bus 16 in response to receiving a bus telegraph from the master circuit 12. In the following text, the bus telegraph transmitted from the master circuit 12 to the slave circuits 14(1)-14(M) is referred to as a “forward bus telegraph”, and the data payload transmitted from the slave circuits 14(1)-14(M) to the master circuit 12 is referred to as a “reverse bus telegraph”.

[0035] Figure 1B It provides access through Figure 1A This is a schematic illustration of an exemplary diagram illustrating one or more bus telegrams 20, 22 transmitted from the master circuit 12 to any one of the slave circuits 14(1)-14(M) via a single-wire bus 16. Each bus telegram 20, 22 begins with an SOS sequence 24 followed by a bus command sequence 26. In one embodiment, the bus command sequence 26 may include a write command frame 28 and a write data frame 30. The write command frame 28 includes a command field 32 (labeled "CMD"), which is encoded with the binary value "100" to indicate a register write operation. The write data frame 30 includes a write data cycle 34. The write data cycle 34 may include one or more write data symbols T. S It is modulated to carry data to slave circuits 14(1)-14(M) during register write operations. In this respect, bus telegrams 20, 22 can be examples of forward bus telegrams.

[0036] SOS sequence 24 always precedes bus command sequence 26 and is always transmitted from master circuit 12 to slave circuits 14(1)-14(M). Bus message 22, following bus message 20, is separated from bus message 20 by a fast charging cycle 36 and an idle cycle 38, the fast charging cycle starting at time T1 and ending at time T2 (T2>T1), and the idle cycle starting at time T2 and ending at time T3 (T3>T2). In general, the duration between time T1 and T3 is also referred to as the pause cycle (T3 - T1).

[0037] Fast charging cycle 36 is configured to allow each slave circuit in circuits 14(1)-14(M) to draw a higher charging current via a single-wire bus 16 and to harvest power from said higher charging current. In this respect, the single-wire bus 16 is referred to as being in a fast charging state during fast charging cycle 36. Idle cycle 38 may be an inactive cycle in which master circuit 12 and slave circuits 14(1)-14(M) may be inactive to help conserve power. Therefore, the single-wire bus 16 is referred to as being in an idle state during idle cycle 38.

[0038] The bus command sequence includes a slave address field 40, followed by a bus pause period 42 and four subsequent acknowledgment (ACK) symbols 44. The slave address field 40 can be used to address slave circuits 14(1)-14(M). The bus pause period 42 can be used to switch between forward and reverse communication modes. The ACK symbols 44 can be used by up to four slave circuits in slave circuits 14(1)-14(M) to acknowledge the corresponding reception of data carried in the write data cycle 34. When the ACK symbols 44 are transmitted immediately before the fast charge cycle 36, each slave circuit in slave circuits 14(1)-14(M) can determine the start time T1 of the fast charge cycle 36 by counting the four ACKs transmitted in the four ACK symbols 44 starting from the end of the bus pause period 42.

[0039] Each slave circuit in 14(1)-14(M) is uniquely identified by a corresponding unique slave identifier (USID). Thus, when the slave address field 40 contains the USID of any slave circuit 14(1)-14(M), the bus command sequence 26 in bus telegrams 20 and 22 can be a unicast command sequence destined for said slave circuit 14(1)-14(M). When the slave address field 40 contains a group slave identifier (GSID) corresponding to a subset of slave circuits 14(1)-14(M), the bus command sequence 26 in bus telegrams 20 and 22 can also be a multicast command sequence destined for said subset of slave circuits 14(1)-14(M). Furthermore, when the slave address field 40 contains a broadcast slave identifier (BSID), the bus command sequence 26 in bus telegrams 20 and 22 can be a broadcast command sequence destined for all slave circuits 14(1)-14(M).

[0040] Figure 1C It provides access through Figure 1A A schematic diagram illustrating an exemplary single-wire bus 16 transmitting one or more bus telegrams 46, 48 from slave circuits 14(1)-14(M) to master circuit 12. Figure 1B and 1C The common elements between them are shown in the document with common element designations, and will not be described again here.

[0041] Each of the bus telegrams 46 and 48 contains a bus command sequence 26. In an embodiment, the bus command sequence 26 may contain a read command frame 50 and a read data frame 52 separated by a bus pause period 42. The read command frame 50 contains a command field 32 (labeled "CMD"), which is encoded with the binary value "010" to indicate a register read operation. The read data frame 52 contains a read data period 54, which contains one or more read data symbols T. S It is modulated to carry a data payload to master circuit 12 during a register read operation. Master circuit 12 first sends a read command frame 50 to slave circuits 14(1)-14(M) identified by slave address field 40 to initiate a register read operation. Then, master circuit 12 tri-states during bus pause cycle 42 to hand over control of single-wire bus 16 to slave circuits 14(1)-14(M). Subsequently, slave circuits 14(1)-14(M) can begin sending a data payload during read data cycle 54. In this respect, bus telegrams 46, 48 can be examples of both forward and reverse bus telegrams.

[0042] Return to reference Figure 1A The master circuit 12 is configured to suspend bus telegraph communication on the single-wire bus 16 during a pause period (T3 - T1). Therefore, the master circuit 12 and slave circuits 14(1)-14(M) are configured to halt the transmission of bus telegraphs and data payloads from time T1 to T3. In this respect, it can be said that the single-wire bus 16 is in a pause period between time T1 and T3. During the pause period (T3 - T1), the master circuit 12 will change the bus voltage V of the single-wire bus 16. BUS Maintain at a high voltage level V HIGH (V) HIGH > 0 V). Thus, each of the circuits 14(1)-14(M) can draw charging current through the single-wire bus 16, thereby collecting power from the main circuit 12.

[0043] Outside of the pause period (T3 - T1), it can be achieved by using a high voltage level V. HIGH With low voltage level V LOW (V) LOW <V HIGH Switching bus voltage V between ) BUS To modulate the write data symbol T in the write data cycle 34 S and the read data symbol T in read data cycle 54 S ,like Figure 1D and 1E As shown. Figure 1D It provides a bus symbol T that is modulated based on voltage PWM to represent a voltage PWM value of one ("1"). S An exemplary illustration is provided.

[0044] It can be the data symbol T that is written. S and read data symbol T S any of the bus symbols T S Modulation is based on a predefined low voltage interval 56 and a predefined high voltage interval 58 configured according to a predefined ratio. To represent a voltage PWM value "1", the predefined low voltage interval 56 is shorter than the predefined high voltage interval 58. For example, bus symbol T S It may contain sixteen (16) digitally controlled oscillators (DCOs), and the predefined configuration ratio between the predefined low-voltage interval 56 and the predefined high-voltage interval 58 is 25% to 75% (or 1 to 3). In a non-limiting example, the DCOs are derived from the clock running at the main circuit 12. Thus, the predefined low-voltage interval 56 lasts for four (4) DCOs, while the predefined high-voltage interval 58 lasts for twelve (12) DCOs.

[0045] In this regard, in order to modulate the bus symbol T S To indicate the voltage PWM value "1", the bus voltage V BUS First, within a predefined low-voltage interval of 56, at a low voltage level V LOW Assertion (V) BUS = V LOW Then, within a predefined high-voltage interval of 58, at a high voltage level V HIGH Assertion (V) HIGH > V LOW ).

[0046] Figure 1E It provides a voltage PWM symbol T that is modulated to represent a voltage PWM value of zero (“0”). S An exemplary illustration is provided. Figure 1D and 1E The common elements between them are shown in the document with common element designations, and will not be described again here.

[0047] To represent a voltage PWM value of "0", the predefined low voltage interval 56 is longer than the predefined high voltage interval 58. Based on... Figure 1D In the same example, the predefined low voltage interval 56 lasts for 12 DCOs, while the predefined high voltage interval 58 lasts for 4 DCOs. Therefore, in order to modulate the bus symbol T S To indicate a voltage PWM value of "0", the bus voltage V BUS First, within a predefined low voltage interval of 56, at a lower voltage level V LOW Assertion (V) BUS = V LOW Then, within a predefined high-voltage interval of 58, at a high voltage level V HIGH Assertion (V)BUS = V HIGH ).

[0048] Figure 1F It provides Figure 1B and 1C A schematic diagram illustrating an exemplary SOS sequence 24. Figure 1B , 1C The common elements between 1F and 1F are shown in the document with common element designations and will not be described again here.

[0049] SOS sequence 24 is a unique sequence that will never appear with any bit combination in bus command sequence 26. Each slave circuit in circuits 14(1)-14(M) is configured to always monitor SOS sequence 24, which indicates the start of bus telegrams 20, 22 and 46, 48. SOS sequence 24 includes a synchronization interval of 60, during which the bus voltage V BUS Maintain at a high voltage level V HIGH The synchronization interval 60 contains multiple DCO pulses 62, thereby allowing each slave circuit in circuits 14(1)-14(M) to establish a corresponding timing basis (e.g., for reading, acknowledgment, and other functions). Following the synchronization interval 60, there is a pair of PWM symbols 64, 66. In a non-limiting example, according to... Figure 1E Modulate PWM symbol 64 to represent binary "0", and according to Figure 1D Modulate the PWM symbol 66 to represent binary "1".

[0050] As mentioned earlier, during the pause period (T3 - T1), the bus voltage V BUS Maintain at a high voltage level V HIGH In this regard, in order to represent the transition from the pause period (T3 - T1) to the SOS sequence 24 using a signal, the main circuit 12 is configured to transmit the bus voltage V. BUS From high voltage level V HIGH Pull down to low voltage level V LOW And the bus voltage V BUS Maintain at a low voltage level V LOW A period of time (½T) S Therefore, circuits 14(1)-14(M) can respond to the detection of bus voltage V. BUS The drop in the value determines the start of the synchronization interval of 60.

[0051] Figure 1G It provides Figure 1A A schematic diagram illustrating an exemplary illustration of any one of the slave circuits 14(1)-14(M) in a conventional single-wire bus device 10. Figure 1A and 1GThe common elements between them are shown in the document with common element designations, and will not be described again here.

[0052] Each slave circuit in circuits 14(1)-14(M) can be configured to include an input node 68, a slave controller 70, a switch 72, and a power acquisition circuit 74. Specifically, the input node 68 is coupled to a single-wire bus 16, the switch 72 is coupled to the input node 68, and the power acquisition circuit 74 is coupled to the switch 72. The power acquisition circuit 74 can be implemented as a resistor-capacitor (RC) circuit, which includes a resistor 78 (with resistance R) and a holding capacitor 80 (with capacitance C). HOLD ).

[0053] The controller 70 is configured to close switch 72 during a pause cycle (T3 - T1) to couple power acquisition circuit 74 to input node 68. Therefore, each slave circuit in circuits 14(1)-14(M) can draw bus current I. BUS To hold capacitor C HOLD Charged to local voltage V CAP Outside of the pause cycle (T3 - T1), switch 72 is disconnected from controller 70 to decouple power acquisition circuit 74 from input node 68. Therefore, capacitor C is held... HOLD The discharge will power certain operations, such as driving external circuitry 76.

[0054] The quality factor of the power acquisition circuit 74 can be determined by the RC time constant τ (τ = R × C). HOLD By definition, the RC time constant represents the time required to charge the holding capacitor 80 to a certain percentage (e.g., 63.2%) of its full capacity via resistor 78. It can be understood that the shorter the RC time constant τ, the faster the power harvesting circuit 74 can harvest energy. In this regard, it may be desirable to reduce the resistance R and / or capacitance C. HOLD This can be done to shorten the RC time constant τ. However, doing so may present some technical challenges.

[0055] One technical challenge is that a small resistor R may prevent the controller 70 from efficiently sensing the bus voltage V. BUS Pull-down (from high voltage level V) HIGH to low voltage level V LOW Therefore, each of the slave circuits in circuits 14(1)-14(M) may fail to detect the SOS sequence 24. As an example, if the single-wire bus 16 has an inherent bus resistance R... BUS And the main circuit 12 will convert the bus voltage V BUS Pull to the ground (e.g., V) LOW = 0 V) ​​to represent the SOS sequence 24, then the bus resistance R BUSThe resistance R of resistor 78 will form a voltage divider to reduce the local voltage V at input node 68. CAP Voltage division is performed. Therefore, the bus voltage V seen at input node 68 is... BUS It can be determined by the following equation (Equation 1).

[0056] V BUS = V CAP × R BUS / (R BUS + R) (Equation 1)

[0057] When the main circuit 12 converts the bus voltage V BUS Pull to the ground (V) LOW When V = 0 V, controller 70 will only detect the bus voltage V. BUS As shown in equation (Equation 1). It can be understood that due to the bus resistance R... BUS Relatively constant, when the resistance R of resistor 78 decreases, the bus voltage V at input node 68... BUS Will be closer to the local voltage V CAP Instead of ground (0 V), the main circuit 12 must increase the drive strength to further pull down the bus voltage V. BUS The SOS sequence 24 is represented by a signal. The drive strength is increased in the main circuit 12 to increase the bus voltage V. BUS Under the constraint of pulling all the way to ground, a voltage divider will be formed according to equation (Equation 1). Therefore, when the resistance R of resistor 78 becomes too small, the bus voltage V seen at input node 68 will be... BUS It will not be at a valid logic level of zero. Therefore, the bus voltage V cannot be detected from controller 70. BUS The falling edge of the signal causes it to miss the SOS sequence 24.

[0058] Another technical challenge is the smaller capacitance C. HOLD This may reduce the holding capacity of the holding capacitor 80, and thus cause a local voltage V. CAP The rate of decline is faster. In other words, to keep the capacitor at 80%, it must be recharged more frequently.

[0059] Undeniably, reducing the resistance R of resistor 78 and / or maintaining the holding capacitance C of capacitor 80... HOLD This can bring very significant benefits. Besides shortening the charging time of the holding capacitor 80, the power acquisition circuit 74 can be miniaturized by reducing the size of the resistor 78 and / or the holding capacitor 80. Therefore, it is expected that the aforementioned technical problems will be effectively solved, thereby shortening the RC time constant τ of the power acquisition circuit 74.

[0060] In this regard, Figure 2This is a schematic diagram of an exemplary single-wire bus device 82, wherein a master circuit 84 and a plurality of slave circuits 86(1)-86(N) are configured according to embodiments of the present disclosure to effectively address the communication with... Figure 1A The technical problems associated with the conventional single-wire bus device 10. Here, the master circuit 84 is coupled to the slave circuits 86(1)-86(N) via a single-wire bus 88, which is connected to... Figure 1A It is the same as the single-wire bus 16 in the middle.

[0061] Similar to a conventional single-wire bus device 10, the main circuit 84 is configured to always pass through the single-wire bus 88. Figure 1B Bus telegrams 20, 22 and / or Figure 1C Bus telegrams 46 and 48 are transmitted to slave circuits 86(1)-86(N) to initiate bus telegram communication. Master circuit 84 and slave circuits 86(1)-86(N) are also configured to... Figure 1D and 1E The PWM modulation example shown modulates each bus symbol T. S To represent binary "1" and "0". In addition, the master circuit 84 is configured to suspend bus communication during the pause cycle (T3 - T1), wherein each of the slave circuits 86(1)-86(N) can harvest power via a single-wire bus 88.

[0062] In this document, each slave circuit in circuits 86(1)-86(N) contains a... Figure 1G Compared to the power acquisition circuit 74, the miniaturized power acquisition circuit 90 has a smaller footprint. More specifically, the miniaturized power acquisition circuit 90 includes... Figure 1G Resistor 78 is smaller than resistor 92 and... Figure 1G The holding capacitor 80 is smaller than the holding capacitor 94.

[0063] Each slave circuit in the series 86(1)-86(N) also includes a switch 96. Switch 96 is coupled between the miniaturized power acquisition circuit 90 and a corresponding input node of the single-wire bus 88 in the series of input nodes 98(1)-98(N). When switch 96 is closed, each slave circuit in the series 86(1)-86(N) draws a bus current I. BUS To charge the smaller holding capacitor 94 to the local voltage V CAP When switch 96 is open, the smaller holding capacitor 94 will be discharged to power the corresponding operations at the slave circuits 86(1)-86(N). Each slave circuit in slave circuits 86(1)-86(N) also includes a slave control circuit 100. Slave control circuit 100 is configured to detect the SOS sequence 24 and control (open and close) switch 96 accordingly.

[0064] Single-wire bus device 82 can effectively solve the problem of... Figure 1A and 1G The technical problems associated with the conventional single-wire bus device 10. Specifically, in order to enable the detection of the SOS sequence 24 using a small resistor 92, the main circuit 84 is configured to increase the bus voltage V during the pause period (T3 - T1). BUS From high voltage level V HIGH Pull to even higher levels V PULL-UP (V) PULL-UP > V HIGH > V LOW The signal is sent to indicate the start of the SOS sequence 24. In addition, to compensate for the insufficient holding capacity of the smaller holding capacitor 94, each of the slave circuits 86(1)-86(N) is configured to take advantage of every opportunity, including but not limited to, during the SOS sequence 24, to recharge the smaller holding capacitor 94.

[0065] Figure 3 This is a schematic diagram providing an exemplary illustration of how a single-wire bus device 82 can be optimized according to embodiments of the present disclosure to effectively solve technical problems associated with a conventional single-wire bus device 10. It is worth noting that the SOS sequence 24 shown herein is related to... Figure 1F The SOS sequence 24 shown is the same. Therefore, Figure 1F and 3 The common elements between them are shown in the document with common element designations, and will not be described again here.

[0066] like Figure 3 As shown, in order to represent the start time T of SOS sequence 24 with a signal START The main circuit 84 first converts the bus voltage V BUS The high voltage level V asserted during the pause period (T3 - T1) HIGH Increase to or even higher voltage levels V PULL-UP Due to the bus voltage V BUS It is pulled up, not pulled down, therefore the bus voltage V seen at input node 68 is... BUS It can be determined by the following equation (Equation 2).

[0067] V BUS = (V PULL-UP - V CAP ) × R BUS / (R BUS + R) (Equation 2)

[0068] In this respect, when the resistance R of the smaller resistor 92 decreases, the bus voltage V seen at input node 68... BUSThis will increase. Therefore, each slave circuit in circuits 86(1)-86(N) will be able to detect the SOS sequence 24 without error.

[0069] Pull-up bus voltage V BUS Subsequently, the main circuit 84 was also configured to start at time T of the SOS sequence 24. START The bus voltage V will be used in the future. BUS Reduce to low voltage level V LOW By adjusting the bus voltage V BUS Reduce to a lower voltage level V LOW The single-wire bus device 82 can only communicate with devices based on the bus voltage V. BUS The pull-down mechanism is used to detect SOS sequence 24, ensuring backward compatibility with conventional slave circuitry. In a non-limiting example, master circuitry 84 can adjust the bus voltage V for 50% of the bus symbol duration (e.g., the first bus symbol in SOS sequence 24). BUS Maintain at a higher voltage level V PULL-UP and low voltage level V LOW .

[0070] In an embodiment, each of the slave circuits 86(1)-86(N) can be configured to operate in a first mode to detect a higher voltage level V. PULL-UP Alternatively, it can operate in the second mode to detect a low voltage level V. LOW Therefore, each of the slave circuits in circuits 86(1)-86(N) can be operated as a conventional slave circuit as needed.

[0071] As previously Figure 1F As discussed herein, synchronization interval 60 includes DCO pulse 62, and synchronization interval 60 is followed by PWM-modulated PWM symbols 64 and 66 to represent binary "0" and "1" respectively. In this regard, each slave circuit in circuits 86(1)-86(N) is configured according to embodiments of this disclosure to whenever the bus voltage V BUS At high voltage level V HIGH At the appropriate time, switch 96 is closed to recharge the smaller holding capacitor 94.

[0072] Specifically, by convention and / or configuration, each slave circuit in circuits 86(1)-86(N) knows that the synchronization interval 60 contains significantly more pulses than PWM symbols 64, 66. Therefore, each slave circuit in circuits 86(1)-86(N) is configured to keep switch 96 closed for a large portion (e.g., 90%) of the synchronization interval 60, thereby charging the smaller holding capacitor 94. In an embodiment, each slave circuit in circuits 86(1)-86(N) is configured to keep switch 96 closed for more than two consecutive DCO pulses in DCO pulse 62 during the synchronization interval 60. Furthermore, each slave circuit in circuits 86(1)-86(N) may be configured to explicitly know that the synchronization interval 60 will follow a higher voltage level V. PULL-UP Then followed by a low voltage level V LOW In an embodiment, each of the slave circuits 86(1)-86(N) may also be configured to recognize that the duration of the synchronization interval 60 will be a higher voltage level V. PULL-UP The duration is four times (4×).

[0073] from Figure 1D and 1E It is understandable that each PWM modulation symbol will have a bus voltage V. BUS At high voltage level V HIGH For a period of time. In this regard, in addition to the synchronization interval 60, each slave circuit in circuits 86(1)-86(N) is also configured to whenever the bus voltage V BUS Under high voltage V HIGH During PWM symbols 64 and 66, switch 96 is closed at the appropriate time. Given that slave circuits 86(1)-86(N) may not have prior knowledge about whether PWM symbols 64 and 66 are modulated to represent binary “0” or “1”, each slave circuit in 86(1)-86(N) will close switch 96 only for a shorter duration (e.g., the duration of two consecutive pulses). By limiting charging to the duration of two consecutive pulses in either PWM symbol 64 or 66, each slave circuit in 86(1)-86(N) can safely charge the smaller holding capacitor 94 without accidentally discharging it, even if all PWM symbols 64 and 66 are modulated to represent binary “0”.

[0074] In addition to PWM symbols 64 and 66, each slave circuit in circuits 86(1)-86(N) can also be configured to close switch 96 over the duration of two consecutive pulses, in order to Figure 1B Bus telegrams 20, 22 and / or Figure 1CDuring each PWM symbol transmitted during bus telegraphs 46 and 48, the smaller holding capacitor 94 is recharged. By recharging the smaller holding capacitor 94 as frequently and timely as possible, each slave circuit in circuits 86(1)-86(N) can thus reduce the holding capacitance C. HOLD It will not adversely affect the corresponding local operations.

[0075] Return to reference Figure 2 By effectively addressing the technical problems associated with conventional single-wire bus devices 10, each smaller resistor 92 and smaller holding capacitor 94 in circuits 86(1)-86(N) can be made much smaller than resistor 78 and holding capacitor 80. In a non-limiting example, the smaller resistor 92 has a resistance of one ohm R (R = 1 Ω), and the smaller holding capacitor 94 has a holding capacitance of one nanofarad C. HOLD (C) HOLD = 1 nF). Therefore, the miniaturized power acquisition circuit 90 will have a time constant τ of one nanosecond (τ = 1 ns). The essentially shorter time constant τ not only allows for rapid ramping of the corresponding local voltage V from each slave circuit in circuits 86(1)-86(N) CAP Moreover, it allows local voltage V CAP This achieves a power level sufficient to drive high-power components such as microelectromechanical system (MEMS) switches. It is understood that this is achieved by using a smaller resistor 92 with a lower resistance R and / or a smaller holding capacitor 94 with a lower holding capacitance C. HOLD Other values ​​may also be available as needed.

[0076] The main circuit 84 may include a bus driver circuit 102, which operates at a low voltage level V. LOW High voltage level V HIGH and higher voltage level V PULL-UP Between drive bus voltage V BUS In one embodiment, the bus driver circuit 102 may be based on a first power supply voltage V. SU1 At low voltage level V LOW With high voltage level V HIGH Switching between bus voltage V BUS And based on the second power supply voltage V SU2 And the bus voltage V BUS Driven to a higher voltage level V PULL-UP Second power supply voltage V SU2 It can be supplied from an alternative voltage source, or, for example, from a charge pump (CP) using a first supply voltage V. SU1 Export.

[0077] In the embodiment, the slave control circuit 100 in each of the slave circuits 86(1)-86(N) is configured based on the local voltage V CAP Feedback V FB To generate control signal 104 to control switch 96. Figure 4 It provides Figure 2 A schematic diagram illustrating an exemplary illustration of the slave control circuit 100 in each of the slave circuits 86(1)-86(N). Figure 2 and 4 The common elements between them are shown in the document with common element designations, and will not be described again here.

[0078] In one embodiment, the control circuit 100 includes a comparator 106, a first input circuit 108 coupled to the positive input (denoted as "+") of the comparator 106, and a second input circuit 110 coupled to the negative input (denoted as "-") of the comparator 106. The first input circuit 108 is configured to receive feedback V associated with a time constant τ. FB and the first feedback V associated with the first time constant τ1 FB1 The positive input ("+") is provided to comparator 106. In the non-restrictive example, the first time constant τ1 is equal to the symbol duration T. S One-quarter (¼) (τ1 = ¼T) S On the other hand, the second input circuit 110 is configured to receive feedback V associated with the time constant τ. FB And the second feedback V associated with the second time constant τ2 FB2 The negative input ("-") is provided to comparator 106. In the non-restricted example, the second time constant τ2 is equal to the symbol duration T. S Four times (τ2 = 4T) S ).

[0079] In one embodiment, the second input circuit 110 may be implemented by an RC delay circuit 112, which feeds back V. FB 4T latency S The RC delay circuit 112 may include resistors R configured as shown. D Capacitor C D and switch S D The RC delay circuit 112 can delay capacitor C. D Capacitor C may leak during long idle periods. D Charged to voltage V D And maintain voltage V D A power-on reset (POR) initiation phase can also be added to the capacitor C. DFast charging. Notably, during fast charging cycle 36, both the main circuit 84 and the slave circuits 86(1)-86(N) are connected to a low-impedance path with a small resistor 92, thereby providing the slave circuits 86(1)-86(N) with the first supply voltage V. SUP1 An excellent opportunity to conduct sampling.

[0080] Can be provided in communication devices Figure 2 A single-wire bus device 82 is provided to support the above embodiments. In this regard, Figure 5 This is a schematic diagram of an exemplary communication device 200, in which a communication device 200 can be provided. Figure 2 82 is a single-wire bus device.

[0081] Here, communication device 200 can be any type of communication device, such as a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, and similar wireless communication devices supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, and near-field communication. Communication device 200 will typically include a control system 202, a baseband processor 204, a transmitting circuit system 206, a receiving circuit system 208, an antenna switching circuit system 210, multiple antennas 212, and a user interface circuit system 214. In a non-limiting example, as an example, the control system 202 can be a field-programmable gate array (FPGA). In this respect, the control system 202 may at least include a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuit system 208 receives radio frequency signals from one or more base stations via antennas 212 and through the antenna switching circuit system 210. Low-noise amplifiers and filters cooperate to amplify and eliminate broadband interference from the received signals for processing. Then, a down-conversion and digitization circuitry system (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0082] The baseband processor 204 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 204 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0083] For transmission, baseband processor 204 receives digitized data, which may represent voice, data, or control information, from control system 202. The baseband processor encodes the digitized data for transmission. The encoded data is output to transmission circuitry 206, where a digital-to-analog converter (DAC) converts the digitized data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to antenna 212 via antenna switching circuitry 210. Multiple antennas 212, along with replicated transmission circuitry 206 and receiving circuitry 208, can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0084] The single-wire bus device 82 can be located anywhere within the communication device 200. In one example, the single-wire bus device 82 can be located in the transmitting circuit system 206, the receiving circuit system 208, and / or the antenna switching circuit system 210. In another example, the single-wire bus device 82 can also be located in the control system 202 and / or the baseband processor 204.

[0085] In an embodiment, it is possible to charge the slave circuits 86(1)-86(N) in the single-wire bus device 82 according to a process. In this regard, Figure 6 It is used to pass Figure 2 A flowchart of an exemplary process 300 in which a single-wire bus 88 in a single-wire bus device 82 charges multiple slave circuits 86(1)-86(N).

[0086] Here, process 300 includes a high voltage level V during a pause period (T3 - T1) in any of the bus telegraphs 20, 22 and 46, 48 in bus telegraph 20 or 46. HIGH Assert the bus voltage V on the single-wire bus 88 BUS Each bus telegram begins with an SOS sequence 24 and ends with a pause period T3-T1 (step 302). Process 300 also includes adjusting the bus voltage V. BUS Increase to above the high voltage level V HIGH Then the bus voltage V BUS Reduced to below the high voltage level V HIGH This instructs the SOS sequence 24 in the next bus telegram 22 or 48 of the plurality of bus telegrams 20, 22 and 46, 48 (step 304). Process 300 also includes responding to the detection of a bus voltage V. BUS The changes are detected by detecting the SOS sequence 24 in each of the bus telegrams 20, 22 and 46, 48 (step 306).

[0087] Those skilled in the art will recognize improvements and modifications to the embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A single-wire bus device, comprising: The main circuit, coupled to a single-wire bus consisting of a single line, is configured to transmit multiple bus messages, each starting with a Sequence Start (SOS) sequence and ending with a pause period. During the pause period in any of the plurality of bus telegrams, the bus voltage on the single-wire bus is asserted at a high voltage level; as well as The bus voltage is increased to a level higher than the high voltage level, and then the bus voltage is decreased to a level lower than the high voltage level, thereby indicating the SOS sequence in the next bus telegram of the plurality of bus telegrams; as well as Multiple slave circuits, each coupled to the single-wire bus and configured to detect the SOS sequence in each of the multiple bus telegrams in response to detecting a change in the bus voltage.

2. The single-wire bus device of claim 1, wherein the master circuit is further configured to increase the bus voltage to a higher voltage level above the high voltage level during a first bus symbol in the SOS sequence, and then decrease the bus voltage to a lower voltage level below the high voltage level, thereby indicating the start of a synchronization interval in the SOS sequence.

3. The single-wire bus device of claim 2, wherein the main circuit is further configured to maintain the bus voltage at the higher voltage level in the first half of the first bus symbol and at the lower voltage level in the second half of the first bus symbol.

4. The single-wire bus device of claim 2, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams in response to detecting the higher voltage level and / or the lower voltage level of the bus voltage.

5. The single-wire bus device of claim 2, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams only in response to detecting the higher voltage level of the bus voltage.

6. The single-wire bus device of claim 2, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams only in response to detecting the lower voltage level of the bus voltage.

7. The single-wire bus device of claim 2, wherein each of the plurality of slave circuits comprises: An input node, which is coupled to the single-wire bus; A switch, coupled to the input node; Miniaturized power acquisition circuit, comprising: A resistor, which is coupled to the switch; and The capacitor is held in place, its coupling between the resistor and ground; and The control circuit is configured as follows: During the pause period, the switch is closed, thereby drawing current through the single-wire bus to charge the holding capacitor; and The switch is disconnected in response to the detection of the start of the synchronization interval.

8. The single-wire bus device of claim 7, wherein the resistor has a resistance of one ohm and the holding capacitor has a capacitance of one nanofarad.

9. The single-wire bus device according to claim 7, wherein: The synchronization interval comprises a plurality of digitally controlled oscillator (DCO) pulses modulated by the high voltage level; and The control circuit is also configured to close the switch during the synchronization interval for the duration of more than two consecutive DCO pulses among the plurality of DCO pulses modulated at the high voltage level, thereby drawing current through the single-wire bus to recharge the holding capacitor during the synchronization interval.

10. The single-wire bus device according to claim 7, wherein: The SOS sequence also includes multiple pulse width modulation (PWM) symbols following the synchronization interval, and each PWM symbol is modulated to include a corresponding number of digitally controlled oscillator (DCO) pulses modulated at the high voltage level; and The control circuit is also configured to close the switch for the duration of two consecutive DCO pulses in the corresponding number of DCO pulses modulated by the high voltage level in each of the plurality of PWM symbols, thereby drawing current through the single-wire bus to recharge the holding capacitor.

11. A wireless device comprising a single-wire bus device, the single-wire bus device comprising: The main circuit, coupled to a single-wire bus consisting of a single line, is configured to transmit multiple bus messages, each starting with a Sequence Start (SOS) sequence and ending with a pause period. During the pause period in any of the plurality of bus telegrams, the bus voltage on the single-wire bus is asserted at a high voltage level; as well as The bus voltage is increased to a level higher than the high voltage level, and then the bus voltage is decreased to a level lower than the high voltage level, thereby indicating the SOS sequence in the next bus telegram of the plurality of bus telegrams; as well as Multiple slave circuits, each coupled to the single-wire bus and configured to detect the SOS sequence in each of the multiple bus telegrams in response to detecting a change in the bus voltage.

12. The wireless device of claim 11, wherein the main circuitry is further configured to increase the bus voltage to a higher voltage level above the high voltage level during a first bus symbol in the SOS sequence, and then decrease the bus voltage to a lower voltage level below the high voltage level, thereby indicating the start of a synchronization interval in the SOS sequence.

13. The wireless device of claim 12, wherein the main circuit is further configured to maintain the bus voltage at the higher voltage level in the first half of the first bus symbol and at the lower voltage level in the second half of the first bus symbol.

14. The wireless device of claim 12, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams in response to detecting the higher voltage level and / or the lower voltage level of the bus voltage.

15. The wireless device of claim 12, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams only in response to detecting the higher voltage level of the bus voltage.

16. The wireless device of claim 12, wherein one or more of the plurality of slave circuits are further configured to detect the SOS sequence in each of the plurality of bus telegrams only in response to detecting the lower voltage level of the bus voltage.

17. The wireless device of claim 12, wherein each of the plurality of slave circuits comprises: An input node, which is coupled to the single-wire bus; A switch, coupled to the input node; Miniaturized power acquisition circuit, comprising: A resistor, which is coupled to the switch; and The capacitor is held in place, its coupling between the resistor and ground; and The control circuit is configured as follows: During the pause period, the switch is closed, thereby drawing current through the single-wire bus to charge the holding capacitor; and The switch is disconnected in response to the detection of the start of the synchronization interval.

18. The wireless device according to claim 17, wherein: The synchronization interval comprises a plurality of digitally controlled oscillator (DCO) pulses modulated by the high voltage level; and The control circuit is also configured to close the switch during the synchronization interval for the duration of more than two consecutive DCO pulses among the plurality of DCO pulses modulated at the high voltage level, thereby drawing current through the single-wire bus to recharge the holding capacitor during the synchronization interval.

19. The wireless device according to claim 17, wherein: The SOS sequence also includes multiple pulse width modulation (PWM) symbols following the synchronization interval, and each PWM symbol is modulated to include a corresponding number of digitally controlled oscillator (DCO) pulses modulated at the high voltage level; and The control circuit is also configured to close the switch for the duration of two consecutive DCO pulses in the corresponding number of DCO pulses modulated by the high voltage level in each of the plurality of PWM symbols, thereby drawing current through the single-wire bus to recharge the holding capacitor.

20. A method for charging any one of a plurality of slave circuits via a single-wire bus, the method comprising: During the pause period in any of the multiple bus telegrams, the bus voltage on the single-wire bus is asserted at a high voltage level, each bus telegram starting with a sequence start (SOS) sequence and ending with the pause period; The bus voltage is increased to a level higher than the high voltage level, and then the bus voltage is decreased to a level lower than the high voltage level, thereby indicating the SOS sequence in the next bus telegram of the plurality of bus telegrams; as well as The SOS sequence in each of the plurality of bus telegrams is detected in response to the detection of a change in the bus voltage.

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