Semiconductor device

Abstract

A semiconductor device according to the present invention is provided with a semiconductor substrate having an upper surface, the semiconductor substrate having: a main transistor section having a main gate trench section including a main gate conductive section; a sensing transistor portion having a sensing gate trench portion including a sensing gate conductive portion; a gate pad disposed over the upper surface of the semiconductor substrate; a main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion; a sensing gate wiring disposed along the sensing transistor section; and a gate wiring connection section that connects the main gate wiring and the sensing gate wiring, the gate wiring connection section being provided with a resistance section.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Previously, an overcurrent protection device for a transistor in which a gate resistor is connected to the current sensing transistor was known (for example, see Patent Document 1). Additionally, a semiconductor device in which a diode and a resistor wiring are arranged in the gate wiring was known (for example, see Patent Document 2).

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 7-146722 Patent Document 2: Japanese Patent No. 6510310 Summary of the Invention

[0004] Technical issues It is preferable to suppress the oscillation of the gate voltage of the sensing transistor.

[0005] Technical solution In a first aspect of the present invention, a semiconductor device having a semiconductor substrate having an upper surface is provided. In the semiconductor device, the semiconductor substrate may have a main transistor portion having a main gate trench portion including a main gate conductive portion. In the semiconductor device, the semiconductor substrate may have a sensing transistor portion having a sensing gate trench portion including a sensing gate conductive portion. In any of the above semiconductor devices, the semiconductor substrate may have a gate pad disposed above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the semiconductor substrate may have a main gate wiring disposed above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion. In any of the above semiconductor devices, the semiconductor substrate may have a sensing gate wiring disposed along the sensing transistor portion. In any of the above semiconductor devices, the semiconductor substrate may have a gate wiring connection portion connecting the main gate wiring and the sensing gate wiring. In any of the above semiconductor devices, a resistor portion may be provided in the gate wiring connection portion.

[0006] In any of the above-described semiconductor devices, the semiconductor substrate may further have a sensing pad disposed adjacent to the sensing transistor portion. In any of the above-described semiconductor devices, the gate wiring connection portion may be disposed on the side opposite to the sensing pad, with reference to the sensing transistor portion.

[0007] In any of the aforementioned semiconductor devices, the sensing gate trench portion may extend along an extension direction. In any of the aforementioned semiconductor devices, the gate wiring connection portion may be disposed at a position overlapping the sensing transistor portion in a direction perpendicular to the extension direction when viewed from above.

[0008] In any of the above-described semiconductor devices, the resistor may include a first polysilicon layer disposed above the upper surface of the semiconductor substrate.

[0009] In any of the aforementioned semiconductor devices, the main gate wiring may include a second polysilicon layer disposed above the upper surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, the first polysilicon layer may be connected to the second polysilicon layer.

[0010] In any of the above-mentioned semiconductor devices, a metal layer may be disposed above the first polysilicon layer, separated by an insulating film.

[0011] When viewed from above any of the aforementioned semiconductor devices, at least a portion of the first polysilicon layer may not be covered by the metal layer.

[0012] In any of the aforementioned semiconductor devices, the main gate wiring may include a second polysilicon layer disposed above the upper surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, the first polysilicon layer may have a different thickness than the second polysilicon layer.

[0013] In any of the aforementioned semiconductor devices, the first polysilicon layer may have a stacked structure consisting of an upper polysilicon layer and a lower polysilicon layer. In any of the aforementioned semiconductor devices, the thickness of the first polysilicon layer may be greater than the thickness of the second polysilicon layer.

[0014] In any of the above semiconductor devices, a portion of the upper surface of the lower polysilicon layer may be omitted from the upper polysilicon layer.

[0015] When viewed from above, the density of the sensing gate trench portion can be greater than the density of the main gate trench portion.

[0016] In any of the above-described semiconductor devices, a plurality of the main gate trench portions and the sensing gate trench portions may be provided. In any of the above-described semiconductor devices, the spacing between the plurality of sensing gate trench portions may be smaller than the spacing between the plurality of main gate trench portions.

[0017] In any of the aforementioned semiconductor devices, a plurality of the main gate trench portions may be provided. In any of the aforementioned semiconductor devices, the main transistor portion may have a plurality of main dummy trench portions. In any of the aforementioned semiconductor devices, a plurality of the sensing gate trench portions may be provided. In any of the aforementioned semiconductor devices, the sensing transistor portion may have a plurality of sensing dummy trench portions. In any of the aforementioned semiconductor devices, the ratio of the number of sensing gate trench portions to the number of sensing dummy trench portions in the sensing transistor portion may be greater than the ratio of the number of main gate trench portions to the number of main dummy trench portions in the main transistor portion.

[0018] In any of the aforementioned semiconductor devices, the short-circuit current density when the rated voltage is applied can be 5000 A / cm². 2 above.

[0019] In any of the above semiconductor devices, the sensing gate wiring can be configured as a closed loop surrounding the sensing transistor portion.

[0020] In any of the above-described semiconductor devices, a drift region of a first conductivity type may be provided on the semiconductor substrate. In any of the above-described semiconductor devices, a trench bottom region of a second conductivity type may be provided at the bottom of the sensing gate trench.

[0021] In any of the above-mentioned semiconductor devices, a trench bottom region of a second conductivity type may be provided at the bottom of the main gate trench.

[0022] In a second aspect of the present invention, a semiconductor device having a semiconductor substrate having an upper surface is provided. In the semiconductor device described above, the semiconductor substrate may have a drift region of a first conductivity type. In any of the above semiconductor devices, the semiconductor substrate may have a main transistor portion having a main gate trench portion including a main gate conductive portion. In any of the above semiconductor devices, the semiconductor substrate may have a sensing transistor portion having a sensing gate trench portion including a sensing gate conductive portion. In any of the above semiconductor devices, the semiconductor substrate may have a gate pad disposed above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the semiconductor substrate may have a main gate wiring disposed above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion. In any of the above semiconductor devices, the semiconductor substrate may have a gate wiring connection portion connecting the main gate wiring and the sensing gate conductive portion. In any of the above semiconductor devices, a resistor portion may be provided in the gate wiring connection portion. In any of the above semiconductor devices, a trench bottom region of a second conductivity type may be provided at the bottom of the sensing gate trench portion.

[0023] In any of the above-mentioned semiconductor devices, a trench bottom region of a second conductivity type may be provided at the bottom of the main gate trench.

[0024] Each of the above-described semiconductor devices may further include a sensing gate wiring disposed along the sensing transistor portion and connected to the sensing gate conductive portion. In any of the above-described semiconductor devices, the gate wiring connection portion can connect the main gate wiring and the sensing gate wiring.

[0025] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0026] Figure 1 This is a diagram illustrating the equivalent circuit of a semiconductor device 100 according to one embodiment of the present invention.

[0027] Figure 2 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0028] Figure 3A yes Figure 2 An enlarged view of region A in the image.

[0029] Figure 3B yes Figure 2 An enlarged view of region A in the image.

[0030] Figure 3C yes Figure 2 An enlarged view of region A in the image.

[0031] Figure 4 It is shown Figure 3A A diagram of an example of section B-B' in the figure.

[0032] Figure 5A This is a graph showing the simulation results of the gate voltage.

[0033] Figure 5B This is a graph showing the simulation results of the gate voltage.

[0034] Figure 5C This is a graph showing the simulation results of the gate voltage.

[0035] Figure 6 It is shown Figure 3A Figures of other examples of the B-B' section.

[0036] Figure 7 It is shown Figure 3A Figures of other examples of the B-B' section.

[0037] Figure 8It is shown Figure 3A Figures of other examples of the B-B' section.

[0038] Figure 9 This is a diagram showing an example of the configuration of the gate wiring connection portion 50 when viewed from above.

[0039] Figure 10 It is shown Figure 9 A diagram of an example of the D-D' section.

[0040] Figure 11 It is shown Figure 3A A diagram of an example of the C-C' section.

[0041] Figure 12 It is shown Figure 2 A diagram of an example of section A-A' in the figure.

[0042] Figure 13 It is shown Figure 2 The diagram shows other examples of region A in the figure.

[0043] Figure 14 It is shown Figure 2 The diagram shows other examples of region A in the figure.

[0044] Figure 15 It is shown Figure 2 Figures of other examples of the A-A' section.

[0045] Figure 16 It is shown Figure 3A Figures of other examples of the B-B' section.

[0046] Symbol Explanation 10. Semiconductor substrate; 12. Emitter region; 14. Base region; 16. Accumulation region; 17. P+ contact region; 18. Drift region; 20. Buffer zone; 21. Upper surface; 22. Collector region; 23. Lower surface; 24. Collector electrode; 29. ​​Main well region; 30. Main dummy trench; 32. Main dummy insulating film; 34. Main dummy conductive part; 37. First insulating film; 38. Interlayer insulating film; 39. Interlayer insulating film; 40. 42. Main gate trench, 44. Main gate insulating film, 48. Main gate conductive portion, 49. Main gate wiring, 40. Second polysilicon layer, 41. Second metal layer, 52. Gate wiring connection, 53. Metal layer, 54. Main emitter electrode, 55. Adjustment portion, 56. Contact hole, 57. Resistor portion, 68. Mesa portion, 69. First polysilicon layer, 60. Lower polysilicon layer, 61. Upper polysilicon layer, 62. Contact hole 65···Low Concentration Region, 66···High Concentration Region, 70···Main Transistor Section, 72···Meta Section, 80···Diode Section, 82···Cathode Region, 90···Edge Termination Structure Section, 100···Semiconductor Device, 111···Temperature Sensing Section, 112···Temperature Sensing Wiring, 114···Sensing Pad, 115···Auxiliary Emitter Pad, 116···Gate Pad, 117···Cathode Pad, 118···Anode Pad, 120···Active Section, 129···Sensing Well region, 130··· Sensing dummy trench, 132··· Sensing dummy insulating film, 134··· Sensing dummy conductive part, 138··· Outer peripheral end, 139··· First end edge, 140··· Sensing gate trench, 142··· Sensing gate insulating film, 144··· Sensing gate conductive part, 148··· Sensing gate wiring, 148-1··· Third polysilicon layer, 148-2··· Third metal layer, 152··· Sensing emitter electrode, 160··· Mesa section, 170··· Sensing transistor section Detailed Implementation

[0047] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the technical solution of the invention. In this specification, identical parts in the figures are labeled with the same symbols, and descriptions are sometimes omitted. Additionally, for ease of explanation, some components are sometimes not shown.

[0048] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0049] In this specification, a rectangular coordinate system with X, Y, and Z axes is sometimes used to illustrate technical matters. The rectangular coordinate system only determines the relative positions of constituent elements and does not limit specific directions. For example, the Z-axis direction is not limited to representing the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0050] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0051] When the terms "same" or "equal" are used in this specification, it may also include cases with errors caused by manufacturing deviations, etc. Such errors may be, for example, within 10%. Additionally, when the terms "parallel" or "perpendicular" are used in this specification, an error within 5° may be included.

[0052] In this specification, the conductivity type of the doped region is described as P-type or N-type. In this specification, "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to introducing donors or acceptors into the semiconductor substrate, thereby creating a semiconductor exhibiting either an N-type conductivity type or a P-type conductivity type. In this specification, the doping concentration of the N-type region is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0053] In this specification, when referred to as P+ or N+ type, it indicates a doping concentration higher than that of P- or N- type; when referred to as P- or N- type, it indicates a doping concentration lower than that of P- or N- type. Unless otherwise specified, the units used in this specification are SI units.

[0054] Figure 1This is a diagram illustrating the equivalent circuit of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a main transistor section 70 and a sensing transistor section 170. The sensing transistor section 170 has the same structure as the main transistor section 70 and measures the current flowing through the main transistor section 70. The main transistor section 70 and the sensing transistor section 170 can be formed within the same chip. In this example, the main transistor section 70 and the sensing transistor section 170 are IGBTs, but they could also be MOSFETs.

[0055] The collector electrode of the main transistor section 70 and the collector electrode of the sensing transistor section 170 are connected to each other and to a common collector terminal (C). The gate of the main transistor section 70 and the gate of the sensing transistor section 170 are connected to a common gate drive circuit via a gate terminal (G). Parasitic resistance components Rg and Rgg and parasitic inductance components Lg and Lgg are respectively present in the gate wiring of the main transistor section 70 and the sensing transistor section 170.

[0056] The emitter electrode (sometimes referred to as the main emitter electrode) of the main transistor section 70 and the emitter electrode (sometimes referred to as the sensing emitter electrode) of the sensing transistor section 170 are electrically separated inside the semiconductor device 100. The main emitter electrode of the main transistor section 70 is connected to the emitter terminal (E) and is thus supplied with an emitter potential. The sensing emitter electrode of the sensing transistor section 170 is connected to the emitter terminal via a sensing resistor Rs. A voltage Vcc is applied from an external power supply between the collector terminal and the emitter terminal.

[0057] When the semiconductor device 100 is operating, a predetermined current flows through the main transistor section 70, and a current corresponding to the current value of the main transistor section 70 flows through the sensing transistor section 170. The current value flowing through the sensing transistor section 170 is measured based on the voltage drop at the sensing resistor Rs at this time. The current value of the main transistor section 70 is estimated based on the measurement result in the sensing transistor section 170. Thus, overcurrent in the main transistor section 70 can be detected and the device can be stopped. It should be noted that Ls represents inductive components such as wires and wiring.

[0058] The main transistor section 70 has a gate-emitter capacitance Cge, a gate-collector capacitance Cgc, and a collector-emitter capacitance Cce. Similarly, the sensing transistor section 170 also has a gate-emitter capacitance Cge, a gate-collector capacitance Cgc, and a collector-emitter capacitance Cce. Since the main transistor section 70 and the sensing transistor section 170 are connected in parallel, a feedback loop is formed by the path from the gate terminal, the sensing transistor section 170, the emitter terminal, the main transistor section 70, and the gate terminal. Therefore, voltage oscillations sometimes occur in this feedback loop. In this specification, this oscillation is sometimes referred to as parallel oscillation.

[0059] The gate-emitter capacitance Cge of the sensing transistor 170 is significantly smaller than that of the main transistor 70. Therefore, if parallel oscillation occurs, the gate signal of the sensing transistor 170 is easily affected, sometimes leading to gate voltage oscillation in the sensing transistor 170. This tendency becomes particularly pronounced if the performance of the semiconductor device 100 is improved. If the gate voltage of the sensing transistor 170 oscillates, malfunctions may occur in either the main transistor 70 or the sensing transistor 170, resulting in a decrease in short-circuit withstand capability. Therefore, it is preferable to suppress parallel oscillation. In embodiments of the present invention, parallel oscillation is suppressed by providing a resistor in the gate wiring of the sensing transistor 170, thereby providing a resistor within the feedback loop.

[0060] Figure 2 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 2 The image shows the positions of the components projected onto the upper surface of the semiconductor substrate 10. Figure 2 In this paper, only a portion of the components of the semiconductor device 100 are shown, and some components are omitted.

[0061] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In this specification, the outer periphery of the semiconductor substrate 10 when viewed from above is designated as the outer periphery end 138. Viewing from above refers to viewing the semiconductor substrate 10 from its upper surface side in a manner parallel to the Z-axis. Furthermore, any one of the outer periphery ends 138 of the semiconductor substrate 10 when viewed from above is designated as the first end edge 139. When viewed from above, the direction parallel to the first end edge 139 is designated as the X-axis direction, and the direction perpendicular to the first end edge 139 is designated as the Y-axis direction.

[0062] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region where a main current flows along the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. The active portion 120 may be a region where a main transistor portion 70 is formed. A main emitter electrode is provided above the active portion 120, but... Figure 2 Omitted in .

[0063] The active section 120 is provided with at least one of a main transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). Figure 2 In this example, the main transistor section 70 and the diode section 80 are arranged alternately along the X-axis. It should be noted that the diode section 80 may also be omitted.

[0064] In this example, the main transistor section 70 and the diode section 80 each have a long side in the Y-axis direction. That is, the length of the main transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The long side direction of the main transistor section 70 and the diode section 80 can be the same as the long side direction of each trench section described later.

[0065] The diode section 80 has an N+ type cathode region in the area that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, sometimes the region where the diode section 80 is extended along the Y-axis to the active well region described later is also included in the diode section 80. A collector region is provided on the lower surface of the extended region.

[0066] Multiple pads are provided above the upper surface of the semiconductor substrate 10. Figure 2 In the example, a sensing pad 114, an auxiliary emitter pad 115, a gate pad 116, a cathode pad 117, and an anode pad 118 are disposed above the upper surface of the semiconductor substrate 10.

[0067] The sensing pad 114 is connected to the sensing transistor section 170. The sensing transistor section 170 has the same structure as the main transistor section 70, but its top-view area (corresponding to the channel area) is smaller than that of the main transistor section 70 (corresponding to the channel area). By detecting the current flowing through the sensing transistor section 170, the current flowing throughout the semiconductor device 100 can be estimated. When routing the output from the sensing transistor section 170 to the main emitter electrode, the routing can be extended from the sensing pad 114.

[0068] The auxiliary emitter pad 115 is connected to the main emitter electrode disposed above the upper surface of the semiconductor substrate 10. In order to set the wiring extending from the sensing pad 114 to the same potential as the main emitter electrode, it can be connected to the main emitter electrode in the auxiliary emitter pad 115 by wire bonding.

[0069] A gate signal is sent from the gate drive circuit to the gate pad 116. The gate pad 116 is connected to the gate of the main transistor section 70 and the sensing transistor section 170 via gate wiring.

[0070] Cathode pad 117 and anode pad 118 are connected to temperature sensing unit 111 via temperature sensing wiring 112. Temperature sensing unit 111 measures the temperature of semiconductor device 100. For example, temperature sensing unit 111 is a diode for temperature measurement. Temperature sensing wiring 112 extends from temperature sensing unit 111 along the upper surface of semiconductor substrate 10 to the region between active portion 120 and outer peripheral end 138, and is connected to cathode pad 117 and anode pad 118. Temperature sensing wiring 112 can be polysilicon. It should be noted that the number and type of pads provided on semiconductor substrate 10 are not limited to... Figure 2 The example shown.

[0071] Each pad is formed of a metal material such as aluminum. Multiple pads can be arranged along a predetermined direction between the active portion 120 and the first end edge 139 on the upper surface of the semiconductor substrate 10. In this example, the multiple pads are arranged along the X-axis direction and configured to be clamped by the active portion 120 and the first end edge 139 in the Y-axis direction. In this example, the multiple pads are positioned above the active main well region 29, which will be described later.

[0072] In the arrangement direction of the multiple pads, the sensing transistor portion 170 can be disposed between any two pads. In this example, the sensing transistor portion 170 is disposed in the X-axis direction between the sensing pad 114 and the auxiliary emitter pad 115.

[0073] As described later, the sensing transistor section 170 has a sensing gate trench section with a trench structure. The sensing gate trench section has a sensing gate conductive section to which a gate voltage is applied. As described later, the main transistor section 70 also has a main gate trench section with a trench structure. The main gate trench section has a main gate conductive section to which a gate voltage is applied.

[0074] The semiconductor substrate 10 has a main gate wiring 48 and a sensing gate wiring 148. The main gate wiring 48 is disposed on the upper surface of the semiconductor substrate 10, surrounding the active portion 120 and at least one of the plurality of pad portions. Furthermore, it is disposed in a manner that traverses the active portion 120. The main gate wiring 48 is connected to the main gate conductive portion of the main transistor portion 70. That is, the main gate wiring 48 extends from the gate pad 116 to the main gate conductive portion.

[0075] The main gate wiring 48 is a wiring that transmits the gate signal to the main gate conductive portion. The main gate wiring 48 can be a wiring through which charging current flows to charge the main gate conductive portion. The main gate wiring 48 can be a gate wiring other than the sensing gate wiring 148 described later. Figure 2 The main gate wiring 48 is represented by a dashed line.

[0076] A sensing gate wiring 148 is disposed above the upper surface of the semiconductor substrate 10 and is arranged along the sensing transistor portion 170. In this example, the sensing gate wiring 148 surrounds the sensing transistor portion 170. The sensing gate wiring 148 is connected to the sensing gate conductive portion of the sensing transistor portion 170. "Arranged along the sensing transistor portion 170" can mean arranged parallel to any side of the sensing transistor portion 170. The distance between the sensing gate wiring 148 and the sensing transistor portion 170 can be smaller than the distance between the sensing transistor portion 170 and the sensing pad 114. For example, if the sensing transistor portion 170 is rectangular, the sensing gate wiring 148 can be arranged parallel to two or more sides of the sensing transistor portion 170, or it can be arranged parallel to three or more sides. In the case where there are multiple gate wirings arranged parallel to any side of the sensing transistor portion 170, the sensing gate wiring 148 can refer to the gate wiring closest to the sensing transistor portion 170.

[0077] The sensing gate wiring 148 is a wiring that transmits a gate signal to the sensing gate conductor. The sensing gate wiring 148 may be a wiring arranged along the outline of the sensing transistor section 170, which is part of the wiring through which charging current flows to charge the sensing gate conductor. The sensing gate wiring 148 may not include wiring through which charging current flows to charge the main gate conductor.

[0078] exist Figure 2 The sensing gate wiring 148 is shown in bold solid lines. In this example, the sensing gate wiring 148 is configured as a closed loop surrounding the sensing transistor portion 170. At least a portion of the main gate wiring 48 and the sensing gate wiring 148 can be a stacked structure of metal and polysilicon. An insulating film can be disposed between the metal wiring and the polysilicon wiring. The metal wiring and the polysilicon wiring can be electrically connected via contact holes disposed in the insulating film. The main gate wiring 48 and the sensing gate wiring 148 are insulated relative to the upper surface of the semiconductor substrate 10 by an interlayer insulating film.

[0079] The semiconductor substrate 10 has a gate wiring connection portion 50 that connects the main gate wiring 48 and the sensing gate wiring 148. In this example, the gate wiring connection portion 50 is disposed between the sensing transistor portion 170 and the auxiliary emitter pad 115. The gate wiring connection portion 50 is a wiring that transmits a gate signal to the sensing gate conductive portion and is a wiring through which a charging current flows to charge the sensing gate conductive portion. That is, the sensing gate wiring 148 is provided Figure 1 The gate terminal (G) in the sensor transistor 170 is connected to the gate of the sensor transistor 170. The gate wiring connection 50 may be a wiring that does not carry charging current for charging the main gate conductive portion.

[0080] The semiconductor substrate 10 has an active main well region 29 formed such that it surrounds the active portion 120 when viewed from above. The active main well region 29 surrounds the main transistor portion 70 and the diode portion 80 when viewed from above. The active main well region 29 is a second conductivity type region extending from the upper surface of the semiconductor substrate 10 into its interior. The active main well region 29 may surround the active portion 120 along the main gate wiring 48. The active main well region 29 is also provided around the pad portion, but... Figure 2 The diagram around the solder pads is omitted.

[0081] An edge termination structure 90 is disposed on the upper surface of the semiconductor substrate 10 between the active well region and the outer peripheral end 138 of the semiconductor substrate 10. The edge termination structure 90 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10, surrounding the active well region. In this example, the edge termination structure 90 is disposed along the outer peripheral end 138 of the semiconductor substrate 10. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include, for example, a protective ring, a field plate, a surface electric field reducing element, and a structure combining these elements.

[0082] Figure 3A yes Figure 2 This is an enlarged view of region A. Region A is the area surrounding the sensing transistor section 170 and the gate wiring connection section 50. In this example, the sensing transistor section 170 is opposite to the main transistor section 70 in the Y-axis direction. As an example, the length of the sensing transistor section 170 in the Y-axis direction is 300 μm or more and 400 μm or less.

[0083] The sensing transistor section 170 has a sensing gate trench section 140 and a sensing dummy trench section 130. In this example, the sensing gate trench section 140 and the sensing dummy trench section 130 extend along the Y-axis direction.

[0084] In this example, the main gate wiring 48 and the sensing gate wiring 148 have a stacked structure of metal and polysilicon. An insulating film may be disposed between the metal wiring and the polysilicon wiring. The metal wiring and the polysilicon wiring can be electrically connected through contact holes disposed in the insulating film. In this specification, the polysilicon of the main gate wiring 48 is designated as a second polysilicon layer 48-1. Furthermore, the polysilicon of the sensing gate wiring 148 is designated as a third polysilicon layer 148-1. Figure 3A In the diagram, the second polysilicon layer 48-1 and the third polysilicon layer 148-1 are marked with shaded areas. However, at least a portion of the main gate wiring 48 and the sensing gate wiring 148 may be a stacked structure, but the entire structure does not need to be a stacked structure.

[0085] The second polysilicon layer 48-1 is disposed along the main transistor section 70, the sensing pad 114, and the auxiliary emitter pad 115 when viewed from above. Additionally, the main gate wiring 48 is disposed to surround the sensing transistor section 170 and the sensing gate wiring 148. An interlayer insulating film (not shown) is formed between the metal of the second polysilicon layer 48-1 and the main gate wiring 48. A contact hole 64 is formed in this interlayer insulating film, through which the metal of the main gate wiring 48 and the second polysilicon layer 48-1 are connected. However, Figure 3A The contact hole 64 shown may actually include multiple through holes.

[0086] The third polysilicon layer 148-1 is configured to form a closed loop surrounding the sensing transistor portion 170 when viewed from above. An interlayer insulating film (not shown) is also formed between the third polysilicon layer 148-1 and the metal of the sensing gate wiring 148. A contact hole 64 is formed in this interlayer insulating film, through which the metal of the sensing gate wiring 148 and the third polysilicon layer 148-1 are connected.

[0087] The third polysilicon layer 148-1 and the sensing gate trench portion 140 overlap when viewed from above, and the third polysilicon layer 148-1 is connected to the sensing gate conductive portion of the sensing gate trench portion 140 in this portion. The third polysilicon layer 148-1 may not be connected to the sensing dummy conductive portion of the sensing dummy trench portion 130. The sensing dummy conductive portion of the sensing dummy trench portion 130 may be connected to the sensing emitter electrode.

[0088] The gate wiring connection portion 50 connects the third polysilicon layer 148-1 to the second polysilicon layer 48-1. The gate signal is transmitted from the main gate wiring 48 to the sensing gate wiring 148 via the gate wiring connection portion 50. A resistor portion 59 is provided in the gate wiring connection portion 50. The resistor portion 59 is a portion in which the resistance per unit length in the direction in which current flows is higher than the resistance per unit length of the main gate wiring 48 or the sensing gate wiring 148 connected to the resistor portion 59. Current flows in the resistor portion 59 along the connection direction (e.g., the X-axis direction) connecting the main gate wiring 48 and the sensing gate wiring 148. The resistance per unit length of the resistor portion 59 in the connection direction is higher than the resistance per unit length of the portion of the main gate wiring 48 connected to the resistor portion 59 in that connection direction, and also higher than the resistance per unit length of the portion of the sensing gate wiring 148 connected to the resistor portion 59 in that connection direction. The resistance value per unit length of the resistor 59 can be more than twice, more than five times, or more than ten times the resistance value per unit length of the main gate wiring 48 or the sensing gate wiring 148. Within the range where the gate wiring connection portion 50 is provided, if the resistance value is higher than when the same wiring as the main gate wiring 48 or the sensing gate wiring 148 is extended as the gate wiring connection portion 50, then the resistor 59 can be provided at the gate wiring connection portion 50. As an example, the resistor 59 is formed of polysilicon. As an example, the portions of the main gate wiring 48 and the sensing gate wiring 148 connected to the resistor 59 are multilayer wirings of polysilicon and metal. Figure 3A In the middle, the polysilicon marking of the resistor section 59 is also shaded.

[0089] Because the gate wiring connection portion 50 has a resistive portion 59, the aforementioned parallel oscillation can be suppressed. Therefore, the oscillation of the gate voltage of the sensing transistor portion 170 can be suppressed. The structure of the gate wiring connection portion 50 will be described later. The third polysilicon layer 148-1 and the second polysilicon layer 48-1 are not connected to any part other than the gate wiring connection portion 50. As an example, the length of the gate wiring connection portion 50 in the Y-axis direction is more than 100 μm and less than 300 μm, and the length in the X-axis direction is more than 100 μm and less than 150 μm.

[0090] In this example, a contact hole 64 is provided on the positive X-axis side of the gate wiring connection portion 50 to connect the main gate wiring 48 to the gate wiring connection portion 50. Additionally, a contact hole 64 is provided on the negative X-axis side of the gate wiring connection portion 50 to connect the sensing gate wiring 148 to the gate wiring connection portion 50. In this example, the contact hole 64 on the negative X-axis side of the gate wiring connection portion 50 is separate from both the contact hole 64 on the positive Y-axis side of the sensing transistor portion 170 and the contact hole 64 on the negative Y-axis side of the sensing transistor portion 170. However, these contact holes 64 could also be configured to continuously surround the sensing transistor portion 170 in a U-shape.

[0091] In this example, the sensing gate trench portion 140 extends along the extension direction (Y-axis direction). The sensing gate wiring 148 in this example is connected to both ends of the sensing gate trench portion 140 in the extension direction. The gate wiring connection portion 50 in this example is positioned to overlap with the sensing transistor portion 170 in a direction perpendicular to the extension direction when viewed from above (X-axis direction). Therefore, the difference in wiring length of the sensing gate wiring 148 from the gate wiring connection portion 50 to the connection point between the gate wiring connection portion 50 and each sensing gate trench portion 140 is reduced. This allows for suppression of gate delay (switching speed deviation) in the sensing gate trench portion 140. The gate wiring connection portion 50 can be positioned in a direction perpendicular to the extension direction, overlapping centrally with the extension direction of the sensing transistor portion 170.

[0092] In this example, the sensing transistor section 170 and the sensing pad 114 are arranged adjacent to each other in the X-axis direction. The gate wiring connection section 50 is provided on the side opposite to the sensing pad 114, with the sensing transistor section 170 as a reference. This arrangement can also suppress gate delay (switching speed deviation) of the sensing gate trench section 140. The sensing pad 114 and the gate wiring connection section 50 can be arranged such that the sensing transistor section 170 is sandwiched between them in a direction perpendicular to the extending direction when viewed from above.

[0093] Figure 3B yes Figure 2 A magnified view of region A in the image. Figure 3B The diagram shows the metal of the main gate wiring 48 (sometimes referred to as the second metal layer 48-2), the metal of the sensing gate wiring 148 (sometimes referred to as the third metal layer 148-2), the main emitter electrode 52, the sensing emitter electrode 152, and the auxiliary emitter pad 115.

[0094] As described above, the second polysilicon layer 48-1 and the second metal layer 48-2 are stacked and connected via a contact hole 64 extending in the direction of current flow. The third polysilicon layer 148-1 and the third metal layer 148-2 are also the same.

[0095] The third metal layer 148-2 is disposed along three sides of the sensing transistor section 170. A sensing emitter electrode 152 is disposed on the other side of the sensing transistor section 170. Therefore, the third metal layer 148-2 does not surround the sensing transistor section 170.

[0096] The sensing emitter electrode 152 extends from above the sensing transistor section 170 in the negative X-axis direction to the sensing pad 114. Therefore, the current flowing through the sensing transistor section 170 is output to the sensing pad 114. The direction in which the sensing emitter electrode 152 extends from the sensing transistor section 170 to the sensing pad 114 can be the same as that of the sensing gate trench section 140 (see reference). Figure 3A The extension direction (Y-axis direction) is perpendicular. In addition, in this example, the sensing emission electrode 152 also extends in the Y-axis direction between the main emission electrode 52 and the third metal layer 148-2, and between the third metal layer 148-2 and the second metal layer 48-2.

[0097] Figure 3C yes Figure 2 A magnified view of region A in the image. Figure 3C In addition to the sensing transistor section 170 and the gate wiring connection section 50, the main well region 29 and the sensing well region 129 are also shown.

[0098] The main sink region 29 surrounds the active part 120. Figure 3C The image shows a portion of the strip surrounding the main well region 29 of the active section 120. The main gate wiring 48, sensing pad 114, and auxiliary emitter pad 115 are arranged overlapping the main well region 29 when viewed from above. The end of the main gate trench portion extending along the Y-axis in the main transistor section 70 may overlap with the main well region 29.

[0099] The sensing well region 129 surrounds the sensing transistor section 170 when viewed from above. The sensing well region 129 is a region of second conductivity type formed from the upper surface of the semiconductor substrate 10 inward. The doping concentrations of the main well region 29 and the sensing well region 129 can be the same or different. By providing the sensing well region 129, holes that wind from the main transistor section 70 to the sensing transistor section 170 can be extracted, and hole accumulation in the sensing transistor section 170 can be suppressed. At least a portion of the sensing well region 129 can be opposite to the main transistor section 70.

[0100] The sensing gate wiring 148 is configured to overlap with the sensing well region 129 when viewed from above. The end of the sensing gate trench portion 140 may overlap with the sensing well region 129. The sensing well region 129 is separate from the main well region 29. In this example, the sensing well region 129 is surrounded by the main well region 29. In addition, the gate wiring connection portion 50 can be provided from a position where it overlaps with the main well region 29 when viewed from above to a position where it overlaps with the sensing well region 129 when viewed from above.

[0101] Figure 4It is shown Figure 3A A diagram illustrating an example of the B-B' cross-section. The B-B' cross-section is the XZ cross-section passing through the emitter region 12, the sense well region 129, and the active main well region 29 of the sense transistor section 170. In the B-B' cross-section, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, a sense emitter electrode 152, a sense gate wiring 148, a main gate wiring 48, and a gate wiring connection portion 50. Figure 4 The configuration of the upper surface side of the semiconductor substrate 10 is shown only.

[0102] The semiconductor substrate 10 has an upper surface 21. An interlayer insulating film 38 is disposed on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass with impurities such as boron or phosphorus, a thermally oxidized film, and other insulating films. Contact holes 54 are provided in the interlayer insulating film 38.

[0103] The sensing emitter electrode 152 is disposed above the interlayer insulating film 38 in the sensing transistor section 170. The sensing emitter electrode 152 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The sensing emitter electrode 152 is formed of a metal material such as aluminum.

[0104] The sensing transistor section 170 has a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is N-type and the base region 14 is P-type.

[0105] The sensing transistor section 170 has a sensing gate trench section 140 and a sensing dummy trench section 130 disposed inwardly from the upper surface 21 of the semiconductor substrate 10. In this example, the sensing gate trench section 140 and the sensing dummy trench section 130 are arranged along the X-axis direction and have a long side in the Y-axis direction. Figure 3A As shown, a plurality of sensing gate trench portions 140 and sensing dummy trench portions 130 are provided.

[0106] The sensing gate trench 140 includes a trench, a sensing gate insulating film 142, and a sensing gate conductive portion 144. The sensing gate insulating film 142 is disposed to cover the inner wall of the trench. The sensing gate insulating film 142 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the trench. The sensing gate conductive portion 144 is disposed inside the trench, further inward than the sensing gate insulating film 142. That is, the sensing gate insulating film 142 insulates the sensing gate conductive portion 144 from the semiconductor substrate 10. The sensing gate conductive portion 144 is formed of a conductive material such as polysilicon.

[0107] The sensing dummy trench portion 130 includes a trench, a sensing dummy insulating film 132, and a sensing dummy conductive portion 134. The structure of the sensing dummy trench portion 130 can be the same as that of the sensing gate trench portion 140. However, the sensing gate conductive portion 144 is connected to the sensing gate wiring 148, but the sensing dummy trench portion 130 may not be connected to the sensing gate wiring 148. The sensing dummy conductive portion 134 can be connected to the sensing emitter electrode 152 in a cross-section different from the B-B' cross-section. In the B-B' cross-section, the sensing gate trench portion 140 and the sensing dummy trench portion 130 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.

[0108] The sensing transistor section 170 has a mesa 160, which is the region between the sensing gate trench section 140 and the sensing dummy trench section 130. In this example, the mesa 160 is disposed between the trench sections in the X-axis direction and extends along the Y-axis direction. An emitter region 12, a base region 14, and an accumulation region 16 are disposed on the mesa 160 from the upper surface 21.

[0109] The sensing transistor section 170 has a first conductivity type emitter region 12 disposed on the upper surface 21. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is grounded to the sensing gate trench section 140 and the sensing dummy trench section 130. The emitter region 12 can be connected to the trench sections on both sides of the mesa section 160. The doping concentration of the emitter region 12 is higher than that of the drift region 18. In this example, the emitter region 12 is N+ type.

[0110] The base region 14 is disposed below the emitter region 12. In this example, the base region 14 is grounded to the emitter region 12. The base region 14 can be connected to the trench portions on both sides of the mesa 160. The sensing gate conductive portion 144 can be made longer than the base region 14 in the depth direction. If a predetermined gate voltage is applied to the sensing gate conductive portion 144, a channel formed by an electron inversion layer is formed on the surface of the interface in the base region 14 that is connected to the sensing gate trench portion 140. As a result, current flows between the main emitter electrode 52 and the collector electrode in the main transistor portion 70.

[0111] Accumulation region 16 is disposed below base region 14. Accumulation region 16 is an N+ type region with a higher doping concentration than drift region 18. In this example, semiconductor substrate 10 is provided with accumulation region 16-1 and accumulation region 16-2, but the number of accumulation regions 16 is not limited to two. The number, doping concentration, etc. of accumulation regions 16 can be the same as those of main transistor section 70. The same applies to other regions.

[0112] The mesa 160 at the far end of the sensing transistor section 170 in the X-axis direction may not have an emitter region 12 and an accumulation region 16. A P+ contact region 17 may also be provided on the surface side of the base region 14 in this mesa 160. The region between the trench portion (sensing gate trench portion 140 in this example) at the far end of the sensing transistor section 170 in the X-axis direction and the sensing well region 129 may also not have an emitter region 12 and an accumulation region 16. In this region, a P+ contact region 17 may be provided on the surface side of the base region 14 adjacent to the sensing well region 129. For example, the P+ contact region 17 is configured to contact the inner periphery of the sensing well region 129 and surround the sensing transistor section 170. The P+ contact region 17 is connected to the sensing emitter electrode 152 via a contact hole 54. This allows for easy extraction of holes flowing into the sensing well region 129.

[0113] In a cross-section different from the B-B' cross-section, a contact region of a second conductivity type can be provided in the sensing transistor section 170. The contact region can be provided between the base region 14 and the upper surface 21. The contact region can be a P+ type region with a higher doping concentration than the base region 14. By providing the contact region in the sensing transistor section 170, holes that have wound into the main transistor section 70 can be extracted via the contact region.

[0114] The main well region 29 and the sensing well region 129 are formed from the upper surface 21 of the semiconductor substrate 10 in the depth direction. In this example, the main well region 29 and the sensing well region 129 are P+ type. The main well region 29 and the sensing well region 129 can be formed to a depth greater than the sensing gate trench portion 140 and the sensing dummy trench portion 130. The sensing well region 129 can be connected to the sensing emitter electrode 152 via the contact hole 54. A base region 14 and a P+ contact region 17 can be formed between the main well region 29 and the sensing well region 129.

[0115] An interlayer insulating film 39 is provided on the upper surface 21 above the main well region 29 and the sensing well region 129. The interlayer insulating film 39 can be a natural oxide film or a film obtained by forming a sensing gate insulating film 142 on the upper surface 21 of the semiconductor substrate 10.

[0116] A second polysilicon layer 48-1 and a third polysilicon layer 148-1 are disposed above the interlayer insulating film 39. A second metal layer 48-2 is disposed above the second polysilicon layer 48-1, separated by the interlayer insulating film 38. The second polysilicon layer 48-1 and the second metal layer 48-2 are connected via contact holes 64 formed in the interlayer insulating film 38. Similarly, a third metal layer 148-2 is disposed above the third polysilicon layer 148-1, separated by the interlayer insulating film 38. The third polysilicon layer 148-1 and the third metal layer 148-2 are connected via contact holes 64 formed in the interlayer insulating film 38.

[0117] A gate wiring connection portion 50 is provided between the main gate wiring 48 and the sensing gate wiring 148. The gate wiring connection portion 50 connects the main gate wiring 48 and the sensing gate wiring 148. The gate wiring connection portion 50 has a resistive portion 59. In this example, the resistive portion 59 includes polysilicon disposed above the upper surface 21 of the semiconductor substrate 10. In this specification, the polysilicon of the resistive portion 59 is designated as a first polysilicon layer 61.

[0118] A first polysilicon layer 61 is formed above the interlayer insulating film 39. The first polysilicon layer 61 is connected to the second polysilicon layer 48-1. Additionally, the first polysilicon layer 61 is connected to the third polysilicon layer 148-1. That is, the first polysilicon layer 61 connects the second polysilicon layer 48-1 and the third polysilicon layer 148-1. In this example, the first polysilicon layer 61 is formed from the end closest to the gate wiring connection portion 50 in the contact hole 64 connecting the second polysilicon layer 48-1 and the second metal layer 48-2 to the end closest to the gate wiring connection portion 50 in the contact hole 64 connecting the third polysilicon layer 148-1 and the third metal layer 148-2.

[0119] The main gate wiring 48 and the sensing gate wiring 148 have a stacked structure, but in this example, the gate wiring connection portion 50 uses the first polysilicon layer 61 to transmit the gate signal. Therefore, its resistance value is higher than that of the main gate wiring 48 and the sensing gate wiring 148. Therefore, the parallel oscillation mentioned above can be suppressed, and the oscillation of the gate voltage of the sensing transistor portion 170 can be suppressed.

[0120] The first polysilicon layer 61 can be formed in the same process as the second polysilicon layer 48-1 and the third polysilicon layer 148-1. Therefore, the first polysilicon layer 61 can be formed without adding any manufacturing steps. The doping concentration of the first polysilicon layer 61 can be the same as that of the second polysilicon layer 48-1 and the third polysilicon layer 148-1. The thickness of the first polysilicon layer 61 can be the same as that of the second polysilicon layer 48-1 and the third polysilicon layer 148-1. As an example, the thickness of the first polysilicon layer 61 is 0.5 μm or more and 1.0 μm or less.

[0121] A first insulating film 37 is disposed above the first polysilicon layer 61, and a metal layer 51 is disposed therethrough the first insulating film 37. Additionally, although in Figure 4 The details are omitted, but a polyimide protective film is disposed above the sensing emission electrode 152, the metal layer 51, the main gate wiring 48, and the sensing gate wiring 148.

[0122] Without the metal layer 51 formed, the polyimide is in contact with the first insulating film 37 above the first polysilicon layer 61. In this state, if the polyimide is charged, a charge is induced on the upper surface of the first polysilicon layer 61 through the first insulating film 37, causing a change in the resistance value of the first polysilicon layer 61. As will be described later, since the resistance value of the resistive portion 59 affects the characteristics of the semiconductor device 100, it is preferable to set it to a predetermined value. By providing the metal layer 51, the resistance value of the resistive portion 59 can be stabilized. Furthermore, atomic diffusion from the polyimide can be prevented.

[0123] The metal layer 51 can cover more than 50%, more than 80%, or even 100% of the area of ​​the first polysilicon layer 61. However, when viewed from above, at least a portion of the first polysilicon layer 61 may not be covered by the metal layer 51. This could be more than 30%, more than 50%, or more than 80% of the area of ​​the first polysilicon layer 61 that is not covered by the metal layer 51.

[0124] In this example, the metal layer 51 is insulated from the first polysilicon layer 61 in the gate wiring connection portion 50 by the first insulating film 37. In this specification, when an insulating film clamping region exists where the first insulating film 37 is provided between the metal layer 51 and the first polysilicon layer 61, the configuration is such that even if the metal layer 51 and the first polysilicon layer 61 are connected in other regions, the metal layer 51 and the first polysilicon layer 61 are still insulated in the insulating film clamping region. The region where the first insulating film 37 is provided between the metal layer 51 and the first polysilicon layer 61, and where no contact holes are provided in the first insulating film 37, is the insulating film clamping region. A region where the contact holes provided in the first insulating film 37 extend along the Y-axis direction may not be considered an insulating film clamping region. The insulating film clamping region may also refer to a portion of the metal layer 51 where gate current does not flow and it does not function as a wiring.

[0125] In other examples, a contact hole may be formed in the first insulating film 37, connecting the metal layer 51 and the first polysilicon layer 61. In this case, an insulating film clamping region insulating the metal layer 51 and the first polysilicon layer 61 may also be provided in the X-axis direction, extending over a range of at least 50% of the length of the gate wiring connection portion 50. In this case, the insulating film clamping region may extend from the end of the contact hole in the first insulating film 37 closest to the second metal layer 48-2 to the end of the metal layer 51 closest to the second metal layer 48-2.

[0126] Metal layer 51 can be connected to either the main gate wiring 48 or the sensing gate wiring 148. In this example, metal layer 51 is connected to the third metal layer 148-2 of the sensing gate wiring 148. Metal layer 51 can be a portion of the second metal layer 48-2 or the third metal layer 148-2 extending above the gate wiring connection portion 50. However, metal layer 51 may also not be connected to either the main gate wiring 48 or the sensing gate wiring 148. Figure 4 In this example, metal layer 51 is configured to extend from the third metal layer 148-2 along the direction of the second metal layer 48-2. Metal layer 51 may be electrically floated without being connected to either the second metal layer 48-2 or the third metal layer 148-2.

[0127] Figure 5A , 5B Figure 5C is a graph showing the simulation results of the gate voltage. Figure 5A , 5B In Figure 5C, the changes in the gate voltages of the main transistor section 70 and the sensing transistor section 170 from the time the semiconductor device 100 is turned on until it is turned off are simulated. The horizontal axis of each figure represents time, and the vertical axis represents voltage.

[0128] exist Figure 5A The simulation results show that the resistance value of the gate wiring connection 50 is 0.3Ω. In this example, it is assumed that the gate wiring connection 50 does not have a resistor 59 and uses the main gate wiring 48 or the sensing gate wiring 148 as the gate wiring connection 50. In this case, the oscillation of the gate voltage of the sensing transistor 170 was confirmed after a certain period of time from turning on the semiconductor device 100.

[0129] exist Figure 5B The simulation results show a resistance value of 5.0Ω for the gate wiring connection portion 50. This example assumes the gate wiring connection portion 50 has a resistive portion 59. In this case, the oscillation of the gate voltage of the sensing transistor portion 170 is also confirmed. However, the amplitude of the gate voltage is... Figure 5A The situation is smaller. Additionally, the gate voltage oscillates for a shorter period than... Figure 5A The situation is short. This is believed to be due to the gate wiring connection portion 50 having a resistive portion 59.

[0130] exist Figure 5C The simulation results are shown with a resistance value of 10.0Ω for the gate wiring connection portion 50. This example assumes a further increase in the resistance value of the gate wiring connection portion 50. In this case, no gate voltage oscillation was observed. That is, it was confirmed that increasing the resistance value of the gate wiring connection portion 50 suppresses gate voltage oscillation.

[0131] However, if the resistance value of the gate wiring connection portion 50 is too large, the gate signal of the sensing transistor portion 170 will be delayed compared to the gate signal of the main transistor portion 70. In particular, if the gate signal of the sensing transistor portion 170 is delayed during turn-off, current will concentrate in the sensing transistor portion 170, potentially damaging it. Therefore, it is preferable to adjust the resistance value of the gate wiring connection portion 50 to an appropriate value.

[0132] Figure 6 It is shown Figure 3A Figures of other examples of the B-B' cross-section. In this example, the first polysilicon layer 61 and... Figure 4 The thickness of the first polysilicon layer 61 shown is different from that of the previous layer. Other components are similar. Figure 4 The structures shown are identical, therefore explanations are omitted.

[0133] In this example, the first polysilicon layer 61 has a different thickness than the second polysilicon layer 48-1. The first polysilicon layer 61 in this example has a stacked structure of an upper polysilicon layer 63 and a lower polysilicon layer 62. The thickness t1 of the first polysilicon layer 61 in this example is greater than the thickness t2 of the second polysilicon layer 48-1. By adjusting the thickness t1 of the first polysilicon layer 61, the resistance value of the gate wiring connection portion 50 can be adjusted. The thickness t1 can be more than twice the thickness t2. The thickness of the polysilicon layer can use either an average value or a maximum value.

[0134] However, the thickness t1 can also be smaller than the thickness t2. In this case, the first polysilicon layer 61 may not have a stacked structure such as an upper polysilicon layer 63 and a lower polysilicon layer 62. For example, by etching the first polysilicon layer 61, the thickness t1 can be reduced. The thickness t1 can be less than twice the thickness t2.

[0135] In this example, the upper polysilicon layer 63 covers the entire lower polysilicon layer 62. The upper polysilicon layer 63 can be connected to the temperature sensing wiring 112 described above (see reference). Figure 2 The polysilicon layer 63 and the lower polysilicon layer 62 are formed in the same process. The lower polysilicon layer 62 can be formed in the same process as the second polysilicon layer 48-1. Thus, the upper polysilicon layer 63 and the lower polysilicon layer 62 can be formed without adding manufacturing steps.

[0136] The thickness of the upper polysilicon layer 63 can be equal to the thickness of the temperature sensing wiring 112, and the doping concentration of the upper polysilicon layer 63 can also be equal to the doping concentration of the temperature sensing wiring 112. The thickness of the lower polysilicon layer 62 can be equal to the thickness of the second polysilicon layer 48-1, and the doping concentration of the lower polysilicon layer 62 can also be equal to the doping concentration of the second polysilicon layer 48-1. The thicknesses of the upper polysilicon layer 63 and the lower polysilicon layer 62 can be different, and their doping concentrations can also be different. Figure 6 The examples shown can be combined with, except for Figure 7 Any combination of variations other than the shown variations.

[0137] Figure 7 It is shown Figure 3A Figures for other examples of the B-B' cross-section. The first polysilicon layer 61 in this example is also... Figure 6 It also has a stacked structure with an upper polysilicon layer 63 and a lower polysilicon layer 62. However, in this example, the upper polysilicon layer 63 is not disposed on a portion of the upper surface of the lower polysilicon layer 62. In this example, the upper polysilicon layer 63 can be formed by partially etching the upper polysilicon layer 63. This etching can be performed in the same process as etching the temperature sensing wiring 112. With this configuration, the resistance value of the gate wiring connection portion 50 can also be adjusted. The upper polysilicon layer 63 can be disposed in a range of 20% to 40% of the upper surface of the lower polysilicon layer 62, or in a range of 40% to 60%, or in a range of 60% to 80%. Figure 7 The examples shown can be combined with, except for Figure 6 Any combination of variations other than the shown variations.

[0138] Figure 8 It is shown Figure 3A Figures of other examples of the B-B' cross-section. In this example, the first polysilicon layer 61 forms regions with different doping concentrations. Due to other configurations and Figure 4 The structures shown are identical, therefore explanations are omitted.

[0139] In this example, the first polysilicon layer 61 includes a high-concentration region 66 with a predetermined dopant concentration and a low-concentration region 65 with a lower dopant concentration than the high-concentration region 66. The high-concentration region 66 can be implanted with a dopant of a first conductivity type. The low-concentration region 65 can be the remaining area without dopant implantation. Even with this configuration, the resistance value of the gate wiring connection portion 50 can be adjusted. Figure 8 The example shown can be combined with any other variation.

[0140] Figure 9 This is a top view illustrating an example of the configuration of the gate wiring connection portion 50. Figure 9 The diagram shows the positions of the gate wiring connection portion 50, the second polysilicon layer 48-1, the third polysilicon layer 148-1, and the sensing transistor portion 170 in a top view.

[0141] The gate wiring connection portion 50 in this example also has a first polysilicon layer 61 and a metal layer 51. However, the gate wiring connection portion 50 in this example has a corrugated structure that folds back multiple times from the connection point with the second polysilicon layer 48-1 to the connection point with the third polysilicon layer 148-1. Even with this configuration, the resistance value of the gate wiring connection portion 50 can be adjusted.

[0142] Figure 10 It is shown Figure 9 A diagram illustrating an example of a D-D' cross-section. In the D-D' cross-section, the gate wiring connection portion 50 has a first polysilicon layer 61 and a metal layer 51. In this example, the metal layer 51 is connected to the first polysilicon layer 61 via a contact hole provided in the first insulating film 37. The metal layer 51 corresponds to the peak or valley portion of the ripple, and the first polysilicon layer 61 is connected to the first polysilicon layer 61 of other cross-sections via the metal layer 51.

[0143] In the gate wiring connection portion 50, the area above the first insulating film 37 is designated as the adjustment portion 53. One of the two metal layers 51 in the D-D' cross section can extend into the adjustment portion 53 and connect to the other metal layer 51. In this case, the resistance value of the gate wiring connection portion 50 in the D-D' cross section becomes lower, and the resistance value of the entire gate wiring connection portion 50 also becomes lower. Alternatively, a portion of the metal layer 51 can be formed from polysilicon. Even with this configuration, the resistance value of the gate wiring connection portion 50 can be adjusted.

[0144] Figure 11 It is shown Figure 3A A diagram showing an example of a C-C' cross-section. The C-C' cross-section is a section that extends from the sensing gate wiring 148 along the Y-axis to the main gate wiring 48. In the C-C' cross-section, a sensing well region 129 and a main well region 29 are provided on the semiconductor substrate 10.

[0145] A second polysilicon layer 48-1 and a third polysilicon layer 148-1 are disposed above the upper surface 21 of the semiconductor substrate 10, separated by an interlayer insulating film 39. A second metal layer 48-2 is disposed above the second polysilicon layer 48-1, separated by an interlayer insulating film 38. The second polysilicon layer 48-1 and the second metal layer 48-2 are connected by contact holes 64 in the interlayer insulating film 38. The third polysilicon layer 148-1 and the third metal layer 148-2 are similar.

[0146] The sensing emission electrode 152 extends between the second metal layer 48-2 and the third metal layer 148-2. In the C-C' section, the sensing emission electrode 152 is insulated from the second polysilicon layer 48-1 and the third polysilicon layer 148-1 by an interlayer insulating film 38.

[0147] Figure 12 It is shown Figure 2 A diagram showing an example of the A-A' cross-section. The A-A' cross-section is the XZ section passing through the emitter region 12 of the main transistor section 70 and the diode section 80. In the A-A' cross-section, the semiconductor device 100 includes a semiconductor substrate 10, a collector electrode 24, an interlayer insulating film 38, and a main emitter electrode 52. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor substrate 10. Hereinafter, with regard to the... Figure 4 The configuration is the same as that of the sensing transistor section 170 described in the previous section, so the description is omitted as appropriate.

[0148] An interlayer insulating film 38 is disposed on the upper surface 21 of the semiconductor substrate 10. A main emitter electrode 52 is disposed above the interlayer insulating film 38. The main emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through contact holes 54 in the interlayer insulating film 38. A collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The main emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0149] The main transistor section 70 and the diode section 80 have a drift region 18 of a first conductivity type and a base region 14 of a second conductivity type disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is N-type and the base region 14 is P-type.

[0150] In the main transistor section 70, a plurality of main gate trench sections 40 and a plurality of main dummy trench sections 30 are provided from the upper surface 21 of the semiconductor substrate 10 inward. In this example, the main gate trench sections 40 and the main dummy trench sections 30 are arranged along the X-axis direction and have a long side in the Y-axis direction. The main gate trench section 40 has a trench, a main gate insulating film 42, and a main gate conductive section 44. The main gate insulating film 42 is provided to cover the inner wall of the trench. The main gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the trench. The main gate conductive section 44 is provided inside the trench at a position further inward than the main gate insulating film 42. That is, the main gate insulating film 42 insulates the main gate conductive section 44 from the semiconductor substrate 10. The main gate conductive section 44 is formed of a conductive material such as polysilicon.

[0151] The main dummy trench portion 30 has a trench, a main dummy insulating film 32, and a main dummy conductive portion 34. The structure of the main dummy trench portion 30 can be the same as that of the main gate trench portion 40. However, while the main gate conductive portion 44 is connected to the main gate wiring 48, the main dummy trench portion 30 may not be connected to the main gate wiring 48. The main dummy conductive portion 34 can be connected to the main emitter electrode 52 in a cross-section different from the A-A' cross-section. The diode portion 80 also has multiple main dummy trench portions 30.

[0152] The main transistor section 70 has a mesa 60, which is the region between the main gate trench section 40 and the main dummy trench section 30. Similarly, the diode section 80 has a mesa 72, which is the region between the main dummy trench sections 30. A base region 14 is provided on each mesa.

[0153] The main transistor section 70 has a first conductivity type emitter region 12 disposed on the upper surface 21. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is grounded to the main gate trench section 40 or the main dummy trench section 30. The emitter region 12 can be connected to the main gate trench section 40 or the main dummy trench section 30 on both sides of the mesa section 60.

[0154] The base region 14 is located below the transmitter region 12. In this example, the base region 14 is grounded to the transmitter region 12. The base region 14 can be connected to the main gate trench portion 40 or the main dummy trench portion 30 on both sides of the mesa portion 60.

[0155] Accumulation region 16 is disposed below base region 14. Accumulation region 16 is an N+ type region with a higher doping concentration than drift region 18. By providing a high-concentration accumulation region 16 between drift region 18 and base region 14, the carrier injection enhancement effect (IE effect) can be improved and the turn-on voltage reduced. Accumulation region 16 can be configured to cover the entire lower surface of base region 14 in each mesa 60.

[0156] A P-type base region 14 is provided on the mesa 72 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An emitter region 12 is not provided on the mesa 72 of the diode section 80.

[0157] The main transistor section 70 has a collector region 22 of a second conductivity type disposed on the lower surface 23 of the semiconductor substrate 10. In this example, the collector region 22 is P+ type. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may include the same acceptors as the base region 14, or it may include acceptors different from those in the base region 14. The acceptors in the collector region 22 are, for example, boron.

[0158] The diode section 80 has a first conductivity type cathode region 82 disposed on the lower surface 23 of the semiconductor substrate 10. In this example, the cathode region 82 is N+ type. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donors of the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above.

[0159] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10.

[0160] The main transistor section 70 may be a region on the lower surface 23 where a collector region 22 is provided. The diode section 80 may be a region on the lower surface 23 where a cathode region 82 is provided. The boundary between the main transistor section 70 and the diode section 80 may be the boundary between the cathode region 82 and the collector region 22.

[0161] An N+ type buffer 20 may be disposed between the drift region 18 and the collector region 22 and the cathode region 82. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22.

[0162] In a cross-section different from A-A', a contact region of a second conductivity type can be provided in the main transistor section 70 and the diode section 80. The contact region can be located between the base region 14 and the upper surface 21. The contact region can be a P+ type region with a higher doping concentration than the base region 14.

[0163] The main gate trench 40 and the main dummy trench 30 extend from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, contact region, and accumulation region 16 is provided, the main gate trench 40 and the main dummy trench 30 also extend through these doped regions to reach the drift region 18. The trench extending through the doped region is not limited to a method in which the trench is formed after the doped region is formed. A method in which the doped region is formed between the trenches after the trenches are formed is also included in the method of trenches extending through the doped region. It should be noted that the bottom of the trench may be a downwardly convex curved surface (curved in cross-section).

[0164] The main gate conductive portion 44 can be configured to be longer than the base region 14 in the depth direction. The main gate trench portion 40 is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The main gate conductive portion 44 is electrically connected to the main gate wiring 48. If a predetermined gate voltage is applied to the main gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that is in contact with the main gate trench portion 40. As a result, in the main transistor portion 70, the main current flows between the main emitter electrode 52 and the collector electrode 24.

[0165] Figure 13 It is shown Figure 2 The diagram shows other examples of region A in the image. Figure 13 The image shows the configuration of the main gate trench portion 40 and the main dummy trench portion 30 of the main transistor portion 70, and the configuration of the sensing gate trench portion 140 and the sensing dummy trench portion 130 of the sensing transistor portion 170.

[0166] Multiple main gate trench portions 40, main dummy trench portions 30, sensing gate trench portions 140, and sensing dummy trench portions 130 are respectively provided. Each trench portion can extend along the same direction. In this example, each trench portion extends along the Y-axis direction and is arranged along the X-axis direction. Furthermore, in Figure 13 In the diagram, the second polysilicon layer 48-1 and the third polysilicon layer 148-1 are not shaded. Furthermore, the contact holes 64 on the positive and negative sides of the Y-axis direction of the sensing transistor section 170 are omitted.

[0167] When viewed from above, the density of the sensing gate trench portion 140 can be greater than the density of the main gate trench portion 40. This density is the number of trench portions per unit area. In this case, even if the ends of the straight sections of each trench portion are connected, the number of straight sections can still be counted. Therefore, since the gate-emitter capacitance of the sensing transistor portion 170 increases, oscillations in the gate voltage of the sensing transistor portion 170 can be suppressed.

[0168] The spacing D1 between the plurality of sensing gate trench portions 140 can be smaller than the spacing D2 between the plurality of main gate trench portions 40. Therefore, since the density of the sensing gate trench portions 140 increases and the gate-emitter capacitance of the sensing transistor portion 170 increases, gate voltage oscillations can be suppressed. Sensing dummy trench portions 130 can be provided between the plurality of sensing gate trench portions 140, or main dummy trench portions 30 can be provided between the plurality of main gate trench portions 40. The spacing D1 can be less than half the spacing D2. Figure 13 The example shown can be combined with any other variation.

[0169] Figure 14 It is shown Figure 2 The diagram shows other examples of region A in the image. Figure 14 In the middle, the configuration of the sensing gate trench portion 140 and the sensing dummy trench portion 130 of the sensing transistor portion 170 is similar to... Figure 13 The examples shown are different.

[0170] The ratio R1 of the number of sensing gate trenches 140 in the sensing transistor section 170 to the number of sensing dummy trenches 130 can be greater than the ratio R2 of the number of main gate trenches 40 in the main transistor section 70 to the number of main dummy trenches 30. In this example, the ratio R1 is 1, while the ratio R2 is 0.5. As a result, since the density of the sensing gate trenches 140 increases and the gate-emitter capacitance of the sensing transistor section 170 increases, gate voltage oscillations can be suppressed. The ratio R1 can be more than 2 times, more than 3 times, or more than 4 times the ratio R2. Figure 14 The example shown can be combined with any other variation.

[0171] In either example, the short-circuit current density of the semiconductor device 100 when its rated voltage is applied can be 5000 A / cm². 2 That's all. Additionally, the width W1 of the mesa 160 of the sensing transistor section 170 (refer to...) Figure 4 The width W3 of the mesa 60 of the main transistor section 70 (see reference) Figure 12 The spacing can be less than 1 μm. Additionally, the cell pitch W2 of the sensing transistor section 170 (refer to...) Figure 4 ) and the cell spacing W4 of the main transistor section 70 (refer to Figure 12 The gate diameter (GD) can be greater than 1 μm and less than 3 μm. As the performance of the semiconductor device 100 improves, gate voltage oscillations become more likely to occur, so it is preferable to suppress oscillations.

[0172] Figure 15 It is shown Figure 2 Figure 1 shows another example of the A-A' cross-section. In this example, a trench bottom region 26 of a second conductivity type is provided at the bottom of the main gate trench 40. In this example, the trench bottom region 26 is P+ type. By providing the trench bottom region 26, conduction losses can be reduced. A drift region 18 may exist between the trench bottom region 26 and the base region 14 or the accumulation region 16. The trench bottom region 26 may be provided at the bottom of the main dummy trench 30, or it may be provided at the bottom of multiple trenches.

[0173] Figure 16 It is shown Figure 3A Figure 1 shows another example of the B-B' cross-section. In this example, a trench bottom region 26 of the second conductivity type is provided at the bottom of the sensing gate trench 140. From the viewpoint of current detection, it is preferable that the main transistor 70 and the sensing transistor 170 have the same configuration. Therefore, if the main transistor 70 has a trench bottom region 26, it is preferable that the sensing transistor 170 also has a trench bottom region 26. However, in this case, the voltage dependence of the gate-emitter capacitance of the sensing transistor 170 changes, and oscillation becomes more likely to occur. Therefore, it is preferable to use the above configuration to suppress oscillation.

[0174] A drift region 18 may exist between the trench bottom region 26 and the base region 14 or the accumulation region 16. The trench bottom region 26 may be provided at the bottom of the sensing dummy trench section 130, or it may be provided at the bottom of multiple trench sections. The trench bottom region 26 of the sensing transistor section 170 and the trench bottom region 26 of the main transistor section 70 may have the same doping concentration, or they may be formed in the same process. However, the trench bottom region 26 may also be provided in either the main transistor section 70 or the sensing transistor section 170.

[0175] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As will be clearly understood from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that, It includes a semiconductor substrate, the semiconductor substrate having an upper surface. The semiconductor substrate has: The main transistor section has a main gate trench section including a main gate conductive section; A sensing transistor section having a sensing gate trench section including a sensing gate conductive section; A gate pad is disposed above the upper surface of the semiconductor substrate; The main gate wiring is disposed above the upper surface of the semiconductor substrate and extends from the gate pad to the main gate conductive portion; A sensing gate wiring is configured along the sensing transistor portion; as well as A gate wiring connection portion connects the main gate wiring and the sensing gate wiring. A resistor is provided in the gate wiring connection portion.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate also has sensing pads, which are disposed adjacent to the sensing transistor portion. The gate wiring connection portion is disposed on the side opposite to the sensing pad, with the sensing transistor portion as a reference.

3. The semiconductor device according to claim 1, characterized in that, The sensing gate trench extends along the extension direction. The gate wiring connection portion is disposed at a position overlapping the sensing transistor portion in a direction perpendicular to the extension direction when viewed from above.

4. The semiconductor device according to claim 1, characterized in that, The resistive portion includes a first polysilicon layer disposed above the upper surface of the semiconductor substrate.

5. The semiconductor device according to claim 4, characterized in that, The main gate wiring includes a second polysilicon layer disposed above the upper surface of the semiconductor substrate. The first polysilicon layer is connected to the second polysilicon layer.

6. The semiconductor device according to claim 4, characterized in that, A metal layer is disposed above the first polycrystalline silicon layer, separated by an insulating film.

7. The semiconductor device according to claim 6, characterized in that, When viewed from above, at least a portion of the first polycrystalline silicon layer is not covered by the metal layer.

8. The semiconductor device according to claim 4, characterized in that, The main gate wiring includes a second polysilicon layer disposed above the upper surface of the semiconductor substrate. The first polysilicon layer has a different thickness than the second polysilicon layer.

9. The semiconductor device according to claim 8, characterized in that, The first polysilicon layer has a stacked structure consisting of an upper polysilicon layer and a lower polysilicon layer. The thickness of the first polysilicon layer is greater than the thickness of the second polysilicon layer.

10. The semiconductor device according to claim 9, characterized in that, The upper polysilicon layer is not disposed on a portion of the upper surface of the lower polysilicon layer.

11. The semiconductor device according to claim 1, characterized in that, When viewed from above, the density of the sensing gate trench is greater than that of the main gate trench.

12. The semiconductor device according to claim 11, characterized in that, The system is provided with multiple main gate trench portions and multiple sensing gate trench portions. The spacing between the plurality of sensing gate trenches is smaller than the spacing between the plurality of main gate trenches.

13. The semiconductor device according to claim 11, characterized in that, The main gate trench is provided with multiple such trench portions. The main transistor section has multiple main dummy trench sections. The sensing gate trench is provided with a plurality of the aforementioned trench portions. The sensing transistor section has multiple sensing dummy trench sections. The ratio of the number of sensing gate trenches in the sensing transistor section to the number of sensing dummy trenches is greater than the ratio of the number of main gate trenches in the main transistor section to the number of main dummy trenches.

14. The semiconductor device according to claim 1, characterized in that, The short-circuit current density when the rated voltage is applied is 5000 A / cm. 2 above.

15. The semiconductor device according to claim 1, characterized in that, The sensing gate wiring is configured as a closed loop surrounding the sensing transistor portion.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that, A drift region of a first conductivity type is provided in the semiconductor substrate. A second conductivity type trench bottom region is provided at the bottom of the sensing gate trench.

17. The semiconductor device according to claim 16, characterized in that, A second conductivity type trench bottom region is provided at the bottom of the main gate trench.

18. A semiconductor device, characterized in that, It includes a semiconductor substrate, the semiconductor substrate having an upper surface. The semiconductor substrate has: The drift region of the first conductivity type; The main transistor section has a main gate trench section including a main gate conductive section; A sensing transistor section having a sensing gate trench section including a sensing gate conductive section; A gate pad is disposed above the upper surface of the semiconductor substrate; The main gate wiring is disposed above the upper surface of the semiconductor substrate and extends from the gate pad to the main gate conductive portion; as well as A gate wiring connection portion connects the main gate wiring and the sensing gate conductive portion. A resistor is provided in the gate wiring connection portion. A second conductivity type trench bottom region is provided at the bottom of the sensing gate trench.

19. The semiconductor device according to claim 18, characterized in that, A second conductivity type trench bottom region is provided at the bottom of the main gate trench.

20. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes a sensing gate wiring disposed along the sensing transistor portion and connected to the sensing gate conductive portion. The gate wiring connection portion connects the main gate wiring and the sensing gate wiring.

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