Display device

Abstract

The display device may include: a plurality of pixels disposed in a display area; a plurality of scan lines connected to the pixels; a plurality of data lines connected to the pixels; a plurality of vertical initialization lines connected to the pixels; and a common line disposed in the non-display area around the display area, where the common line is adjacent to a first side of the display area and a first fillet of the display area, and a vertical initialization line is adjacent to the first side and the first fillet, connected to the common line, and extending in a second direction from the common line.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to display devices. Background Technology

[0002] Typically, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs, include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen.

[0003] The display device includes multiple pixels for generating images and multiple lines connected to the pixels. The pixels are driven by receiving drive signals through the lines.

[0004] In recent years, with the development of display devices of various shapes, display devices can have rounded quadrilateral shapes where the corners of a quadrilateral are rounded. The display area of ​​a display device can have a rounded quadrilateral shape depending on the shape of the display device. There is a need to develop techniques for easily connecting lines to pixels located at the rounded corners. Summary of the Invention Technical issues

[0005] Embodiments of this disclosure provide a display device that can improve display quality by uniformly forming the line resistance of pixels in the display area. Technical solution

[0006] According to an embodiment, the display device includes: a plurality of pixels disposed in a display area; a plurality of scan lines connected to the pixels; a plurality of data lines connected to the pixels; a plurality of vertical initialization lines connected to the pixels; and a common line disposed in a non-display area surrounding the display area. The display area includes a first side extending in a first direction, a second side extending in a second direction adjacent to one end of the first side and intersecting the first direction, and a first rounded corner connecting the one end of the first side to the end of the second side adjacent to the one end of the first side. The common line is adjacent to the first side and the first rounded corner, and the vertical initialization lines are adjacent to the first side and the first rounded corner, connected to the common line, and extending from the common line in the second direction.

[0007] According to an embodiment, the display device includes: a plurality of pixels disposed in a display area; a plurality of scan lines connected to the pixels; a plurality of data lines connected to the pixels; a common line disposed in a non-display area surrounding the display area; and a plurality of vertical initialization lines connected to the pixels. The display area includes a first side extending in a first direction, a second side and a third side extending in a second direction adjacent to both ends of the first side and intersecting the first direction, a first rounded corner connecting the first side and the second side, and a second rounded corner connecting the first side and the second side. The common line is adjacent to the first side, the first rounded corner, and the second rounded corner, and the vertical initialization lines are adjacent to the first side, the first rounded corner, and the second rounded corner, connected to the common line, and extending from the common line in the second direction.

[0008] According to an embodiment, the display device includes: a plurality of pixels disposed within a display area, the display area including sides of a quadrilateral extending in a first direction and a second direction intersecting the first direction, and rounded corners connecting the sides; a plurality of scan lines connected to the pixels; a plurality of data lines connected to the pixels; a common line disposed in a non-display area surrounding the display area and adjacent to at least one side and at least one rounded corner; and a plurality of vertical initialization lines disposed adjacent to the at least one side and the at least one rounded corner, and connected to the pixels and the common line. The vertical initialization lines extend from the common lines in a direction intersecting the extension direction of the at least one side. Beneficial effects

[0009] According to embodiments of this disclosure, the vertical initialization lines connected to the pixels are not only provided on the first side extending along the first direction, but also on the first and second rounded corners connected to both ends of the first side. Therefore, the line resistance of the pixels in the display area can be uniformly formed. Consequently, the display quality of the display device can be improved. Attached Figure Description

[0010] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0011] Figure 2 It is an illustrative diagram. Figure 1 The diagram shows a cross-sectional view of the display device.

[0012] Figure 3 It is an illustrative diagram. Figure 2 The diagram shows a cross-sectional view of the display panel.

[0013] Figure 4 yes Figure 1 The block diagram of the display device shown in the figure.

[0014] Figure 5 It is a diagram. Figure 4A view of the equivalent circuit of any pixel in the diagram.

[0015] Figure 6 It is used to describe Figure 5 The diagram shows the timing of the scanning and emission signals for the pixel operation.

[0016] Figure 7 It is an illustrative diagram. Figure 5 The diagram shows a cross-sectional view of the light-emitting elements, first transistor, fourth transistor, and sixth transistor of the pixel.

[0017] Figure 8 yes Figure 4 The diagram shows a floor plan of the display panel.

[0018] Figure 9 It is a separate icon setting Figure 8 The diagram shows a view of the construction of the first initialization line on the display panel.

[0019] Figure 10 It is a separate icon setting Figure 8 The diagram shows a view of the construction of the second initialization line on the display panel.

[0020] Figure 11a It is the display panel and Figure 9 The enlarged view of the portion adjacent to the first rounded corner in the diagram.

[0021] Figure 11b It is the display panel and Figure 9 The enlarged view of the portion adjacent to the second rounded corner in the diagram.

[0022] Figure 11c and Figure 11d It is the display panel and Figure 9 An enlarged view of the portion adjacent to the third rounded corner in the diagram.

[0023] Figure 12a It is a plan view illustrating the connection structure between the first initialization line, the second initialization line, and the pixel at the center of the display panel.

[0024] Figure 12b It is a planar diagram illustrating the connection structure between the first initialization line, the second initialization line, and the pixel adjacent to the first rounded corner.

[0025] Figure 13 It is a diagram and Figure 9 The figure shows a cross-sectional view of the first vertical initialization line and the first horizontal initialization line corresponding to a contact hole.

[0026] Figure 14 This is a view illustrating the construction of a comparison display panel according to an embodiment.

[0027] Figures 15 to 17 This is a view illustrating the construction of common lines according to an embodiment of the present disclosure. Detailed Implementation

[0028] In this specification, the description of a first component (or area, layer, component, part, etc.) being "set on" a "second component", "connected to" a "second component", or "attached to" a "second component" means that the first component is directly set on / connected to / attached to the second component, or means that a third component is located therebetween.

[0029] The same reference numerals refer to the same parts. Furthermore, in order to effectively depict the technical content, the thickness, proportions, and dimensions of the parts are exaggerated in the accompanying drawings.

[0030] The term "and / or" includes all combinations of one or more components that may be defined by the relevant construction.

[0031] Although the terms “first,” “second,” etc., may be used to describe various components, the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0032] In addition, terms such as "below," "under," "above," and "over" are used to describe the relationships between the components illustrated in the accompanying drawings. These terms are conceptually relative, based on the orientation shown in the drawings.

[0033] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (e.g., those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0034] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, figures, steps, operations, elements or components or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, figures, steps, operations, elements or components or combinations thereof.

[0035] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0036] Figure 1This is a perspective view of a display device according to an embodiment of the present disclosure.

[0037] refer to Figure 1 According to embodiments of the present disclosure, the display device DD may have a long side extending parallel to a first direction DR1 and a short side extending parallel to a second direction DR2 intersecting the first direction DR1. The corner connecting the long and short sides of the display device DD may have a curved shape. The curved corner of the display device DD may be defined as a rounded corner. The shape of the display device DD may be defined as a rounded quadrilateral shape.

[0038] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in the specification, the meaning "when viewed on a plane" is defined as the state of viewing from the third direction DR3.

[0039] The front surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the display device DD can be provided to the user through the display surface DS.

[0040] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA displays an image, while the non-display area NDA does not display an image. The non-display area NDA may surround the display area DA and define an edge of the display device DD printed in a predetermined color.

[0041] Depending on the shape of the display device DD, the display area DA can have a rounded quadrilateral shape. For example, the display area DA may include sides of the quadrilateral extending in the first direction DR1 and the second direction DR2, as well as rounded corners connecting the sides. The side extending in the first direction DR1 can be defined as the long side, and the side extending in the second direction DR2 can be defined as the short side.

[0042] The display device DD can sense input applied from outside the display device DD. For example, the display device DD can sense a first input via a stylus PEN and a second input via a touch TC. The stylus PEN can be defined as an input device.

[0043] The stylus (PEN) can be an active pen that outputs signals. A second input via the touch TC can include various types of external inputs, such as a part of the user's body, light, heat, or pressure.

[0044] The display device DD and the stylus PEN can communicate bidirectionally with each other. The display device DD can provide uplink signals to the stylus PEN. For example, the uplink signals may include information such as panel information and protocol version, but this disclosure is not limited thereto.

[0045] The stylus pen (PEN) can provide downlink signals to the display device (DD). The downlink signals may include synchronization signals or status information of the stylus pen (PEN). For example, the downlink signals may include coordinate information of the stylus pen (PEN), battery information of the stylus pen (PEN), tilt information of the stylus pen (PEN), and / or various information stored in the stylus pen (PEN), but this disclosure is not specifically limited thereto.

[0046] The display device DD can be used in large electronic devices such as televisions, monitors, or billboards. Furthermore, the display device DD can be used in small to medium-sized electronic devices such as personal computers (PCs), laptops, personal digital terminals, vehicle navigation systems, game consoles, smartphones, tablet PCs, or cameras. However, these are merely presented as examples, and the display device DD can be used in other electronic devices, provided that the other electronic devices do not depart from the concept of this disclosure.

[0047] Figure 2 It is an illustrative diagram. Figure 1 The diagram shows a cross-sectional view of the display device.

[0048] Illustratively, Figure 2 This is a cross-sectional view of the display device DD when viewed in the second direction DR2.

[0049] refer to Figure 2 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, a first adhesive layer AL1, and a second adhesive layer AL2.

[0050] The display panel DP according to embodiments of the present disclosure can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel can include quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0051] The input sensing unit ISP can be disposed on the display panel DP. The input sensing unit ISP may include multiple sensing units (e.g., multiple sensors or sensor electrodes) for capacitively sensing external input. When manufacturing the display device DD, the input sensing unit ISP can be directly fabricated on the display panel DP. However, this disclosure is not limited thereto, and the input sensing unit ISP can be fabricated as a panel independent of the display panel DP and attached to the display panel DP via an adhesive layer.

[0052] The anti-reflective layer RPL can be disposed on the input sensing unit ISP. When manufacturing the display device DD, the anti-reflective layer RPL can be directly fabricated on the input sensing unit ISP. However, this disclosure is not limited thereto, and the anti-reflective layer RPL can be manufactured as a separate panel and attached to the input sensing unit ISP via an adhesive layer.

[0053] An anti-reflective layer (RPL) can be defined as an external light anti-reflective film. The RPL reduces the reflectivity of external light input from the top of the display device (DD) towards the display panel (DP). Due to the RPL, external light is not visually perceptible to the user.

[0054] When external light propagating toward the display panel DP is reflected back by the display panel DP and provided to an external user, the user can visually perceive the external light as if it were a mirror. To prevent this phenomenon, illustratively, the anti-reflective layer RPL may include multiple color filters that display the same colors as the pixels of the display panel DP.

[0055] A color filter can filter external light into the same color as the pixel. In this case, the external light may not be visually perceived by the user. However, this disclosure is not limited to this, and the anti-reflective layer RPL may include a phase retarder and / or a polarizer for reducing the reflectivity of external light.

[0056] The WIN window can be installed on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor unit ISP, and anti-reflective layer RPL from external scratches and impacts.

[0057] A panel protective film (PPF) can be applied beneath the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0058] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be adhered to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be adhered to each other through the second adhesive layer AL2.

[0059] Figure 3 It is an illustrative diagram. Figure 2 The diagram shows a cross-sectional view of the display panel.

[0060] Illustratively, Figure 3 The illustration shows a cross-section of the display panel DP when viewed in the second direction DR2.

[0061] refer to Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0062] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0063] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0064] A thin-film encapsulation layer (TFE) can be deposited on the DP-CL circuit element layer to cover the DP-OLED display element layer. The TFE can protect the pixels from moisture, oxygen, and foreign matter.

[0065] Figure 4 yes Figure 1 The block diagram of the display device shown in the figure.

[0066] refer to Figure 4 The display device DD may include a display panel DP, a timing controller TC, a scan driver SDV, a data driver DDV, a light-emitting driver EDV, and a voltage generator VG.

[0067] The display panel DP may include multiple scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, multiple light emission lines EML1 to EMLm, multiple data lines DL1 to DLn, and multiple pixels PX. “m” and “n” are natural numbers.

[0068] Pixel PX can be electrically connected to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, light emission lines EML1 to EMLm, and data lines DL1 to DLn. Each pixel PX can be electrically connected to its corresponding four scan lines, one data line, and one light emission line.

[0069] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include multiple initialization scan lines GIL1 to GILm, multiple compensation scan lines GCL1 to GCLm, multiple write scan lines GWL1 to GWLm, and multiple bias scan lines GBL1 to GBLm.

[0070] Each pixel PX can be connected to a corresponding initialization scan line GIL1 to GILm, a corresponding compensation scan line GCL1 to GCLm, a corresponding write scan line GWL1 to GWLm, and a corresponding bias scan line GBL1 to GBLm.

[0071] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm can be connected to the scan driver SDV, can extend in the first direction DR1, and can be arranged in the second direction DR2. Emission lines EML1 to EMLm can be connected to the emission driver EDV, can extend in the first direction DR1, and can be arranged in the second direction DR2. Data lines DL1 to DLn can be connected to the data driver DDV, can extend in the second direction DR2, and can be arranged in the first direction DR1.

[0072] The scan driver (SDV), light emission driver (EDV), and data driver (DDV) can be essentially mounted on the display panel (DP), and these components will be located below. Figure 8 The diagram in the middle is shown.

[0073] The timing controller TC can receive image signals RGB and control signals CTRL. The timing controller TC can generate an image data signal DAS by converting the data format of the image signals RGB to meet the interface specifications with the data driver DDV. The timing controller TC can output a scan control signal SCS, a data control signal DCS, and an illumination control signal ECS in response to the control signal CTRL.

[0074] The voltage generator VG generates the voltages required to operate the display panel DP. The voltage generator VG generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. These voltages can be applied to pixels PX.

[0075] The scan driver SDV can receive scan control signals SCS from the timing controller TC. In response to the scan control signals SCS, the scan driver SDV can output scan signals to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals can be applied to pixels PX through scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0076] The data driver DDV receives data control signals DCS and image data signals DAS from the timing controller TC. The data driver DDV converts the image data signals DAS into data signals and outputs the converted data signals. The data signals can be defined as analog voltages corresponding to the gray levels of the image data signals DAS. The data signals can be applied to pixels PX via data lines DL1 to DLn.

[0077] The EDV (Emitting Driver) can receive the ECS (Emitting Control Signal) from the timing controller TC. In response to the ECS, the EDV can output an emitting signal to the emitting lines EML1 to EMLm. The emitting signal can be applied to the pixel PX through the emitting lines EML1 to EMLm.

[0078] A pixel (PX) can receive a data voltage in response to a scan signal. A pixel (PX) can display an image by emitting light with a brightness corresponding to the data voltage in response to a light emission signal.

[0079] Figure 5 It is a diagram. Figure 4 A view of the equivalent circuit of any pixel in the diagram.

[0080] Illustratively, Figure 5 The diagram illustrates pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi. "i" and "j" are natural numbers.

[0081] refer to Figure 5 A pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC can drive the light-emitting element OLED.

[0082] The pixel circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST control the amount of current flowing through the light-emitting element OLED. The light-emitting element OLED can produce light with a predetermined brightness according to the amount of current supplied.

[0083] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCI. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th emission line EMLi can receive the i-th emission signal EMi.

[0084] Pixel PXij can be connected to the j-th data line DLj, the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0085] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS. The first power line PL1 can receive the first drive voltage ELVDD, and the second power line PL2 can receive the second drive voltage ELVSS.

[0086] Each of transistors T1 through T8 may include a source electrode, a drain electrode, and a gate electrode. In the following text, in Figure 5 For convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other is defined as the second electrode. Furthermore, the gate electrode is defined as the control electrode.

[0087] Transistors T1 to T8 may include first transistor T1 to eighth transistor T8. First transistor T1, second transistor T2, and fifth transistor T5 to eighth transistor T8 may be P-type metal-oxide-semiconductor (PMOS) transistors. Third transistor T3 and fourth transistor T4 may be N-type metal-oxide-semiconductor (NMOS) transistors.

[0088] The first transistor T1 can be defined as a driving transistor, and the second transistor T2 can be defined as a switching transistor. The third transistor T3 can be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors. The eighth transistor T8 can be defined as a bias transistor.

[0089] The light-emitting element (OLED) can be defined as an organic light-emitting element. The OLED can include an anode (AE) and a cathode (CE). The anode (AE) can receive a first driving voltage (ELVDD) via a fifth transistor (T5), a first transistor (T1), and a sixth transistor (T6). The first driving voltage (ELVDD) can be applied to the pixel circuit (PC) via a first power line (PL1).

[0090] The cathode CE can receive a second driving voltage ELVSS that is lower than the level of the first driving voltage ELVDD. The second driving voltage ELVSS can be applied to the pixel circuit PC through the second power line PL2.

[0091] The first transistor T1 can be positioned between the fifth transistor T5 and the sixth transistor T6, and connected to both transistors T5 and T6. The first transistor T1 can be connected to the first power line PL1 via the fifth transistor T5 and to the anode AE ​​via the sixth transistor T6.

[0092] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the anode AE ​​via a sixth transistor T6, and a control electrode connected to the first node N1.

[0093] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1, the first node N1.

[0094] The second transistor T2 can be disposed between the first transistor T1 and the j-th data line DLj, and connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWLi.

[0095] The second transistor T2 can be turned on by the i-th write scan signal GWi applied through the i-th write scan line GWLi to electrically connect the j-th data line DLj and the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage VD (corresponding to the aforementioned data signal) applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0096] The third transistor T3 can be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0097] The third transistor T3 can be turned on by the i-th compensation scan signal GCI applied through the i-th compensation scan line GCLi to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 can be connected to each other by a diode.

[0098] A fourth transistor T4 may be connected to a first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to a first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on by an i-th initialization scan signal GIi applied through the i-th initialization scan line GILi to provide a first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0099] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light-emitting line EMLi.

[0100] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light-emitting line EMLi.

[0101] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal EMi applied through the i-th emission line EMi. The first driving voltage ELVDD is provided to the light-emitting element OLED by the turned-on fifth transistor T5 and the turned-on sixth transistor T6, so that the driving current can flow in the light-emitting element OLED. Therefore, the light-emitting element OLED can emit light.

[0102] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi to provide the second initialization voltage VAINT received through the second initialization line VIL2 to the anode AE ​​of the light-emitting element OLED.

[0103] In embodiments of this disclosure, the second initialization voltage VAINT may have a different level than the first initialization voltage VINT, but this disclosure is not limited thereto, and the second initialization voltage VAINT may have the same level as the first initialization voltage VINT.

[0104] The seventh transistor T7 can improve the black level performance of pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the OLED light-emitting element can be discharged. Therefore, when achieving black brightness, the OLED light-emitting element does not emit light due to the leakage current of the first transistor T1, and correspondingly, the black level performance can be improved.

[0105] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CST.

[0106] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0107] The eighth transistor T8 can be turned on by the i-th bias scan signal GBi to provide the bias voltage VBIAS applied through the bias line VBL to the first electrode of the first transistor T1.

[0108] Figure 6 It is used to describe Figure 5 The diagram shows the timing of the scanning and emission signals for the pixel operation.

[0109] refer to Figure 5 and Figure 6 The i-th emission signal EMi can have a high level during the non-emission period NLP and a low level during the emission period LP.

[0110] The activation period of each of the i-th write scan signal GWi and the i-th bias scan signal GBi can be limited to the low level of each of the i-th write scan signal GWi and the i-th bias scan signal GBi.

[0111] The activation period of each of the i-th compensation scan signal GCI and the i-th initialization scan signal GII can be defined as the high level of each of the i-th compensation scan signal GCI and the i-th initialization scan signal GII.

[0112] After the i-th initialization scan signal GIi is activated, the i-th compensation scan signal GCI and the i-th write scan signal GWi can be activated. Subsequently, the i-th bias scan signal GBi can be activated.

[0113] During the non-light-emitting NLP period, the activated i-th initialization scan signal GIi, the i-th compensation scan signal GCI, the i-th write scan signal GWi, and the i-th bias scan signal GBi can be applied to pixel PXij.

[0114] The i-th initialization scan signal GIi can be applied to the fourth transistor T4 to turn it on. The first initialization voltage VINT can be provided to the first node N1 through the fourth transistor T4. Therefore, the first initialization voltage VINT can be applied to the control electrode of the first transistor T1, and the first transistor T1 can be initialized by the first initialization voltage VINT. This operation can be defined as an initialization operation.

[0115] The i-th write scan signal GWi can be applied to the second transistor T2 to turn on the second transistor T2. In addition, the i-th compensation scan signal GCI can be applied to the third transistor T3 to turn on the third transistor T3.

[0116] The first transistor T1 and the third transistor T3 can be diode-connected to each other. In this case, a compensation voltage (Vd-Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data voltage VD provided through the j-th data line DLj can be applied to the control electrode of the first transistor T1. This operation can be defined as a write operation (or programming operation) and a compensation operation.

[0117] The first driving voltage ELVDD and the compensation voltage (Vd-Vth) can be applied to the first and second electrodes of the capacitor CST, respectively. The charge corresponding to the difference between the voltage at the first electrode and the voltage at the second electrode of the capacitor CST can be stored in the capacitor CST.

[0118] Subsequently, the i-th bias scan signal GBi can be applied to the seventh transistor T7 and the eighth transistor T8 to turn on the seventh transistor T7 and the eighth transistor T8. The second initialization voltage VAINT can be provided to the anode AE ​​through the seventh transistor T7, so that the anode AE ​​can be initialized by the second initialization voltage VAINT. The bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8.

[0119] Subsequently, during the light-emitting period LP, the i-th light-emitting signal EMi can be applied to the fifth transistor T5 and the sixth transistor T6 through the i-th light-emitting line EMi, thereby turning on the fifth transistor T5 and the sixth transistor T6. In this case, a drive current Id corresponding to the difference between the voltage of the control electrode of the first transistor T1 and the first drive voltage ELVDD can be generated. The drive current Id can be provided to the light-emitting element OLED through the sixth transistor T6, so that the light-emitting element OLED can emit light.

[0120] During the light-emitting period LP, the gate-source voltage (Vgs) of the first transistor T1 can be defined as Vgs = ELVDD - (Vd - Vth) due to the capacitor CST. The current-voltage relationship of the first transistor T1 can be defined as Id = (1 / 2)μCox (W / L) (Vgs - Vth). 2 This equation is the general expression for the current-voltage relationship of a transistor.

[0121] When Vgs is substituted into the current-voltage relationship expression, the threshold voltage (Vth) can be eliminated, and the drive current Id can be the square of the value obtained by subtracting the data voltage VD from the first drive voltage ELVDD (ELVDD-Vd). 2 Proportional. Therefore, regardless of the threshold voltage (Vth) of the first transistor T1, the drive current Id can be determined. This operation can be defined as threshold voltage compensation operation.

[0122] After the threshold voltage of the first transistor T1 is compensated and before the OLED emits light, a bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8. The shift in the hysteresis curve of the first transistor T1 can be suppressed by the bias voltage VBIAS. This operation can be defined as a bias operation.

[0123] Figure 7 It is an illustrative diagram. Figure 5 The diagram shows a cross-sectional view of the light-emitting elements, first transistor, fourth transistor, and sixth transistor of the pixel.

[0124] refer to Figure 7 An OLED (Optical Display Cell) light-emitting element may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML. The first electrode AE ​​can be... Figure 5 The anode AE ​​is shown in the diagram, and the second electrode CE can be... Figure 5 The cathode CE is shown in the diagram. The second electrode CE can be disposed above the first electrode AE, and the hole control layer HCL, electron control layer ECL, and light-emitting layer EML can be disposed between the first electrode AE ​​and the second electrode CE.

[0125] The first transistor T1, the fourth transistor T4, and the sixth transistor T6, as well as the light-emitting element OLED, can be disposed on the substrate SUB. The display area DA may include a light-emitting area LEA corresponding to the pixel PXij and a non-light-emitting area NLEA adjacent to the light-emitting area LEA. The light-emitting element OLED can be disposed in the light-emitting area LEA.

[0126] The lower metal layer BML can be disposed on the substrate SUB. The lower metal layer BML can overlap with the first transistor T1. Although not shown, a constant voltage can be applied to the lower metal layer BML. When the constant voltage is applied to the lower metal layer BML, the threshold voltage (Vth) of the first transistor T1 disposed on the lower metal layer BML can be maintained without change.

[0127] The lower metal layer (BML) can block light input to the first transistor T1 from below the lower metal layer (BML). The lower metal layer (BML) may include reflective metal. The lower metal layer (BML) can be omitted.

[0128] A buffer layer BFL can be disposed on the substrate SUB, and the buffer layer BFL can be an inorganic layer. The buffer layer BFL can cover the underlying metal layer BML. The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 can be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 can include polycrystalline silicon. However, this disclosure is not limited thereto, and the semiconductor layers S1, A1, D1, S6, A6, and D6 can include amorphous silicon.

[0129] Semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with N-type or P-type dopant. Semiconductor layers S1, A1, D1, S6, A6, and D6 may include highly doped and lightly doped regions. The highly doped regions may have a higher conductivity than the lightly doped regions and substantially serve as the source and drain electrodes of the first transistor T1 and the sixth transistor T6. The lightly doped regions may substantially correspond to the active regions (or channels) of the first transistor T1 and the sixth transistor T6.

[0130] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 can be formed by semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 can be formed by semiconductor layers S6, A6, and D6. The first channel region A1 can be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 can be disposed between the sixth source region S6 and the sixth drain region D6.

[0131] A first insulating layer INS1 can be disposed on a buffer layer BFL to cover semiconductor layers S1, A1, D1, S6, A6, and D6. The first gate electrode G1 (or control electrode) of the first transistor T1 and the sixth gate electrode G6 (or control electrode) of the sixth transistor T6 can be disposed on the first insulating layer INS1. When viewed in a planar plane, the first gate electrode G1 can overlap with the first channel region A1, and the sixth gate electrode G6 can overlap with the sixth channel region A6.

[0132] Although not illustrated, the source, channel, drain, and gate electrode structures of each of the second transistor T2, the fifth transistor T5, and the seventh transistor T7 can be substantially the same as those of the first transistor T1 and the sixth transistor T6.

[0133] A second insulating layer INS2 can be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. A dummy electrode DME can be disposed on the second insulating layer INS2. The dummy electrode DME can be disposed on the first gate electrode G1 and can overlap with the first gate electrode G1 when viewed in a plane. The dummy electrode DME can form a capacitor CST together with the first gate electrode G1.

[0134] The third insulating layer INS3 can be disposed on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layers S4, A4, and D4 of the fourth transistor T4 can be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and D4 can include oxide semiconductors formed of metal oxides. The oxide semiconductors can include crystalline or amorphous oxide semiconductors.

[0135] Semiconductor layers S4, A4, and D4 may include multiple regions divided depending on whether the metal oxide is reduced. Regions where the metal oxide is reduced (hereinafter referred to as reduced regions) have higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). Reduced regions may substantially function as either the source or drain electrode of the fourth transistor T4. Non-reduced regions may substantially correspond to the active region (or channel) of the fourth transistor T4.

[0136] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 can be formed by semiconductor layers S4, A4, and D4. The fourth channel region A4 can be disposed between the fourth source region S4 and the fourth drain region D4.

[0137] A fourth insulating layer INS4 can be disposed on the third insulating layer INS3 to cover semiconductor layers S4, A4, and D4. The fourth gate electrode G4 of the fourth transistor T4 can be disposed on the fourth insulating layer INS4. When viewed in a planar plane, the fourth gate electrode G4 can overlap with the fourth channel region A4.

[0138] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. Although not shown, the structure of the source region, channel region, drain region and gate electrode of the third transistor T3 can be substantially the same as the structure of the source region, channel region, drain region and gate electrode of the fourth transistor T4.

[0139] The buffer layer BFL and the first insulating layers INS1 to the fifth insulating layers INS5 may include inorganic layers. Illustratively, the buffer layer BFL, the first insulating layer INS1, and the fourth insulating layer INS4 may include silicon oxide layers, and the second insulating layer INS2 may include a silicon nitride layer.

[0140] The third insulating layer INS3 and the fifth insulating layer INS5 may comprise multiple inorganic insulating layers comprising different materials and laminated on top of each other. For example, the third insulating layer INS3 may comprise sequentially laminated silicon nitride and silicon oxide layers, and the fifth insulating layer INS5 may comprise sequentially laminated silicon oxide and silicon nitride layers. The thickness of each of the third insulating layer INS3 and the fifth insulating layer INS5 may be greater than the thickness of the buffer layer BFL and each of the first insulating layer INS1, the second insulating layer INS2, and the fourth insulating layer INS4.

[0141] The connecting electrode CNE can be disposed between the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE can electrically connect the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0142] The first connecting electrode CNE1 can be disposed on the fifth insulating layer INS5 and can be connected to the sixth drain region D6 through the first contact hole CH1 defined by the first insulating layer INS1 to the fifth insulating layer INS5. The sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 to cover the first connecting electrode CNE1.

[0143] The second connecting electrode CNE2 can be disposed on the sixth insulating layer INS6. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CH2 defined by the sixth insulating layer INS6.

[0144] The seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 to cover the second connecting electrode CNE2. The sixth insulating layer INS6 and the seventh insulating layer INS7 can include inorganic or organic layers.

[0145] The first electrode AE ​​can be disposed on the seventh insulating layer INS7. The first electrode AE ​​can be electrically connected to the second connecting electrode CNE2 through the third contact hole CH3 defined by the seventh insulating layer INS7.

[0146] A pixel-defining film (PDL) exposing a predetermined portion of the first electrode AE ​​can be disposed on the first electrode AE ​​and the seventh insulating layer INS7. An opening PX_OP exposing the predetermined portion of the first electrode AE ​​can be defined in the pixel-defining film (PDL).

[0147] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel defining film (PDL). The HCL can be commonly disposed in the light-emitting region (LEA) and the non-light-emitting region (NLEA). The HCL may include a hole transport layer and a hole injection layer.

[0148] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (PX_OP). The EML can include organic and / or inorganic materials. The EML can produce light of any one of red, green, and blue hues.

[0149] The electronic control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can also be commonly disposed in the light-emitting region (LEA) and the non-light-emitting region (NLEA). The ECL may include an electron transport layer and an electron injection layer.

[0150] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can be commonly disposed in multiple pixels PX. That is, the second electrode CE can be commonly disposed on multiple light-emitting layers EML of multiple pixels PX.

[0151] The layer from the buffer layer BFL to the seventh insulating layer INS7 can be defined as the circuit element layer DP-CL. The layer in which the light-emitting element OLED is disposed can be defined as the display element layer DP-OLED.

[0152] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element (OLED). The TFE can comprise sequentially laminated inorganic, organic, and inorganic layers. The inorganic layer can comprise inorganic materials and can protect the pixel from moisture / oxygen. The organic layer can comprise organic materials and can protect the pixel (PX) from foreign matter such as dust particles.

[0153] A first driving voltage ELVDD can be applied to the first electrode AE, and a second driving voltage ELVSS can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EML combine with each other to form excitons, and the light-emitting element OLED emits light when the excitons transition to the ground state. The light-emitting element OLED can emit light to display images.

[0154] Figure 8 yes Figure 4 The diagram shows a floor plan of the display panel.

[0155] Figure 4 This is a view of the functional blocks of the main display device DD, and Figure 8 This is a planar view of the main display panel (DP).

[0156] refer to Figure 8 The display device DD may include a display panel DP, a scan driver SDV, multiple data drivers DDV, an EDV, and multiple pads PD. The display panel DP may have a rounded quadrilateral shape to correspond to the shape of the display device DD.

[0157] The edge of the display panel DP may have a long side extending parallel to a first direction DR1 and a short side extending parallel to a second direction DR2. The long and short sides of the display panel DP may correspond to the sides of a quadrilateral shape. The edge of the display panel DP may include rounded corners connecting the long and short sides of the display panel DP. Each of the rounded corners can connect adjacent long and short sides.

[0158] The display panel DP may include a display area DA and a non-display area NDA disposed around and surrounding the display area DA. The display area DA may have a rounded quadrilateral shape to correspond to the shape of the display panel DP.

[0159] To have a rounded quadrilateral shape, the display area DA may include a first side SI1 to a fourth side SI4 and a first rounded corner CR1 to a third rounded corner CR3. The first side SI1 to the fourth side SI4 can define the four sides of the quadrilateral. The first rounded corner CR1 to the third rounded corner CR3 can define the four rounded corners of the quadrilateral.

[0160] First side SI1 and fourth side SI4 can extend parallel to each other in the first direction DR1 and face each other in the second direction DR2. Second side SI2 and third side SI3 can extend parallel to each other in the second direction DR2 and face each other in the first direction DR1. First side SI1 and fourth side SI4 can be longer than second side SI2 and third side SI3. First side SI1 and fourth side SI4 can be defined as long sides, and second side SI2 and third side SI3 can be defined as short sides.

[0161] The second side SI2 and the third side SI3 can be adjacent to both ends of the first side SI1 and extend in the second direction DR2. The second side SI2 can be adjacent to one end of the first side SI1 and extend in the second direction DR2. The third side SI3 can be adjacent to the other end of the first side SI1 and extend in the second direction DR2. One end of the second side SI2 can be adjacent to that end of the first side SI1, and one end of the third side SI3 can be adjacent to that other end of the first side SI1.

[0162] The fourth side SI4 may be adjacent to the other end of the second side SI2 and the other end of the third side SI3, and extends in the first direction DR1. One end of the fourth side SI4 may be adjacent to the other end of the second side SI2, and the other end of the fourth side SI4 may be adjacent to the other end of the third side SI3.

[0163] One end of the first side SI1 and the other end can be defined as opposite ends of the first side SI1 in the first direction DR1. One end of the second side SI2 and the other end can be defined as opposite ends of the second side SI2 in the second direction DR2. One end of the third side SI3 and the other end can be defined as opposite ends of the third side SI3 in the second direction DR2. One end of the fourth side SI4 and the other end can be defined as opposite ends of the fourth side SI4 in the first direction DR1.

[0164] In the first direction DR1, the distance between the second side SI2 and the third side SI3 can be greater than the length of the first side SI1 and the length of the fourth side SI4. In the second direction DR2, the distance between the first side SI1 and the fourth side SI4 can be greater than the length of the second side SI2 and the length of the third side SI3.

[0165] When viewed in the second direction DR2, the first side SI1 and the fourth side SI4 can be positioned between the second side SI2 and the third side SI3. When viewed in the first direction DR1, the second side SI2 and the third side SI3 can be positioned between the first side SI1 and the fourth side SI4.

[0166] The first rounded corner CR1 can connect the first side SI1 and the second side SI2. For example, the first rounded corner CR1 can connect one end of the first side SI1 and the other end of the second side SI2 that are adjacent to each other. The first rounded corner CR1 can have a curved shape that bends convexly toward the non-display area NDA.

[0167] The second rounded corner CR2 can connect the first side SI1 and the third side SI3. For example, the second rounded corner CR2 can connect the other end of the first side SI1 and the end of the third side SI3 that are adjacent to each other. The second rounded corner CR2 can have a curved shape that bends convexly toward the non-display area NDA.

[0168] Two third rounded corners CR3 can connect the two ends of the fourth side SI4 to the other end of the second side SI2 and the other end of the third side SI3. One third rounded corner CR3 can connect the other end of the second side SI2 and the first end of the fourth side SI4 that are adjacent to each other. Another third rounded corner CR3 can connect the other end of the third side SI3 and the other end of the fourth side SI4 that are adjacent to each other. The third rounded corner CR3 can have a curved shape that bends convexly toward the non-display area NDA.

[0169] The first fillet CR1 and the second fillet CR2 can have shapes that are symmetrical to each other in the first direction DR1. The third fillet CR3 can have shapes that are symmetrical to each other in the first direction DR1. The first fillet CR1, the second fillet CR2, and the third fillet CR3 can have shapes that are symmetrical to each other in the second direction DR2.

[0170] The display panel (DP) may include multiple pixels (PX), multiple scan lines (SL1 to SLm), multiple data lines (DL1 to DLn), and multiple light-emitting lines (EML1 to EMLm). Pixels (PX) may be located within the display area (DA). Pixels (PX) may be connected to scan lines (SL1 to SLm), data lines (DL1 to DLn), and light-emitting lines (EML1 to EMLm).

[0171] Scan lines SL1 to SLm may include Figure 4The diagram illustrates scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. For example, among scan lines SL1 to SLm, the i-th scan line may include the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, and the i-th bias scan line GBLi. Therefore, the aforementioned scan signal can be applied to pixel PX through scan lines SL1 to SLm.

[0172] Data cables DL1 to DLn and LED cables EML1 to EMLm can be used with Figure 4 The data lines DL1 to DLn and the light-emitting lines EML1 to EMLm shown in the diagram are the same.

[0173] The scan driver SDV and the light-emitting driver EDV can be located in the non-display area NDA, adjacent to each other on opposite sides of the display panel DP in the first direction DR1. The scan driver SDV can be adjacent to the second side SI2, the first rounded corner CR1, and the third rounded corner CR3 connected to the second side SI2. The light-emitting driver EDV can be adjacent to the third side SI3, the second rounded corner CR2, and the third rounded corner CR3 connected to the third side SI3.

[0174] The portion of the scan driver SDV adjacent to the first rounded corner CR1 and the portion of the scan driver SDV adjacent to the third rounded corner CR3 connected to the second side SI2 may have a curved shape. The portion of the light-emitting driver EDV adjacent to the second rounded corner CR2 and the portion of the light-emitting driver EDV adjacent to the third rounded corner CR3 connected to the third side SI3 may have a curved shape.

[0175] Figure 4 The data drive DDV shown in the diagram can be as follows: Figure 8 The diagram shows that multiple data drivers (DDVs) are provided in the display panel DP. The data drivers (DDVs) can be located in the non-display area NDA adjacent to one of the two opposite sides of the display panel DP in the second direction DR2. When viewed in a flat plane, the data drivers (DDVs) can be adjacent to the lower end of the display panel DP. For example, the data drivers (DDVs) can be adjacent to the first side SI1.

[0176] Scan lines SL1 to SLm can extend along the first direction DR1 and can be connected to the pixel PX and the scan driver SDV. Data lines DL1 to DLn can extend along the second direction DR2 and can be connected to the pixel PX and the data driver DDV. Emitting lines EML1 to EMLm can extend along the first direction DR1 and can be connected to the pixel PX and the emitting driver EDV.

[0177] The data drivers DDV can be spaced apart from each other on the first direction DR1. A predetermined number of data lines can be connected to the data drivers DDV individually. Illustratively, two data drivers DDV are illustrated, but the number of data drivers DDV is not limited to this. For example, as the left and right areas of the display panel DP increase, the number of data drivers DDV can also be increased.

[0178] The pad PD can be located in the non-display area NDA adjacent to the lower end of the display panel DP, and can be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV can be connected to the pad PD. Data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0179] Figure 4 The timing controller TC and voltage generator VG shown in the diagram can be mounted on a printed circuit board and connected to the pad PD via the printed circuit board.

[0180] Figure 9 It is a separate icon setting Figure 8 The diagram shows a view of the construction of the first initialization line on the display panel. Figure 10 It is a separate icon setting Figure 8 The diagram shows a view of the construction of the second initialization line on the display panel. Figure 11a It is the display panel and Figure 9 The enlarged view of the portion adjacent to the first rounded corner in the diagram. Figure 11b It is the display panel and Figure 9 The enlarged view of the portion adjacent to the second rounded corner in the diagram. Figure 11c and Figure 11d It is the display panel and Figure 9 An enlarged view of the portion adjacent to the third rounded corner in the diagram.

[0181] Illustratively, Figure 9 and Figure 10 The diagram illustrates the scan driver SDV, the data driver DDV, and the light-emitting driver EDV, along with the first initialization line VIL1 and the second initialization line VIL2.

[0182] refer to Figure 9 and Figure 10 The first initialization line VIL1 may include multiple first vertical initialization lines VL1 and multiple first horizontal initialization lines HL1. The second initialization line VIL2 may include multiple second vertical initialization lines VL2 and multiple second horizontal initialization lines HL2.

[0183] Each of the first initialization line VIL1 and the second initialization line VIL2 can be defined as an initialization line. Furthermore, the first vertical initialization line VL1 and the second vertical initialization line VL2 can be defined as vertical initialization lines, and the first horizontal initialization line HL1 and the second horizontal initialization line HL2 can be defined as horizontal initialization lines.

[0184] The arrangement of the second vertical initialization line VL2 and the second horizontal initialization line HL2 can be substantially the same as the arrangement of the first vertical initialization line VL1 and the first horizontal initialization line HL1. Therefore, in the following text, the construction of the first vertical initialization line VL1 and the first horizontal initialization line HL1 will be mainly described, and the construction of the second vertical initialization line VL2 and the second horizontal initialization line HL2 will be briefly described.

[0185] The following will refer to Figure 12a and Figure 12b Describe the structure in which the first vertical initialization line VL1, the first horizontal initialization line HL1, the second vertical initialization line VL2, and the second horizontal initialization line HL2 are connected to the pixel PX.

[0186] The display panel DP may include a common line CL connected to the first initialization line VIL1 and a common line CL' connected to the second initialization line VIL2.

[0187] The common line CL may include the first common line CL1, the second-first common line CL2-1, and the second-second common line CL2-2. The common line CL' may include the first common line CL1', the second-first common line CL2-1', and the second-second common line CL2-2'.

[0188] The display panel DP may include a first repair initialization line RVIL1 extending from opposite sides of the first common line CL1 in the first direction DR1 and a second repair initialization line RVIL2 extending from opposite sides of the first common line CL1' in the first direction DR1.

[0189] The arrangement of the first common line CL1', the second-1 common line CL2-1', the second-2 common line CL2-2', and the first repair initialization line RVIL1 can be substantially the same as the arrangement of the first common line CL1, the second-1 common line CL2-1, the second-2 common line CL2-2, and the second repair initialization line RVIL2.

[0190] Therefore, the construction of the first common line CL1, the second-first common line CL2-1, the second-second common line CL2-2 and the first repair initialization line RVIL1 will be described in detail below, and the construction of the first common line CL1', the second-first common line CL2-1', the second-second common line CL2-2' and the second repair initialization line RVIL2 will be described briefly below.

[0191] refer to Figure 9 and Figures 11a to 11d The first vertical initialization line VL1 and the first horizontal initialization line HL1 can be set in the display area DA. The first vertical initialization line VL1 can extend in the second direction DR2 and be arranged in the first direction DR1. The first horizontal initialization line HL1 can extend in the first direction DR1 and be arranged in the second direction DR2.

[0192] In the display area DA, the first vertical initialization line VL1 and the first horizontal initialization line HL1 can extend to intersect each other. The first vertical initialization line VL1 and the first horizontal initialization line HL1 can be arranged to define a matrix shape.

[0193] The first vertical initialization line VL1 can be disposed adjacent to the first side SI1, the first fillet CR1, and the second fillet CR2, and extend in the second direction DR2. The first vertical initialization line VL1 can extend toward the third fillet CR3 and the fourth side SI4.

[0194] The first vertical initialization line VL1 can be set between a first fillet CR1 and a third fillet CR3 that face each other along the second direction DR2. Alternatively, the first vertical initialization line VL1 can be set between a second fillet CR2 and another third fillet CR3 that face each other along the second direction DR2.

[0195] The first vertical initialization line VL1 can be connected to the first horizontal initialization line HL1. The contact hole CH' can be positioned at the intersection of the first vertical initialization line VL1 and the first horizontal initialization line HL1, and the first vertical initialization line VL1 can be electrically connected to the first horizontal initialization line HL1 through the contact hole CH'. The structure of the contact hole CH' will be described below. Figure 13 The diagram in the middle is shown.

[0196] The first vertical initialization line VL1 can be connected to pixel PX. For example, the first vertical initialization line VL1 can be connected to pixel PX via the first horizontal initialization line HL1. This construction will be explained below. Figure 12a and Figure 12b The diagram in the middle is shown.

[0197] The common line CL can be disposed adjacent to at least one edge and at least one rounded corner that are adjacent to each other. The first vertical initialization line VL1 can be disposed adjacent to the at least one edge and the at least one rounded corner that are adjacent to each other, and can be connected to the common line CL.

[0198] For example, the common line CL can be set in the non-display area NDA and adjacent to the first side SI1, the first rounded corner CR1, and the second rounded corner CR2. The first vertical initialization line VL1 can be set adjacent to the first side SI1, the first rounded corner CR1, and the second rounded corner CR2, can extend to the non-display area NDA, and can be connected to the common line CL.

[0199] The first vertical initialization line VL1 can extend from the common line CL along the second direction DR2 and connect to the pixel PX within the display area DA. The second direction DR2 can be defined as the direction that intersects the extension direction of the first side SI1 (e.g., the first direction DR1).

[0200] The first common line CL1 can be set in the non-display area NDA. The first common line CL1 can be set adjacent to the first side SI1. The first common line CL1 can extend along the first direction DR1.

[0201] The second-first common line CL2-1 can be disposed in the non-display area NDA. The second-first common line CL2-1 can be adjacent to the first rounded corner CR1 and can have a curved shape corresponding to the first rounded corner CR1. However, this disclosure is not limited thereto, and the second-first common line CL2-1 can have a straight shape.

[0202] The second-2 common line CL2-2 can be located in the non-display area NDA. The second-2 common line CL2-2 can be adjacent to the second fillet CR2 and can have a curved shape corresponding to the second fillet CR2. However, this disclosure is not limited thereto, and the second-2 common line CL2-2 can also have a straight shape.

[0203] refer to Figure 11a and Figure 11b The second-first common line CL2-1 can extend between the scan driver SDV and the first rounded corner CR1. The second-first common line CL2-1 can be positioned between the scan driver SDV and the first rounded corner CR1. The second-first common line CL2-1 can be closer to the first rounded corner CR1 than the scan driver SDV.

[0204] The 2-2 common line CL2-2 can extend between the LED driver EDV and the second fillet CR2. The 2-2 common line CL2-2 can be positioned between the LED driver EDV and the second fillet CR2. The 2-2 common line CL2-2 can be closer to the second fillet CR2 than the LED driver EDV.

[0205] refer to Figure 9 and Figures 11a to 11d The second-1 common line CL2-1 and the second-2 common line CL2-2 can extend from the first common line CL1. The second-1 common line CL2-1 can extend in a curved shape from one side of the first common line CL1, and the second-2 common line CL2-2 can extend in a curved shape from the other side of the first common line CL1.

[0206] The first vertical initialization line VL1 can extend to the non-display area NDA and can be connected to the first common line CL1, the second-1 common line CL2-1, and the second-2 common line CL2-2.

[0207] In the first vertical initialization line VL1, the first vertical initialization line VL1 adjacent to the first side SI1 can be connected to the first common line CL1, and can extend from the first common line CL1 in the second direction DR2. The first vertical initialization line VL1 adjacent to the first side SI1 can extend toward the fourth side SI4.

[0208] In the first vertical initialization line VL1, the first vertical initialization line VL1 adjacent to the first fillet CR1 can be connected to the second-first common line CL2-1, and can extend from the second-first common line CL2-1 in the second direction DR2. The first vertical initialization line VL1 adjacent to the first fillet CR1 can extend toward the third fillet CR3 facing the first fillet CR1 in the second direction DR2.

[0209] In the first vertical initialization line VL1, the first vertical initialization line VL1 adjacent to the second fillet CR2 can be connected to the second-2 common line CL2-2, and can extend from the second-2 common line CL2-2 in the second direction DR2. The first vertical initialization line VL1 adjacent to the second fillet CR2 can extend toward the third fillet CR3 facing the second fillet CR2 in the second direction DR2.

[0210] The first horizontal initialization line HL1 may be adjacent to the first fillet CR1, the second side SI2, and the third fillet CR3 connected to the second side SI2, and may extend in the first direction DR1. The first horizontal initialization line HL1 may extend toward the second fillet CR2, the third side SI3, and the third fillet CR3 connected to the third side SI3.

[0211] The first common line CL1 can be connected to the first pad PD1. The first pad PD1 can be adjacent to the lower part of the display panel DP, and the data driver DDV can be disposed between the first pads PD1. However, the arrangement of the first pad PD1 is not limited to this. The first pad PD1 can receive the first initialization voltage VINT.

[0212] The common line CL may not be set in the non-display area NDA adjacent to the second side SI2, the third side SI3, the third rounded corner CR3, and the fourth side SI4.

[0213] refer to Figure 9 The first repair initialization line RVIL1 can extend between the display area DA and the scan driver SDV, and between the display area DA and the light-emitting driver EDV. The first repair initialization line RVIL1 can be adjacent to the scan driver SDV and the light-emitting driver EDV. The first repair initialization line RVIL1 can extend outward from the 2-1 common line CL2-1 and the 2-2 common line CL2-2.

[0214] The display panel (DP) may include multiple pixel repair circuits. For ease of description, these are not shown in the reduced view. Figure 9 The middle image shows the repair of the pixel circuit, while the enlarged image shows... Figures 11a to 11d The diagram in the middle shows the repair of the pixel circuit.

[0215] refer to Figures 11a to 11d The repair pixel circuit RPC can be located between the display area DA and the scan driver SDV, and between the display area DA and the light-emitting driver EDV. The repair pixel circuit RPC can be adjacent to both the scan driver SDV and the light-emitting driver EDV. The repair pixel circuit RPC can be located between the scan driver SDV and the first repair initialization line RVIL1 of the adjacent scan driver SDV. Furthermore, the repair pixel circuit RPC can be located between the light-emitting driver EDV and the first repair initialization line RVIL1 of the adjacent light-emitting driver EDV.

[0216] The first repair initialization line RVIL1 can be connected to the repair pixel circuit RPC. Each of the repair pixel circuit RPCs can be connected to... Figure 5 The pixel circuit PC shown in the diagram has the same construction.

[0217] Some pixel circuits (PCs) within a pixel (PX) may be damaged. Damaged pixel circuits (PCs) can be connected to repair pixel circuits (RPCs) via repair lines (not shown).

[0218] Since the repair pixel circuit RPC should be driven in the same way as the pixel circuit PC, the first initialization voltage VINT should also be applied to the repair pixel circuit RPC. The first repair initialization line RVIL1 can be connected to the repair pixel circuit RPC to apply the first initialization voltage VINT to the repair pixel circuit RPC.

[0219] refer to Figure 10The second vertical initialization line VL2 can extend along the second direction DR2, and the second horizontal initialization line HL2 can extend along the first direction DR1. The second vertical initialization line VL2 and the second horizontal initialization line HL2 can be set in the display area DA and intersect each other.

[0220] The second vertical initialization line VL2 may be adjacent to the first side SI1, the first fillet CR1, and the second fillet CR2 and extend in the second direction DR2. The second horizontal initialization line HL2 may be adjacent to the first fillet CR1, the second side SI2, and the third fillet CR3 connected to the second side SI2, and extend in the first direction DR1.

[0221] The second vertical initialization line VL2 can be connected to the second horizontal initialization line HL2 via a contact hole CH' defined at the intersection of the second vertical initialization line VL2 and the second horizontal initialization line HL2. The second vertical initialization line VL2 can be connected to pixel PX via the second horizontal initialization line HL2, and this configuration will be explained below. Figure 12a and Figure 12b The diagram in the middle is shown.

[0222] The first common line CL1', the second-first common line CL2-1', and the second-second common line CL2-2' can be disposed in the non-display area NDA. The first common line CL1' can be adjacent to the first edge SI1 and can extend in the first direction DR1. The second-first common line CL2-1' can be adjacent to the first rounded corner CR1 and can have a curved shape corresponding to the first rounded corner CR1. The second-second common line CL2-2' can be adjacent to the second rounded corner CR2 and can have a curved shape corresponding to the second rounded corner CR2.

[0223] The second-1 common line CL2-1' and the second-2 common line CL2-2' can extend from the first common line CL1'. The second vertical initialization line VL2 can extend to the non-display area NDA and can be connected to the first common line CL1', the second-1 common line CL2-1', and the second-2 common line CL2-2'. The second vertical initialization line VL2 can extend from the first common line CL1', the second-1 common line CL2-1', and the second-2 common line CL2-2' in the second direction DR2 and can be connected to the pixel PX within the display area DA.

[0224] The first common line CL1' can be connected to the second pad PD2, which is located adjacent to the lower part of the display panel DP and receives the second initialization voltage VAINT.

[0225] The common line CL' may not be set in the non-display area NDA adjacent to the second side SI2, the third side SI3, the third rounded corner CR3, and the fourth side SI4.

[0226] The second repair initialization line RVIL2 can extend between the display area DA and the scan driver SDV, and between the display area DA and the light-emitting driver EDV. The second repair initialization line RVIL2 can be adjacent to the scan driver SDV and the light-emitting driver EDV. The second repair initialization line RVIL2 can extend outward from the 2-1 common line CL2-1' and the 2-2 common line CL2-2'.

[0227] Although not shown in the enlarged view, the second repair initialization line RVIL2, like the first repair initialization line RVIL1, can be connected to... Figures 11a to 11d The diagram shows the repair pixel circuit RPC. Therefore, the repair pixel circuit RPC can receive the second initialization voltage VAINT through the second repair initialization line RVIL2.

[0228] Figure 12a It is a plan view illustrating the connection structure between the first initialization line, the second initialization line, and the pixel at the center of the display panel. Figure 12b It is a planar diagram illustrating the connection structure between the first initialization line, the second initialization line, and the pixel adjacent to the first rounded corner.

[0229] refer to Figure 12a and Figure 12b The display panel DP may include multiple pixel groups PG. Illustratively, the pixel groups PG can be arranged in a matrix on a first direction DR1 and a second direction DR2. The first direction DR1 may correspond to rows, and the second direction DR2 may correspond to columns. Therefore, the pixel groups PG can be arranged in multiple rows and multiple columns.

[0230] Each pixel in pixel group PG may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be associated with... Figure 5 and Figure 7 The pixel PXij in the diagram corresponds to this.

[0231] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can display different colors. For example, the first pixel PX1 can display red, the second pixel PX2 can display green, and the third pixel PX3 can display blue.

[0232] The first vertical initialization line VL1 and the second vertical initialization line VL2 may extend in the second direction DR2 and may be alternately arranged in the first direction DR1. The first vertical initialization line VL1 and the second vertical initialization line VL2 may be alternately arranged on the side of the pixel group PG arranged in columns. Illustratively, the first vertical initialization line VL1 and the second vertical initialization line VL2 may be alternately arranged on the right side of the pixel group PG arranged in columns, but the arrangement position of the first vertical initialization line VL1 and the second vertical initialization line VL2 is not limited to this.

[0233] The first horizontal initialization line HL1 and the second horizontal initialization line HL2 can be arranged in pairs adjacent to each other. A pair of first horizontal initialization lines HL1 and second horizontal initialization lines HL2 adjacent to each other can be arranged adjacent to the lower part of the pixel group PG in the corresponding row, but the arrangement position of the first horizontal initialization lines HL1 and second horizontal initialization lines HL2 is not limited to this.

[0234] The first horizontal initialization line HL1 can be connected to the first pixel PX1, the second pixel PX2, and the third pixel PX3, as well as the first vertical initialization line VL1. The first vertical initialization line VL1 can be connected to the first pixel PX1, the second pixel PX2, and the third pixel PX3 through the first horizontal initialization line HL1.

[0235] The second horizontal initialization line HL2 can be connected to the first pixel PX1, the second pixel PX2, and the third pixel PX3, as well as the second vertical initialization line VL2. The second vertical initialization line VL2 can be connected to the first pixel PX1, the second pixel PX2, and the third pixel PX3 through the second horizontal initialization line HL2.

[0236] The first pixel PX1, the second pixel PX2, and the third pixel PX3 adjacent to the first rounded corner CR1 can be connected to the first vertical initialization line VL1 and the second vertical initialization line VL2 adjacent to the first rounded corner CR1 through the first horizontal initialization line HL1 and the second horizontal initialization line HL2.

[0237] Figure 13 It is a diagram and Figure 9 The figure shows a cross-sectional view of the first vertical initialization line and the first horizontal initialization line corresponding to a contact hole.

[0238] refer to Figure 13 The first horizontal initialization line HL1 can be set on the fifth insulating layer INS5, and the sixth insulating layer INS6 can be set on the first horizontal initialization line HL1. The first vertical initialization line VL1 can be set on the sixth insulating layer INS6, and the seventh insulating layer INS7 can be set on the first vertical initialization line VL1.

[0239] Depending on the cross-sectional structure, the first vertical initialization line VL1 and the first horizontal initialization line HL1 can be set on different layers. The first vertical initialization line VL1 can be set above the first horizontal initialization line HL1.

[0240] The first horizontal initialization line HL1 can be connected to the fourth drain region D4 of the fourth transistor T4 through the first contact hole CH1' defined by the fourth insulating layer INS4 and the fifth insulating layer INS5. The first vertical initialization line VL1 can be connected to the first horizontal initialization line HL1 through the second contact hole CH2' defined by the sixth insulating layer INS6. Figure 9 The contact hole CH' shown in the diagram may include Figure 13 The diagram shows the first contact hole CH1' and the second contact hole CH2'.

[0241] The first vertical initialization line VL1 can be connected to the fourth transistor T4 via the first horizontal initialization line HL1. The first initialization voltage VINT can be provided to the fourth transistor T4 via the first vertical initialization line VL1 and the first horizontal initialization line HL1.

[0242] Although not illustrated, the second vertical initialization line VL2 and the second horizontal initialization line HL2 can be disposed on the same layer as the first vertical initialization line VL1 and the first horizontal initialization line HL1, respectively. Furthermore, the second vertical initialization line VL2 and the second horizontal initialization line HL2 can be connected with substantially the same connection structure as the first vertical initialization line VL1 and the first horizontal initialization line HL1. The second vertical initialization line VL2 can be connected to the seventh transistor T7 via the second horizontal initialization line HL2.

[0243] Figure 14 This is a view illustrating the construction of a comparison display panel according to an embodiment.

[0244] Illustratively, Figure 14 Is with Figure 9 The corresponding floor plan, and in the following text, will focus on the... Figure 9 The diagram illustrates different construction methods while describing them. Figure 14 The structure is shown in the diagram.

[0245] refer to Figure 14 The first common line CL1 can be positioned adjacent to the first side SI1. The first vertical initialization line VL1 can be connected to the first common line CL1. Figure 9 Unlike other systems, the first common line CL1 connected to the first vertical initialization line VL1 may not be adjacent to the first fillet CR1 and the second fillet CR2.

[0246] The first vertical initialization line VL1 may not be adjacent to the first fillet CR1 and the second fillet CR2. The first vertical initialization line VL1 may not be located between the first fillet CR1 and the third fillet CR3 that are opposite each other along the second direction DR2, or between the second fillet CR2 and the third fillet CR3 that are opposite each other along the second direction DR2.

[0247] The areas between the first fillet CR1 and the third fillet CR3 that are opposite each other on the second direction DR2, and between the second fillet CR2 and the third fillet CR3 that are opposite each other on the second direction DR2, can be defined as side areas SA. The areas between side areas SA can be defined as central areas CA, and the first vertical initialization line VL1 can be set in the central area CA.

[0248] When the first vertical initialization line VL1 is not set in the side area SA and is set in the central area CA, the line resistance of the pixel PX set in the central area CA and the line resistance of the pixel PX set in the side area SA may be different from each other. In this case, a difference may occur between the image quality of the pixel PX set in the central area CA and the image quality of the pixel PX set in the side area SA, and therefore the display quality may be reduced.

[0249] Although not illustrated, in a comparison display panel DP, the second initialization line VIL2 and the common line connected to the second initialization line VIL2 can also be configured in essentially the same way as the first initialization line VIL1 and the first common line CL1. Therefore, as described above, the display quality may be reduced.

[0250] refer to Figure 9 and Figure 10 In the embodiments of this disclosure, the first vertical initialization line VL1 and the second vertical initialization line VL2 may also be set... Figure 14 In the side region SA shown in the diagram, the line resistance of the pixel PX located in the central region CA and the line resistance of the pixel PX located in the side region SA can become more consistent. Therefore, the difference between the image quality of the pixel PX located in the central region CA and the image quality of the pixel PX located in the side region SA can be reduced, and thus the display quality can be improved.

[0251] Figures 15 to 17 This is a view illustrating the construction of common lines according to an embodiment of the present disclosure.

[0252] Illustratively, in relation to Figure 9 The corresponding planar diagram is shown. Figures 15 to 17 And below we will focus on... Figure 9 The different constructions shown in the text are described simultaneously. Figures 15 to 17 The structure shown in the figure.

[0253] also, Figures 15 to 17 The diagram shows common lines CL-1, CL-2, and CL-3 connected to the first initialization line VIL1, but the common lines connected to the second initialization line VIL2 can also have essentially the same form as common lines CL-1, CL-2, and CL-3.

[0254] refer to Figure 15 The common line CL-1 can extend along the first side SI1, the second side SI2, and the third side SI3, as well as the first rounded corner CR1, the second rounded corner CR2, and the third rounded corner CR3. The common line CL-1 can be arranged adjacent to the first side SI1, the second side SI2, and the third side SI3, as well as the first rounded corner CR1, the second rounded corner CR2, and the third rounded corner CR3.

[0255] The first vertical initialization line VL1 can be connected to the common line CL-1. Figure 9 In contrast, the first vertical initialization line VL1 can be further connected to the common line CL-1 adjacent to the third fillet CR3.

[0256] refer to Figure 16 The common line CL-2 can be configured to surround the display area DA. Therefore, with Figure 15 In contrast, the common line CL-2 can be further extended along the fourth side SI4.

[0257] The first vertical initialization line VL1 can be connected to the common line CL-2. Figure 15 In contrast, the first vertical initialization line VL1 can extend to the non-display area NDA and further connect to the common line CL-2 adjacent to the fourth side SI4.

[0258] refer to Figure 17 The common line CL-3 can be configured to surround the display area DA. The first vertical initialization line VL1 can extend to the non-display area NDA and can be connected to the common line CL-3. The first horizontal initialization line HL1 can extend to the non-display area NDA and can be connected to the common line CL-3.

[0259] Although embodiments have been described above, those skilled in the art will understand that various modifications and alterations can be made to this disclosure without departing from the spirit and scope of the disclosure as set forth in the appended claims. Furthermore, it should be understood that the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, and that all technical spirit within the appended claims and their equivalents is included within the scope of this disclosure. Industrial applicability

[0260] Since this invention can provide users with a display device that can improve display quality by uniformly forming the line resistance of pixels in the display area, it has high industrial applicability.

Claims

1. A display device, comprising: Multiple pixels are set in the display area; Multiple scan lines are connected to the pixel; Multiple data lines are connected to the pixel; Multiple vertical initialization lines are connected to the pixel; and The common line is located in the non-display area surrounding the display area. The display area includes a first side extending in a first direction, a second side adjacent to one end of the first side and extending in a second direction intersecting the first direction, and a first rounded corner connecting the one end of the first side to the end of the second side adjacent to the one end of the first side. Wherein, the common line is adjacent to the first side and the first rounded corner, and The vertical initialization line is adjacent to the first side and the first rounded corner, connected to the common line, and extends from the common line in the second direction.

2. The display device according to claim 1, wherein, The common line is not located in the non-display area adjacent to the second side.

3. The display device according to claim 1, wherein, The common line includes: A first common line is disposed in the non-display area and adjacent to the first side; and The second-1 common line is located in the non-display area and is adjacent to the first rounded corner.

4. The display device according to claim 3, wherein, The first common line extends in the first direction, and the second-first common line extends from the first common line and has a curved shape corresponding to the first rounded corner.

5. The display device according to claim 3, wherein, The first common line is connected to the pad that receives the initialization voltage.

6. The display device according to claim 3, further comprising: A scan driver is disposed in the non-display area, adjacent to the second side and the first rounded corner, and connected to the scan line.

7. The display device according to claim 6, wherein, The second-1 common line is disposed between the scan driver and the first fillet.

8. The display device according to claim 6, further comprising: Repair the initialization line, which extends from the first common line between the display area and the scan line; as well as The pixel circuitry is positioned between the display area and the scan line, and adjacent to the scan driver. The repair initialization line is connected to the pixel circuit.

9. The display device according to claim 3, wherein, The display area further includes a third side adjacent to the other end of the first side and extending in the second direction, and a second rounded corner connecting the other end of the first side to the end of the third side adjacent to the other end of the first side. The common line further includes a second-2 common line disposed in the non-display area and adjacent to the second rounded corner, and The vertical initialization line is further disposed adjacent to the second rounded corner, further connected to the second-2 common line, and extends from the second-2 common line in the second direction.

10. The display device according to claim 9, wherein, The common line is not located in the non-display area adjacent to the third side.

11. The display device according to claim 9, wherein, The second-2 common line extends from the first common line and has a curved shape corresponding to the second rounded corner.

12. The display device according to claim 9, further comprising: Multiple light-emitting lines are connected to the pixel; as well as A light-emitting driver is disposed in the non-display area, adjacent to the third side and the second rounded corner, and connected to the light-emitting line.

13. The display device according to claim 12, wherein, The second-2 common line is disposed between the light-emitting driver and the second rounded corner.

14. The display device according to claim 1, further comprising: Multiple horizontal initialization lines are provided in the display area and extend to intersect with the vertical initialization lines.

15. The display device according to claim 14, wherein, The horizontal initialization line is connected to the vertical initialization line and the pixel.

16. The display device according to claim 15, wherein, The vertical initialization line and the horizontal initialization line are set on different layers.

17. The display device according to claim 16, wherein, The vertical initialization line is positioned above the horizontal initialization line.

18. The display device according to claim 14, wherein, The common line is configured to surround the display area, and The vertical initialization line and the horizontal initialization line extend to the non-display area and connect to the common line.

19. A display device, comprising: Multiple pixels are set in the display area; Multiple scan lines are connected to the pixel; Multiple data lines are connected to the pixel; A common line is disposed in a non-display area surrounding the display area; and Multiple vertical initialization lines are connected to the pixel. The display area includes a first side extending in a first direction, a second side and a third side extending in a second direction adjacent to both ends of the first side and intersecting the first direction, a first rounded corner connecting the first side and the second side, and a second rounded corner connecting the first side and the second side. Wherein, the common line is adjacent to the first edge, the first rounded corner, and the second rounded corner, and The vertical initialization line is adjacent to the first side, the first rounded corner, and the second rounded corner, connects to the common line, and extends from the common line in the second direction.

20. The display device according to claim 19, wherein, The common line is not located in any of the non-display areas adjacent to the second side and the third side.

21. A display device, comprising: Multiple pixels are disposed within a display area, the display area comprising the sides of a quadrilateral extending in a first direction and in a second direction intersecting the first direction, and rounded corners connecting the sides; Multiple scan lines are connected to the pixel; Multiple data lines are connected to the pixel; A common line is disposed in a non-display area surrounding the display area and is adjacent to at least one of the edges and at least one of the rounded corners that are adjacent to each other. as well as Multiple vertical initialization lines are arranged adjacent to the at least one edge and the at least one rounded corner, and are connected to the pixel and the common line. The vertical initialization line extends from the common line in a direction that intersects the extension direction of the at least one edge.

Images