Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including a word line extending in a direction perpendicular to a substrate, a plurality of channel layers surrounding the word line, having a ring-shaped horizontal cross section surrounding the word line in a plan view, a plurality of bit lines disposed at one end of each of the plurality of channel layers in a first direction, a plurality of capacitors disposed at the other end of each of the plurality of channel layers in the first direction, having a ring-shaped horizontal cross section in a plan view, the plurality of capacitors being spaced apart from each other in a direction perpendicular to the substrate, and a plurality of protection layers disposed between two capacitors adjacent in the direction perpendicular to the substrate and at the one end of the plurality of capacitors in the first direction, can avoid the influence of a thermal budget of a capacitor manufacturing process on the channel layers, and improve the density and performance of a three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] Due to the development of electronic technology, the miniaturization of semiconductor devices has progressed rapidly. Three-dimensional memory has received widespread attention and research because of its small footprint, high storage density, and low production cost per unit storage cell.

[0003] However, as the number of storage cell layers in 3D memory increases and the density becomes larger, the distance between the capacitor and the channel layer in 3D memory becomes smaller and smaller. The thermal budget of the capacitor manufacturing process has a more and more obvious impact on the channel layer, affecting the performance of 3D memory and increasing the manufacturing difficulty of 3D memory. Summary of the Invention

[0004] Based on this, embodiments of this application provide a semiconductor device and a method for fabricating a semiconductor device, which can protect the channel layer in a three-dimensional memory, avoid the impact of the thermal budget of the capacitor fabrication process on the channel layer, and improve the density and performance of the three-dimensional memory.

[0005] In a first aspect, this application provides a semiconductor device according to some embodiments, comprising: Word lines, which extend in a direction perpendicular to the substrate; Multiple channel layers surround the word line and have an annular horizontal cross section surrounding the word line in a top view; the multiple channel layers are spaced apart from each other in a direction perpendicular to the substrate. Multiple bit lines are disposed at one end of each of the multiple channel layers along a first direction and extend along a second direction and are spaced apart from each other in a direction perpendicular to the substrate, wherein the first direction and the second direction are perpendicular. A plurality of capacitors are disposed at the other end of each of the plurality of channel layers along a first direction, having an annular horizontal cross section in a top view, the plurality of capacitors being spaced apart from each other in a direction perpendicular to the substrate; Multiple protective layers are disposed between two adjacent capacitors along a direction perpendicular to the substrate, and located at one end of the multiple capacitors along a first direction near the multiple channel layers.

[0006] In some embodiments, the plurality of capacitors includes: Multiple lower electrode layers are electrically connected to the multiple channel layers respectively. Each of the multiple lower electrode layers has an annular horizontal cross section and includes a vertical cross section with a U-shape rotated 90 degrees. An upper electrode layer extends in a direction perpendicular to the substrate and is located within the annular holes of the plurality of lower electrode layers; A capacitor dielectric layer is located between the plurality of lower electrode layers and the upper electrode layer.

[0007] In some embodiments, the upper electrode layer includes a plurality of first protrusions located within a U-shape rotated 90 degrees in the plurality of lower electrode layers, the plurality of first protrusions having an annular horizontal cross section, and the U-shaped groove of the lower electrode layer conformally covering the first protrusions.

[0008] In some embodiments, the upper electrode layer further includes a plurality of second protrusions disposed between the plurality of lower electrode layers in a direction perpendicular to the substrate, the plurality of second protrusions having a fan-shaped horizontal cross section, the central angle of the fan-shaped section facing away from the capacitor.

[0009] In some embodiments, the plurality of protective layers are disposed between the plurality of lower electrode layers in a direction perpendicular to the substrate, and the plurality of protective layers and the plurality of lower electrode layers are disposed alternately.

[0010] In some embodiments, the plurality of protective layers include a vertical cross-section with a U-shape rotated 90 degrees, the opening direction of the vertical cross-section of the U-shape of the plurality of protective layers being opposite to the opening direction of the vertical cross-section of the U-shape of the plurality of lower electrode layers in a first direction.

[0011] In some embodiments, the capacitor dielectric layer conformally overlaps with the surfaces of the first protrusion and the second protrusion of the upper electrode layer.

[0012] In some embodiments, the horizontal cross-section of the word line has a circular or elliptical shape, the word line has a plurality of raised sections along a direction perpendicular to the substrate, and the plurality of channel layers surround the word line and are disposed between the plurality of raised sections.

[0013] In some embodiments, the channel layer comprises an oxide semiconductor material, a group IV semiconductor material, a group III-V compound semiconductor material, an epitaxial semiconductor material, or a two-dimensional semiconductor material.

[0014] In some embodiments, the channel layer includes a first doped region at one end in contact with a bit line in a first direction and a second doped region at the other end in contact with a capacitor.

[0015] Secondly, according to some embodiments, this application also provides a method for fabricating a semiconductor device, comprising: A substrate is provided on which word lines are formed, the word lines extending in a direction perpendicular to the substrate; Multiple channel layers are formed around the word line, having an annular horizontal cross section around the word line in a top view, and the multiple channel layers are spaced apart from each other in a direction perpendicular to the substrate; Multiple bit lines are formed, which are disposed at one end of each of the multiple channel layers along a first direction and extend along a second direction and are spaced apart from each other in a direction perpendicular to the substrate, wherein the first direction and the second direction are perpendicular. A plurality of capacitors are formed, the plurality of capacitors being disposed at the other end of each of the plurality of channel layers along a first direction, having an annular horizontal cross section in a top view, the plurality of capacitors being spaced apart from each other in a direction perpendicular to the substrate; Multiple protective layers are formed, which are disposed between two adjacent capacitors along a direction perpendicular to the substrate and located at one end of the multiple capacitors along a first direction near the multiple channel layers.

[0016] In some embodiments, the process includes, prior to forming the bit line: A substrate is provided on which a multilayer structure of alternating first dielectric layers and second dielectric layers is formed; The stacked structure is etched to form bit line vias, and the bit line is formed within the bit line vias.

[0017] In some embodiments, the forming capacitance includes: The stacked structure is etched to form capacitor vias and word line vias, and multiple lower electrode layers are formed in the capacitor vias and multiple protective layers are formed in the word line vias. A capacitor dielectric layer and an upper electrode layer are formed within the capacitor via.

[0018] In some embodiments, forming word lines includes: Multiple channel layers and conductive material for filling the word lines are formed within the through-holes.

[0019] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects: The semiconductor device and its fabrication method provided in this application include a semiconductor device in which multiple protective layers are disposed between two adjacent capacitors along a direction perpendicular to the substrate, and located at one end of the multiple capacitors along a first direction near the multiple channel layers, thereby avoiding the influence of the thermal budget of the capacitor fabrication process on the channel layers and improving the density and performance of the three-dimensional memory. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A three-dimensional schematic diagram of a semiconductor device provided in an embodiment of this application; Figure 2 for Figure 1 A top view of a local area; Figure 3 for Figure 2 A schematic diagram along section AA; Figures 4-10 A three-dimensional schematic diagram of a method for forming a semiconductor device provided in an embodiment of this application; Explanation of reference numerals in the attached figures: 100: Substrate; 101: First dielectric layer; 102: Second dielectric layer; 200: Bit line; 300: Capacitor; 301: Lower electrode layer; 302: Capacitor dielectric layer; 303: Upper electrode layer; 3031: First bump; 3032: Second bump; 304: Capacitor interconnect; 400: Protective layer; 501: Word line; 502: Gate oxide layer; 600: Channel layer; 700: Disconnect layer; T1: Capacitor via; T2: Word line via; T3: Bit line groove. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms "first," "second," etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0025] Spatial relation terms such as “on top of” can be used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “on top of” will be oriented “below” other elements or features. Therefore, the exemplary term “on top of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0027] Figure 1This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device includes a word line 501 extending in a direction perpendicular to the substrate (e.g., the Z direction), a plurality of channel layers 600 surrounding the word line 501, having an annular horizontal cross-section surrounding the word line 501 in a top view, the plurality of channel layers 600 being spaced apart from each other in a direction perpendicular to the substrate (e.g., the Z direction), and a plurality of bit lines 200 disposed at one end of each of the plurality of channel layers 600 in a first direction (e.g., the X direction) and extending in a second direction (e.g., the Y direction) and spaced apart from each other in a direction perpendicular to the substrate (e.g., the Z direction). A plurality of capacitors 300 are spaced apart, with the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) perpendicular to each other. The plurality of capacitors 300 are disposed at the other end of each of a plurality of channel layers 600 along the first direction (e.g., the X direction) and have an annular horizontal cross-section in a top view. The plurality of capacitors 300 are spaced apart from each other along a direction perpendicular to the substrate (e.g., the Z direction). A plurality of protective layers 400 are disposed between two adjacent capacitors 300 along a direction perpendicular to the substrate (e.g., the Z direction) and located at one end of the plurality of capacitors 300 along the first direction (e.g., the X direction) near the plurality of channel layers. The multiple protective layers 400 in the semiconductor device, disposed between two adjacent capacitors 300 along a direction perpendicular to the substrate (e.g., the Z direction) and located at one end of the plurality of capacitors 300 along the first direction (e.g., the X direction) near the plurality of channel layers, isolate the channel layers 600 from the capacitors 300, avoid the impact of the thermal budget of the capacitor fabrication process on the channel layers 600, and improve the density and performance of the three-dimensional memory.

[0028] Continue to refer to Figure 1 In some embodiments of this application, the semiconductor device includes a substrate 100, a capacitor 300, a channel layer 600, and bit lines 200 stacked in a direction perpendicular to the substrate 100 (e.g., the Z direction). Word lines 501 extend along a direction perpendicular to the substrate (e.g., the Z direction). The substrate 100 can be a single-crystal silicon wafer, a polycrystalline silicon wafer, a germanium-silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other wafers on which semiconductor devices are formed. The substrate may be doped with one or more of germanium, carbon, phosphorus, boron, arsenic, gallium, or indium to improve the conductivity of the substrate. Multiple word lines 501 extend along a direction perpendicular to the substrate 100 (e.g., the Z direction) and are distributed in an array on the substrate. The horizontal cross-section of the word lines 501 can be circular, elliptical, square, or other polygonal patterns. Figure 2 , Figure 2 for Figure 1Partial top view. In some embodiments, the word line further includes multiple protrusions in a direction perpendicular to the substrate, and the channel layer 600 is located between adjacent protrusions. The multiple protrusions and the channel layer 600 are alternately spaced, which can increase the horizontal cross-sectional width of the word line, reduce the conductivity resistance of the word line, and at the same time increase the fabrication window of the word line and improve the stability of the word line. The word line 501 is a material with conductive properties, such as at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials such as tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides are used. In some embodiments, the word line 501 may comprise multiple layers, such as a conductive barrier layer. A gate oxide layer 502 is disposed around the word line 501, conformally covering the word line 501. The gate oxide layer 502 may be at least one selected from high-k dielectric materials or ferroelectric materials having a dielectric constant higher than that of silicon oxide. In some embodiments, the gate oxide layer 502 may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). In some embodiments, the gate oxide layer 502 may comprise a metal oxide containing a dopant, for example, the dopant may comprise at least one of zirconium (Zr), gadolinium (Gd), lanthanum (La), silicon (Si), or aluminum (Al), but is not limited thereto. In some examples, the gate oxide layer 502 may comprise hafnium oxide with a specific concentration of dopant.

[0029] Continue to refer to Figure 1 and Figure 2Multiple channel layers 600 surround word lines 501 and have an annular horizontal cross-section surrounding word lines 501. The multiple channel layers 600 are spaced apart from each other in a direction perpendicular to the substrate (e.g., the Z direction). The horizontal cross-section of the channel layer 600 can be circular, elliptical, square, or other polygonal. One end of the channel layer 600 is connected to the capacitor 300 along a first direction (e.g., the X direction), and the other end is connected to the bit line 200. In some embodiments, the material of the channel layer 600 can be monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, doped monocrystalline silicon, germanium silicon, doped germanium silicon, etc. In some embodiments, the material of the channel layer 600 may include oxide semiconductor materials, group IV semiconductor materials, group III-V compound semiconductor materials, epitaxial semiconductor materials, or two-dimensional semiconductor materials, for example, oxide semiconductor materials such as In-Ga oxide (IGO), In-Zn oxide (IZO), and In-Ga-Zn oxide (IGZO), group IV semiconductor materials such as Si or Ge, group III-V compound semiconductor materials such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), epitaxial semiconductor materials formed by selective epitaxial growth (EG) processes, and two-dimensional semiconductor materials such as MoS2, MoSe2, ReS2, HfSe2, InSe, GeSe, WSe2, graphene, and carbon nanotubes. In some embodiments, the channel region 600 may be doped with a variety of ions, such as boron, nitrogen, phosphorus or other metal ions. One end of the channel region 600 connected to the bit line has a first doped region, and the other end connected to the capacitor 300 has a second doped region. The first doped region and the second doped region can reduce the resistance at the connection points with the capacitor and the bit line, respectively.

[0030] Continue to refer to Figure 1 and Figure 2 In some embodiments, a plurality of capacitors 300 are disposed at the other end of each of a plurality of channel layers 600 along a first direction (e.g., the X direction), having an annular horizontal cross-section in a top view, and the plurality of capacitors 300 are spaced apart from each other in a direction perpendicular to the substrate (e.g., the Z direction). The capacitors include a lower electrode layer 301, an upper electrode layer 303, and a capacitor dielectric layer 302 located between the upper electrode layer 303 and the lower electrode layer 301. In some embodiments, the lower electrode layer 301 has an annular horizontal cross-section, such as being circular, elliptical, square, or other polygonal, and is connected to one end of the channel layer 600 in the first direction (e.g., the X direction). The material of the lower electrode layer 301 is a conductive material, such as at least one of the following: single-crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single-crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicides, etc.

[0031] Figure 3 for Figure 2 A schematic diagram along section AA, combined with Figure 1 and Figure 2 In some embodiments, the lower electrode layer 301 further has a U-shaped vertical cross-section rotated 90 degrees. The lower electrode layer 302 includes a first portion extending perpendicular to the substrate direction (e.g., the Z direction) and a second and third portion extending horizontally. The second and third portions are respectively connected to both ends of the first portion to form a U-groove. The first, second, and third portions all have annular cross-sections. In some embodiments, the lengths of the second portion extending at different angles in the horizontal direction can be different, and the lengths of the third portion extending at different angles in the horizontal direction can also be different. In some embodiments, the lengths of the second portion extending in the same horizontal direction and the lengths of the third portion extending in the horizontal direction can be different. Multiple lower electrode layers 301 are stacked along a direction perpendicular to the substrate (e.g., the Z direction), and there is a gap between the multiple lower electrode layers 301.

[0032] Continue to refer to Figure 1 , Figure 2 and Figure 3In some embodiments, the upper electrode layer 303 extends along a direction perpendicular to the substrate (e.g., the Z direction), penetrates multiple lower electrode layers 301, and is located within an annular hole of the lower electrode layer 301. The upper electrode layer 303 has a horizontal cross-section that is annular, elliptical, square, or other polygonal, and is conformally oriented with the lower electrode layer 301. In some embodiments, the upper electrode layer 303 further has multiple first protrusions 3031, which are spaced apart along a direction perpendicular to the substrate (e.g., the Z direction). The multiple first protrusions 3031 have a horizontal cross-section that is annular, elliptical, square, or other polygonal, and are conformally oriented with the lower electrode layer 301, and are located within a U-shaped groove of the lower electrode layer 301. The U-shaped groove of the lower electrode layer 301 conformally covers the first protrusions 3031. In some embodiments, the upper electrode layer 303 further includes a plurality of second protrusions 3032, which are spaced apart along a direction perpendicular to the substrate (e.g., the Z direction). Simultaneously, the first protrusions 3031 and the second protrusions 3032 are also spaced apart along a direction perpendicular to the substrate (e.g., the Z direction). The second protrusions 3032 have a fan-shaped horizontal cross-section. In some embodiments, the central angle of the fan-shaped section faces away from the capacitor, and the central angle can be 60°, 90°, 120°, 150°, 180°, or 210°, or other angles. In some embodiments, the material of the upper electrode is a material with conductive properties, such as at least one of the following materials: single-crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single-crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides. The material of the upper electrode layer 303 can be the same as or different from that of the lower electrode layer 301.

[0033] Continue to refer to Figure 1 In some embodiments, the semiconductor device further includes a capacitor interconnect 304, which is connected to the upper electrode layer 303, located on the upper electrode layer 303, and connected to a plurality of upper electrode layers 303 arranged along the second direction. In some embodiments, the capacitor interconnect 304 may be integrally formed with the upper electrode layer 303, and the material of the capacitor interconnect 304 is a material with conductive properties, such as at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicides, etc.

[0034] Continue to refer to Figure 1 , Figure 2 and Figure 3 In some embodiments, the capacitor dielectric layer 302 is located between the lower electrode layer 301 and the upper electrode layer 303. The capacitor dielectric layer 302 is conformally located within the U-shaped groove of the lower electrode layer 301. In some embodiments, the capacitor dielectric layer 302 also conformally covers the surface of the upper electrode layer 303 and the first protrusion 3031 and the second protrusion 3032. The material of the capacitor dielectric layer 302 may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O), or lead scandium tantalum oxide (PbScTaO).

[0035] Continue to refer to Figure 1 , Figure 2 and Figure 3 In some embodiments, the semiconductor device further includes a plurality of protective layers 400 stacked in a direction perpendicular to the substrate (e.g., the Z direction) and a plurality of lower electrode layers arranged alternately on the surface of the lower electrode layer at the end that contacts the channel layer. In some embodiments, the protective layer 400 has a fan-shaped horizontal cross-section, and the central angle of the fan-shaped protective layer 400 and the central angle of the second protrusion 3032 are mutually combined, i.e., the sum of the central angle of the fan-shaped protective layer 400 and the central angle of the second protrusion 3032 is 360°. In some embodiments, the protective layer 400 has a U-shaped vertical cross-section rotated 90 degrees in a direction perpendicular to the substrate (e.g., the Z direction), and the opening direction of the U-shaped vertical cross-section of the protective layer is opposite to the opening direction of the U-shaped vertical cross-section of the lower electrode layer 301 in a first direction. In other embodiments, the protective layer 400 fills between two adjacent lower electrode layers 301 in a direction perpendicular to the substrate (e.g., the Z direction), and one end of the protective layer is flush with the end of the lower electrode layer 301 away from the channel layer 600. The protective layer 400 is made of one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon oxycarbonate, or silicon oxide.

[0036] Continue to refer to Figure 1 , Figure 2 and Figure 3In some embodiments, the semiconductor device has multiple bit lines 200 extending along a second direction (e.g., the Y direction), spaced apart in a direction perpendicular to the substrate (e.g., the Z direction), and connected to one end of the channel layer in a first direction (e.g., the X direction). The bit lines 200 are connected to a first doped region of the channel layer 600. In some embodiments, a protective layer 400 is also located between two adjacent bit lines 200 in a direction perpendicular to the substrate (e.g., the Z direction), and the protective layer 400 and the bit lines 200 are spaced apart in a direction perpendicular to the substrate (e.g., the Z direction). In some embodiments, the material of the bit lines is a material with conductive properties, such as at least one of the following: single-crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single-crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials such as tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides can be used. The bit line 200 can have one layer or multiple layers. In other embodiments, there can also be a contact layer, such as a metal silicide layer, between the bit line 200 and the channel layer 600, which can reduce the contact resistance between the bit line 200 and the channel layer 600.

[0037] Continue to refer to Figure 1 In some embodiments, the semiconductor device further includes a partition layer 700 located on the substrate 100, which separates adjacent bit lines 200 along a first direction (e.g., the X direction). The material of the partition layer 700 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbide nitride. In other embodiments, the partition layer 700 may also have an air gap, which can reduce the parasitic capacitance between adjacent bit lines 200.

[0038] Figures 4-10 This is a three-dimensional schematic diagram of a method for forming a semiconductor device provided in an embodiment of this application.

[0039] refer to Figure 4In some embodiments, a substrate 100 is provided, on which a first dielectric layer 101 and a second dielectric layer 102 are sequentially stacked. The first dielectric layer 101 and the second dielectric layer 102 are stacked sequentially in a direction perpendicular to the substrate (e.g., the Z direction). In some embodiments, the substrate 10 may be a single-crystal silicon wafer, a polycrystalline silicon wafer, a germanium-silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other wafers on which semiconductor devices are formed. The substrate may be doped with one or more of germanium, carbon, phosphorus, boron, arsenic, gallium, or indium to improve the conductivity of the substrate. The first dielectric layer 101 and the second dielectric layer 102 may be one of single-crystal silicon, polycrystalline silicon, germanium-silicon, silicon oxide, silicon nitride, or silicon oxynitride. The first dielectric layer 101 and the second dielectric layer 102 may have different etching selectivity ratios. In some embodiments, an etching stop layer may be provided between the first dielectric layer 101 and the substrate 100, which can protect the substrate 100 during etching of the first dielectric layer 101 and the second dielectric layer 102. A mask layer is formed on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, and a plurality of capacitor vias T1 and a plurality of word line vias T2 are patterned and etched, penetrating the stacked structure of the first dielectric layer 101 and the second dielectric layer 102. The plurality of capacitor vias T1 are arranged in an array along a first direction (e.g., the X direction) and a second direction (e.g., the Y direction), and the capacitor vias T1 and word line vias T2 are arranged alternately in the first direction (e.g., the X direction). In some embodiments, the horizontal cross-section of the capacitor vias T1 and the word line vias T2 is circular, elliptical, square, or other polygonal, and the horizontal cross-sectional shape of the capacitor vias T1 and the horizontal cross-sectional pattern of the word line vias T2 may be different. A sacrificial layer is filled into the capacitor via T1 and the word line via T2, and then ground flat. The sacrificial layer can be spin-coated carbon, silicon oxide compound, or other materials that are easily etched away.

[0040] refer to Figure 5In some embodiments, a mask layer is formed on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, and a bit line groove T3 is patterned and etched. The bit line groove T3 penetrates the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, dividing the stacked structure of the first dielectric layer 101 and the second dielectric layer 102 along a first direction (e.g., the X direction). In some embodiments, during the formation of the bit line groove T3, by adjusting the etching conditions, the second dielectric layer 102 on both sides of the bit line groove T3 is selectively removed, and the formed bit line groove T3 exposes the word line via T2. Conductive material is filled into the bit line groove T3, and the groove is ground and flattened to form bit line 200. Bit line 200 fills the gaps where the second dielectric layer 102 has been removed and the portion of bit line groove T3 perpendicular to the substrate direction (e.g., the Z direction). The material of bit line 200 is a conductive material, such as at least one of the following: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used for filling bit lines include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides. Bit lines 200 can have one or multiple layers. In other embodiments, a contact layer, such as a metal silicide layer, can be present between the bit line 200 and the channel layer 600 to reduce the contact resistance between the bit line 200 and the channel layer 600. Methods for filling bit lines can include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In some embodiments, the voids where the second dielectric layer 102 has been removed can be filled first, followed by filling the portion of the bit line groove T3 perpendicular to the substrate direction (e.g., the Z direction), or other multi-step methods. The material deposited each time can be the same or different.

[0041] refer to Figure 6A mask layer is deposited on the stacked surface of the first dielectric layer 101 and the second dielectric layer 102, and patterned etching is performed to reopen the capacitor via T1. Alternatively, selective etching is used to remove sacrificial material from the capacitor via T1 to reopen it. In some embodiments, during the process of reopening the capacitor via T1, the etching conditions are adjusted to selectively etch away a portion of the second dielectric layer 102 surrounding the capacitor via T1. In some embodiments, the void left by the removed portion of the second dielectric layer 102 has an annular horizontal cross-section surrounding the capacitor via T1. The annular horizontal cross-section can be circular, elliptical, square, or other polygonal. A conductive material is deposited in the voids left by the removal of the second dielectric layer 102 to form a lower electrode layer 301. The lower electrode layer 301 conformally covers the sidewalls of the voids left by the removal of the second dielectric layer 102. The lower electrode layer 301 has an annular horizontal cross-section, such as a circle, ellipse, square, or other polygon. In some embodiments, the lower electrode layer 301 also has a U-shaped vertical cross-section rotated 90 degrees. The lower electrode layer 302 includes a first portion extending perpendicular to the substrate direction (e.g., the Z direction) and a second and third portion extending in a horizontal direction. The second and third portions are respectively connected to the two ends of the first portion to form a U-groove. The first, second, and third portions all have an annular cross-section. In some embodiments, the lengths of the second portion extending in the horizontal direction at different angles can be different, and the lengths of the third portion extending in the horizontal direction at different angles can be different. In some embodiments, the lengths of the second portion extending in the same horizontal direction and the lengths of the third portion extending in the horizontal direction can be different. Multiple lower electrode layers 301 are stacked in a direction perpendicular to the substrate (e.g., the Z direction), and there is a gap between the multiple lower electrode layers 301. The material of the lower electrode layer 301 is a conductive material, such as at least one of the following: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicides, etc.Methods for forming the lower electrode layer 301 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In some embodiments, an atomic layer deposition (ALD) process can be used to form a conductive material layer inside the capacitor via T1, and then the sidewall of the original capacitor via T1, i.e., the portion along the direction perpendicular to the substrate (e.g., the Z direction), can be etched away. This can sever the connection between two adjacent lower electrode layers 301 along the direction perpendicular to the substrate (e.g., the Z direction). A sacrificial material layer is then filled and polished flat.

[0042] refer to Figure 7In some embodiments, a mask layer is deposited on the stacked surface of the first dielectric layer 101 and the second dielectric layer 102, and patterned etching is performed to reopen the word line via T2, or selective etching is used to remove sacrificial material in the word line via T2 to reopen the word line via T2. In some embodiments, during the reopening process of forming the word line via T2, the etching conditions are adjusted to selectively etch away a portion of the first dielectric layer 101 surrounding the word line via T2. In some embodiments, the void left by the removed portion of the first dielectric layer 101 has an annular horizontal cross-section surrounding the word line via T2, which can be circular, elliptical, square, or other polygonal. An insulating material is deposited at the void left by the removed portion of the first dielectric layer 101 to form a protective layer 400. The protective layer 400 conformally covers the sidewalls of the void left by the removed portion of the first dielectric layer 101. The protective layer 400 has an annular horizontal cross-section, which can be, for example, circular, elliptical, square, or other polygonal. In some embodiments, the protective layer 400 has a U-shaped vertical cross-section rotated 90 degrees in a direction perpendicular to the substrate (e.g., the Z direction), and the opening direction of the U-shaped vertical cross-section of the protective layer is opposite to the opening direction of the U-shaped vertical cross-section of the lower electrode layer 301 in a first direction. In other embodiments, the protective layer 400 completely fills the space between two adjacent lower electrode layers 301 in a direction perpendicular to the substrate (e.g., the Z direction), with one end of the protective layer flush with the end of the lower electrode layer 301 away from the channel layer 600. The material of the protective layer 400 is one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon oxycarbide, or silicon oxide, and the material of the protective layer 400 is different from the material of the first dielectric layer 101, having an etching selectivity. Methods for forming the protective layer 400 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In some embodiments, an insulating material layer may be first formed in the word line via T2 using atomic layer deposition (ALD), and then the sidewall of the word line via T2, i.e., the portion along the direction perpendicular to the substrate (e.g., the Z direction), may be etched away, a sacrificial material layer may be filled, and the surface may be polished flat.

[0043] refer to Figure 8In some embodiments, a mask layer is deposited on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, and patterned etching is performed to reopen the capacitor via T1. Alternatively, selective etching is used to remove sacrificial material from the capacitor via T1, thereby reopening the capacitor via T1 and exposing the lower electrode layer 301. In some embodiments, during the reopening process of forming the capacitor via T1, the etching conditions are adjusted to selectively etch away a portion of the first dielectric layer 101 surrounding the capacitor via T1. In some embodiments, since the material of the first dielectric layer 101 is different from the material of the protective layer 400, the first dielectric layer 101 can be selectively removed while retaining the protective layer 400. Therefore, the void left by the removed portion of the first dielectric layer 101 has a fan-shaped horizontal cross-section surrounding the capacitor via T1. A conductive material is filled into the capacitor via T1 to form the upper electrode layer 303. In some embodiments, the upper electrode layer 303 extends along a direction perpendicular to the substrate (e.g., the Z direction), penetrates multiple lower electrode layers 301, and is located within an annular hole of the lower electrode layer 301. The upper electrode layer 303 has a horizontal cross-section that is annular, elliptical, square, or other polygonal, and conforms to the lower electrode layer 301. In some embodiments, the upper electrode layer 303 further has multiple first protrusions 3031, which are spaced apart along a direction perpendicular to the substrate (e.g., the Z direction). The multiple first protrusions 3031 have a horizontal cross-section that is annular, elliptical, square, or other polygonal, and conform to the lower electrode layer 301, and are located within a U-shaped groove of the lower electrode layer 301. The U-shaped groove of the lower electrode layer 301 conformally covers the first protrusions 3031. In some embodiments, the upper electrode layer 303 further includes a plurality of second protrusions 3032 located at a portion of the first dielectric layer 101 surrounding the capacitor via T1. The plurality of second protrusions 3032 are spaced apart along a direction perpendicular to the substrate (e.g., the Z-direction), while the first protrusions 3031 and second protrusions 3032 are also spaced apart along a direction perpendicular to the substrate (e.g., the Z-direction). The second protrusions 3032 have a fan-shaped horizontal cross-section. In some embodiments, the central angle of the fan-shaped section faces away from the connection point with the capacitor. The central angle can be 60°, 90°, 120°, 150°, 180°, or 210°, etc. (Reference) Figure 2 and Figure 3 In some embodiments, the upper electrode is made of a conductive material, such as at least one of the following: single-crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single-crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used for the upper electrode layer 303 include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides. The material of the upper electrode layer 303 can be the same as or different from the material of the lower electrode layer 301. Methods for forming the upper electrode layer 303 can include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0044] Continue to refer to Figure 8 , Figure 2 and Figure 3In some embodiments, before depositing the upper electrode 303, a capacitor dielectric layer 302 is also deposited in the capacitor via T1. The capacitor dielectric layer 302 is located between the lower electrode layer 301 and the upper electrode layer 303. The capacitor dielectric layer 302 conformally covers the U-shaped groove of the lower electrode layer 301. In some embodiments, the capacitor dielectric layer 302 also conformally covers the surface of the upper electrode layer 303 and the first protrusion 3031 and the second protrusion 3032. The material of the capacitor dielectric layer 302 may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O), or lead scandium tantalum oxide (PbScTaO). Methods for forming the capacitor dielectric layer 302 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), etc.

[0045] refer to Figure 8 and Figure 9In some embodiments, during the deposition of the upper electrode layer 303, a conductive material layer can be formed on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, ground and flattened, a mask layer is formed on the conductive material layer, and a capacitor interconnect 304 is patterned and etched. The capacitor interconnect 304 is connected to the upper electrode layer 303, located on the upper electrode layer 303, and connected to a plurality of upper electrode layers 303 arranged along the second direction. In some embodiments, the capacitor interconnect 304 can be integrally formed with the upper electrode layer 303, and the material of the capacitor interconnect 304 is a material with conductive properties, such as at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicides, etc.

[0046] refer to Figure 10In some embodiments, a mask layer is deposited on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102, and patterned etching is performed to reopen the word line via T2, or selective etching is used to remove the sacrificial material in the word line via T2 to reopen the word line via T2. In some embodiments, during the process of reopening the word line via T2, the etching conditions are adjusted to selectively etch away a portion of the second dielectric layer 102 around the word line via T2, exposing the bit line 200 and the lower electrode layer 301 in a first direction (e.g., the X direction). In some embodiments, the void left by the removed portion of the second dielectric layer 102 has an annular horizontal cross-section around the word line via T2, which can be circular, elliptical, square, or other polygonal. Semiconductor material is deposited in the gaps left by the removal of the second dielectric layer 102 to form a channel layer 600. The channel layer 600 conformally covers the sidewalls of the gaps left by the removal of the second dielectric layer 102. Multiple channel layers 600 are spaced apart from each other in a direction perpendicular to the substrate (e.g., the Z direction). Multiple channel layers 600 and multiple protective layers 400 are stacked alternately in a direction perpendicular to the substrate (e.g., the Z direction). The channel layer 600 has an annular horizontal cross section, which can be circular, elliptical, square or other polygonal. In some embodiments, the material of the channel layer 600 may be single-crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single-crystal silicon, germanium silicon, doped germanium silicon, etc. In some embodiments, the material of the channel layer 600 may include oxide semiconductor materials, group IV semiconductor materials, group III-V compound semiconductor materials, epitaxial semiconductor materials, or two-dimensional semiconductor materials, etc. For example, it may include oxide semiconductor materials such as In-Ga oxide (IGO), In-Zn oxide (IZO), and In-Ga-Zn oxide (IGZO); it may include group IV semiconductor materials such as Si or Ge; it may include group III-V compound semiconductor materials such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP); and the epitaxial semiconductor material formed by selective epitaxial growth (EG) may include two-dimensional semiconductor materials such as MoS2, MoSe2, ReS2, HfSe2, InSe, GeSe, WSe2, graphene, and carbon nanotubes. In some embodiments, the channel region 600 may be doped with a variety of ions, such as boron, nitrogen, phosphorus or other metal ions. One end of the channel region 600 connected to the bit line has a first doped region, and the other end connected to the capacitor 300 has a second doped region. The first doped region and the second doped region can reduce the resistance at the connection points with the capacitor and the bit line, respectively.Methods for forming the channel layer 600 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In some embodiments, the channel layer material can be formed on the sidewall of the word line via T2 by atomic layer deposition (ALD), and then the channel material on the sidewall of the word line via T2 is etched away. Since the channel material is formed in the voids left by the removal of part of the second dielectric layer 102, it will not be etched away, thus forming a channel layer 600 that is alternately stacked with the protective layer 400 in a direction perpendicular to the substrate (e.g., the Z direction).

[0047] Continue to refer to Figure 2 , Figure 3 and Figure 10 In some embodiments, during the etching process of reopening the word line via T2, the etching conditions can be adjusted to selectively etch a portion of the protective layer 400 around the word line via T2. In some embodiments, the gap left by the removed portion of the protective layer 400 has an annular horizontal cross-section surrounding the word line via T2. The annular horizontal cross-section can be circular, elliptical, square, or other polygonal. Conductive material is filled into the word line via, and the surface is ground flat to form the word line 501. The word line 501 extends along a direction perpendicular to the substrate 100 (e.g., the Z direction) and is distributed in an array on the substrate. The horizontal cross-section of the word line 501 can be circular, elliptical, square, or other polygonal patterns. In some embodiments, the word line also includes multiple protrusions in the direction perpendicular to the substrate, with a channel layer 600 located between adjacent protrusions. The multiple protrusions and the channel layer 600 are alternately spaced, which can increase the horizontal cross-sectional width of the word line, reduce the conductivity resistance of the word line, and simultaneously increase the fabrication window and improve the stability of the word line. The word line 501 is made of a conductive material, such as at least one of the following: monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, doped monocrystalline silicon, germanium silicon, doped germanium silicon, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), and metal silicides. In some embodiments, word line 501 may comprise multiple layers, such as a conductive barrier layer.

[0048] Continue to refer to Figure 2 , Figure 3 and Figure 10 In some embodiments, a gate oxide layer 502 is deposited before filling the word line conductive material. The gate oxide layer 502 is disposed around the word line 501 and conformally covers the word line 501. The gate oxide layer 502 may be at least one selected from high-k dielectric materials or ferroelectric materials having a dielectric constant higher than that of silicon oxide. In some embodiments, the gate oxide layer 502 may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). In some embodiments, the gate oxide layer 502 may comprise a metal oxide containing a dopant, for example, the dopant may comprise at least one of zirconium (Zr), gadolinium (Gd), lanthanum (La), silicon (Si), or aluminum (Al), but is not limited thereto. In some examples, the gate oxide layer 502 may comprise hafnium oxide with a specific concentration of dopant.

[0049] Continue to refer to Figure 1 In some embodiments, a mask layer is formed on the stacked structure of the first dielectric layer 101 and the second dielectric layer 102. The bit line groove T3 is patterned and etched to reopen the stacked structure of the first dielectric layer 101 and the second dielectric layer 102. The bit line groove T3 penetrates the stacked structure of the first dielectric layer 101 and the second dielectric layer 102 and divides the stacked structure of the first dielectric layer 101 and the second dielectric layer 102 along a first direction (e.g., the X direction). The bit line groove T3 is filled with insulating material and polished flat to form a partition layer 700. The partition layer 700 is located on the substrate 100 and separates adjacent bit lines 200 along the first direction (e.g., the X direction). The material of the partition layer 700 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or silicon carbide nitride. In other embodiments, the partition layer 700 may also have an air gap, which can reduce the parasitic capacitance between adjacent bit lines 200.

[0050] By first forming a protective layer 400 in the three-dimensional memory, then forming a capacitor 300, and finally forming a channel layer 600 and word line 501, the protective layer is located around the channel layer 600. This can isolate the mutual influence between the fabrication process of the capacitor 301 and the fabrication processes of the bit line 200 and the isolation layer 700. At the same time, it can avoid the influence of the thermal budget of the capacitor fabrication process on the channel layer 600, thereby improving the density and performance of the three-dimensional memory and reducing the fabrication difficulty of the three-dimensional memory.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Word lines, which extend in a direction perpendicular to the substrate; Multiple channel layers surround the word line and have an annular horizontal cross section surrounding the word line in a top view; the multiple channel layers are spaced apart from each other in a direction perpendicular to the substrate. Multiple bit lines are disposed at one end of each of the multiple channel layers along a first direction and extend along a second direction and are spaced apart from each other in a direction perpendicular to the substrate, wherein the first direction and the second direction are perpendicular. A plurality of capacitors are disposed at the other end of each of the plurality of channel layers along a first direction, having an annular horizontal cross section in a top view, the plurality of capacitors being spaced apart from each other in a direction perpendicular to the substrate; Multiple protective layers are disposed between two adjacent capacitors along a direction perpendicular to the substrate, and located at one end of the multiple capacitors along a first direction near the multiple channel layers.

2. The semiconductor device according to claim 1, characterized in that, The plurality of capacitors includes: Multiple lower electrode layers are electrically connected to the multiple channel layers respectively. Each of the multiple lower electrode layers has an annular horizontal cross section and includes a vertical cross section with a U-shape rotated 90 degrees. An upper electrode layer extends in a direction perpendicular to the substrate and is located within the annular holes of the plurality of lower electrode layers; A capacitor dielectric layer is located between the plurality of lower electrode layers and the upper electrode layer.

3. The semiconductor device according to claim 2, characterized in that, The upper electrode layer includes a plurality of first protrusions located within a U-shape rotated 90 degrees in the plurality of lower electrode layers. The plurality of first protrusions have an annular horizontal cross section, and the U-shaped groove of the lower electrode layer conformally covers the first protrusions.

4. The semiconductor device according to claim 3, characterized in that, The upper electrode layer further includes a plurality of second protrusions, which are disposed between the plurality of lower electrode layers in a direction perpendicular to the substrate. The plurality of second protrusions have a fan-shaped horizontal cross section, with the central angle of the fan-shaped section pointing away from the capacitor.

5. The semiconductor device according to claim 2, characterized in that, The plurality of protective layers are disposed between the plurality of lower electrode layers in a direction perpendicular to the substrate, and the plurality of protective layers and the plurality of lower electrode layers are disposed alternately.

6. The semiconductor device according to claim 5, characterized in that, The plurality of protective layers include a U-shaped vertical cross-section with a 90-degree rotation, the opening direction of the U-shaped vertical cross-section of the plurality of protective layers being opposite to the opening direction of the U-shaped vertical cross-section of the plurality of lower electrode layers in a first direction.

7. The semiconductor device according to claim 4, characterized in that, The capacitor dielectric layer conformally overlaps with the surfaces of the first protrusion and the second protrusion of the upper electrode layer.

8. The semiconductor device according to claim 5, characterized in that, The horizontal cross-section of the character line has a circular or elliptical shape, and the character line has multiple raised sections along a direction perpendicular to the substrate. The multiple channel layers surround the character line and are disposed between the multiple raised sections.

9. The semiconductor device according to claim 5, characterized in that, The channel layer includes oxide semiconductor materials, group IV semiconductor materials, group III-V compound semiconductor materials, epitaxial semiconductor materials, or two-dimensional semiconductor materials.

10. The semiconductor device according to claim 5, characterized in that, The channel layer includes a first doped region at one end in contact with the bit line in a first direction and a second doped region at the other end in contact with the capacitor.

11. A method for fabricating a semiconductor device, characterized in that, A substrate is provided on which word lines are formed, the word lines extending in a direction perpendicular to the substrate; Multiple channel layers are formed around the word line, having an annular horizontal cross section around the word line in a top view, and the multiple channel layers are spaced apart from each other in a direction perpendicular to the substrate; Multiple bit lines are formed, which are disposed at one end of each of the multiple channel layers along a first direction and extend along a second direction and are spaced apart from each other in a direction perpendicular to the substrate, wherein the first direction and the second direction are perpendicular. A plurality of capacitors are formed, the plurality of capacitors being disposed at the other end of each of the plurality of channel layers along a first direction, having an annular horizontal cross section in a top view, the plurality of capacitors being spaced apart from each other in a direction perpendicular to the substrate; Multiple protective layers are formed, which are disposed between two adjacent capacitors along a direction perpendicular to the substrate and located at one end of the multiple capacitors along a first direction near the multiple channel layers.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, Before forming the bit line, the following is included: A substrate is provided on which a multilayer structure of alternating first dielectric layers and second dielectric layers is formed; The stacked structure is etched to form bit line vias, and the bit line is formed within the bit line vias.

13. The method for fabricating a semiconductor device according to claim 12, wherein forming the capacitor comprises: The stacked structure is etched to form capacitor vias and word line vias, and multiple lower electrode layers are formed in the capacitor vias and multiple protective layers are formed in the word line vias. A capacitor dielectric layer and an upper electrode layer are formed within the capacitor via.

14. The method for fabricating a semiconductor device according to claim 13, wherein forming word lines comprises: Multiple channel layers and conductive material for filling the word lines are formed within the through-holes.

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