Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the semiconductor device comprises a plurality of storage units which are distributed in different layers and are distributed in a stacking manner in the direction perpendicular to a substrate; each layer comprises a plurality of storage units which are distributed at intervals along the row direction and the column direction; the memory cell includes a transistor; the transistor comprises a first electrode, a second electrode, and a semiconductor layer, a gate insulating layer, a ferroelectric layer and a gate electrode which are positioned between the first electrode and the second electrode and are sequentially distributed; the extending direction of the word line is the same as that of the semiconductor layer, and the gate electrode is a part of the word line; the bit line and the source line are respectively connected with the first electrode and the second electrode of the row of storage units which are distributed at intervals; the extension directions of the bit lines and the source lines are the same; the extension direction of the bit lines is perpendicular to the extension direction of the word lines; and the bit line and the source line are positioned on the same side of the column of memory cells connected with the bit line and the source line. The semiconductor device is simple in structure and high in storage density.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device has a simple structure and high storage density.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Multiple memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; each layer includes multiple memory cells spaced apart along row and column directions parallel to the substrate; each memory cell includes a transistor; each transistor includes a first electrode, a second electrode, a semiconductor layer located between the first electrode and the second electrode, and a gate electrode, wherein a gate insulating layer and a ferroelectric dielectric layer are provided between the semiconductor layer and the gate electrode, and the ferroelectric dielectric layer is located between the gate electrode and the gate insulating layer;

[0008] A word line extends through the transistor, and the gate electrode is a part of the word line; the extension direction of the word line is the same as the extension direction of the semiconductor layer.

[0009] Bit lines and source lines are respectively connected to the first electrode and the second electrode, which are spaced apart along the extension direction of the semiconductor layer; the extension direction of the bit lines is the same as the extension direction of the source lines; the extension direction of the bit lines is perpendicular to the extension direction of the word lines.

[0010] The bit line and the source line are located on the same side of the semiconductor layer away from the gate electrode.

[0011] In some embodiments of this application, the semiconductor layer at least partially surrounds the word line; the first electrode and the second electrode are located on the sidewalls of the semiconductor layer;

[0012] The bit line is located on the side of the first electrode away from the semiconductor layer, and the source line is located on the side of the second electrode away from the semiconductor layer.

[0013] In some embodiments of this application, the semiconductor layer exposes at least a portion of the sidewalls of the word line.

[0014] In some embodiments of this application, the semiconductor layer has opposing first and second sidewalls and a third sidewall connected to the same side of the first and second sidewalls, the first, second, and third sidewalls surrounding the word line, and the side of the first and second sidewalls away from the third sidewall having an opening that exposes the sidewall of the word line.

[0015] In some embodiments of this application, the outer contour of the semiconductor layer in a cross section perpendicular to the extension direction of the semiconductor layer is "C" shaped.

[0016] In some embodiments of this application, both the semiconductor layer and the word line extend along the column direction; the word line passes through transistors of a plurality of memory cells spaced apart along the column direction;

[0017] Both the bit line and the source line extend in a direction perpendicular to the substrate; the bit line and the source line are respectively connected to the first electrode and the second electrode of a plurality of memory cells stacked in a direction perpendicular to the substrate.

[0018] In some embodiments of this application, both the semiconductor layer and the word line extend in a direction perpendicular to the substrate; the word line passes through transistors of a plurality of memory cells stacked in a direction perpendicular to the substrate;

[0019] Both the bit line and the source line extend along the column direction; the bit line and the source line are respectively connected to the first electrode and the second electrode of a plurality of memory cells that are spaced apart along the column direction.

[0020] In some embodiments of this application, the semiconductor layers of two adjacent memory cells in any direction are spaced apart.

[0021] In some embodiments of this application, the gate insulating layer of a column of memory cells spaced apart along the column direction is a single, integral structure; and / or,

[0022] The gate insulating layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is a single, integral structure; and / or,

[0023] The ferroelectric dielectric layer of a column of memory cells spaced apart along the column direction is a single, integral structure; and / or,

[0024] The ferroelectric dielectric layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is a single-piece structure.

[0025] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0026] Multiple first sacrificial layers and multiple second sacrificial layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0027] The stacked structure is patterned and etched, and the patterned stacked structure includes a main region extending along a column direction parallel to the substrate and a plurality of branch regions connected to both sides of the main region and distributed at intervals.

[0028] Remove at least one end of the branch region away from the main region of the second sacrificial layer, and form an electrode groove between two adjacent first sacrificial layers in the branch region;

[0029] An electrode is formed within the electrode groove, the electrode comprising a first electrode and a second electrode;

[0030] A conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate.

[0031] The backbone region is broken in a row direction parallel to the substrate, exposing the second sacrificial layer of the backbone region;

[0032] Remove the second sacrificial layer and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode;

[0033] A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode extending along the column direction are sequentially formed in the gate trench; a plurality of gate electrodes distributed along the column direction are connected together to form a word line extending along the column direction.

[0034] In some embodiments of this application, removing at least one end of the second sacrificial layer of the branch region away from the main trunk region, and forming an electrode trench between two adjacent first sacrificial layers in the branch region, includes:

[0035] Etching is performed on the end of the branch region away from the trunk region to form a first via extending in a direction toward the substrate in the branch region, the first via exposing the second sacrificial layer of the branch region;

[0036] The second sacrificial layer of the branch region is laterally etched within the first through-hole to remove at least one end of the second sacrificial layer of the branch region away from the main region, thereby forming the electrode trench between two adjacent first sacrificial layers of the branch region.

[0037] In some embodiments of this application, the electrode is formed in the electrode groove, the electrode including a first electrode and a second electrode, comprising:

[0038] An electrode is formed in the electrode groove, the electrode is located between two adjacent first sacrificial layers in the branch region, and the electrode exposes a portion of the sidewall of the first sacrificial layer in the branch region;

[0039] In the column direction, any two adjacent electrodes are either a first electrode or a second electrode; a plurality of first electrodes are stacked and spaced apart in a direction perpendicular to the substrate, and a plurality of second electrodes are stacked and spaced apart in a direction perpendicular to the substrate.

[0040] In some embodiments of this application, a conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate, comprising:

[0041] A conductive layer is formed in each of the first through holes, the conductive layer being connected to the electrode and extending in a direction perpendicular to the substrate;

[0042] The conductive layer connected to the first electrode is a bit line; the conductive layer connected to the second electrode is a source line.

[0043] In some embodiments of this application, the step of breaking the backbone region in a row direction parallel to the substrate to expose the second sacrificial layer of the backbone region includes:

[0044] A barrier layer covering the conductive layer is formed on the substrate;

[0045] The barrier layer and the backbone region are etched to form a trench in the backbone region extending in a direction toward the substrate. The trench penetrates the backbone region in the column direction, breaking the backbone region in the row direction parallel to the substrate, thus exposing the second sacrificial layer of the backbone region.

[0046] In some embodiments of this application, the removal of the second sacrificial layer involves forming a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode; and sequentially forming a semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode within the gate trench, comprising:

[0047] Laterally etch the second sacrificial layers on both sides in the trench to remove all of the second sacrificial layers, and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing a plurality of electrodes spaced apart along the column direction;

[0048] A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode layer are sequentially formed on the inner walls of the trench and the gate trench.

[0049] Disconnect the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer located in different layers, and disconnect the semiconductor layer in the column direction;

[0050] The remaining gate electrode layer consists of word lines including the gate electrode.

[0051] In some embodiments of this application, disconnecting the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer located in different layers, and disconnecting the semiconductor layer in the column direction, includes:

[0052] Remove the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer from the end face of the trench that covers the first sacrificial layer;

[0053] Remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, each group of electrodes comprising two adjacent electrodes distributed along the column direction.

[0054] In some embodiments of this application, removing the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer covering the end face of the first sacrificial layer on the sidewall of the trench includes:

[0055] The semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer on the sidewalls and bottom wall of the trench are etched in the trench to expose the end face of the first sacrificial layer extending along the column direction;

[0056] An insulating layer is filled into the trench.

[0057] In some embodiments of this application, the removal of the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, each group of electrodes comprising two adjacent electrodes distributed along the column direction, includes:

[0058] Two adjacent electrodes distributed along the column direction are used as a group of electrodes. An isolation hole extending toward the substrate is formed between two adjacent groups of electrodes distributed along the column direction. The isolation hole exposes the semiconductor layer on the sidewall of the gate trench.

[0059] The exposed semiconductor layer is etched within the isolation hole to remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, while retaining the semiconductor layer located between each group of electrodes on the sidewall of the gate trench. The retained semiconductor layer is connected to the two electrodes of each group of electrodes.

[0060] An isolation layer is filled into the isolation hole.

[0061] In some embodiments of this application, the manufacturing method further includes: after removing the semiconductor layer located between two adjacent sets of electrodes on the sidewalls of the gate trench,

[0062] Remove the gate insulating layer and the ferroelectric dielectric layer located between two adjacent sets of electrodes on the sidewall of the gate trench, and disconnect the gate insulating layer and the ferroelectric dielectric layer on the sidewall of the gate trench in the column direction.

[0063] In some embodiments of this application, the step of sequentially and alternately depositing multiple first sacrificial layers and multiple second sacrificial layers on a substrate to obtain a stacked structure includes:

[0064] A first sacrificial layer and a second sacrificial layer are sequentially and alternately deposited on the substrate to obtain an initial stacked structure consisting of multiple first sacrificial layers and multiple second sacrificial layers;

[0065] The initial stacked structure is etched along the direction toward the substrate to form at least one isolation trench extending along the column direction in the initial stacked structure, the isolation trench spacing the initial stacked structure into a plurality of stacked structures spaced apart along the row direction;

[0066] An insulating layer is filled in the isolation groove, and adjacent stacked structures are isolated from each other by the insulating layer.

[0067] In some embodiments of this application, the patterning etching of the stacked structure includes:

[0068] The stacked structure is etched along the direction toward the substrate to form a plurality of second vias penetrating the stacked structure. The plurality of second vias are spaced apart in the row and column directions parallel to the substrate. The stacked structure is divided into the main region and the plurality of branch regions by the plurality of second vias.

[0069] An insulating layer is filled into the second through hole.

[0070] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0071] The semiconductor device in this application embodiment places the bit line BL and the source line SL on the same side of the semiconductor layer away from the gate electrode, that is, the bit line BL and the source line SL are located on the same side of the memory cell, which can reduce the area of ​​the memory cell, and the structure is simple, which can achieve higher storage density and simplify the word line formation process.

[0072] Furthermore, the semiconductor device in this application embodiment uses the gate electrode of the transistor to control the switching of the channel. The polarization reversal of the ferroelectric dielectric layer can be achieved through the voltage difference between the gate electrode and the bit line. The different polarization states of the ferroelectric dielectric layer cause the threshold voltage of the transistor to change, resulting in a change in the switching state of the transistor, thereby enabling the reading of stored information.

[0073] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0074] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0075] Figure 1A A three-dimensional structural schematic diagram of a semiconductor device as an exemplary embodiment of this application;

[0076] Figure 1B for Figure 1A The diagram shows a cross-sectional view of the semiconductor device parallel to the substrate.

[0077] Figure 1C for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section aa' perpendicular to the substrate;

[0078] Figure 1D for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb').

[0079] Figure 1E for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0080] Figure 1F for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0081] Figure 2 A three-dimensional structural schematic diagram of another semiconductor device according to an exemplary embodiment of this application;

[0082] Figure 3 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0083] Figure 4A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the initial stacked structure is formed, on a section aa' perpendicular to the substrate;

[0084] Figure 4B for Figure 4A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0085] Figure 4C for Figure 4A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0086] Figure 4D for Figure 4A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0087] Figure 5A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a stacked structure, on a section perpendicular to the substrate (aa').

[0088] Figure 5B for Figure 5A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0089] Figure 5C for Figure 5A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0090] Figure 5D for Figure 5A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0091] Figure 6A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after filling an insulating layer in an isolation trench;

[0092] Figure 6B for Figure 6A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0093] Figure 6C for Figure 6A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0094] Figure 6D for Figure 6A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0095] Figure 7A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a second via, on a section parallel to the substrate;

[0096] Figure 7B for Figure 7A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section aa' perpendicular to the substrate;

[0097] Figure 7C for Figure 7A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0098] Figure 8A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after filling an insulating layer into a second via;

[0099] Figure 8B for Figure 8A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section aa' perpendicular to the substrate;

[0100] Figure 8C for Figure 8A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0101] Figure 9A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first through-hole, on a section parallel to the substrate;

[0102] Figure 9B for Figure 9A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb').

[0103] Figure 9C for Figure 9A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0104] Figure 10A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method, after forming electrode trenches, in a section parallel to the substrate, as an exemplary embodiment of this application;

[0105] Figure 10B for Figure 10A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb').

[0106] Figure 10C for Figure 10A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0107] Figure 11A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of electrodes, on a section parallel to the substrate;

[0108] Figure 11B for Figure 11A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb').

[0109] Figure 11C for Figure 11A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0110] Figure 12A This is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method after the formation of a conductive layer, which is an exemplary embodiment of this application, on a section parallel to the substrate.

[0111] Figure 12B for Figure 12A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb').

[0112] Figure 12C for Figure 12A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0113] Figure 13AThis is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method after the formation of a barrier layer, which is an exemplary embodiment of this application, on a section aa' perpendicular to the substrate.

[0114] Figure 13B for Figure 13A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0115] Figure 13C for Figure 13A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0116] Figure 13D for Figure 13A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0117] Figure 14A This is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method after the formation of a conductive layer, which is an exemplary embodiment of this application, on a section parallel to the substrate.

[0118] Figure 14B for Figure 14A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section aa' perpendicular to the substrate;

[0119] Figure 14C for Figure 14A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0120] Figure 14D for Figure 14A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0121] Figure 14E for Figure 14A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0122] Figure 15A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method after forming a gate trench, in a section perpendicular to the substrate, according to an exemplary embodiment of this application.

[0123] Figure 15B for Figure 15A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0124] Figure 15C for Figure 15A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0125] Figure 15D for Figure 15A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0126] Figure 16A This is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the gate electrode layer is formed in the trench and gate trench, on a section parallel to the substrate.

[0127] Figure 16B for Figure 16A The diagram shows a schematic longitudinal section of the semiconductor structure on the section aa' perpendicular to the substrate.

[0128] Figure 16C for Figure 16A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0129] Figure 16D for Figure 16A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0130] Figure 16E for Figure 16A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0131] Figure 17A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing the semiconductor layer on the inner wall of the trench;

[0132] Figure 17B for Figure 17A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0133] Figure 17C for Figure 17A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0134] Figure 17D for Figure 17A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0135] Figure 18A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after filling the trench with an insulating layer;

[0136] Figure 18B for Figure 18AThe diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section.

[0137] Figure 18C for Figure 18A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate;

[0138] Figure 18D for Figure 18A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate;

[0139] Figure 19A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of an isolation hole, on a section parallel to the substrate;

[0140] Figure 19B for Figure 19A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure on the cc' section perpendicular to the substrate;

[0141] Figure 20A This is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing the semiconductor layer between two adjacent sets of electrodes, on a section parallel to the substrate.

[0142] Figure 20B for Figure 20A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure on the cc' section perpendicular to the substrate;

[0143] Figure 21 This is a schematic diagram of the cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing the semiconductor layer between two adjacent sets of electrodes, in a section parallel to the substrate. Detailed Implementation

[0144] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0145] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0146] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0147] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0148] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0149] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0150] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0151] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0152] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0153] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0154] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0155] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.

[0156] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0157] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0158] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0159] This application provides a semiconductor device. Figure 1A A three-dimensional structural schematic diagram of a semiconductor device as an exemplary embodiment of this application; Figure 1B for Figure 1A The diagram shows a cross-sectional view of the semiconductor device parallel to the substrate. Figure 1C for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section aa' perpendicular to the substrate; Figure 1D for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb'). Figure 1E for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the cc' section perpendicular to the substrate; Figure 1F for Figure 1A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the dd' section perpendicular to the substrate; Figure 2 This is a three-dimensional structural schematic diagram of another semiconductor device according to an exemplary embodiment of this application.

[0160] like Figures 1A to 2 As shown, the semiconductor device includes: a plurality of memory cells, a word line (WL), a bit line (BL), and a source line (SL) located on the substrate 10;

[0161] Multiple memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate 10; each layer includes multiple memory cells spaced apart along row and column directions parallel to the substrate 10; each memory cell includes a transistor 20; the transistor 20 includes a first electrode 21, a second electrode 22, a semiconductor layer 23 located between the first electrode 21 and the second electrode 22, and a gate electrode 24, wherein a gate insulating layer 25 and a ferroelectric dielectric layer 26 are provided between the semiconductor layer 23 and the gate electrode 24, and the ferroelectric dielectric layer 26 is located between the gate electrode 24 and the gate insulating layer 25;

[0162] The word line WL passes through the transistor 20, and the gate electrode 24 is a part of the word line WL; the extension direction of the word line WL is the same as the extension direction of the semiconductor layer 23.

[0163] Bit line BL and source line SL are respectively connected to the first electrode 21 and the second electrode 22, which are distributed at intervals along the extension direction of semiconductor layer 23; the extension direction of bit line BL is the same as the extension direction of source line WL; the extension direction of bit line BL is perpendicular to the extension direction of word line WL.

[0164] Bit line BL and source line SL are located on the same side of semiconductor layer 23 away from gate electrode 24.

[0165] The semiconductor device in this application embodiment places the bit line BL and the source line SL on the same side of the semiconductor layer away from the gate electrode, that is, the bit line BL and the source line SL are located on the same side of the memory cell, which can reduce the area of ​​the memory cell, and the structure is simple, which can achieve higher storage density and simplify the word line formation process.

[0166] Furthermore, the semiconductor device in this application embodiment uses the gate electrode of the transistor to control the switching of the channel. The polarization reversal of the ferroelectric dielectric layer can be achieved through the voltage difference between the gate electrode and the bit line. The different polarization states of the ferroelectric dielectric layer cause the threshold voltage of the transistor to change, resulting in a change in the switching state of the transistor, thereby enabling the reading of stored information.

[0167] The following uses the operating voltages shown in the table below as an example to illustrate the data writing and reading process of the semiconductor device in this application embodiment.

[0168]

[0169] In the ferroelectric dielectric layer, the polarization reversal voltage of the ferroelectric material is greater than the threshold voltage V of the transistor. 阈值 When the transistor's turn-on voltage V is applied to the word line WL WL (can be understood as V) WL =V 阈值 When ), the polarization state of the ferroelectric material will not be changed.

[0170] Data writing

[0171] When writing data "1" to the selected memory cell, a voltage of, for example, 1V is applied to the word line WL, and a voltage of, for example, -1V is applied to the bit line BL and the source line SL. At this time, the ferroelectric dielectric layer is subjected to a positive voltage of +2V, causing the polarization of the ferroelectric material to flip to a positive alignment, and the stored data is "1". When writing data "0" to the selected memory cell, a voltage of, for example, -1V is applied to the word line WL, and a voltage of, for example, +1V is applied to the bit line BL and the source line SL. At this time, the ferroelectric dielectric layer is subjected to a negative voltage of -2V, causing the polarization of the ferroelectric material to flip to a negative alignment, and the stored data is "0".

[0172] Data reading

[0173] By applying V to the word line WL WL Apply a small read voltage V to the bit line BL read A voltage of, for example, 0V is applied to the source line SL, and the polarization direction of the ferroelectric material is used to affect the transistor threshold voltage V. 阈值The influence of the transistor's switching state (positive polarization makes it easier for the transistor to turn on, while negative polarization makes it easier for the transistor to turn off) allows us to read the current magnitude based on the transistor's switching state, corresponding to the stored data being "1" or "0".

[0174] In some embodiments of this application, such as Figure 1A , Figure 1D , Figure 1F and Figure 2 As shown, the semiconductor layer 23 at least partially surrounds the word line WL; the first electrode 21 and the second electrode 22 are located on the sidewalls of the semiconductor layer 23;

[0175] Bit line BL is located on the side of the first electrode 21 away from the semiconductor layer 23, and source line SL is located on the side of the second electrode 22 away from the semiconductor layer 23.

[0176] In some embodiments of this application, such as Figures 1A to 1D , Figure 1F and Figure 2 As shown, semiconductor layer 23 exposes at least a portion of the sidewalls of word line WL.

[0177] In some embodiments of this application, such as Figure 1A , Figure 1C , Figure 1D , Figure 1F and Figure 2 As shown, the semiconductor layer 23 has opposing first sidewalls 231 and second sidewalls 232 and a third sidewall 233 connected to the same side of the first sidewalls 231 and second sidewalls 232. The first sidewalls 231, second sidewalls 232 and third sidewalls 233 surround the word line WL. The side of the first sidewalls 231 and second sidewalls 232 away from the third sidewall 233 has an opening that exposes the sidewall of the word line WL.

[0178] In some embodiments of this application, such as Figure 1A , Figure 1C , Figure 1D , Figure 1F and Figure 2 As shown, the outer contour of the semiconductor layer 23 in a cross section perpendicular to the extension direction of the semiconductor layer 23 is "C" shaped.

[0179] In some embodiments of this application, such as Figure 1A and Figure 1B As shown, both the semiconductor layer 23 and the word line WL extend along the column direction (i.e., the Y direction); the word line WL passes through the transistors 20 of a plurality of memory cells spaced apart along the column direction;

[0180] Both the bit line BL and the source line SL extend along a direction perpendicular to the substrate 10 (i.e., the Z direction); the bit line BL and the source line SL are respectively connected to the first electrode 21 and the second electrode 22 of a plurality of memory cells stacked and distributed along a direction perpendicular to the substrate 10. In this scheme, the "column" of memory cells connected to the bit line BL and the source line SL is a "column" of memory cells stacked and spaced apart along a direction perpendicular to the substrate.

[0181] Compared to horizontal bit lines, vertical bit line structures can significantly improve the problem of excessive load caused by severe bit line coupling.

[0182] In some embodiments of this application, such as Figure 2 As shown, both the semiconductor layer 23 and the word line WL extend in a direction perpendicular to the substrate 10; the word line WL passes through the transistors 20 of the plurality of memory cells stacked in a direction perpendicular to the substrate 10.

[0183] Both the bit line BL and the source line SL extend along the column direction; the bit line BL and the source line SL are respectively connected to the first electrode 21 and the second electrode 22 of a plurality of memory cells spaced apart along the column direction. In this scheme, the "column" of memory cells connected to the bit line BL and the source line SL is the "column" of memory cells spaced apart along the column direction.

[0184] In some embodiments of this application, the semiconductor layers 23 of two adjacent memory cells in any direction are spaced apart. Spacing the semiconductor layers of different memory cells between and within layers can reduce or eliminate at least part of parasitic interlayer or intralayer MOS, thereby improving device stability.

[0185] In some embodiments of this application, such as Figure 1B As shown, the gate insulating layer 25 of a column of memory cells distributed at intervals along the column direction is an integral structure.

[0186] In some embodiments of this application, the gate insulating layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is a single-piece structure.

[0187] In some embodiments of this application, such as Figure 1B As shown, the ferroelectric dielectric layer 26 of the storage cells distributed at intervals along the column direction is an integral structure.

[0188] In some embodiments of this application, the ferroelectric dielectric layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is an integral structure.

[0189] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0190] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0191] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0192] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0193] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0194] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0195] For example, the materials of the bit line and the source line can each be independently selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0196] In some embodiments of this application, the materials of the gate electrode and the word line can be any one or more of the following different types of materials:

[0197] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0198] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0199] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0200] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0201] Low-K materials, such as silicon oxide.

[0202] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0203] In some embodiments of this application, the material of the ferroelectric dielectric layer may include hafnium-based oxides such as HfZrO, HfAlO, and HfLaO, lead zirconate titanate, and materials such as strontium-doped strontium oxide, or ferroelectric / dielectric composite structures, structures of different ferroelectric stacks, etc.

[0204] In some embodiments of this application, the semiconductor device may be a 3D memory, such as a 3D DRAM. The 3D memory may be a 1T1C or 2T1C structure, or a 1T0C or 2T0C structure (containing read transistors and write transistors).

[0205] This application also provides a method for manufacturing a semiconductor device. Figure 3This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application. The semiconductor device described above can be obtained by this method.

[0206] like Figure 3 As shown, the manufacturing method includes:

[0207] Multiple first sacrificial layers and multiple second sacrificial layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0208] The stacked structure is patterned and etched, and the patterned stacked structure includes a main region extending along a column direction parallel to the substrate and a plurality of branch regions connected to both sides of the main region and distributed at intervals.

[0209] Remove at least one end of the branch region away from the main region of the second sacrificial layer, and form an electrode groove between two adjacent first sacrificial layers in the branch region;

[0210] An electrode is formed within the electrode groove, the electrode comprising a first electrode and a second electrode;

[0211] A conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate.

[0212] The backbone region is broken in a row direction parallel to the substrate, exposing the second sacrificial layer of the backbone region;

[0213] Remove the second sacrificial layer and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode;

[0214] A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode extending along the column direction are sequentially formed in the gate trench; a plurality of gate electrodes distributed along the column direction are connected together to form a word line extending along the column direction.

[0215] In some embodiments of this application, removing at least one end of the second sacrificial layer of the branch region away from the main trunk region, and forming an electrode trench between two adjacent first sacrificial layers in the branch region, includes:

[0216] Etching is performed on the end of the branch region away from the trunk region to form a first via extending in a direction toward the substrate in the branch region, the first via exposing the second sacrificial layer of the branch region;

[0217] The second sacrificial layer of the branch region is laterally etched within the first through-hole to remove at least one end of the second sacrificial layer of the branch region away from the main region, thereby forming the electrode trench between two adjacent first sacrificial layers of the branch region.

[0218] In some embodiments of this application, the electrode is formed in the electrode groove, the electrode including a first electrode and a second electrode, comprising:

[0219] An electrode is formed in the electrode groove, the electrode is located between two adjacent first sacrificial layers in the branch region, and the electrode exposes a portion of the sidewall of the first sacrificial layer in the branch region;

[0220] In the column direction, any two adjacent electrodes are either a first electrode or a second electrode; a plurality of first electrodes are stacked and spaced apart in a direction perpendicular to the substrate, and a plurality of second electrodes are stacked and spaced apart in a direction perpendicular to the substrate.

[0221] In some embodiments of this application, a conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate, comprising:

[0222] A conductive layer is formed in each of the first through holes, the conductive layer being connected to the electrode and extending in a direction perpendicular to the substrate;

[0223] The conductive layer connected to the first electrode is a bit line; the conductive layer connected to the second electrode is a source line.

[0224] In some embodiments of this application, the step of breaking the backbone region in a row direction parallel to the substrate to expose the second sacrificial layer of the backbone region includes:

[0225] A barrier layer covering the conductive layer is formed on the substrate;

[0226] The barrier layer and the backbone region are etched to form a trench in the backbone region extending in a direction toward the substrate. The trench penetrates the backbone region in the column direction, breaking the backbone region in the row direction parallel to the substrate, thus exposing the second sacrificial layer of the backbone region.

[0227] In some embodiments of this application, the removal of the second sacrificial layer involves forming a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode; and sequentially forming a semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode within the gate trench, comprising:

[0228] Laterally etch the second sacrificial layers on both sides in the trench to remove all of the second sacrificial layers, and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing a plurality of electrodes spaced apart along the column direction;

[0229] A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode layer are sequentially formed on the inner walls of the trench and the gate trench.

[0230] Disconnect the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer located in different layers, and disconnect the semiconductor layer in the column direction;

[0231] The remaining gate electrode layer consists of word lines including the gate electrode.

[0232] In some embodiments of this application, disconnecting the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer located in different layers, and disconnecting the semiconductor layer in the column direction, includes:

[0233] Remove the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer from the end face of the trench that covers the first sacrificial layer;

[0234] Remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, each group of electrodes comprising two adjacent electrodes distributed along the column direction.

[0235] In some embodiments of this application, removing the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer covering the end face of the first sacrificial layer on the sidewall of the trench includes:

[0236] The semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer on the sidewalls and bottom wall of the trench are etched in the trench to expose the end face of the first sacrificial layer extending along the column direction;

[0237] An insulating layer is filled into the trench.

[0238] In some embodiments of this application, the removal of the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, each group of electrodes comprising two adjacent electrodes distributed along the column direction, includes:

[0239] Two adjacent electrodes distributed along the column direction are used as a group of electrodes. An isolation hole extending toward the substrate is formed between two adjacent groups of electrodes distributed along the column direction. The isolation hole exposes the semiconductor layer on the sidewall of the gate trench.

[0240] The exposed semiconductor layer is etched within the isolation hole to remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, while retaining the semiconductor layer located between each group of electrodes on the sidewall of the gate trench. The retained semiconductor layer is connected to the two electrodes of each group of electrodes.

[0241] An isolation layer is filled into the isolation hole.

[0242] In some embodiments of this application, the manufacturing method further includes: after removing the semiconductor layer located between two adjacent sets of electrodes on the sidewalls of the gate trench,

[0243] Remove the gate insulating layer and the ferroelectric dielectric layer located between two adjacent sets of electrodes on the sidewall of the gate trench, and disconnect the gate insulating layer and the ferroelectric dielectric layer on the sidewall of the gate trench in the column direction.

[0244] In some embodiments of this application, the step of sequentially and alternately depositing multiple first sacrificial layers and multiple second sacrificial layers on a substrate to obtain a stacked structure includes:

[0245] A first sacrificial layer and a second sacrificial layer are sequentially and alternately deposited on the substrate to obtain an initial stacked structure consisting of multiple first sacrificial layers and multiple second sacrificial layers;

[0246] The initial stacked structure is etched along the direction toward the substrate to form at least one isolation trench extending along the column direction in the initial stacked structure, the isolation trench spacing the initial stacked structure into a plurality of stacked structures spaced apart along the row direction;

[0247] An insulating layer is filled in the isolation groove, and adjacent stacked structures are isolated from each other by the insulating layer.

[0248] In some embodiments of this application, the patterning etching of the stacked structure includes:

[0249] The stacked structure is etched along the direction toward the substrate to form a plurality of second vias penetrating the stacked structure. The plurality of second vias are spaced apart in the row and column directions parallel to the substrate. The stacked structure is divided into the main region and the plurality of branch regions by the plurality of second vias.

[0250] An insulating layer is filled into the second through hole.

[0251] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0252] like Figures 4A to 21 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0253] S10: First sacrificial layer 11 and second sacrificial layer 12 are sequentially and alternately deposited on substrate 10 to obtain a stacked structure composed of multiple first sacrificial layers 11 and multiple second sacrificial layers 12.

[0254] For example, step S10 may include steps S11 to S13.

[0255] S11: Provide a substrate 10, and sequentially deposit a first sacrificial layer 11 and a second sacrificial layer 12 alternately on the substrate 10 to obtain an initial stacked structure composed of multiple first sacrificial layers 11 and multiple second sacrificial layers 12, such as Figures 4A to 4D As shown.

[0256] In this embodiment, the positions of cross sections aa', bb', cc', and dd' are as follows: Figure 1B As shown.

[0257] In some embodiments of this application, the materials forming the first sacrificial layer and the second sacrificial layer can each be independently a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon oxide or other silicon-containing films. However, the materials of the first sacrificial layer and the second sacrificial layer are different. For example, the material of the first sacrificial layer can be silicon oxide, and the material of the second sacrificial layer can be silicon nitride.

[0258] For example only. Figure 4A The initial stacking structure shown includes four first sacrificial layers 11 and three second sacrificial layers 12. In other embodiments, the initial stacking structure may include more or fewer alternating layers of first sacrificial layers 11 and second sacrificial layers 12.

[0259] S12: The initial stacked structure is etched along the direction toward the substrate 10, forming at least one isolation trench 16 extending in a column direction parallel to the substrate 10 in the initial stacked structure. The isolation trench 16 divides the initial stacked structure into a plurality of stacked structures spaced apart in a row direction parallel to the substrate 10, such as... Figures 5A to 5D As shown.

[0260] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. Exemplarily, the row direction can be as follows: Figure 1A and Figure 2 The X direction shown, or as shown in the figure. Figure 1B The directions shown are aa', bb', cc', or dd'; the column direction can be as follows: Figure 1A and Figure 2 The Y direction is shown; the direction perpendicular to the substrate can be as follows: Figure 1A and Figure 2 The Z direction is shown.

[0261] In this application, multiple components distributed along the row direction can be referred to as a row component, for example, a row of storage cells. Multiple components distributed along the column direction can be referred to as a column component, for example, a column of storage cells.

[0262] In some embodiments of this application, such as Figures 5A to 5D As shown, the isolation trench 16 can extend in a direction perpendicular to the substrate 10; the isolation trench 16 can extend into the first sacrificial layer 11 in contact with the substrate 10 and expose the first sacrificial layer 11 in contact with the substrate 10.

[0263] S13: Fill the isolation groove 16 with insulating layer 13, and isolate adjacent stacked structures from each other through insulating layer 13, such as Figures 6A to 6D As shown.

[0264] A subsequent stacking structure is used to form multiple memory cells, the multiple memory cells comprising two columns of memory cells spaced apart along the row direction. If the semiconductor device to be formed comprises only two columns of memory cells, the initial stacking structure obtained in step S11 is used as the stacking structure.

[0265] In some embodiments of this application, the materials forming the insulating layer can each be independently low-K dielectric materials, i.e., dielectric materials with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films. For example, the material of the insulating layer can be silicon oxide.

[0266] S20: Pattern the stacked structure by etching.

[0267] Exemplarily, step S20 may include the following steps S21 and S22.

[0268] S21: Etch the stacked structure in a direction towards the substrate 10 to form a plurality of second through-holes K2 penetrating the stacked structure. The plurality of second through-holes K2 are spaced apart in the row direction and the column direction; the patterned stacked structure includes a main region 17 extending along the column direction parallel to the substrate 10 and a plurality of branch regions 18 connected to both sides of the main region 17 and spaced apart, as Figures 7A to 7C shown. Among them, Figure 7A the cross-section in Figure 7A passes through the first sacrificial layer 11, Figure 6B and Figure 6D the schematic longitudinal cross-sectional structures of the semiconductor structure shown in the bb' cross-section and the dd' cross-section perpendicular to the substrate are respectively the same as

[0269] In some embodiments of the present application, as Figures 7A to 7C shown, the main region 17 is formed by a plurality of patterned first sacrificial layers 11 and a plurality of patterned second sacrificial layers 12 alternately and stacked; the branch regions 18 are formed by a plurality of patterned first sacrificial layers 11 and a plurality of patterned second sacrificial layers 12 alternately and stacked. The main region 17 and the plurality of branch regions 18 connected thereto are an integral structure; the plurality of branch regions 18 distributed along the column direction are spaced apart by the second through-holes K2, and the branch regions 18 may extend along the row direction. Exemplarily, the patterned stacked structure may be a "rich" character structure.

[0270] In some embodiments of the present application, as Figure 7B and Figure 7C shown, the second through-hole K2 may extend in a direction perpendicular to the substrate 10; the second through-hole K2 may extend into the first sacrificial layer 11 in contact with the substrate 10 and expose the first sacrificial layer 11 in contact with the substrate 10. The depth of the second through-hole K2 in the direction perpendicular to the substrate 10 may be the same as the depth of the isolation groove 16 in the direction perpendicular to the substrate 10. The second through-hole K2 exposes the insulating layer 13 in the isolation groove 16.

[0271] S22: Fill the insulating layer 13 in the second through-hole K2, as Figures 8A to 8C shown; among them, Figure 8A the cross-section in Figure 8A passes through the first sacrificial layer 11, Figure 6B and Figure 6D the schematic longitudinal cross-sectional structures of the semiconductor structure shown in the bb' cross-section and the dd' cross-section perpendicular to the substrate are respectively the same as

[0272] S30: Remove at least one end of the second sacrificial layer 12 of the branch region 18 that is far from the main trunk region 17, and form an electrode groove between two adjacent first sacrificial layers 11 of the branch region 18.

[0273] For example, step S30 may include steps S31 and S32.

[0274] S31: Etch the end of the branch region 18 away from the main region 17 along the direction toward the substrate 10 to form a first via K1 penetrating each of the second sacrificial layers 12 in the branch region 18. The first via K1 exposes the second sacrificial layer 12 of the branch region 18, as shown. Figures 9A to 9C As shown; where, Figure 9A The cross section in the middle passes through the first sacrificial layer 11. Figure 9A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa' and cc' perpendicular to the substrate, respectively. Figure 8B and Figure 8C same;

[0275] like Figures 9A to 9C As shown, the first through hole K1 exposes the insulating layer 13 inside the isolation groove 16.

[0276] In some embodiments of this application, such as Figure 9B and Figure 9C As shown, the first via K1 can extend in a direction perpendicular to the substrate 10. The first via K1 can extend into the first sacrificial layer 11 that contacts the substrate 10 and expose the first sacrificial layer 11 that contacts the substrate 10. The depth of the first via K1 in the direction perpendicular to the substrate 10 can be the same as the depth of the isolation trench 16 in the direction perpendicular to the substrate 10.

[0277] S32: Laterally etch the second sacrificial layer 12 of the branch region 18 within the first through-hole K1 to remove at least one end of the second sacrificial layer 12 of the branch region 18 away from the main region 17, forming an electrode trench 27 between two adjacent first sacrificial layers 11 of the branch region 18, such as... Figures 10A to 10C As shown. Among them, Figure 10A The cross section in the middle passes through the second sacrificial layer 12. Figure 10A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa' and cc' perpendicular to the substrate, respectively. Figure 8B and Figure 8C same.

[0278] In some embodiments of this application, such as Figures 10A to 10CAs shown, the lateral etching in step S32 can remove the second sacrificial layer 12 of the entire branch region 18. Therefore, after step S32 is completed, the width of the second sacrificial layer 12 in any region in the column direction is the same in the row direction, and the surface of the second sacrificial layer 12 distributed along the row direction is flush in the column direction.

[0279] In other embodiments, the lateral etching in step S32 may remove a portion of the second sacrificial layer 12 at the end of the branch region 18 away from the main trunk region 17, in which case the surface of the second sacrificial layer 12 distributed along the row direction is not flush with the column direction.

[0280] S40: An electrode is formed in the electrode groove 27, such as Figures 11A to 11C As shown. Among them, Figure 11A The cross section in the middle passes through the second sacrificial layer 12. Figure 11A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa' and cc' perpendicular to the substrate, respectively. Figure 8B and Figure 8C same.

[0281] For example, step S40 may include:

[0282] An electrode is formed in the electrode groove 27. The electrode is located between two adjacent first sacrificial layers 11 in the branch region 18, and the electrode exposes part of the sidewall of the first sacrificial layer 11 in the branch region 18. Any two adjacent electrodes in the column direction, one of which is a first electrode 21 and the other is a second electrode 22. A plurality of first electrodes 21 are stacked and spaced apart in a direction perpendicular to the substrate 10, and a plurality of second electrodes 22 are stacked and spaced apart in a direction perpendicular to the substrate 10.

[0283] S50: A conductive layer is formed on the side of the electrode away from the main region 17, connected to the electrode and extending in a direction perpendicular to the substrate 10, such as... Figures 12A to 12C As shown. Among them, Figure 12A The cross section in the middle passes through the second sacrificial layer 12. Figure 12A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa' and cc' perpendicular to the substrate, respectively. Figure 8B and Figure 8C same.

[0284] For example, step S50 may include:

[0285] A conductive layer connected to each electrode is deposited in each first via K1, the conductive layer extending in a direction perpendicular to the substrate 10; wherein the conductive layer connected to the first electrode 21 is a bit line BL; and the conductive layer connected to the second electrode 22 is a source line SL.

[0286] S60: The main trunk 17 is disconnected in the row direction, exposing the second sacrificial layer 12 of the main trunk 17.

[0287] For example, step S60 may include:

[0288] S61: A barrier layer 14 covering the conductive layer is formed on the top surface of the substrate 10. The barrier layer 14 also covers the insulating layer 13 and the main region 17 within the isolation trench 16, such as... Figures 13A to 13D As shown;

[0289] S62: Etch the barrier layer 14 and the backbone region 17 to form a trench 19 extending in the direction toward the substrate 10 in the backbone region 17. The trench 19 penetrates the backbone region 17 in the column direction, breaking the backbone region 17 in the row direction parallel to the substrate 10, exposing the second sacrificial layer 12 of the backbone region 17, as shown. Figures 14A to 14E As shown. Among them, Figure 14A The cross section passes through the second sacrificial layer 12.

[0290] In some embodiments of this application, the trench 19 may extend in a direction perpendicular to the substrate 10. The trench 19 may extend into and expose the first sacrificial layer 11 in contact with the substrate 10. The depth of the trench 19 in the direction perpendicular to the substrate 10 may be the same as the depth of the isolation trench 16 in the direction perpendicular to the substrate 10.

[0291] In some embodiments of this application, the materials forming the barrier layers can each be independently low-K dielectric materials, i.e., dielectric materials with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films. For example, the material of the barrier layer can be silicon oxide.

[0292] S70: Laterally etch the exposed second sacrificial layers 12 on both sides within the trench 19 until all the second sacrificial layers 12 are removed. A gate trench 28 extending along the column direction is formed between two adjacent first sacrificial layers 11 in the main region 17. The gate trench 28 exposes a plurality of electrodes spaced apart along the column direction. Figures 15A to 15D As shown.

[0293] S80: A semiconductor layer 23, a gate insulating layer 25, a ferroelectric dielectric layer 26, and a gate electrode layer 24' are sequentially formed on the inner walls of the trench 19 and the gate trench 28, such as... Figures 16A to 16E As shown. Among them, Figure 16A The cross section passes through the electrode.

[0294] S90: Disconnect the semiconductor layer 23, gate insulating layer 25, ferroelectric dielectric layer 26 and gate electrode layer 24' located in different layers, and disconnect the semiconductor layer 23 in the column direction.

[0295] For example, step S90 may include the following steps S91 to S92.

[0296] S91: Remove the semiconductor layer 23, gate insulating layer 25, ferroelectric dielectric layer 26 and gate electrode layer 24' covering the end face of the first sacrificial layer 11 on the sidewall of the trench 19.

[0297] For example, step S91 may include:

[0298] S911: Etch the semiconductor layer 23, gate insulating layer 25, ferroelectric dielectric layer 26, and gate electrode layer 24' on the inner wall (including sidewall and bottom wall) of the trench 19, for example, by wet etching, to remove the semiconductor layer 23, gate insulating layer 25, ferroelectric dielectric layer 26, and gate electrode layer 24' covering the end face of the first sacrificial layer 11 on the sidewall of the trench 19, exposing the end face of the first sacrificial layer 11 extending along the column direction, such as... Figures 17A to 17D As shown;

[0299] S912: Fill the trench 19 with insulating layer 13, such as Figures 18A to 18D As shown.

[0300] like Figures 17A to 17D As shown, step S911 can remove the semiconductor layer 23, gate insulating layer 25, ferroelectric dielectric layer 26 and gate electrode layer 24' on the surface of the barrier layer at the same time.

[0301] S92: Remove the semiconductor layer 23 located between two adjacent groups of electrodes on the sidewall (or bottom of the gate trench 28), each group of electrodes including an adjacent first electrode and a second electrode distributed along the column direction.

[0302] For example, step S92 may include steps S921 to S93.

[0303] S921: Taking an adjacent first electrode 21 and a second electrode 22 distributed along the column direction as a group of electrodes, the insulating layer 13 between two adjacent groups of electrodes distributed along the column direction is etched to form an isolation hole K3 extending toward the substrate 10. The isolation hole K3 exposes the semiconductor layer 23 on the sidewall (or bottom of the gate trench 28), such as... Figure 19A and Figure 19B As shown. Figure 19A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa', bb', and cc' perpendicular to the substrate, respectively. Figure 18A , Figure 18B and Figure 18D same.

[0304] In some embodiments of this application, such as Figure 19B As shown, the isolation hole K3 can extend in a direction perpendicular to the substrate 10; the isolation hole K3 can extend into the first sacrificial layer 11 in contact with the substrate 10 and expose the first sacrificial layer 11 in contact with the substrate 10. The depth of the isolation hole K3 in the direction perpendicular to the substrate 10 can be the same as the depth of the isolation trench 16 in the direction perpendicular to the substrate 10.

[0305] S922: The exposed semiconductor layer 23 is etched within the isolation via K3, for example, by wet etching, to remove the semiconductor layer 23 located between two adjacent groups of electrodes on the sidewall of the gate trench 28, retaining the semiconductor layer 23 located between each group of electrodes on the sidewall of the gate trench 28. The two ends of the retained semiconductor layer 23 are connected to the first electrode 21 and the second electrode 22 of each group of electrodes, respectively. Figure 20A and Figure 20B As shown. Figure 20A The schematic diagrams of the longitudinal cross-sectional structures of the semiconductor structure shown are located at sections aa', bb', and cc' perpendicular to the substrate, respectively. Figure 18A , Figure 18B and Figure 18D same.

[0306] In the semiconductor device obtained in step S922, the gate insulating layer 25 and the ferroelectric dielectric layer 26 of the column of memory cells distributed at intervals along the column direction are both integral structures.

[0307] In other embodiments, step S922 may be followed by:

[0308] S923: Remove the gate insulating layer 25 and / or ferroelectric dielectric layer 26 located between two adjacent sets of electrodes on the sidewall of the gate trench 28, disconnecting the gate insulating layer 25 and ferroelectric dielectric layer 26 on the sidewall of the gate trench 28 in the column direction, leaving the remaining gate electrode layer 24' as the gate electrode 24, as shown. Figure 21 As shown.

[0309] The semiconductor device obtained in step S923 has the gate insulating layer 25 and / or ferroelectric dielectric layer 26 spaced apart in a column of the memory cells distributed along the column direction.

[0310] S93: Fill the isolation layer 15 into the isolation hole K3 to obtain the following result. Figures 1A to 1F The semiconductor device shown.

[0311] The semiconductor device manufacturing method of the present application embodiment can use a simple method to remove parasitic MOS between and within layers, thereby improving the performance of the semiconductor device.

[0312] Setting the bit lines to extend in the vertical direction can avoid coupling effects between bit lines.

[0313] This application also provides an electronic device, which includes the semiconductor device provided in the above embodiments of this application, or a semiconductor device manufactured according to the above semiconductor device manufacturing method.

[0314] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0315] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; each layer includes multiple memory cells spaced apart along row and column directions parallel to the substrate; each memory cell includes a transistor; each transistor includes a first electrode, a second electrode, a semiconductor layer located between the first electrode and the second electrode, and a gate electrode, wherein a gate insulating layer and a ferroelectric dielectric layer are provided between the semiconductor layer and the gate electrode, and the ferroelectric dielectric layer is located between the gate electrode and the gate insulating layer; A word line runs through the transistor, and the gate electrode is a part of the word line; The extension direction of the word line is the same as the extension direction of the semiconductor layer; Bit lines and source lines are respectively connected to the first electrode and the second electrode, which are spaced apart along the extension direction of the semiconductor layer; the extension direction of the bit lines is the same as the extension direction of the source lines. The extension direction of the bit line is perpendicular to the extension direction of the word line; The bit line and the source line are located on the same side of the semiconductor layer away from the gate electrode.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor layer at least partially surrounds the word line; the first electrode and the second electrode are located on the sidewall of the semiconductor layer; The bit line is located on the side of the first electrode away from the semiconductor layer, and the source line is located on the side of the second electrode away from the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor layer exposes at least a portion of the sidewalls of the word line.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor layer has opposing first and second sidewalls and a third sidewall connected to the same side of the first and second sidewalls, the first sidewall, the second sidewall and the third sidewall surrounding the word line, and an opening on the side of the first and second sidewalls away from the third sidewall, the opening exposing the sidewall of the word line.

5. The semiconductor device according to claim 4, characterized in that, The outer contour of the semiconductor layer in a cross section perpendicular to the extension direction of the semiconductor layer is "C" shaped.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, Both the semiconductor layer and the word line extend along the column direction; the word line passes through transistors of a plurality of memory cells spaced apart along the column direction; Both the bit line and the source line extend in a direction perpendicular to the substrate; the bit line and the source line are respectively connected to the first electrode and the second electrode of a plurality of memory cells stacked in a direction perpendicular to the substrate.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that, Both the semiconductor layer and the word line extend in a direction perpendicular to the substrate; the word line passes through transistors of a plurality of memory cells stacked in a direction perpendicular to the substrate; Both the bit line and the source line extend along the column direction; the bit line and the source line are respectively connected to the first electrode and the second electrode of a plurality of memory cells that are spaced apart along the column direction.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that, The semiconductor layers of two adjacent memory cells in any direction are spaced apart.

9. The semiconductor device according to claim 1, characterized in that, The gate insulating layer of a column of memory cells spaced apart along the column direction is a single, integral structure; and / or, The gate insulating layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is a single, integral structure; and / or, The ferroelectric dielectric layer of a column of memory cells spaced apart along the column direction is a single, integral structure; and / or, The ferroelectric dielectric layer of a row of memory cells spaced apart along a direction perpendicular to the substrate is a single-piece structure.

10. A method for manufacturing a semiconductor device, characterized in that, include: Multiple first sacrificial layers and multiple second sacrificial layers are sequentially and alternately deposited on a substrate to obtain a stacked structure; The stacked structure is patterned and etched, and the patterned stacked structure includes a main region extending along a column direction parallel to the substrate and a plurality of branch regions connected to both sides of the main region and distributed at intervals. Remove at least one end of the branch region away from the main region of the second sacrificial layer, and form an electrode groove between two adjacent first sacrificial layers in the branch region; An electrode is formed within the electrode groove, the electrode comprising a first electrode and a second electrode; A conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate. The backbone region is broken in a row direction parallel to the substrate, exposing the second sacrificial layer of the backbone region; Remove the second sacrificial layer and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode; A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode extending along the column direction are sequentially formed in the gate trench; Multiple gate electrodes distributed along the column direction are connected together to form word lines extending along the column direction.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The removal of at least one end of the second sacrificial layer from the branch region, away from the main trunk region, and the formation of an electrode trench between two adjacent first sacrificial layers in the branch region, includes: Etching is performed on the end of the branch region away from the trunk region to form a first via extending in a direction toward the substrate in the branch region, the first via exposing the second sacrificial layer of the branch region; The second sacrificial layer of the branch region is laterally etched within the first through-hole to remove at least one end of the second sacrificial layer of the branch region away from the main region, thereby forming the electrode trench between two adjacent first sacrificial layers of the branch region.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, An electrode is formed within the electrode groove, the electrode comprising a first electrode and a second electrode, including: An electrode is formed in the electrode groove, the electrode is located between two adjacent first sacrificial layers in the branch region, and the electrode exposes a portion of the sidewall of the first sacrificial layer in the branch region; In the column direction, any two adjacent electrodes are either a first electrode or a second electrode; a plurality of first electrodes are stacked and spaced apart in a direction perpendicular to the substrate, and a plurality of second electrodes are stacked and spaced apart in a direction perpendicular to the substrate.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, A conductive layer is formed on the side of the electrode away from the main region, connected to the electrode and extending in a direction perpendicular to the substrate. The conductive layer includes a bit line and a source line extending in a direction perpendicular to the substrate, comprising: A conductive layer is formed in each of the first through holes, the conductive layer being connected to the electrode and extending in a direction perpendicular to the substrate; The conductive layer connected to the first electrode is a bit line; the conductive layer connected to the second electrode is a source line.

14. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The step of breaking the backbone region in a row direction parallel to the substrate to expose the second sacrificial layer of the backbone region includes: A barrier layer covering the conductive layer is formed on the substrate; The barrier layer and the backbone region are etched to form a trench in the backbone region extending in a direction toward the substrate. The trench penetrates the backbone region in the column direction, breaking the backbone region in the row direction parallel to the substrate, thus exposing the second sacrificial layer of the backbone region.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The removal of the second sacrificial layer involves forming a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing the electrode; A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode are sequentially formed within the gate trench, including: Laterally etch the second sacrificial layers on both sides in the trench to remove all of the second sacrificial layers, and form a gate trench extending along the column direction between two adjacent first sacrificial layers in the main region, the gate trench exposing a plurality of electrodes spaced apart along the column direction; A semiconductor layer, a gate insulating layer, a ferroelectric dielectric layer, and a gate electrode layer are sequentially formed on the inner walls of the trench and the gate trench. Disconnect the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer located in different layers, and disconnect the semiconductor layer in the column direction; The remaining gate electrode layer consists of word lines including the gate electrode.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The step of disconnecting the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer located in different layers, and disconnecting the semiconductor layer in the column direction, includes: Remove the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer from the end face of the trench that covers the first sacrificial layer; Remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, each group of electrodes comprising two adjacent electrodes distributed along the column direction.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The removal of the semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer, and the gate electrode layer covering the end face of the trench sidewall, which covers the first sacrificial layer, includes: The semiconductor layer, the gate insulating layer, the ferroelectric dielectric layer and the gate electrode layer on the sidewalls and bottom wall of the trench are etched in the trench to expose the end face of the first sacrificial layer extending along the column direction; An insulating layer is filled into the trench.

18. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench is removed, each group of electrodes comprising two adjacent electrodes distributed along the column direction, including: Two adjacent electrodes distributed along the column direction are used as a group of electrodes. An isolation hole extending toward the substrate is formed between two adjacent groups of electrodes distributed along the column direction. The isolation hole exposes the semiconductor layer on the sidewall of the gate trench. The exposed semiconductor layer is etched within the isolation hole to remove the semiconductor layer located between two adjacent groups of electrodes on the sidewall of the gate trench, while retaining the semiconductor layer located between each group of electrodes on the sidewall of the gate trench. The retained semiconductor layer is connected to the two electrodes of each group of electrodes. An isolation layer is filled into the isolation hole.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, Also includes: After removing the semiconductor layer located between two adjacent sets of electrodes on the sidewalls of the gate trench, Remove the gate insulating layer and the ferroelectric dielectric layer located between two adjacent sets of electrodes on the sidewall of the gate trench, and disconnect the gate insulating layer and the ferroelectric dielectric layer on the sidewall of the gate trench in the column direction.

20. A method for manufacturing a semiconductor device according to any one of claims 10 to 19, characterized in that, The method of sequentially and alternately depositing multiple first sacrificial layers and multiple second sacrificial layers on a substrate to obtain a stacked structure includes: A first sacrificial layer and a second sacrificial layer are sequentially and alternately deposited on the substrate to obtain an initial stacked structure consisting of multiple first sacrificial layers and multiple second sacrificial layers; The initial stacked structure is etched along the direction toward the substrate to form at least one isolation trench extending along the column direction in the initial stacked structure, the isolation trench spacing the initial stacked structure into a plurality of stacked structures spaced apart along the row direction; An insulating layer is filled in the isolation groove, and adjacent stacked structures are isolated from each other by the insulating layer.

21. The method for manufacturing a semiconductor device according to any one of claims 10 to 19, characterized in that, The patterning etching of the stacked structure includes: The stacked structure is etched along the direction toward the substrate to form a plurality of second vias penetrating the stacked structure. The plurality of second vias are spaced apart in the row and column directions parallel to the substrate. The stacked structure is divided into the main region and the plurality of branch regions by the plurality of second vias. An insulating layer is filled into the second through hole.

22. An electronic device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 9, or the semiconductor device obtained by the manufacturing method according to any one of claims 10 to 21.

Images