Silicon-on-insulator substrate and preparation method thereof

Abstract

The invention provides a silicon-on-insulator substrate and a preparation method thereof. The silicon-on-insulator substrate comprises a support wafer; the silicon oxide layer is arranged on the supporting wafer; the stacked monocrystalline silicon layer is arranged on the silicon oxide layer; wherein the stacked monocrystalline silicon layer at least comprises a first sub monocrystalline silicon layer and a second sub monocrystalline silicon layer, and the first sub monocrystalline silicon layer and the second sub monocrystalline silicon layer are connected through a first silicon-silicon bonding interface without a dielectric layer. The silicon-on-insulator substrate has the advantages of both thickness and uniformity, and breaks through the technical bottleneck existing in the industry. According to the silicon-on-insulator substrate provided by the embodiment of the invention, the thickness can be accumulated by stacking the sub monocrystalline silicon layers with relatively good uniformity, so that the thickness required by a high-voltage device and the high-precision uniformity required by large-scale manufacturing are structurally integrated.

Description

Technical Field

[0001] This application relates to the field of semiconductor materials technology, and in particular to silicon-on-insulator substrates and methods for their fabrication. Background Technology

[0002] Silicon-on-Insulator (SOI) technology is a key platform technology in modern semiconductor manufacturing. SOI substrates provide excellent electrical isolation for integrated circuits, effectively reducing parasitic capacitance and leakage current, and significantly improving their operational stability and reliability under harsh environments such as high temperature and high pressure.

[0003] With the global energy structure shifting towards electrification and the rapid development of information technology, various sectors are facing an ever-increasing demand for high-efficiency, high-power-density power semiconductor devices. Power-SOI (SOI) substrates, designed for certain applications, have become one of the core materials driving the development of these cutting-edge technologies because they can support the integration of high-voltage power devices and low-voltage control circuits on a single chip. However, existing Power-SOI substrate manufacturing technologies still face significant challenges and inherent technical bottlenecks in simultaneously meeting the requirements of micron-thick top silicon layers for high-voltage applications and good film thickness uniformity for large-scale production. Summary of the Invention

[0004] This application provides a silicon-on-insulator substrate and a method for fabricating the same. This silicon-on-insulator substrate offers advantages in both thickness and uniformity, overcoming existing technical bottlenecks in the industry.

[0005] The technical solution of this application is implemented as follows: In a first aspect, some embodiments of this application provide a silicon-on-insulator substrate, comprising: Support wafer; A silicon oxide layer disposed on a support wafer; Stacked single-crystal silicon layers disposed on a silicon oxide layer, The stacked single-crystal silicon layers include at least a first sub-single-crystal silicon layer and a second sub-single-crystal silicon layer, and the first sub-single-crystal silicon layer and the second sub-single-crystal silicon layer are connected by a first silicon-silicon bonding interface without a dielectric layer.

[0006] In some examples, the first silicon-silicon bonding interface is formed through surface activation bonding.

[0007] In some examples, the first silicon-silicon bonding interface includes an amorphous silicon layer with a thickness of less than 10 nm.

[0008] In some examples, the total thickness of the stacked monocrystalline silicon layers is between 1µm and 10µm.

[0009] In some examples, the thickness of the stacked single-crystal silicon layers varies by less than 5 nm.

[0010] In some examples, the silicon-on-insulator substrate further includes a third sub-monocrystalline silicon layer, which is connected to the second sub-monocrystalline silicon layer via a second silicon-silicon bonding interface without a dielectric layer.

[0011] Secondly, some embodiments of this application provide a method for fabricating a silicon-on-insulator substrate, comprising: An initial silicon-on-insulator structure is provided, the initial silicon-on-insulator structure including a support wafer, a silicon oxide layer disposed on the support wafer, and a first sub-monocrystalline silicon layer disposed on the silicon oxide layer; Surface activation treatment is performed on the surface of the first sub-monocrystalline silicon layer and the surface of the first donor wafer; By bonding the surface-activated surface of the first donor wafer to the surface-activated surface of the first sub-monocrystalline silicon layer, a first silicon-silicon bonding interface without a dielectric layer is formed; and By transferring a second sub-monocrystalline silicon layer from a first donor wafer onto a first sub-monocrystalline silicon layer, stacked monocrystalline silicon layers are formed to obtain a silicon-on-insulator substrate.

[0012] In some examples, providing the initial silicon-on-insulator structure includes: Provide a second donor wafer; The second donor wafer is bonded to the support wafer via a silicon oxide layer; The first sub-monocrystalline silicon layer is transferred from the second donor wafer.

[0013] In some examples, the step of transferring the second sub-monocrystalline silicon layer from the first donor wafer includes: implanting ions into the first donor wafer to form a release layer, and peeling along the release layer.

[0014] In some examples, the fabrication method further includes: after transferring the second sub-single-crystal silicon layer, performing a surface planarization process on the surface of the second sub-single-crystal silicon layer.

[0015] In some examples, surface planarization includes: Rapid heat treatment in a hydrogen-containing atmosphere; and After rapid thermal processing, a sacrificial oxide layer is formed and removed on the surface of the second sub-monocrystalline silicon layer.

[0016] In some examples, the preparation method also includes: After the step of transferring the second sub-monocrystalline silicon layer from the first donor wafer, the first donor wafer is subjected to surface polishing. The first donor wafer, after surface polishing, is reused as a donor wafer in subsequent substrate fabrication processes.

[0017] In some examples, the steps of surface activation, bonding, and transfer are repeated to form a third sub-monocrystalline silicon layer on the second sub-monocrystalline silicon layer.

[0018] This application provides a silicon-on-insulator (SiS) substrate and its fabrication method. The SiS substrate includes a supporting wafer, a silicon oxide layer, and stacked single-crystal silicon layers. The stacked single-crystal silicon layers include a first sub-single-crystal silicon layer and a second sub-single-crystal silicon layer connected by a first silicon-silicon bonding interface without a dielectric layer. Because the first silicon-silicon bonding interface without a dielectric layer ensures that silicon atoms between the two sub-single-crystal silicon layers directly form covalent bonds, thus achieving atomic-level connectivity both electrically and crystallographically, this structure can synthesize two independent thin single-crystal silicon layers into a unified, continuous thick single-crystal silicon layer. Based on this, the SiS substrate provided in this application can accumulate thickness by stacking sub-single-crystal silicon layers, which inherently possess good uniformity, thereby structurally combining the thickness required for high-voltage devices with the high-precision uniformity required for large-scale manufacturing. Attached Figure Description

[0019] Figure 1 A schematic cross-sectional view of a silicon-on-insulator substrate provided for some embodiments of this application.

[0020] Figure 2 A schematic cross-sectional view of a silicon-on-insulator substrate provided for other embodiments of this application.

[0021] Figure 3 A schematic cross-sectional view of a silicon-on-insulator substrate provided for further embodiments of this application.

[0022] Figure 4 A flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided for some embodiments of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and beneficial effects of this application clearer and more explicit, the following detailed description of this application will be provided in conjunction with the accompanying drawings.

[0024] Silicon-on-insulator (SOI) technology provides excellent electrical isolation for semiconductor devices by introducing a buried oxide (BOX) layer into its three-layer structure of silicon-insulator-silicon. This effectively suppresses latch-up, reduces parasitic capacitance and leakage current, and significantly improves the robustness of devices under high temperature and high pressure environments. Therefore, it is recognized as one of the ideal substrate platforms for manufacturing advanced integrated circuits.

[0025] During the research and development process, the inventors discovered that the fabrication of SOI substrates, especially when applied to high-voltage power devices, faces a pair of mutually restrictive core technological challenges. On the one hand, to achieve high breakdown voltage (e.g., >200V) and low on-resistance, the top single-crystal silicon active layer (SOI layer) must have sufficient thickness, typically ranging from 1 micrometer (µm) to 5 micrometers, or even thicker. On the other hand, to ensure high yield and consistent device performance in large-scale integrated circuit manufacturing, the uniformity of the SOI layer thickness needs to be precisely controlled, with thickness deviations across the entire wafer even needing to be controlled at the nanometer (nm) level. The inventors noted that SOI substrates produced using existing different technological routes often only meet one of the requirements: for technologies capable of fabricating thick silicon layers, the device performance exhibits significant inconsistencies at different locations on the wafer; while for technologies capable of fabricating highly uniform silicon layers, the products cannot withstand high voltages due to the silicon layer being too thin.

[0026] To address this issue, the inventors first attempted to improve a thin-film transfer technique that achieves better uniformity. This technique precisely defines the thickness of the film to be transferred through ion implantation, thus offering excellent uniformity. In the field of ion implantation, increasing the energy of the implanted ions typically increases the implantation depth, thereby obtaining a thicker silicon layer in a single transfer. However, due to limitations in the ion implantation process itself, it is usually impossible to obtain SOI substrates with a top silicon film thickness exceeding 1.5 μm. To obtain films thicker than 1.5 μm, the inventors attempted to stack the films from a single transfer to achieve the desired film thickness. The inventors noted that in some applications of current 3D device technology, multilayer SOI substrates are used, and traditional Smart Cut is repeatedly performed... TM The process yields a multilayer structure of silicon / buried oxide / silicon / buried oxide / silicon… In other words, it's possible to stack multiple thin silicon layers with good thickness uniformity by repeatedly using hydrogen ion implantation and bonding processes to obtain a thick film layer with micron-level thickness and excellent thickness uniformity. However, a problem arises: thin silicon layers typically have a natural oxide layer several nanometers thick, resulting in thin oxide layers between the bonded silicon layers. This oxide layer hinders vertical current conduction, introducing unnecessary parasitic capacitance, making it unsuitable for vertical power devices requiring thick silicon layers. Therefore, current technology still cannot achieve high-performance thick silicon layer transfer through simple stacking.

[0027] Through in-depth analysis of the above schemes, the root of the problem lies in the choice of bonding process. The standard hydrophilic bonding process, by its chemical mechanism, forms a layer of silicon dioxide (Si-O-Si) at the bonding interface, acting as a "binder." This silicon dioxide layer is essentially an electrical insulator. This insulator plays a dual role in the SOI structure, and its advantages and disadvantages depend entirely on its location and the function to be achieved.

[0028] Specifically, the interface between the top active region and the underlying supporting wafer is also referred to as the "isolation interface" in this application, and its core function is to achieve electrical isolation. Here, forming a high-quality silicon dioxide insulating layer (i.e., the BOX layer) is the fundamental source of the advantages of SOI technology; therefore, the use of hydrophilic bonding is advantageous.

[0029] However, the interface formed by stacking and connecting two sub-monocrystalline silicon layers to increase the overall thickness, also referred to in the disclosure as a "connection interface," has a completely different core function. This connection interface needs to achieve atomic-level electrical and crystal structure connections to form a macroscopically uniform monocrystalline silicon layer that is stacked in thickness. In this case, if an insulating layer of silicon dioxide is artificially introduced between two silicon layers that should be conductive, this silicon dioxide layer will have adverse effects. Specifically, in terms of electrical performance, this silicon dioxide layer acts as a barrier, hindering or completely blocking the vertical flow of current in the thick silicon layer, which is unacceptable for many vertically structured power devices; in terms of physical structure, this silicon dioxide layer disrupts the continuity of the monocrystalline silicon, making the final product not a true "thick-film monocrystalline silicon," but merely a stack of multiple thin films. This discontinuous structure introduces additional interface states, defects, and parasitic capacitances, thereby degrading device performance.

[0030] Based on the above analysis, the inventors realized that completely different bonding technologies must be used for these two interfaces with completely different functions, namely the "isolation interface" and the "connection interface".

[0031] In view of this, the inventors propose a "multi-modal bonding strategy," which includes bonding of different modes throughout the entire multilayer stacking fabrication process. For example, it includes: first-mode bonding, i.e., the bonding step to form the initial bottom SOI structure (including the supporting substrate, BOX layer, and the first sub-monocrystalline silicon layer), using conventional hydrophilic bonding to form a high-quality BOX isolation layer; and second-mode bonding, i.e., the bonding step of continuing to stack new sub-monocrystalline silicon layers on the already formed sub-monocrystalline silicon layer, i.e., the stacking bonding of subsequent layers after the formation of the BOX isolation layer, which employs "Surface Activated Bonding (SAB)" bonding technology. SAB technology involves removing the natural oxide layer on the silicon surface through ion beam physical cleaning in a high-vacuum environment, and then directly forming silicon-silicon (Si-Si) covalent bonds without any intermediate medium at room temperature. In this way, multiple sub-monocrystalline silicon layers prepared by high-precision thin-film transfer technology can be synthesized at the atomic level into a thick, uniform, interface-free monocrystalline silicon layer. The SOI substrate obtained in this way can simultaneously meet the requirements of "thickness" and "uniformity".

[0032] To overcome the limitations of the prior art, embodiments of this application provide silicon-on-insulator substrates and methods for their fabrication.

[0033] The following description, in conjunction with specific embodiments of this application, provides further details.

[0034] Reference Figure 1 Some embodiments of this application provide a silicon-on-insulator (SOI) substrate 100. The SOI substrate 100 may include a support wafer 20, a silicon oxide layer 40, and a stacked single-crystal silicon layer 60, wherein the silicon oxide layer 40 is located between the support wafer 20 and the stacked single-crystal silicon layer 60.

[0035] The support wafer 20 provides stable mechanical support for the functional layers formed thereon, ensuring the entire SOI substrate 100 maintains structural integrity during complex semiconductor manufacturing processes and serves as the primary heat dissipation channel during final device operation, effectively conducting away heat generated in the active region. The support wafer 20 can be a single-crystal silicon wafer, for example, a P-type or N-type silicon wafer with a diameter of 300 mm. The crystal orientation, resistivity, and other parameters of the support wafer 20 can be flexibly selected according to the application requirements of the final device. For example, for power devices requiring good thermal conductivity, a support wafer with low resistivity may be chosen to improve heat dissipation efficiency.

[0036] A silicon oxide layer 40 can be disposed on the support wafer 20. In the field of SOI technology, the silicon oxide layer 40 can also be called a buried oxide (BOX) layer, which can be an electrically insulating thin film composed of silicon dioxide (SiO2) uniformly disposed on the surface of the support wafer 20. As a core feature of the SOI structure, the silicon oxide layer 40's fundamental function is to provide high-quality electrical isolation between the top active region and the underlying support wafer 20, thereby effectively suppressing latch-up effects and reducing parasitic capacitance and leakage current. This silicon oxide layer 40 can be formed by various methods, such as chemical vapor deposition (CVD). The thickness of the silicon oxide layer 40 can also be designed according to the device's voltage withstand requirements, ranging from tens of nanometers to several micrometers.

[0037] The stacked single-crystal silicon layer 60 can be disposed on the silicon oxide layer 40 for fabricating the active region of a semiconductor device. According to some embodiments of this application, the stacked single-crystal silicon layer 60 is not formed by conventional single-film transfer or thinning processes, but is a composite thick film formed by stacking and atomically connecting at least two independent, thin single-crystal silicon layers, i.e., sub-single-crystal silicon layers.

[0038] Compared to conventional single-layer SOI, the stacked structure provided in this application is fundamentally different. Specifically, as explained above, in conventional Smart Cut™ SOI structures, the thickness of the top silicon layer is limited by ion implantation energy, typically failing to break through the 1.5µm bottleneck. Furthermore, the thick silicon layers prepared by traditional BESOI technology, formed through thinning methods such as mechanical grinding and chemical mechanical polishing (CMP), exhibit poor uniformity, usually only reaching the micrometer level. In contrast, the stacked single-crystal silicon layer 60 in the SOI substrate 100 provided in this application can achieve a balance between thick silicon layers and uniformity by iteratively "building" multiple sub-single-crystal silicon layers with superior uniformity. For example, the stacked single-crystal silicon layer 60 can have a total thickness of 1µm to 10µm to meet the high-voltage requirements of Power-SOI while inheriting the excellent uniformity of each sub-layer, allowing the final total thickness variation to be controlled to less than 5nm.

[0039] The basic unit constituting the stacked single-crystal silicon layer 60 described above can be multiple sub-single-crystal silicon layers, for example, in Figure 1In this process, there may be a first sub-monocrystalline silicon layer 602 and a second sub-monocrystalline silicon layer 604. The first sub-monocrystalline silicon layer 602 and the second sub-monocrystalline silicon layer 604 are two independent, physically separated monocrystalline silicon films that are permanently joined together and stacked to form a thicker structure using the fabrication method provided in this application. In the specific fabrication process, these two sub-monocrystalline silicon layers can be transferred from different donor wafers, for example, using a high-precision Smart Cut™ technique. The thickness of each sub-monocrystalline silicon layer can be precisely set by controlling the ion implantation energy. For example, two sub-monocrystalline silicon layers, each with a thickness of 0.8 µm, can be transferred to form a stacked monocrystalline silicon layer 60 with a total thickness of 1.6 µm.

[0040] The physical interface connecting the first sub-monocrystalline silicon layer 602 and the second sub-monocrystalline silicon layer 604 is a dielectric-free first silicon-silicon bonding interface 80. The term "dielectric-free" explicitly defines this interface as a direct, homogeneous bond in terms of chemical composition and physical structure; that is, silicon atoms directly form covalent bonds with each other, without any intermediate dielectric layer composed of heterogeneous atoms (such as oxygen atoms) that would impede electrical conduction. This is fundamentally different from the oxide-containing (Si-O-Si) interface formed after traditional hydrophilic bonding. This first silicon-silicon bonding interface 80 can be formed, for example, using surface-activated bonding (SAB) technology. In a high-vacuum environment, the SAB process uses an ion beam, such as an argon ion beam, to physically bombard and remove the natural oxide layers and contaminants from the two silicon surfaces to be bonded, "activating" the surface atoms and making them highly reactive. When two such surfaces come into contact, they immediately form strong silicon-silicon (Si-Si) covalent bonds at room temperature.

[0041] Although this application uses SAB technology as an example, the concept of dielectric-free to oxide-free is intended to encompass a class of technologies in which the native oxide layer is removed via an in-situ process prior to contact bonding to form direct silicon-silicon (Si-Si) covalent bonds at low or room temperature. A common feature of these technologies is the final cleaning and activation of the bonding surface in a controlled environment, such as ultra-high vacuum.

[0042] For example, in some implementations, ex-situ wet chemical pretreatment can be combined with in-situ physical activation. This method first involves cleaning with hydrofluoric acid (HF) solution or hydrochloric acid (HCl) to remove most of the oxides and form a hydrogen-passivated surface; subsequently, in an ultra-high vacuum environment, a final physical sputtering cleaning and surface activation is performed using a low-energy argon (Ar) ion beam; finally, the two surfaces are pressed together at room temperature to form a direct covalent bond with virtually no intermediate oxide layer.

[0043] Reference Figure 2 Because the bombardment of high-energy ion beams in the SAB process disturbs the ordered arrangement of the crystal lattice, the actual first silicon-silicon bonding interface 80 formed may contain an extremely thin amorphous silicon layer 802 at the outermost interface. Figure 2 To illustrate the amorphous silicon layer 802, it is not drawn to scale and is only shown schematically. The term "amorphous" refers to the fact that the silicon atoms in this layer have lost the long-range ordered lattice structure they possess in single-crystal silicon, exhibiting a short-range ordered, long-range disordered atomic arrangement, similar to the microstructure of fused silica. In contrast, the first sub-single-crystal silicon layer 602 and the second sub-single-crystal silicon layer 604 are composed of single-crystal silicon, in which all atoms are strictly arranged according to a uniform lattice periodicity in three-dimensional space, which is the foundation for realizing high-performance semiconductor devices. Because the amorphous silicon layer 802 is extremely thin, for example, its thickness can be less than 10 nm, in subsequent possible heat treatment processes, the amorphous silicon layer 802 can undergo solid-phase epitaxial recrystallization using the single-crystal silicon layers on both sides as templates. That is, the disordered atoms will rearrange and restore the ordered single-crystal structure, thus crystallographically integrating with the sub-single-crystal silicon layers on both sides, further eliminating the interface and achieving perfect crystal continuity.

[0044] The SOI substrate 100 provided in the above embodiments of this application is a functionally synergistic whole, and its structural integrity and unique functions stem from the precise interrelationships between its constituent layers. The SOI substrate 100 exhibits a clear vertical hierarchy: the supporting wafer 20 can be located at the bottom layer, directly covered by the silicon oxide layer 40, while the stacked single-crystal silicon layer 60 is disposed above the silicon oxide layer 40, forming the top functional area of ​​the entire structure. Inside the stacked single-crystal silicon layer 60, the first sub-single-crystal silicon layer 602 is in direct contact with the underlying silicon oxide layer 40, and the second sub-single-crystal silicon layer 604 is stacked above the first sub-single-crystal silicon layer 602. This hierarchical structure embodies "functional separation." Specifically, the silicon oxide layer 40 located in the middle of the structure plays a crucial role in achieving electrical isolation through a standard Si / SiO2 interface; while the first silicon-silicon bonding interface 80, located inside the stacked single-crystal silicon layer and without a dielectric layer, plays the opposite crucial role, achieving electrical and crystallographic connections by forming Si-Si covalent bonds. It is this differentiated treatment of different interface functions that enables two independent sub-single-crystal silicon layers to be synthesized into a whole at the atomic level, ensuring that current can flow vertically between the stacked sub-single-crystal silicon layers without obstruction, and that the entire stacked layer macroscopically appears as a continuous single crystal, which is crucial for vertical power devices.

[0045] In summary, the SOI substrate 100 provided in the above embodiments of this application includes a supporting wafer 20, a silicon oxide layer 40, and a stacked single-crystal silicon layer 60. The stacked single-crystal silicon layer 60 includes a first sub-single-crystal silicon layer 602 and a second sub-single-crystal silicon layer 604 connected by a first silicon-silicon bonding interface 80 without a dielectric layer. Since the first silicon-silicon bonding interface 80 without a dielectric layer ensures that silicon atoms between the two sub-single-crystal silicon layers directly form covalent bonds, thereby achieving atomic-level connectivity both electrically and crystallographically, this structure can synthesize two independent thin single-crystal silicon layers into a unified, continuous thick single-crystal silicon layer. Based on this, the SOI substrate 100 provided in the embodiments of this application can accumulate thickness by stacking sub-single-crystal silicon layers, which inherently possess better film thickness uniformity, thus structurally combining the thickness required for high-voltage devices with the high-precision uniformity required for large-scale manufacturing. In some embodiments, the first silicon-silicon bonding interface 80 without a dielectric layer can be formed using surface activated bonding (SAB) technology. One feature of SAB technology is that its bonding process can be completed at room temperature. This avoids thermal stress that may be introduced by high-temperature processing, or unnecessary atomic diffusion of the already formed dopant distribution. In addition, this also provides the possibility of applying this technology to the integration of heterogeneous materials in the future.

[0046] Furthermore, in the embodiment where the first silicon-silicon bonding interface 80 is formed using SAB technology, the thickness of the amorphous silicon layer 802 can be controlled to less than 10 nm. This ensures that the solid-state epitaxial recrystallization process can be completed efficiently and completely within the standard thermal budget of semiconductor manufacturing. This transforms the interface layer from a process byproduct into a controllable structure compatible with existing mainstream processes, eliminating the need for additional dedicated thermal treatment steps to repair the interface.

[0047] Regarding the specific product specifications of the SOI substrate 100, according to some embodiments, the total thickness of the stacked single-crystal silicon layer 60 can be between 1µm and 10µm to meet the application requirements of different power devices. Correspondingly, the thickness variation range of the stacked single-crystal silicon layer 60 can be controlled to less than 5nm. Combining micron-level total thickness with nanometer-level uniformity control helps ensure good consistency in device performance.

[0048] Furthermore, the technical solution of this application has good scalability. The stacked single-crystal silicon layer 60 can be composed of two or more sub-single-crystal silicon layers. For example, see... Figure 3In addition to the first sub-monocrystalline silicon layer 602 and the second sub-monocrystalline silicon layer 604, the SOI substrate 100 may also include a third sub-monocrystalline silicon layer 606, and in embodiments not shown, may even include more sub-monocrystalline silicon layers. In such a multilayer structure, each sub-monocrystalline silicon layer is connected to its adjacent sub-monocrystalline silicon layer through a silicon-silicon bonding interface without a dielectric layer. For example, the third sub-monocrystalline silicon layer 606 can be connected to the second sub-monocrystalline silicon layer 604 through a second silicon-silicon bonding interface 90. That is, the second sub-monocrystalline silicon layer 604 is connected to the first sub-monocrystalline silicon layer 602 below it and the third sub-monocrystalline silicon layer 606 above it through the first silicon-silicon bonding interface 80 and the second silicon-silicon bonding interface 90, respectively. This modular and iterative characteristic provides a new technical path for the fabrication of customized SOI substrates.

[0049] Other embodiments of this application also provide a method for fabricating a silicon-on-insulator substrate. (Refer to...) Figure 4 The method may include the following steps S100 to S400: In step S100, an initial silicon-on-insulator (SiI) structure is provided. This initial SiI structure serves as the foundation platform for subsequent stacking processes and includes a support wafer 20, a silicon oxide layer 40 disposed thereon, and a first sub-monocrystalline silicon layer 602 serving as the stacking starting point. In some embodiments, step S100 can be performed using a high-precision thin-film transfer technique. Specifically, it may include: providing a second donor wafer; bonding the second donor wafer to the support wafer 20 via the silicon oxide layer 40; and then transferring the first sub-monocrystalline silicon layer 602 from the second donor wafer. In some examples, a dense, uniform silicon dioxide layer can be formed on the second donor wafer using a furnace tube thermal oxidation method, which will become the silicon oxide layer 40 (BOX layer) in the final structure. The furnace tube thermal oxidation method is a way to form a high-quality BOX layer due to its simple process, low cost, and the resulting dense, uniform oxide layer with superior electrical properties. Next, a hydrophilic bonding technique is used to bond the second donor wafer with the silicon oxide layer 40 to the support wafer 20. The purpose of choosing hydrophilic bonding is to utilize its ability to form high-quality Si-O-Si bonds at the bonding interface, which helps to construct the isolation interface as the electrical isolation core. Finally, the first sub-monocrystalline silicon layer 602 can be transferred from the second donor wafer using a high-precision thin-film transfer technique, such as Smart Cut™. This step completes the first mode of bonding in the multimode bonding strategy, laying the foundation for subsequent silicon layer stacking using the second mode of bonding (dielectric-free bonding).

[0050] In step S300, surface activation treatment is performed on the surface of the first sub-monocrystalline silicon layer and the surface of the first donor wafer. This treatment can be performed in a high vacuum environment by physically bombarding the two silicon surfaces to be bonded with an ion beam to remove the native oxide layer and contaminants on the surface and activate the surface atoms.

[0051] In step S300, a first silicon-silicon bonding interface 80 without a dielectric layer is formed by bonding the surface-activated surface of the first donor wafer to the surface-activated surface of the first sub-monocrystalline silicon layer. After the two surfaces are activated, they are brought into contact with each other to form strong, direct silicon-silicon covalent bonds at room temperature.

[0052] In step S400, a stacked single-crystal silicon layer 60 is formed by transferring a second sub-single-crystal silicon layer 604 from the first donor wafer onto the first sub-single-crystal silicon layer to obtain an SOI substrate 100. This transfer step can be accomplished by pre-implanting ions into the first donor wafer to form a release layer, and then precisely peeling along the release layer.

[0053] By performing the above steps S100 to S400, an insulator-on-silicon substrate containing two sub-single-crystal silicon layers can be obtained.

[0054] In some embodiments, the method may also include a surface planarization step after step S400. For example, the roughness of the stripped surface and defects may be reduced and defects removed by rapid heat treatment in a hydrogen-containing atmosphere and / or by growing and removing a sacrificial oxide layer.

[0055] Furthermore, considering manufacturing costs, this method may also include the recycling of the donor wafer. After the second sub-monocrystalline silicon layer 604 is transferred from the first donor wafer in step S400, the remaining first donor wafer can be surface polished to restore it to a reusable state.

[0056] This fabrication method is iterative. By repeatedly executing the core process cycle of steps S200, S300, and S400, more sub-single-crystal silicon layers can be formed on the second sub-single-crystal silicon layer, thereby flexibly constructing SOI substrate products with different total thicknesses.

[0057] Examples and Comparative Examples To further verify the beneficial effects of the technical solutions provided in the embodiments of this application, the following comparative description is provided through specific embodiments and comparative examples.

[0058] Example 1: SOI substrate was prepared using the preparation method provided in the examples of this application.

[0059] Step 1: Provide the initial SOI structure. Using hydrophilic bonding and Smart Cut™ technology, a silicon oxide layer 40 with a thickness of 200 nm and a first sub-monocrystalline silicon layer 602 with a thickness of 0.8 µm and a thickness variation range of less than 5 nm are formed on a support wafer 20 with a diameter of 300 mm.

[0060] Step 2: Provide a first donor wafer, which has a lift-off layer pre-formed at a depth of 0.8µm by ion implantation. Place the initial SOI structure and the first donor wafer in a high-vacuum chamber, and use an argon ion beam to physically bombard the surface of the first sub-single-crystal silicon layer 602 and the surface of the first donor wafer to complete the surface activation treatment.

[0061] Step 3: In a vacuum environment, the activated first donor wafer surface is aligned and bonded to the surface of the first sub-single crystal silicon layer 602 to form a first silicon-silicon bonding interface 80 without a dielectric layer at room temperature.

[0062] Step 4: Perform heat treatment on the bonded wafer and peel it off along the release layer of the first donor wafer to transfer the second sub-single crystal silicon layer 604 with a thickness of 0.8µm onto the first sub-single crystal silicon layer 602, forming a stacked single crystal silicon layer 60 with a total thickness of 1.6µm.

[0063] Step 5: Measure the surface of the final stacked single-crystal silicon layer 60 to obtain its total thickness and film thickness uniformity.

[0064] Comparative Example 1: SOI substrates were fabricated using conventional BESOI technology. Two wafers were bonded together, and one wafer was then thinned using mechanical grinding and chemical mechanical polishing (CMP) until the top silicon layer reached a thickness of 1.6 µm. The uniformity of the film thickness was also measured.

[0065] Comparative Example 2: SOI substrates were fabricated using conventional single-pass Smart Cut™ technology. A thick-film SOI was attempted through a single high-energy ion implantation and stripping process. Due to the limitations of the equipment's energy limits, the final top silicon layer thickness was 0.8 µm. The uniformity of the film thickness was measured.

[0066] Comparative Example 3: A stacked SOI substrate was prepared using multiple ion implantation and peeling processes followed by multiple hydrophilic bonding processes. The process flow was similar to that of Example 1, but the surface activation bonding in steps S200 and S300 was replaced with conventional hydrophilic bonding. The final total thickness of the stacked layers was 1.6 µm. The interlayer interface structure was observed using transmission electron microscopy (TEM).

[0067] Results Comparison: The key performance indicators of the above embodiments and comparative examples are summarized in the table below: Table 1: Performance Comparison of Examples and Comparative Examples

[0068] As can be seen from the results in the table above, the SOI substrate provided in the above embodiments of this application can simultaneously possess micron-level thickness and nanometer-level uniformity. Furthermore, by introducing surface-activated bonding, a high-quality silicon-silicon bonding interface is formed, ensuring the electrical and crystallographic integrity of the top silicon layer. In contrast, each comparative example can only meet some of the requirements or has fatal structural defects, failing to achieve the same or equivalent technical effects as this application.

[0069] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon-on-insulator substrate, characterized in that, include: Support wafer; A silicon oxide layer disposed on the support wafer; Stacked single-crystal silicon layers disposed on the silicon oxide layer The stacked single-crystal silicon layer includes at least a first sub-single-crystal silicon layer and a second sub-single-crystal silicon layer, and the first sub-single-crystal silicon layer and the second sub-single-crystal silicon layer are connected by a first silicon-silicon bonding interface without a dielectric layer.

2. The silicon-on-insulator substrate according to claim 1, characterized in that, The first silicon-silicon bonding interface is formed through surface activation bonding.

3. The silicon-on-insulator substrate according to claim 2, characterized in that, The first silicon-silicon bonding interface includes an amorphous silicon layer with a thickness of less than 10 nm.

4. The silicon-on-insulator substrate according to claim 1, characterized in that, The total thickness of the stacked single-crystal silicon layers is between 1µm and 10µm.

5. The silicon-on-insulator substrate according to claim 1 or 4, characterized in that, The thickness of the stacked single-crystal silicon layer varies by less than 5 nm.

6. The silicon-on-insulator substrate according to claim 1, characterized in that, It also includes a third sub-monocrystalline silicon layer, which is connected to the second sub-monocrystalline silicon layer through a second silicon-silicon bonding interface without a dielectric layer.

7. A method for preparing a silicon-on-insulator substrate, characterized in that, include: An initial silicon-on-insulator structure is provided, the initial silicon-on-insulator structure comprising a support wafer, a silicon oxide layer disposed on the support wafer, and a first sub-monocrystalline silicon layer disposed on the silicon oxide layer; Surface activation treatment is performed on the surface of the first sub-monocrystalline silicon layer and the surface of the first donor wafer; By bonding the surface of the first donor wafer, which has undergone surface activation treatment, to the surface of the first sub-monocrystalline silicon layer, a first silicon-silicon bonding interface without a dielectric layer is formed. as well as By transferring a second sub-monocrystalline silicon layer from the first donor wafer onto the first sub-monocrystalline silicon layer, a stacked monocrystalline silicon layer is formed to obtain a silicon-on-insulator substrate.

8. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, The provision of the initial silicon-on-insulator structure includes: Provide a second donor wafer; The second donor wafer is bonded to the support wafer via the silicon oxide layer; The first sub-monocrystalline silicon layer is transferred from the second donor wafer.

9. The method for preparing a silicon-on-insulator substrate according to claim 7 or 8, characterized in that, The step of transferring the second sub-monocrystalline silicon layer from the first donor wafer includes: implanting ions into the first donor wafer to form a release layer, and stripping along the release layer.

10. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, Also includes: After the second sub-monocrystalline silicon layer is transferred, the surface of the second sub-monocrystalline silicon layer is planarized.

11. The method for fabricating a silicon-on-insulator substrate according to claim 10, characterized in that, The surface planarization process includes: Rapid heat treatment in a hydrogen-containing atmosphere; and Following the rapid thermal treatment, a sacrificial oxide layer is formed and removed on the surface of the second sub-monocrystalline silicon layer.

12. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, Also includes: After the step of transferring the second sub-single-crystal silicon layer from the first donor wafer, the first donor wafer is subjected to surface polishing. The first donor wafer, after surface polishing, is reused as a donor wafer in subsequent substrate fabrication processes.

13. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, Also includes: Repeat the steps of surface activation treatment, bonding, and transfer to form a third sub-monocrystalline silicon layer on the second sub-monocrystalline silicon layer.

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