Semiconductor device and forming method thereof
By connecting the conductive structures between multiple chips using wafer-level bonding technology, the problem of high interconnect density of multiple chips is solved, resulting in higher signal transmission rates and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUBEI 3D SEMICON INTEGRATED INNOVATION CENT CO LTD
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-22
AI Technical Summary
Existing packaging technologies cannot meet the development needs of high interconnect density between multiple chips, especially when the number of chip I/O increases, it is difficult to improve the interconnect density and signal transmission rate of the redistribution layer.
A wafer-level bonding process is used to connect the first conductive structure and the second conductive structure. Through bonding between the first wafer and the second wafer, interconnection between multiple chips is achieved. The wafer-level bonding process replaces the redistribution layer, thereby increasing interconnection density and shortening interconnection trace distance.
It increases the interconnect density between multiple chips, shortens the interconnect trace distance, improves the signal transmission rate, and reduces the power consumption of semiconductor devices.
Smart Images
Figure CN122074009A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology
[0002] As integrated circuit chip performance improves and miniaturization advances, different chips are connected together during the chip packaging process, achieving interconnection between multiple chips. However, with the increasing number of I / Os on chips, current packaging technologies are no longer sufficient to meet the growing demand for high interconnection density between multiple chips due to limitations in equipment, materials, and manufacturing processes.
[0003] Therefore, how to increase the interconnect density between multiple chips is a technical problem that needs to be solved. Summary of the Invention
[0004] This application provides a semiconductor device and a method for forming the same, to improve the interconnection density between multiple chips, thereby at least partially solving the above-mentioned technical problems.
[0005] To achieve the above objectives, according to a first aspect of this application, a method for forming a semiconductor device is provided, the method comprising:
[0006] A first wafer is formed, the first wafer including a first substrate, a first chip and a first bonding layer, the first chip being embedded inside the first substrate, the first bonding layer being located on the surface of the first substrate and the surface of the first chip, the first bonding layer including a first conductive structure, the first conductive structure being connected to the first chip;
[0007] A second wafer is formed, the second wafer including a second substrate, a first device layer and a second bonding layer, the first device layer and the second bonding layer being located on the second substrate, and the second bonding layer including a second conductive structure;
[0008] The first bonding layer is bonded to the second bonding layer, and the first conductive structure is connected to the second conductive structure.
[0009] According to a second aspect of this application, a semiconductor device is provided, comprising:
[0010] A first semiconductor structure includes a first substrate, a first chip, and a first bonding layer. The first chip is embedded inside the first substrate, and the first bonding layer is located on the surface of the first substrate and the surface of the first chip. The first bonding layer includes a first conductive structure, and the first conductive structure is connected to the first chip.
[0011] The second semiconductor structure is located on one side of the first semiconductor structure and includes a second substrate, a first device layer and a second bonding layer. The first device layer and the second bonding layer are located on the second substrate. The second bonding layer includes a second conductive structure. The first bonding layer and the second bonding layer are located between the first substrate and the second substrate and are bonded to each other. The first conductive structure is connected to the second conductive structure.
[0012] In some embodiments of the semiconductor device and the method of forming the same, a wafer-level bonding process is used between a first wafer and a second wafer to connect a first conductive structure and a second conductive structure, thereby achieving interconnection between a first chip in the first wafer and a chip including a first device layer in the second wafer. The interconnection density of the first conductive structure and the second conductive structure is large, thereby improving the interconnection density of interconnection traces between multiple chips. Attached Figure Description
[0013] Figure 1 This is a cross-sectional schematic diagram of a packaging structure.
[0014] Figure 2 A schematic flowchart illustrating a method for forming a semiconductor device provided for some embodiments of this application;
[0015] Figures 3 to 9 A schematic diagram of the formation process of a semiconductor device provided for some embodiments of this application;
[0016] Figures 10 to 11 Schematic diagrams of the formation process of semiconductor devices provided for other embodiments of this application;
[0017] Figures 12 to 13 This is a schematic diagram of the formation process of a semiconductor device provided for some other embodiments of this application.
[0018] Explanation of reference numerals in the attached figures:
[0019] 1. Packaging structure;
[0020] 11. Chip stacking structure; 111. Memory chip; 112. Through-silicon via (TSV);
[0021] 12. Computing chip;
[0022] 13. Silicon interposer; 131. Rewiring layer;
[0023] 141. First conductive protrusion; 142. Second conductive protrusion;
[0024] 100. Semiconductor device; 101. First semiconductor structure; 102. Second semiconductor structure; 103. Third semiconductor structure;
[0025] 2. The first wafer;
[0026] 21. First substrate; 21A. First surface; 21B. Second surface; 21C. First chip receiving slot; 21D. Second chip receiving slot;
[0027] 221, First chip; 222, Second chip; 2211, 2221, Solder pads;
[0028] 23. First bonding layer; 231. First conductive structure; 232. Third conductive structure;
[0029] 24. First dielectric layer; 241. First opening; 242. Third opening;
[0030] 25. Thermal conductive layer; 251. Initial thermal conductive layer;
[0031] 3. Second wafer;
[0032] 31. Second substrate; 31A. Third surface; 31B. Fourth surface; 31C. Third chip receiving slot; 31D. Fourth chip receiving slot;
[0033] 32. First device layer; 321. Third chip; 322. Fourth chip; 3211, 3221. Pads; 323. First non-chip device;
[0034] 33. Second bonding layer; 331. Second conductive structure; 332. Fourth conductive structure;
[0035] 34. Second dielectric layer; 341. Second opening; 342. Fourth opening;
[0036] 35. First interconnect layer; 351. First conductive interconnect structure;
[0037] 36. Second interconnect layer; 361. Second conductive interconnect structure;
[0038] 371. Through-contact point;
[0039] 38. Third bonding layer; 381. Fifth conductive structure;
[0040] 4. Third wafer;
[0041] 41. The third basement;
[0042] 42. Second device layer; 421. Second non-chip device;
[0043] 43. Fourth bonding layer; 431. Sixth conductive structure. Detailed Implementation
[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0045] Please refer to Figure 1 As shown, the package structure 1 includes a chip stack structure 11, a computing chip 12, and a silicon interposer 13. The chip stack structure 11 is adjacent to the computing chip 12, and both are connected to the silicon interposer 13 via a first conductive bump 141 and interconnected via a redistribution layer 131 in the silicon interposer 13. The chip stack structure 11 includes multiple stacked memory chips 111. Adjacent memory chips 111 are connected via through-silicon vias (TSVs) 112 and second conductive bumps 142. Signals are input to or output to the memory chips 111 through the TSVs 112.
[0046] To increase the number of I / Os in the memory chip 111, it is necessary to increase the number of through-silicon vias 112 and the density of interconnects in the redistribution layer 131. However, due to limitations in process technology, current packaging techniques cannot further increase the density of interconnects in the redistribution layer 131.
[0047] To address the aforementioned problems, this application provides a method for forming a semiconductor device. Please refer to... Figure 2 As shown, the method for forming a semiconductor device includes:
[0048] Step S101: Form a first wafer. The first wafer includes a first substrate, a first chip, and a first bonding layer. The first chip is embedded inside the first substrate. The first bonding layer is located on the surface of the first substrate and the surface of the first chip. The first bonding layer includes a first conductive structure and is connected to the first chip.
[0049] Step S102: Form a second wafer, the second wafer including a second substrate, a first device layer and a second bonding layer, the first device layer and the second bonding layer being located on the second substrate, the second bonding layer including a second conductive structure;
[0050] Step S103: Bond the first bonding layer to the second bonding layer and connect the first conductive structure to the second conductive structure.
[0051] In some embodiments of the semiconductor device formation method of this application, a wafer-level bonding process is used between a first wafer and a second wafer to connect a first conductive structure and a second conductive structure, thereby achieving interconnection between a first chip in the first wafer and a chip including a first device layer in the second wafer. The high interconnection density of the first and second conductive structures increases the interconnection density of interconnect traces between multiple chips. In other words, using a wafer-level bonding process to replace the redistribution layer for interconnection between multiple chips increases the interconnection density of interconnect traces between multiple chips. Furthermore, the wafer-level bonding process for interconnection between different chips can shorten the distance of interconnect traces, increase the signal transmission rate between different chips, and reduce the power consumption of the semiconductor device.
[0052] Figures 3 to 9 The diagram below illustrates the structural process of forming a semiconductor device according to some embodiments of this application. Figures 2 to 9 The methods for forming semiconductor devices according to some embodiments of this application will be described in detail.
[0053] Reference Figures 3 to 7 As shown, perform the above step S101.
[0054] In some embodiments, step S101 above may include:
[0055] Step S1011: Provide a first substrate 21 and a first chip 221, wherein the first substrate 21 has a first surface 21A and a second surface 21B opposite to each other;
[0056] Step S1012: A first chip receiving groove 21C is formed in the first substrate 21, and the first chip receiving groove 21C is recessed from the first surface 21A toward the second surface 21B;
[0057] Step S1013: Place the first chip 221 in the first chip receiving slot 21C.
[0058] Through the above steps S1011 to S1013, the first chip 221 is embedded in the first substrate 21 so that the first chip 221 can be interconnected with chips in other wafers through the bonding process of the first wafer 2 with other wafers.
[0059] In some related technologies, bonding processes between chips and wafers are used to interconnect different chips. After forming the chip-wafer bonding structure, the subsequent metal wire routing process is quite complex. For example, the back-side planarization process of the chip is limited by the filling of the dielectric layer between chips and the chip thickness, which increases the difficulty of the planarization process and thus affects the yield of semiconductor devices. Furthermore, in other related technologies, two device wafers are bonded together at the wafer level. The yield inspection of individual chips in the device wafer is time-consuming and labor-intensive, which also affects the yield of semiconductor devices.
[0060] In some embodiments of this application, the first chip 221 to be interconnected is embedded in the first substrate 21 to form a first wafer 2. The interconnection of the first chip 221 is achieved using the bonding process of the first wafer 2, which eliminates the need for dielectric layer filling and planarization processes during chip-wafer bonding, optimizes wafer defects, and thus improves the yield of the semiconductor device 100. Furthermore, the first chip can be tested before being embedded in the first substrate, and the first chip that passes the test can be embedded in the first substrate to further improve the yield of the semiconductor device.
[0061] In some embodiments, in step S1011, the first substrate 21 may include a semiconductor substrate, which may include silicon (Si), germanium (Ge) or silicon-germanium (GeSi), silicon carbide (SiC), or other materials. In other embodiments, the first substrate 21 may include a semiconductor substrate and one or more other films formed on the semiconductor substrate, which may be an oxide film (SiO2), a silicon nitride film (SiN), or a silicon oxynitride film (SiON), etc. For example, as... Figure 3 As shown, the first substrate 21 includes a silicon substrate.
[0062] In some embodiments, in step S1011, the first chip 221 can be any one of a memory chip, a computing chip, a power chip, and a sensor chip.
[0063] In some embodiments, such as Figure 3 As shown, the first chip 221 includes a back surface and a functional surface disposed opposite to each other, and the functional surface is provided with pads 2211. The pads 2211 are used to transmit electrical signals.
[0064] In some embodiments, in step S1012, photoresist can be coated on the first surface 21A of the first substrate 21, exposed to light passing through a photomask, and then treated with a developer to obtain patterned photoresist. Next, using the patterned photoresist as a mask, an etching process is employed to remove a portion of the first substrate 21, forming a first chip accommodating groove 21C within the first substrate 21. The photomask is designed according to the pre-embedded first chip.
[0065] In some embodiments, in the direction from the first surface 21A to the second surface 21B, the cross-sectional shape of the first chip receiving groove 21C can be either rectangular or inverted trapezoidal. For example, as... Figure 5 As shown, in the direction from the first surface 21A to the second surface 21B, the cross-sectional shape of the first chip receiving groove 21C can be an inverted trapezoid.
[0066] In some embodiments, the volume of the first chip receiving groove 21C is larger than the volume of the first chip 221, which reduces the difficulty of placing the first chip 221 in the first chip receiving groove 21C and also facilitates the complete embedding of the first chip 221 in the first substrate 21.
[0067] In some embodiments, the depth of the first chip receiving trench 21C may be greater than the thickness of the first chip 221, so as to facilitate the placement of the first chip 221 in the first chip receiving trench 21C and reduce the thickness of the first wafer 2. In other embodiments, the depth of the first chip receiving trench 21C may be less than or equal to the thickness of the first chip 221. The thickness of the first chip 221 is equal to the distance between the functional surface and the back surface of the first chip 221. The depth of the first chip receiving trench 21C is equal to the dimension of the first chip receiving trench 21C in the direction from the first surface 21A to the second surface 21B.
[0068] In some embodiments, the first substrate 21 may further include a chip receiving groove recessed from the second surface 21B toward the first surface 21A. This allows for the full utilization of the first substrate 21 to provide more receiving grooves for embedding chips.
[0069] In some embodiments, such as Figure 6 As shown, step S1013, which involves placing the first chip 221 in the first chip receiving groove 21C, includes placing the back side of the first chip 221 at the bottom of the first chip receiving groove 21C. The first chip 221 includes a back side and a functional side that are disposed opposite to each other, and the functional side is provided with pads 2211. In this way, the functional side of the first chip 221 is disposed away from the bottom of the first chip receiving groove 21C, which helps to simplify the formation process of the first conductive structure 231 connected to the pads 2211.
[0070] In some embodiments, such as Figures 3 to 6 As shown, step S101 above, forming the first wafer 2, may further include:
[0071] Step S1014: Provide a second chip 222, the power of which is greater than that of the first chip 221;
[0072] Step S1015: A second chip receiving groove 21D is formed in the first substrate 21. The second chip receiving groove 21D is recessed from the first surface 21A toward the second surface 21B and is spaced apart from the first chip receiving groove 21C.
[0073] Step S1016: A thermally conductive layer 25 is formed on the wall of the second chip receiving groove 21D;
[0074] Step S1017: Place the second chip 222 in the second chip receiving slot 21D and place it on the thermal conductive layer 25.
[0075] Through steps S1014 to S1017, a heat-conducting layer 25 is formed in the second chip receiving groove 21D where the second chip 222 is placed, so that the heat generated during the operation of the high-power second chip 222 can be conducted to the first substrate 21 and dissipated more quickly through the heat-conducting layer 25, thereby balancing the heat dissipation effect between the first chip 221 and the second chip 222 with different powers.
[0076] It should be noted that in step S1014, the power of the second chip 222 is greater than that of the first chip 221, resulting in greater power consumption of the second chip 222 than that of the first chip 221, and thus more heat generation during operation. By forming a thermally conductive layer 25 on the wall of the second chip receiving slot 21D, the heat dissipation rate of the second chip 222 can be accelerated.
[0077] In some embodiments, the second chip 222 and the first chip 221 may have the same function, for example, both may be memory chips. In other embodiments, the functions of the second chip 222 and the first chip 221 may be different, for example, one may be a memory chip and the other may be a computing chip.
[0078] In some embodiments, steps S1011 and S1014 may be performed simultaneously. In other embodiments, steps S1011 and S1014 may be performed separately.
[0079] In some embodiments, the second chip receiving slot 21D may be the same as the first chip receiving slot 21C, so as to form the second chip receiving slot 21D and the first chip receiving slot 21C simultaneously, simplifying the formation process of the first wafer 2. When the second chip receiving slot 21D is the same as the first chip receiving slot 21C, steps S1015 and S1012 can be performed simultaneously.
[0080] In other embodiments, such as Figure 5As shown, the second chip receiving slot 21D can be different from the first chip receiving slot 21C, for example, their groove depths may differ, so that two chips of different sizes can be placed in them respectively, thus satisfying the requirement of placing chips of different sizes. When the second chip receiving slot 21D is different from the first chip receiving slot 21C, steps S1015 and S1012 can be executed simultaneously, or steps S1015 and S1012 can be executed step by step.
[0081] For example, such as Figure 4 and Figure 5 As shown, step S1015 is performed before step S1012. That is, before forming the first chip accommodating trench 21C in the first substrate 21, the second chip accommodating trench 21D is formed in the first substrate 21. The formation of the second chip accommodating trench 21D in the first substrate 21 is also achieved through the above-described photolithography and etching processes.
[0082] In some implementations, such as Figure 4 and Figure 5 As shown, step S1016, which involves forming a thermally conductive layer 25 on the wall of the second chip receiving groove 21D, includes: forming an initial thermally conductive layer 251, the initial thermally conductive layer 251 being located on the wall of the second chip receiving groove 21D and on the first surface 21A; and removing the initial thermally conductive layer 251 outside the second chip receiving groove 21D, the remaining initial thermally conductive layer 251 constituting the thermally conductive layer 25 on the wall of the second chip receiving groove 21D.
[0083] For example, step S1011 is performed after step S1016 is completed. This reduces the difficulty of removing the initial thermal conductive layer 251 outside the second chip accommodating slot 21D.
[0084] In some embodiments, the removal of the initial thermally conductive layer 251 outside the second chip accommodating groove 21D can be achieved by etching or chemical mechanical polishing.
[0085] In some embodiments, the initial thermally conductive layer 251 can be formed by a thin film deposition process. The thin film deposition process includes, but is not limited to, at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
[0086] In some embodiments, the thermally conductive layer 25 on the wall of the second chip receiving groove 21D may include at least one of silicon carbide, polysilicon, and metal nitride. This ensures that the thermally conductive layer 25 on the wall of the second chip receiving groove 21D has high thermal conductivity, guaranteeing that the heat from the second chip 222 in the second chip receiving groove 21D can be conducted more quickly through the thermally conductive layer 25 to the first substrate 21 and then dissipated.
[0087] In some embodiments, the metal nitride includes at least one of boron nitride and aluminum nitride.
[0088] In some embodiments, the thermally conductive layer 25 on the wall of the second chip receiving groove 21D can be one or more different thermally conductive layers 25. In some embodiments, the thermally conductive layer 25 on the wall of the second chip receiving groove 21D may include a first thermally conductive layer and a second thermally conductive layer. The first thermally conductive layer is located between the wall of the second chip receiving groove 21D and the second thermally conductive layer. The adhesion between the first thermally conductive layer and the first substrate 21 is greater than the adhesion between the second thermally conductive layer and the first substrate 21, and the thermal conductivity of the second thermally conductive layer is greater than the thermal conductivity of the first thermally conductive layer. Thus, different first and second thermally conductive layers cooperate to ensure that the thermally conductive layer 25 on the wall of the second chip receiving groove 21D has high thermal conductivity, while the first thermally conductive layer also ensures good adhesion between the thermally conductive layer 25 and the first substrate 21. Exemplarily, the first thermally conductive layer includes polycrystalline silicon, and the second thermally conductive layer includes silicon carbide.
[0089] In some embodiments, the thickness of the thermally conductive layer 25 on the wall of the first chip accommodating groove 21C can be from 0.1 micrometers to 50 micrometers. In this way, while ensuring that the thermally conductive layer 25 has high thermal conductivity, the problem of the thermally conductive layer 25 occupying too much space and increasing the thickness of the first wafer 2 is improved.
[0090] In some embodiments, when a thermally conductive layer 25 is formed on the wall of the second chip receiving slot 21D, the method further includes forming a thermally conductive layer on the wall of the first chip receiving slot 21C, wherein the thermal conductivity of the thermally conductive layer on the wall of the first chip receiving slot 21C is less than the thermal conductivity of the thermally conductive layer 25 on the wall of the second chip receiving slot 21D. Thus, based on the heat difference caused by the power difference between the first chip 221 and the second chip 222, thermally conductive layers with different thermal conductivity are formed in the first chip receiving slot 21C and the second chip receiving slot 21D respectively, to balance the heat dissipation effect between the different chips.
[0091] In some embodiments, the thermally conductive layer 25 on the wall of the first chip accommodating groove 21C includes at least one of silicon carbide, polysilicon, and metal nitride.
[0092] In some embodiments, the thickness of the thermally conductive layer on the wall of the first chip receiving groove 21C is less than the thickness of the thermally conductive layer 25 on the wall of the second chip receiving groove 21D, and / or, the thermal conductivity of the material of the thermally conductive layer 25 on the wall of the first chip receiving groove 21C is less than the thermal conductivity of the material of the thermally conductive layer 25 on the wall of the second chip receiving groove 21D. That is, through the differentiated design of at least one of the thickness and material of the thermally conductive layer, the thermal conductivity of the thermally conductive layer on the wall of the first chip receiving groove 21C is less than the thermal conductivity of the thermally conductive layer 25 on the wall of the second chip receiving groove 21D.
[0093] In some embodiments, the thickness of the thermally conductive layer 25 on the wall of the second chip accommodating groove 21D can be from 0.1 micrometers to 50 micrometers. In this way, while ensuring that the thermally conductive layer 25 has high thermal conductivity, the problem of the thermally conductive layer 25 occupying too much space and increasing the thickness of the first wafer 2 is mitigated.
[0094] In some embodiments, such as Figure 6 As shown, in step S1017 above, placing the second chip 222 in the second chip receiving groove 21D and on the thermally conductive layer 25 includes: placing the back side of the second chip 222 on the thermally conductive layer 25 at the bottom of the second chip receiving groove 21D. The second chip 222 includes a back side and a functional side disposed opposite to each other, and the functional side is provided with pads 2221. In this way, the functional side of the second chip 222 is disposed away from the bottom of the second chip receiving groove 21D, which helps to simplify the formation process of the conductive structure connected to the pads 2221 of the second chip 222.
[0095] In some embodiments, such as Figure 7 As shown, forming the first wafer 2 also includes:
[0096] Step S1018: A first dielectric layer 24 is formed to fill the remaining first chip accommodating trench 21C and cover the functional surface and first surface 21A of the first chip 221. The first bonding layer 23 also includes at least a portion of the first dielectric layer 24. Thus, the first dielectric layer 24 not only fills the remaining first chip accommodating trench 21C, but also fixes the first chip 221 within the first chip accommodating trench 21C, and at least a portion of the first dielectric layer 24 is also used for bonding. The first dielectric layer 24 has multiple functions, simplifying the fabrication process of the first wafer 2.
[0097] It should be noted that, compared with using adhesive layers or the like to fix the first chip 221 in the first chip receiving groove 21C, using the first dielectric layer 24 can better fix the first chip 221 in the first chip receiving groove 21C and simplify the manufacturing process of the first wafer 2.
[0098] The first dielectric layer 24 can be a single layer or multiple layers of insulating layers. In some embodiments, the first dielectric layer 24 includes an insulating material. The insulating material may include at least one of inorganic insulating materials and organic insulating materials. The inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The organic insulating material may include epoxy resin, etc. Wherein, when the first dielectric layer 24 is an inorganic insulating material, the first dielectric layer 24 has good high-temperature resistance and a larger process window. Exemplarily, the first dielectric layer 24 may include a silicon oxide layer.
[0099] In some embodiments, the first dielectric layer 24 can be formed by the thin film deposition process described above.
[0100] It should be noted that, as Figure 7 As shown, when a second chip receiving groove 21D is formed within the first substrate 21, and the second chip 222 is placed on the thermally conductive layer 25 of the second chip receiving groove 21D, the first dielectric layer 24 further fills the remaining portion of the second chip receiving groove 21D and covers the second functional surface of the second chip 222. Thus, the first dielectric layer 24 further fills the remaining portion of the second chip receiving groove 21D and fixes the second chip 222 within the second chip receiving groove 21D.
[0101] In some embodiments, such as Figure 7 As shown, forming the first wafer 2 also includes:
[0102] Step S1019: Form a first opening 241 through the first dielectric layer 24 and expose the pad 2211 of the first chip 221;
[0103] In step S1020, a first conductive structure 231 is formed in the first opening 241, and the first conductive structure 231 is connected to the pad 2211.
[0104] Through the above steps S1019 and S1020, a first conductive structure 231 connected to the pad 2211 of the first chip 221 is formed, simplifying the formation process of the first opening 241 and the first conductive structure 231.
[0105] In some embodiments, such as Figure 7 As shown, forming the first wafer 2 further includes: forming a third opening 242 that penetrates the first dielectric layer 24 and exposes the pads 2221 of the second chip 222; and forming a third conductive structure 232 in the third opening 242, wherein the third conductive structure 232 is connected to the pads 2221 of the second chip 222. This achieves the connection between the third conductive structure 232 and the second chip 222.
[0106] In some embodiments, the third opening 242 and the first opening 241 can be formed simultaneously, and the third conductive structure 232 can be formed simultaneously with the first conductive structure 231. In some embodiments, the first opening 241 and the first conductive structure 231 can be formed using a damascus process.
[0107] In some embodiments, the first opening 241 and the third opening 242 are stepped openings. In some embodiments, the first conductive structure 231 and the third conductive structure 232 include at least one of copper, aluminum, and tungsten. Exemplarily, the first conductive structure 231 and the third conductive structure 232 include copper.
[0108] It should be noted that the first wafer 2 may include not only the first chip 221 and the second chip 222 embedded in the first substrate 21, but may also include other chips; that is, three or more chips may be embedded in the first substrate 21. The first bonding layer 23 may include conductive structures connected to each chip to facilitate interconnection with other chips through the conductive structures. Furthermore, Figure 7 The illustration only shows a first chip 221 and a second chip 222 in the first wafer 2. In reality, the first chip 221 and the second chip 222 are embedded in the first substrate 21 in an array. That is, the first wafer 2 includes a plurality of first chips 221 and a plurality of second chips 222 arranged in an array.
[0109] As described above, in step S101, the first chip 221 is embedded in the first substrate 21, and a first bonding layer 23 is formed on the surfaces of the first substrate 21 and the first chip 221 to form a chip wafer in which the first chip 221 is embedded. Interconnection between different chips is achieved by using wafer-level bonding between the first wafer 221 and other wafers.
[0110] In some embodiments, such as Figure 8 As shown, step S102 above, which forms the second wafer 3, includes:
[0111] Step S1021: Provide a second substrate 31 and a third chip 321, wherein the second substrate 31 has opposing third surfaces 31A and fourth surfaces 31B;
[0112] Step S1022: A third chip receiving groove 31C is formed in the second substrate 31, and the third chip receiving groove 31C is recessed from the third surface 31A toward the fourth surface 31B;
[0113] Step S1023: Place the third chip 321 in the third chip receiving slot 31C, and the first device layer 32 includes the third chip 321 in the third chip receiving slot 31C.
[0114] Through steps S1021 to S1023, the third chip 321 is embedded in the second substrate 31 so that the third chip 321 can be interconnected with the first chip 221 in the first wafer 2 through the bonding process of the second wafer 3, while reducing the thickness of the second wafer 3.
[0115] In some embodiments, the second substrate 31 may be the same as the first substrate 21. In some embodiments, the second substrate 31 may include a semiconductor substrate. In other embodiments, the second substrate 31 may further include a semiconductor substrate and one or more other film layers formed on the semiconductor substrate.
[0116] The third chip 321 has a back surface and a functional surface disposed opposite to each other, and the functional surface is provided with pads 3211. In some embodiments, the function of the third chip 321 may be the same as that of the first chip 221. Exemplarily, both the third chip 321 and the first chip 221 are memory chips. In other embodiments, the function of the third chip 321 may be different from that of the first chip 221. Exemplarily, the first chip 221 is a memory chip, and the third chip 321 is a logic chip.
[0117] In some embodiments, the shape of the cross-section of the third chip receiving groove 31C along the direction from the third surface 31A to the fourth surface 31B can be either rectangular or inverted trapezoidal.
[0118] In some embodiments, the volume of the third chip receiving slot 31C is larger than the volume of the third chip 321. This simplifies the process of placing the third chip 321 in the third chip receiving slot 31C and ensures that the third chip 321 is embedded in the second substrate 31.
[0119] In some embodiments, such as Figure 8 As shown, forming the second wafer 3 also includes:
[0120] Step S1024: Form a second dielectric layer 34 to fill the remaining third chip receiving trench 31C and cover the third chip 321 and the third surface 31A. The second dielectric layer 34 includes a second opening 341 that exposes the pads 3211 of the third chip 321. The second bonding layer 33 also includes at least a portion of the second dielectric layer 34; and,
[0121] Step S1025: A second conductive structure 331 is formed in the second opening 341, and the second conductive structure 331 is connected to the pad 3211 of the third chip 321.
[0122] Through the aforementioned steps S1024 and S1025, the second dielectric layer 34 fills the gap between the third chip 321 and the third chip receiving groove 31C, and also fixes the third chip 321 in the third chip receiving groove 31C. Furthermore, at least a portion of the second dielectric layer 34 also serves as the dielectric layer of the second bonding layer 33, meaning that the second dielectric layer 34 has multiple different functions, simplifying the manufacturing process of the second wafer 3.
[0123] In some embodiments, the second dielectric layer 34 may be one or more insulating layers. The second dielectric layer 34 may be the same as or different from the first dielectric layer 24. In some embodiments, the second dielectric layer 34 includes an insulating material. The insulating material may include at least one of inorganic insulating materials and organic insulating materials. Inorganic insulating materials may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Organic insulating materials may include epoxy resin, etc. Exemplarily, the second dielectric layer 34 may include silicon oxide.
[0124] It should be noted that the method for forming the second dielectric layer 34 can be the same as the method for forming the first dielectric layer 24 described above. The method for forming the second conductive structure 331 can be the same as the method for forming the first conductive structure 231 described above.
[0125] In some embodiments, such as Figure 8 As shown, forming the second wafer 3 also includes:
[0126] Step S1026: A fourth chip receiving groove 31D is formed in the second substrate 31. The fourth chip receiving groove 31D is recessed from the third surface 31A toward the fourth surface 31B and is spaced apart from the third chip receiving groove 31C.
[0127] Step S1027: Place the fourth chip 322 in the fourth chip receiving slot 31D.
[0128] Through the above steps S1026 and S1027, the fourth chip 322 is embedded in the second substrate 31 so that the fourth chip 322 can be interconnected with the chip in the first wafer 2 through the bonding process of the second wafer 3.
[0129] In some embodiments, at least one of the fourth chip receiving slot 31D and the third chip receiving slot 31C is provided with a thermally conductive layer. The formation process of the thermally conductive layer in at least one of the third chip receiving slot 31C and the fourth chip receiving slot 31D is the same as the formation process of the thermally conductive layer in the second chip receiving slot described above, and will not be repeated here.
[0130] In some embodiments, the fourth chip 322 may have the same or different functions as the third chip 321. The function of the fourth chip 322 may also be the same as or different from that of at least one of the first chip 221 and the second chip 222.
[0131] It should be noted that the second dielectric layer 34 formed in step S1024 can also fill the gap between the fourth chip receiving groove 31D and the fourth chip 322, and cover the fourth chip 322. Furthermore, the second dielectric layer 34 also includes a fourth opening 342 exposing the pads 2211 of the fourth chip 322. In step S1025, during the formation of the second conductive structure 331, a fourth conductive structure 332 connected to the pads 3221 of the fourth chip 322 is also formed in the fourth opening 342.
[0132] It should also be noted that, in addition to embedding the third chip 321 and the fourth chip 322, other chips can also be embedded in the second wafer 3. Furthermore, Figure 8 This only illustrates a third chip 321 and a fourth chip 322. The array of third chip 321 and fourth chip 322 is embedded in the second substrate 21.
[0133] In some embodiments, such as Figure 9 As shown, perform step S103 as described above.
[0134] for Figure 9 The semiconductor device shown achieves interconnection between the first chip 221 and the third chip 321 through wafer-level bonding between the second wafer 3 and the first wafer 2, and the connection between the first conductive structure 231 and the second conductive structure 331. This increases the density of the interconnect traces connecting the first chip 221 and the third chip 321, meeting the requirements for high-density interconnection of multiple chips. Simultaneously, it shortens the distance of the interconnect traces between the first chip 221 and the third chip 321, thereby increasing the signal transmission rate and reducing the power consumption of the semiconductor device 100.
[0135] In some embodiments, such as Figure 9 As shown, step S103 further includes connecting the third conductive structure 232 and the fourth conductive structure 332. Thus, the interconnection between the second chip 222 and the fourth chip 322 is achieved through the bonding process between the first wafer 2 and the second wafer 3.
[0136] In some embodiments, the first bonding layer 23 and the second bonding layer 33 are bonded together by a hybrid bonding process.
[0137] It should be noted that, Figure 9 The semiconductor device 100 shown is only schematically illustrated to show the interconnection between the first chip 221 and the third chip 321. In other embodiments, the first chip 221 may be interconnected with both the third chip 321 and the fourth chip 322 via the aforementioned wafer-level bonding process, or the first chip 221 may be interconnected with three or more chips in the second substrate 31. Furthermore, the second chip 222 may be interconnected with at least one of the third chip 321 and the fourth chip 322 via the aforementioned wafer-level bonding process.
[0138] In other embodiments, such as Figure 10 As shown, step S102 above, forming the second wafer 3, includes:
[0139] A second substrate 31 is provided; a first device layer 32 is formed on the second substrate 31, the first device layer 32 including a first non-chip device 323;
[0140] A second bonding layer 33 is formed, which is located on the first device layer 32 and the second substrate 31.
[0141] In other embodiments, Figure 10 The second wafer 3 shown is a device wafer. Since the second bonding layer 33 is located on the first device layer 32, when bonding is performed using the second bonding layer 33 of the second wafer 3, the front side of the second wafer 3 is bonded to the first wafer 2. The first device layer 32 of the second wafer 3 can be one or more layers.
[0142] In other embodiments, the first non-chip device 323 may include at least one of a MOS device, a sensor, a memory, and a passive device.
[0143] In other embodiments, such as Figure 10 As shown, after forming the first device layer 32 on the second substrate 31 and before forming the second bonding layer 33, forming the second wafer 3 further includes: forming a first interconnect layer 35, the first interconnect layer 35 being located on the first device layer 32 and including a first conductive interconnect structure 351, the first conductive interconnect structure 351 being connected to the first non-chip device 323. The first conductive interconnect structure 351 may include one or more conductive layers, and an insulating layer is disposed between adjacent conductive layers.
[0144] In other embodiments, such as Figure 10 As shown, the second conductive structure 331 of the second bonding layer 33 is connected to the first conductive interconnect structure 351.
[0145] In other embodiments, such as Figure 11 As shown, step S103 is executed. Through wafer-level bonding between the front side of the second wafer 3 and the first wafer 2, and the connection between the first conductive structure 231 and the second conductive structure 331, interconnection between the first chip 221 and the chip including the first non-chip device 323 is achieved. This increases the density of interconnect traces between chips, meeting the requirements for high-density interconnection of multiple chips. Simultaneously, the distance of the interconnect traces is shortened, thereby increasing the signal transmission rate and reducing the power consumption of the semiconductor device 100.
[0146] It should be noted that, Figure 11In the semiconductor device shown, the first device layer 32 may include a device structure of one or more chips. This allows for the interconnection between the first chip 221 and one or more chips in the second wafer 3. Furthermore, Figure 11 The semiconductor device shown is formed by the following process and Figure 9 The formation processes of the semiconductor devices shown are basically similar, except for the formation process of the second wafer. The similarities will not be described again.
[0147] In some other embodiments, such as Figure 12 As shown, step S102 above, forming the second wafer 3, includes:
[0148] Provide a second substrate 31;
[0149] A first device layer 32 is formed on the second substrate 31, and the first device layer 32 includes a first non-chip device 323;
[0150] A through contact 371 is formed that penetrates the second substrate 31;
[0151] A second bonding layer 33 is formed on the surface of the second substrate 31 opposite to the first device layer 32, and the second conductive structure 331 is connected to the through contact 371.
[0152] In yet other embodiments, Figure 12 The second wafer 3 shown is a device wafer. Since the second bonding layer 33 is located on the surface of the second substrate 31 away from the first device layer 32, when bonding is performed using the second bonding layer 33 of the second wafer 3, the back side of the second wafer 3 is bonded to the first wafer 2.
[0153] In some other embodiments, such as Figure 12 As shown, after forming the first device layer 32 on the second substrate 31, forming the second wafer 3 further includes: forming a first interconnect layer 35, the first interconnect layer 35 being located on the first device layer 32 and including a first conductive interconnect structure 351, the first conductive interconnect structure 351 being connected to the first non-chip device 323. A through contact 371 also extends into the first interconnect layer 35 and is connected to the first conductive interconnect structure 351.
[0154] In some other embodiments, such as Figure 12 As shown, before forming the second bonding layer 33 on the surface of the second substrate 31 opposite to the first device layer 32, forming the second wafer 3 further includes forming a second interconnect layer 36 on the surface of the second substrate 31 opposite to the first device layer 32. The second interconnect layer 36 includes a second conductive interconnect structure 361. The second conductive interconnect structure 361 connects the second conductive structure 331 and the through contact 371. Thus, the connection between the first device layer 32 and the second conductive structure 331 is achieved through the through contact 371, the first conductive interconnect structure 351, and the second conductive interconnect structure 361.
[0155] In some other embodiments, such as Figure 12 As shown, the method also includes:
[0156] A third bonding layer 38 is formed, which is located on the side of the second substrate 31 opposite to the second bonding layer 33;
[0157] A third wafer 4 is formed, which includes a third substrate 41, a second device layer 42 and a fourth bonding layer 43, with the second device layer 42 and the fourth bonding layer 43 located on the third substrate 41.
[0158] The third bonding layer 38 is bonded to the fourth bonding layer 43.
[0159] Based on the interconnection of the internal chips of the first wafer 2 and the second wafer 3 through the wafer-level bonding process, the connection between the two is achieved through the wafer-level bonding process between the third wafer 4 and the second wafer 3, thereby increasing the number of chips in the semiconductor device 100 and improving the performance of the semiconductor device 100.
[0160] In other embodiments, the second device layer 42 may include a chip or a non-chip device. The non-chip device may include at least one of a MOS device, a sensor, a memory, and a passive device. In one exemplary embodiment, the second device layer 42 includes a second non-chip device 421.
[0161] In some other embodiments, the third bonding layer 38 includes a fifth conductive structure 381, and the fourth bonding layer 43 includes a sixth conductive structure 431, with the fifth conductive structure 381 and the sixth conductive structure 431 connected. Thus, the interconnection density between the chips in the third wafer 4 and the chips in the second wafer 3 is increased through the fifth conductive structure 381 and the sixth conductive structure 431.
[0162] In some embodiments, the fourth bonding layer 43 may be located on the surface of the third substrate 41 facing away from the second device layer 42. The third wafer 4 may further include a third interconnect layer, through-contacts, and a fourth interconnect layer. The third interconnect layer is located between the fourth bonding layer 43 and the third substrate 41 and includes a third conductive interconnect structure, which is connected to the sixth conductive structure 431. The fourth interconnect layer is located on the second device layer 42 and the third substrate 41 and includes a fourth conductive interconnect structure, which is connected to the devices in the second device layer 42. The through-contacts penetrate the third substrate 41 and connect the third conductive interconnect structure and the fourth conductive interconnect structure. In this way, the connection between the sixth conductive structure 431 and the devices in the second device layer 42 is achieved.
[0163] In some other embodiments, such as Figure 12 and Figure 13As shown, the third wafer 4 can be bonded to the second wafer 3 to obtain a stacked wafer, and then the second wafer 3 in the stacked wafer can be bonded to the first wafer 2 at the wafer level. In some other embodiments, the second wafer 3 can be bonded to the first wafer 2 to obtain a stacked wafer, and then the third wafer 4 can be bonded to the second wafer 3 of the stacked wafers.
[0164] In some other embodiments, such as Figure 13 As shown, after the wafer-level bonding of the first wafer 2 to the third wafer 4 is completed, other wafers can be bonded to at least one of the third wafer 4 and the first wafer 2 on the side away from the second wafer 3. The number of wafers can be set according to actual needs, and no specific limit is made here.
[0165] It should be noted that after the wafer bonding process is completed, a back-end-of-line (BEOL) process can be performed to obtain a wafer stack structure. Next, the wafer stack structure is diced to form a semiconductor device 100, which includes multiple vertically interconnected chips.
[0166] Accordingly, please refer to Figure 9 As shown in the figure, this application embodiment also provides a semiconductor device 100.
[0167] Semiconductor device 100 includes a first semiconductor structure 101 and a second semiconductor structure 102. The first semiconductor structure 101 includes a first substrate 21, a first chip 221, and a first bonding layer 23. The first chip 221 is embedded within the first substrate 21. The first bonding layer 23 is located on the surface of the first substrate 21 and the surface of the first chip 221. The first bonding layer 23 includes a first conductive structure 231, which is connected to the first chip 221. The second semiconductor structure 102 is located on one side of the first semiconductor structure 101 and includes a second substrate 31, a first device layer 32, and a second bonding layer 33. The first device layer 32 and the second bonding layer 33 are located on the second substrate 31. The second bonding layer 33 includes a second conductive structure 331. The first bonding layer 23 and the second bonding layer 33 are located between the first substrate 21 and the second substrate 31 and are bonded together. The first conductive structure 231 is connected to the second conductive structure 331.
[0168] In some embodiments of this application, the first chip 221 and the second semiconductor structure 102 are interconnected through a first conductive structure 231 of the first bonding layer 23 and a second conductive structure 331 of the second bonding layer 33. The high interconnection density of the first conductive structure 231 and the second conductive structure 331 increases the interconnection density of the interconnection traces between the first chip 221 and the second semiconductor structure 102. Furthermore, the interconnection between the first chip 221 and the second semiconductor structure 102 through the first conductive structure 231 of the first bonding layer 23 and the second conductive structure 331 of the second bonding layer 33 shortens the distance of the interconnection traces between the first chip 221 and the second semiconductor structure 102, increases the signal transmission rate between the first chip 221 and the second semiconductor structure 102, and reduces the power consumption of the semiconductor device 100. Moreover, since the first chip 221 is embedded in the first substrate 21, the semiconductor device can be obtained without a planarization process, improving the yield of the semiconductor device.
[0169] In some embodiments, the first substrate 21 has a first surface 21A and a second surface 21B disposed opposite to each other. The first substrate 21 includes a first chip receiving groove 21C, which is recessed from the first surface 21A toward the second surface 21B. The first chip 221 is located in the first chip receiving groove 21C. This facilitates the interconnection between the first chip 221 in the first substrate 21 and the second semiconductor structure 102, while reducing the thickness of the first semiconductor structure 101, thereby reducing the size of the semiconductor device 100.
[0170] In some embodiments, the first semiconductor structure 101 further includes a second chip receiving groove 21D, a thermally conductive layer 25, and a second chip 222. The second chip receiving groove 21D is recessed from the first surface 21A toward the second surface 21B and is spaced apart from the first chip receiving groove 21C. The thermally conductive layer 25 is located on the groove wall of the second chip receiving groove 21D. The second chip 222 is placed in the second chip receiving groove 21D and is located on the thermally conductive layer 25, and the power of the second chip 222 is greater than that of the first chip 221. Thus, a thermally conductive layer 25 is formed in the second chip receiving groove 21D in which the second chip 222 is placed, so that the heat generated during the operation of the high-power second chip 222 can be conducted to the first substrate 21 more quickly through the thermally conductive layer 25 and dissipated, balancing the heat dissipation effect between the first chip 221 and the second chip 222 with different power.
[0171] In some embodiments, the first chip 221 has a back side and a functional side disposed opposite to each other, the functional side being provided with pads 2211, and the back side of the first chip 221 being located at the bottom of the first chip receiving groove 21C. This facilitates a simplified fabrication process for the first conductive structure 231 connected to the pads 2211 of the first chip 221.
[0172] In some embodiments, the semiconductor device 100 further includes a first dielectric layer 24, which fills the gap between the sidewall of the first chip accommodating trench 21C and the first chip 221, and covers the functional surface and the first surface 21A. The first bonding layer 23 includes at least a portion of the first dielectric layer 24. Thus, the first dielectric layer 24 not only fills the remaining portion of the first chip accommodating trench 21C, but also secures the first chip 221 within the first chip accommodating trench 21C. Compared to securing the first chip 221 within the first chip accommodating trench 21C using an adhesive layer or the like, the first dielectric layer 24 provides a better fixation of the first chip 221 within the first chip accommodating trench 21C and simplifies the manufacturing process of the semiconductor device 100. Furthermore, the first dielectric layer 24 serves to fill, fix, and bond, thereby simplifying the manufacturing process of the semiconductor device 100.
[0173] In some embodiments, the first conductive structure 231 is located inside the first dielectric layer 24 and is connected to the pad 2211 of the first chip 221. This achieves the connection between the first chip 221 and the first conductive structure 231.
[0174] In some embodiments, the first device layer 32 includes a third chip 321, which is embedded in the second substrate 31. Thus, the first chip 221 and the third chip 321 are interconnected through a first conductive structure 231 of the first bonding layer 23 and a second conductive structure 331 of the second bonding layer 33, increasing the density of the interconnect traces connecting the first chip 221 and the third chip 321, meeting the requirements for high-density interconnection of multiple chips. Simultaneously, the distance between the interconnect traces between the first chip 221 and the third chip 321 is shortened, thereby increasing the signal transmission rate and reducing the power consumption of the semiconductor device 100.
[0175] In some embodiments, the semiconductor device 100 further includes a second dielectric layer 34, which fills the gap between the third chip 321 and the second substrate 31 and covers both the third chip 321 and the second substrate 31. A second conductive structure 331 is located inside the second dielectric layer 34 and connected to the pads 3211 of the third chip 321. A second bonding layer 33 includes at least a portion of the second dielectric layer 34. Thus, the second dielectric layer 34 fills the gap between the third chip 321 and the third chip receiving groove 31C, and also fixes the third chip 321 in the third chip receiving groove 31C. At least a portion of the second dielectric layer 34 also serves as a bonding layer. The second dielectric layer 34 has various functions, simplifying the manufacturing process of the semiconductor device.
[0176] In other embodiments, reference is made to Figure 11As shown, the first device layer 32 includes a first non-chip device 323, and the second bonding layer 33 is located on the first device layer 32 and the second substrate 31. Thus, the first chip 221 and the second semiconductor structure 102 including the first non-chip device 323 are interconnected through the first conductive structure 231 of the first bonding layer 23 and the second conductive structure 331 of the second bonding layer 33. The high interconnection density of the first conductive structure 231 and the second conductive structure 331 further increases the interconnection density of the interconnection traces between the first chip 221 and the second semiconductor structure 102. Furthermore, the second bonding layer 33 located on the first device layer 32 is bonded to the first bonding layer 23, such that the front side of the second semiconductor structure 102 is bonded to the first chip 221.
[0177] In other embodiments, reference is made to Figure 11 As shown, the second semiconductor structure 102 also includes a first interconnect layer 35, which is located between the second bonding layer 33 and the first device layer 32. The first interconnect layer 35 includes a first conductive interconnect structure 351, which is connected to the first non-chip device 323 and the second conductive structure 331.
[0178] In yet other embodiments, reference is made to Figure 13 As shown, the second bonding layer 33 is located on the surface of the second substrate 31 facing away from the first device layer 32. The semiconductor device 100 also includes a through contact 371, which penetrates the second substrate 31 and is connected to the second conductive structure 331. Thus, the second bonding layer 33 located on the surface of the second substrate 31 facing away from the first device layer 32 is bonded to the first bonding layer 23, so that the back side of the second semiconductor structure 102 is bonded to the first chip 221.
[0179] In yet other embodiments, reference is made to Figure 13 As shown, the second semiconductor structure 102 further includes a first interconnect layer 35 and a second interconnect layer 36. The first interconnect layer 35 is located on the first device layer 32 and includes a first conductive interconnect structure 351. A through contact 371 extends into the first interconnect layer 35 and is connected to the first conductive interconnect structure 351. The first conductive interconnect structure 351 is connected to the first non-chip device 323. The second interconnect layer 36 is located between the second substrate 31 and the second bonding layer 33 and includes a second conductive interconnect structure 361, which is connected between the through contact 371 and the second conductive structure 361.
[0180] In yet other embodiments, reference is made to Figure 13As shown, the semiconductor device 100 also includes a third bonding layer 38 and a third semiconductor structure 103. The third bonding layer 38 is located on the side of the second substrate 31 opposite to the second bonding layer 33. The third semiconductor structure 103 includes a third substrate 41, a second device layer 42, and a fourth bonding layer 43. The second device layer 42 and the fourth bonding layer 43 are located on the third substrate 41, and the third bonding layer 38 and the fourth bonding layer 43 are located between the second substrate 31 and the third substrate 41 and bonded together. In this way, the number of semiconductor structures in the semiconductor device 100 is increased, thereby improving performance.
[0181] It should be noted that, Figure 9 , Figure 11 as well as Figure 13 The semiconductor device 100 shown is manufactured by the above-described method for forming semiconductor device 100. The relevant content in the method for forming semiconductor device 100 applies to semiconductor device 100 and will not be repeated here.
[0182] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0183] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0184] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0185] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A method for forming a semiconductor device, characterized in that, The method includes: A first wafer is formed, the first wafer including a first substrate, a first chip and a first bonding layer, the first chip being embedded inside the first substrate, the first bonding layer being located on the surface of the first substrate and the surface of the first chip, the first bonding layer including a first conductive structure, the first conductive structure being connected to the first chip; A second wafer is formed, the second wafer including a second substrate, a first device layer and a second bonding layer, the first device layer and the second bonding layer being located on the second substrate, and the second bonding layer including a second conductive structure; The first bonding layer is bonded to the second bonding layer, and the first conductive structure is connected to the second conductive structure.
2. The method for forming a semiconductor device according to claim 1, characterized in that, The formation of the first wafer includes: A first substrate and a first chip are provided, wherein the first substrate has opposing first and second surfaces; A first chip receiving groove is formed within the first substrate, the first chip receiving groove being recessed from the first surface toward the second surface; Place the first chip in the first chip receiving slot.
3. The method for forming a semiconductor device according to claim 2, characterized in that, The formation of the first wafer also includes: A second chip is provided, the power of which is greater than that of the first chip; A second chip receiving groove is formed in the first substrate, the second chip receiving groove being recessed from the first surface toward the second surface and spaced apart from the first chip receiving groove; A thermally conductive layer is formed on the wall of the second chip accommodating slot; The second chip is placed in the second chip receiving slot and is located on the thermal conductive layer.
4. The method for forming a semiconductor device according to claim 3, characterized in that, Before forming the first chip receiving groove in the first substrate, a second chip receiving groove is formed in the first substrate, and a thermally conductive layer is formed on the groove wall of the second chip receiving groove.
5. The method for forming a semiconductor device according to claim 2, characterized in that, The step of placing the first chip in the first chip receiving slot includes: The back side of the first chip is placed at the bottom of the first chip receiving slot. The first chip includes the back side and the functional side, which are disposed opposite to each other. The functional side is provided with pads.
6. The method for forming a semiconductor device according to claim 5, characterized in that, The formation of the first wafer also includes: A first dielectric layer is formed to fill the remaining first chip receiving slot and cover the functional surface and the first surface of the first chip. The first bonding layer also includes at least a portion of the first dielectric layer.
7. The method for forming a semiconductor device according to claim 6, characterized in that, The formation of the first wafer also includes: A first opening is formed through the first dielectric layer and exposes the pads of the first chip; The first conductive structure is formed in the first opening, and the first conductive structure is connected to the pad.
8. The method for forming a semiconductor device according to any one of claims 1 to 7, characterized in that, The formation of the second wafer includes: A second substrate and a third chip are provided, wherein the second substrate has opposing third and fourth surfaces; A third chip receiving groove is formed within the second substrate, the third chip receiving groove being recessed from the third surface toward the fourth surface; The third chip is placed in the third chip receiving slot, and the first device layer includes the third chip in the third chip receiving slot.
9. The method for forming a semiconductor device according to claim 8, characterized in that, The method further includes: A second dielectric layer is formed to fill the remaining third chip receiving groove and cover the third chip and the third surface. The second dielectric layer includes a second opening that exposes the pads of the third chip. The second bonding layer also includes at least a portion of the second dielectric layer. The second conductive structure is formed in the second opening, and the second conductive structure is connected to the pad of the third chip.
10. A semiconductor device, characterized in that, include: A first semiconductor structure includes a first substrate, a first chip, and a first bonding layer. The first chip is embedded inside the first substrate, and the first bonding layer is located on the surface of the first substrate and the surface of the first chip. The first bonding layer includes a first conductive structure, and the first conductive structure is connected to the first chip. The second semiconductor structure is located on one side of the first semiconductor structure and includes a second substrate, a first device layer and a second bonding layer. The first device layer and the second bonding layer are located on the second substrate. The second bonding layer includes a second conductive structure. The first bonding layer and the second bonding layer are located between the first substrate and the second substrate and are bonded to each other. The first conductive structure is connected to the second conductive structure.
11. The semiconductor device according to claim 10, characterized in that, The first substrate has a first surface and a second surface disposed opposite to each other. The first substrate includes a first chip receiving groove, which is recessed from the first surface toward the second surface, and the first chip is located in the first chip receiving groove.
12. The semiconductor device according to claim 11, characterized in that, The first semiconductor structure further includes: The second chip receiving slot is recessed from the first surface toward the second surface and is spaced apart from the first chip receiving slot; The thermal conductive layer is located on the wall of the second chip accommodating slot; The second chip is located in the second chip accommodating slot and on the thermal conductive layer, and the power of the second chip is greater than that of the first chip.
13. The semiconductor device according to claim 11, characterized in that, The first chip has a back side and a functional side that are disposed opposite to each other. The functional side is provided with pads. The back side of the first chip is located at the bottom of the first chip receiving groove.
14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a first dielectric layer, which fills the gap between the sidewall of the first chip accommodating trench and the first chip, and covers the functional surface and the first surface.
15. The semiconductor device according to claim 14, characterized in that, The first conductive structure is located inside the first dielectric layer and is connected to the pad.
16. The semiconductor device according to any one of claims 10 to 15, characterized in that, The first device layer includes a third chip, which is embedded in the second substrate.
17. The semiconductor device according to claim 16, characterized in that, The semiconductor device further includes a second dielectric layer that fills the gap between the third chip and the second substrate and covers the third chip and the second substrate. The second conductive structure is located inside the second dielectric layer and is connected to the pads of the third chip.