Manufacturing method of packaging structure

Abstract

The invention relates to a manufacturing method of a packaging structure, and the method comprises the steps: providing a wafer, arranging a plurality of chips on the wafer in an array manner, and forming a to-be-protected groove in the surface of one side, far away from the wafer, of each chip; a mask plate is placed on the surface of the side, away from the wafer, of the chip, and a plurality of openings formed in the mask plate expose the to-be-protected grooves respectively; forming a protective layer in the groove to be protected; the mask plate is removed; forming an electromagnetic shielding layer on the surface of one side, close to the chip, of the wafer, wherein the electromagnetic shielding layer covers the wafer, the chip and the protective layer; and removing the protective layer and the electromagnetic shielding layer on the protective layer to expose the groove to be protected. According to the invention, one-time formation of the electromagnetic shielding layers of the plurality of chips is realized, and the risk of dislocation or fracture in the manufacturing process of the electromagnetic shielding layers is reduced or avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a method for manufacturing a packaging structure. Background Technology

[0002] In the field of semiconductor technology, there are many integrated circuit (IC) chips that are sensitive to electromagnetic interference, such as radio frequency (RF) chips (especially high-frequency RF chips). Electromagnetic shielding must be done before using such chips to ensure that the chips can operate normally.

[0003] System-in-Package (SiP) is an integrated modular design technology that combines one or more IC chips that perform overall electronic circuit functions, along with their associated discrete components, into a single plastic package. Within a SiP module, the most common shielding method is to use a shielding cover to enclose electromagnetic interference (EMI) sensitive components or components that generate EMI.

[0004] Generally, secondary molding encapsulation and encapsulating components in resin can be used to protect the package and components from mechanical damage, impact, and moisture. This method requires openings on the top and sides of the casing inside the component to facilitate the flow of encapsulating resin. Furthermore, in high-frequency operation, the number and size of these openings must be strictly limited to prevent EMI leakage.

[0005] However, due to the limited flowability of the encapsulating resin, some openings may be blocked by the resin, resulting in residual air inside the casing and the formation of air gaps. This can adversely affect the reliability of the encapsulation structure during subsequent heat transfer, and in severe cases, may even lead to the cracking and displacement of the casing. Summary of the Invention

[0006] Therefore, it is necessary to provide a method for manufacturing a packaging structure to achieve the one-time formation of electromagnetic shielding layers for multiple chips, thereby reducing or avoiding the risk of misalignment or breakage of the electromagnetic shielding layers.

[0007] This application provides a method for manufacturing a packaging structure, including:

[0008] A wafer is provided, on which multiple chips are arranged in an array, and a protective groove is formed on the surface of the chip on the side away from the wafer.

[0009] A mask is placed on the surface of the chip away from the wafer, and multiple openings on the mask expose multiple recesses to be protected.

[0010] A protective layer is formed within the groove to be protected;

[0011] Remove the mask;

[0012] An electromagnetic shielding layer is formed on the surface of the wafer near the chip, and the electromagnetic shielding layer covers the wafer, the chip and the protective layer;

[0013] Remove the protective layer and the electromagnetic shielding layer located on the protective layer to expose the groove to be protected.

[0014] In one embodiment, removing the protective layer and the electromagnetic shielding layer located on the protective layer includes:

[0015] The mask is placed again on the surface of the chip away from the wafer, and the opening exposes the electromagnetic shielding layer on the protective layer.

[0016] Remove the electromagnetic shielding layer and the protective layer exposed by the opening;

[0017] Remove the mask again.

[0018] In one embodiment, during the process of placing a mask on the surface of the chip away from the wafer, and during the process of placing the mask again on the surface of the chip away from the wafer, the projection of the opening toward the surface of the wafer covers the projection of the groove to be protected toward the surface of the wafer.

[0019] In one embodiment, the protective layer includes a photoresist layer; the removal of the protective layer and the electromagnetic shielding layer located on the protective layer includes:

[0020] The protective layer and the electromagnetic shielding layer located on the protective layer are removed by wet etching.

[0021] In one embodiment, the electromagnetic shielding layer is formed using a physical vapor deposition process.

[0022] In one embodiment, after removing the mask and before forming an electromagnetic shielding layer on the surface of the wafer near the chip, the method for manufacturing the packaging structure further includes:

[0023] The wafer was pre-cleaned using a capacitively coupled plasma instrument.

[0024] In one embodiment, the material of the electromagnetic shielding layer includes at least one of metallic and alloy materials.

[0025] In one embodiment, after forming an electromagnetic shielding layer on the surface of the wafer near the chip, the method for manufacturing the packaging structure further includes:

[0026] An electroplating metal process is performed to form a seed layer on the side of the electromagnetic shielding layer away from the wafer.

[0027] In one embodiment, the thickness of the electromagnetic shielding layer ranges from 1µm to 2µm.

[0028] In one embodiment, the mask is made of a metallic material.

[0029] In summary, this application exposes all the grooves to be protected on the wafer simultaneously by setting multiple openings on the mask, so that a protective layer can be accurately formed in all the grooves to be protected at once; by first forming an electromagnetic shielding layer that at least covers the protective layer, and then removing the protective layer, the remaining electromagnetic shielding layer exposes the grooves to be protected while covering the wafer and the chip, thereby achieving the one-time formation of electromagnetic shielding layers for multiple chips, reducing or avoiding the risk of misalignment or breakage during the manufacturing process of the electromagnetic shielding layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A flowchart illustrating a method for manufacturing a packaging structure according to one embodiment of this application.

[0032] Figure 2 This is a schematic diagram of the wafer structure in the step of providing a wafer in a method for manufacturing a packaging structure according to one embodiment of this application, along a direction perpendicular to the wafer surface.

[0033] Figure 3 This is a schematic diagram of the structure corresponding to the step of placing a mask on the surface of the chip away from the wafer in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0034] Figure 4 This is a schematic diagram of the structure corresponding to the step of forming a protective layer in the groove to be protected in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0035] Figure 5This is a schematic diagram of the structure corresponding to the step of removing the mask in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0036] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming an electromagnetic shielding layer on the surface of the wafer close to the chip in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0037] Figure 7 This is a schematic diagram of the structure corresponding to the step of placing the mask back on the surface of the chip away from the wafer in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0038] Figure 8 This is a schematic diagram of the structure corresponding to the step of removing the protective layer and the electromagnetic shielding layer located on the protective layer in the manufacturing method of the packaging structure provided in one embodiment of this application.

[0039] Explanation of reference numerals in the attached figures: 100-wafer; 110-chip; 111-groove to be protected; 120-protective layer; 130-electromagnetic shielding layer; 200-mask; 210-opening. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Generally, electromagnetic shielding of chips involves placing a metal casing around the chip's package or fabricating a metal film outside the package using magnetron sputtering. However, these methods increase the size of the chip package structure, and magnetron sputtering is prone to oversputtering and short circuits during the sputtering process. Furthermore, the metal layer formed by magnetron sputtering has poor adhesion to the package, making it prone to detachment during use.

[0046] System-in-Package (SiP) is an integrated modular design technology that combines one or more IC chips that perform overall electronic circuit functions, along with their associated discrete components, into a single plastic package. Electromagnetic interference (EMI) and radio frequency interference (RFI) are interferences caused by electromagnetic radiation emitted by electronic circuits and components carrying changing electrical signals. In single-package designs, especially when EMI-sensitive components and / or RF components are tightly packed together, EMI is a major factor affecting single-package designs. With the increasing application of wireless technology in small electronic devices, the need to consider EMI during design is growing.

[0047] Within a System-in-Package (SiP) module, the most common shielding method is to use a shield to enclose EMI-sensitive or EMI-generating components. These components are typically mounted on the front side of a support substrate, beneath which is a grounding trace layer. A metal or other shaped conductive enclosure is placed over the component to seal it within. This type of enclosure (including metal and conductive enclosures) occupies a significant portion of the surface area of ​​the support substrate, and the connection between the enclosure and the support substrate may be unstable. The solder joints securing the enclosure to the support substrate are subject to alternating stress, often leading to displacement of the enclosure from the substrate surface.

[0048] Generally, secondary molding encapsulation and encapsulating components (including housings) within resin can protect the package and components from mechanical damage, impact, and moisture corrosion. This method requires openings on the top and sides of the housing to facilitate resin flow, and the number and size of these openings must be strictly limited during high-frequency operation to prevent EMI leakage. However, due to the limited fluidity of the encapsulating resin, some openings may become blocked, leaving air gaps inside the housing. This negatively impacts the reliability of the package structure during subsequent heat transfer, and in severe cases, can even lead to housing breakage and displacement. Furthermore, currently used housings are often too large for high-density board-level packaging.

[0049] Therefore, it is necessary to provide a method for manufacturing a packaging structure to achieve the one-time formation of electromagnetic shielding layers for multiple chips, so as to reduce or avoid the risk of misalignment or breakage of electromagnetic shielding layers, thereby improving the efficiency and yield of high-density board-level packaging.

[0050] Figure 1 A flowchart illustrating a method for manufacturing a packaging structure according to one embodiment of this application. See also... Figure 1 One embodiment of this application provides a method for manufacturing a packaging structure, which includes the following steps S01 to S06.

[0051] Step S01: Provide a wafer on which multiple chips are arranged in an array, and a protection groove is formed on the surface of the chips away from the wafer.

[0052] Step S02: Place a mask on the surface of the chip away from the wafer, and expose multiple openings on the mask to protect multiple grooves.

[0053] It should be noted that the number and position of the openings and the recesses to be protected correspond one-to-one to ensure that the recesses to be protected in all chips on the wafer can be exposed by the mask, so that all chips can be processed simultaneously and the efficiency of the process can be improved.

[0054] Step S03: Form a protective layer in the groove to be protected.

[0055] It should be noted that by forming a protective layer in the groove to be protected, it is helpful to remove the electromagnetic shielding layer subsequently formed on the protective layer in the subsequent process, thereby ensuring that the electromagnetic shielding layer is exposed in the groove to be protected, reducing or avoiding the probability of misalignment of the electromagnetic shielding layer.

[0056] Step S04: Remove the mask.

[0057] Step S05: An electromagnetic shielding layer is formed on the surface of the wafer near the chip, the electromagnetic shielding layer covering the wafer, the chip and the protective layer.

[0058] Step S06: Remove the protective layer and the electromagnetic shielding layer located on the protective layer to expose the groove to be protected.

[0059] As can be seen, the final electromagnetic shielding layer, while covering the wafer and the chip, exposes the grooves inside the chip that need to be protected. This achieves electromagnetic shielding of the chip and facilitates the smooth progress of subsequent packaging processes.

[0060] The packaging structure manufacturing method described above exposes all the grooves to be protected on the wafer simultaneously by setting multiple openings on the mask, so that a protective layer can be accurately formed in all the grooves to be protected at once. By first forming an electromagnetic shielding layer that at least covers the protective layer and then removing the protective layer, the remaining electromagnetic shielding layer exposes the grooves to be protected while covering the wafer and the chip. This achieves the one-time formation of electromagnetic shielding layers for multiple chips, reducing or avoiding the risk of misalignment or breakage during the manufacturing process of the electromagnetic shielding layer.

[0061] See Figure 2 and Figure 3 ( Figure 3 for Figure 2 (A cross-sectional view of the wafer 100 along the AB direction) In one embodiment, multiple chips 110 are arranged in an array on the wafer 100, and a protective groove 111 is formed on the surface of the chip 110 away from the wafer 100.

[0062] Continue reading Figure 3 In one embodiment, a mask 200 is placed on the surface of the chip 110 away from the wafer 100, and a plurality of openings 210 provided on the mask 200 expose a plurality of recesses 111 to be protected. Optionally, the material of the mask 200 includes a metallic material, such as copper or aluminum.

[0063] It should be noted that during the process of placing the mask on the surface of the chip away from the wafer, the projection of the opening towards the wafer surface overlaps the projection of the groove to be protected towards the wafer surface. This ensures that the opening and the groove to be protected are aligned in a direction perpendicular to the wafer surface, thereby reducing or avoiding misalignment problems in the subsequently formed protective layer.

[0064] In other embodiments of this application, the opening may be configured to expose the area to be protected on the chip. The area to be protected may include a groove to be protected, or other semiconductor structures that do not require an electromagnetic shielding layer. This application does not impose any restrictions on this.

[0065] It is important to emphasize that the photomask is a reusable, independent component. The number and arrangement of openings on the photomask can be customized according to the type of wafer and the number and arrangement of chips on the wafer, thereby meeting the process requirements of different wafers. At the same time, the openings on the photomask can also expose other areas on the chip to be protected according to process requirements, as long as the condition that "the photomask covers the portion of the wafer that needs to form an electromagnetic shielding layer" is met; this application does not impose any restrictions on this.

[0066] See Figure 4 In one embodiment, a protective layer 120 is formed within the groove 111 to be protected. Optionally, the protective layer 120 may be formed by chemical vapor deposition (CVD).

[0067] In one embodiment, the surface of the protective layer 120 is higher than the surface of the chip 110 on both sides of the recess 111 to be protected, so as to assist in the alignment of the opening 210 on the mask 200 in subsequent processes. Optionally, the protective layer 120 includes a photoresist layer.

[0068] Next, refer to Figure 5 Remove the mask 200. It is important to emphasize that the mask 200 is a reusable, independent component; therefore, it can simply be removed from the surface of the wafer 100 using a robotic arm or other gripping device. Optionally, if there are residues on the mask 200 (such as impurities generated during the formation of the protective layer), the mask 200 can be cleaned after removal to prevent contamination during subsequent use.

[0069] See Figure 6 In one embodiment, an electromagnetic shielding layer 130 is formed on the surface of wafer 100 near chip 110 using a physical vapor deposition (PVD) process. The electromagnetic shielding layer 130 covers wafer 100, chip 110, and protective layer 120. In one embodiment, the material of the electromagnetic shielding layer 130 includes at least one of a metallic material and an alloy material. Optionally, the thickness of the electromagnetic shielding layer 130 ranges from 1µm to 2µm.

[0070] In one embodiment, after the mask is removed (i.e., after step S04) and before an electromagnetic shielding layer is formed on the surface of the wafer near the chip (i.e., before step S05), the method for manufacturing the package structure further includes: pre-cleaning the wafer using a capacitively coupled (CCP) plasma machine to remove dust and impurity particles from the wafer and chip surfaces.

[0071] See Figure 7 and Figure 8 In one embodiment, the process of removing the protective layer 120 and the electromagnetic shielding layer 130 located on the protective layer 120 includes: first, placing the mask 200 again on the surface of the chip 110 away from the wafer 100, and exposing the electromagnetic shielding layer 130 on the protective layer 120 through the opening 210; then, removing the electromagnetic shielding layer 130 and the protective layer 120 exposed by the opening 210; and then removing the mask 200 again to allow for subsequent packaging processes.

[0072] In one embodiment, during the process of placing the mask back on the surface of the chip away from the wafer, the projection of the opening toward the wafer surface covers the projection of the groove to be protected toward the wafer surface, so as to ensure that the opening and the protective layer are aligned in a direction perpendicular to the wafer surface, thereby reducing or avoiding the problem of misalignment in the final electromagnetic shielding layer.

[0073] When the surface of the protective layer formed in step S03 is higher than the chip surfaces on both sides of the groove to be protected, the process of placing the mask back on the surface of the chip away from the wafer can embed the protective layer that is higher than the chip surface into the opening, thereby further improving the alignment accuracy of the opening and the protective layer in the direction perpendicular to the wafer surface. This can also reduce or avoid the problem of misalignment of the final electromagnetic shielding layer.

[0074] When the protective layer includes a photoresist layer, the protective layer and the electromagnetic shielding layer located on the protective layer can be directly removed by wet etching without the use of a mask, thereby saving process steps and achieving self-alignment of the final electromagnetic shield.

[0075] In one embodiment, after forming an electromagnetic shielding layer on the surface of the wafer near the chip, the method for manufacturing the package structure further includes performing an electroplating metal process to form a seed layer (not shown) on the side of the electromagnetic shielding layer away from the wafer. In subsequent packaging processes, the seed layer can serve as a transition layer between the electromagnetic shielding layer and the encapsulating resin, increasing the adhesion between different film layers and thereby improving the stability of the final package structure.

[0076] In one embodiment, the packaging structure manufacturing method produces a high-density board-level packaging structure (i.e., a board-level packaging structure with a size greater than 300mm × 300mm), which prepares electromagnetic shielding layers for multiple chips in a one-time, batch, and high-density manner, thereby reducing packaging costs and improving packaging efficiency.

[0077] In summary, this application exposes all the grooves to be protected on the wafer simultaneously by setting multiple openings on the mask, so that a protective layer can be accurately formed in all the grooves to be protected at once; by first forming an electromagnetic shielding layer that at least covers the protective layer, and then removing the protective layer, the remaining electromagnetic shielding layer exposes the grooves to be protected while covering the wafer and the chip, thereby achieving the one-time formation of electromagnetic shielding layers for multiple chips, reducing or avoiding the risk of misalignment or breakage during the manufacturing process of the electromagnetic shielding layer.

[0078] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a packaging structure, characterized in that, include: A wafer is provided, on which multiple chips are arranged in an array, and a protective groove is formed on the surface of the chip on the side away from the wafer. A mask is placed on the surface of the chip away from the wafer, and multiple openings on the mask expose multiple recesses to be protected. A protective layer is formed within the groove to be protected; Remove the mask; An electromagnetic shielding layer is formed on the surface of the wafer near the chip, and the electromagnetic shielding layer covers the wafer, the chip and the protective layer; Remove the protective layer and the electromagnetic shielding layer located on the protective layer to expose the groove to be protected.

2. The method for manufacturing the packaging structure according to claim 1, characterized in that, The removal of the protective layer and the electromagnetic shielding layer located on the protective layer includes: The mask is placed again on the surface of the chip away from the wafer, and the opening exposes the electromagnetic shielding layer on the protective layer. Remove the electromagnetic shielding layer and the protective layer exposed by the opening; Remove the mask again.

3. The method for manufacturing the packaging structure according to claim 2, characterized in that, During the process of placing a mask on the surface of the chip away from the wafer, and during the process of placing the mask again on the surface of the chip away from the wafer, the projection of the opening toward the surface of the wafer covers the projection of the groove to be protected toward the surface of the wafer.

4. The method for manufacturing the packaging structure according to claim 1, characterized in that, The protective layer includes a photoresist layer; removing the protective layer and the electromagnetic shielding layer located on the protective layer includes: The protective layer and the electromagnetic shielding layer located on the protective layer are removed by wet etching.

5. The method for manufacturing the packaging structure according to claim 1, characterized in that, The electromagnetic shielding layer is formed using a physical vapor deposition process.

6. The method for manufacturing the packaging structure according to claim 5, characterized in that, After removing the mask and before forming an electromagnetic shielding layer on the surface of the wafer near the chip, the method for manufacturing the packaging structure further includes: The wafer was pre-cleaned using a capacitively coupled plasma instrument.

7. The method for manufacturing the packaging structure according to claim 1, characterized in that, The material of the electromagnetic shielding layer includes at least one of metallic materials and alloy materials.

8. The method for manufacturing the packaging structure according to claim 7, characterized in that, After forming an electromagnetic shielding layer on the surface of the wafer near the chip, the method for manufacturing the packaging structure further includes: An electroplating metal process is performed to form a seed layer on the side of the electromagnetic shielding layer away from the wafer.

9. The method for manufacturing the packaging structure according to claim 1, characterized in that, The thickness of the electromagnetic shielding layer ranges from 1µm to 2µm.

10. The method for manufacturing the packaging structure according to claim 1, characterized in that, The mask is made of metallic materials.

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