Shifting register unit, driving method thereof, display driving circuit and display device

Abstract

A shift register unit and a driving method thereof, a display driving circuit, and a display device, in the shift register unit, an input circuit (01) can transmit power supply signals of different potentials to a control node (PD) in different time periods in response to an input signal and a clock signal, and two output circuits (02, 03) can both respond to the potentials of the control node (PD) and transmit power supply signals of different potentials to the control node (PD) in different time periods. And power supply signals with different potentials are transmitted to the connected output ends in different time periods. Therefore, it can be determined that the shift register unit comprises both the P-type transistor and the N-type transistor. And the two output circuits (02, 03) can independently output signals to the output ends connected with the two output circuits (02, 03). On the basis, the potential of the power supply signal can be flexibly adjusted, so that a driving signal with a required potential can be reliably transmitted to pixels in different refresh frequency regions through a driving output end (Nout) connected with the pixels, and a local brushing function is supported. The shifting register unit is simple in structure and rich in function.

Description

Shift register unit and driving method thereof, display driving circuit and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to PCT International Application No. PCT / CN2024 / 120140, filed on September 20, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular to a shift register unit and driving method thereof, a display driving circuit and a display device. BACKGROUND

[0004] In a display device, a display driving circuit for driving a pixel to emit light is usually arranged on a substrate by using a gate drive on array (GOA) technology. Accordingly, the display driving circuit can also be referred to as a GOA circuit. The GOA circuit usually includes a plurality of shift register units (also referred to as GOA units) connected in cascade. A common GOA circuit is a gate driving circuit that transmits a gate driving signal to a pixel. However, the current GOA circuit structure is relatively complex and has a single function. SUMMARY

[0005] A shift register unit and driving method thereof, a display driving circuit and a display device are provided. The technical solutions are as follows:

[0006] In one aspect, a shift register unit is provided, which includes:

[0007] An input circuit is connected with an input terminal, a first clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal and a control node respectively, and is configured to control the on-off of the first power supply terminal and the control node, and control the on-off of the second power supply terminal and the control node in response to an input signal provided by the input terminal, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal, and the first power supply terminal and the second power supply terminal are turned on with the control node in different time periods respectively;

[0008] A first output circuit is connected with the control node, a third power supply terminal, a fourth power supply terminal and a shift output terminal respectively, and is configured to control the on-off of the third power supply terminal and the shift output terminal, and control the on-off of the fourth power supply terminal and the shift output terminal in response to the potential of the control node, and the third power supply terminal and the fourth power supply terminal are turned on with the control node in different time periods respectively;

[0009] a second output circuit, connected with the control node, the fifth power terminal, the sixth power terminal and the driving output terminal respectively, and configured to control on-off of the fifth power terminal and the driving output terminal and control on-off of the sixth power terminal and the driving output terminal in response to a potential of the control node, and the third power terminal and the fourth power terminal are turned on with the control node in different time periods respectively.

[0010] Optionally, the input circuit comprises:

[0011] a first input sub-circuit, connected with the input terminal, the first power terminal, the second power terminal and a first intermediate node respectively, and configured to control on-off of the first power terminal and the first intermediate node and control on-off of the second power terminal and the first intermediate node in response to the input signal; and the first power terminal and the second power terminal are turned on with the first intermediate node in different time periods respectively;

[0012] a second input sub-circuit, connected with the input terminal, the first clock terminal, the second clock terminal, the first intermediate node, the first power terminal, the second power terminal and the control node respectively, and configured to control on-off of the first intermediate node and the control node in response to the first clock signal, control on-off of the first power terminal and the control node in response to the first clock signal and the input signal, and control on-off of the second power terminal and the control node in response to the second clock signal and the input signal.

[0013] Optionally, the first input sub-circuit comprises: a first transistor and a second transistor; and the first transistor is a first type transistor and the second transistor is a second type transistor;

[0014] a gate of the first transistor is connected with the input terminal, a first pole of the first transistor is connected with the first power terminal, and a second pole of the first transistor is connected with the first intermediate node;

[0015] a gate of the second transistor is connected with the input terminal, a first pole of the second transistor is connected with the second power terminal, and a second pole of the second transistor is connected with the first intermediate node.

[0016] Optionally, the second input sub-circuit comprises:

[0017] a first input unit, connected with the first clock terminal, the first power terminal and a second intermediate node respectively, and configured to control on-off of the first power terminal and the second intermediate node in response to the first clock signal;

[0018] a second input unit connected with the input terminal, the second power terminal and the third intermediate node respectively, and configured to control the second power terminal and the third intermediate node in response to the input signal;

[0019] a third input unit connected with the first clock terminal, the second clock terminal, the input terminal, the first intermediate node, the second intermediate node, the third intermediate node and the control node respectively, and configured to control the first intermediate node and the control node in response to the first clock signal, control the second intermediate node and the control node in response to the input signal, and control the third intermediate node and the control node in response to the second clock signal.

[0020] Optionally, the first input unit comprises a third transistor, the second input unit comprises a fourth transistor, the third input unit comprises a fifth transistor, a sixth transistor and a seventh transistor, and the third transistor, the fifth transistor and the sixth transistor are first type transistors, and the fourth transistor and the seventh transistor are second type transistors.

[0021] a gate of the third transistor is connected with the first clock terminal, a first pole of the third transistor is connected with the first power terminal, and a second pole of the third transistor is connected with the second intermediate node;

[0022] a gate of the fourth transistor is connected with the input terminal, a first pole of the fourth transistor is connected with the second power terminal, and a second pole of the fourth transistor is connected with the third intermediate node;

[0023] a gate of the fifth transistor is connected with the first clock terminal, a first pole of the fifth transistor is connected with the first intermediate node, and a second pole of the fifth transistor is connected with the control node;

[0024] a gate of the sixth transistor is connected with the input terminal, a first pole of the sixth transistor is connected with the second intermediate node, and a second pole of the sixth transistor is connected with the control node;

[0025] a gate of the seventh transistor is connected with the second clock terminal, a first pole of the sixth transistor is connected with the third intermediate node, and a second pole of the sixth transistor is connected with the control node.

[0026] Optionally, the first clock terminal is multiplexed as the second clock terminal, and the first clock terminal and the second clock terminal input same clock signal.

[0027] Optionally, the first input unit comprises a third transistor; the second input unit comprises a fourth transistor; the third input unit comprises a fifth transistor, a sixth transistor and a seventh transistor; and the third transistor, the fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the fourth transistor is a second type transistor.

[0028] The gate of the third transistor is connected with the first clock end, the first pole of the third transistor is connected with the first power supply end, and the second pole of the third transistor is connected with the second intermediate node.

[0029] The gate of the fourth transistor is connected with the input end, the first pole of the fourth transistor is connected with the second power supply end, and the second pole of the fourth transistor is connected with the third intermediate node.

[0030] The gate of the fifth transistor is connected with the first clock end, the first pole of the fifth transistor is connected with the first intermediate node, and the second pole of the fifth transistor is connected with the control node.

[0031] The gate of the sixth transistor is connected with the input end, the first pole of the sixth transistor is connected with the second intermediate node, and the second pole of the sixth transistor is connected with the control node.

[0032] The gate of the seventh transistor is connected with the first clock end, the first pole of the seventh transistor is connected with the third intermediate node, and the second pole of the seventh transistor is connected with the control node.

[0033] Optionally, the first output circuit comprises an eighth transistor and a ninth transistor; and the eighth transistor is a first type transistor, and the ninth transistor is a second type transistor.

[0034] The gate of the eighth transistor is connected with the control node, the first pole of the eighth transistor is connected with the third power supply end, and the second pole of the eighth transistor is connected with the shift output end.

[0035] The gate of the ninth transistor is connected with the control node, the first pole of the ninth transistor is connected with the fourth power supply end, and the second pole of the ninth transistor is connected with the shift output end.

[0036] Optionally, the third power supply end is shared with the first power supply end, and / or the fourth power supply end is shared with the second power supply end.

[0037] Optionally, the second output circuit comprises a tenth transistor and an eleventh transistor; and the tenth transistor is a first type transistor, and the eleventh transistor is a second type transistor.

[0038] The gate of the tenth transistor is connected with the control node, the first pole of the tenth transistor is connected with the fifth power supply end, and the second pole of the tenth transistor is connected with the driving output end.

[0039] The gate of the eleventh transistor is connected with the control node, the first pole of the eleventh transistor is connected with the sixth power supply end, and the second pole of the eleventh transistor is connected with the driving output end.

[0040] Optionally, the second output circuit further comprises a twelfth transistor connected in series between the fifth power supply end and the tenth transistor, and a thirteenth transistor connected in series between the sixth power supply end and the eleventh transistor; and the twelfth transistor and the tenth transistor are transistors of the same type, and the thirteenth transistor and the eleventh transistor are transistors of the same type.

[0041] The gate of the twelfth transistor is connected with the control node, the first pole of the twelfth transistor is connected with the fifth power supply end, and the second pole of the twelfth transistor is connected with the first pole of the tenth transistor.

[0042] The gate of the thirteenth transistor is connected with the control node, the first pole of the thirteenth transistor is connected with the sixth power supply end, and the second pole of the thirteenth transistor is connected with the first pole of the eleventh transistor.

[0043] Optionally, the channel width-length ratio of the tenth transistor and the twelfth transistor connected in series is different.

[0044] And / or, the channel width-length ratio of the eleventh transistor and the thirteenth transistor connected in series is different.

[0045] Optionally, the channel width-length ratio of the tenth transistor is greater than the channel width-length ratio of the twelfth transistor.

[0046] The channel width-length ratio of the eleventh transistor is greater than the channel width-length ratio of the thirteenth transistor.

[0047] Optionally, the first power supply end to the fourth power supply end, and the sixth power supply end are direct current power supply ends, and the fifth power supply end is a direct current power supply end or an alternating current power supply end.

[0048] Optionally, the driving output end is configured to be connected with pixels in a display area of the display panel, for transmitting driving signals to the pixels to drive the pixels to emit light, and the display area comprises a first display area and a second display area, the refresh frequency of the first display area being greater than the refresh frequency of the second display area.

[0049] When driving the pixels in the first display area to emit light, the potential of the fifth power signal provided by the fifth power end is greater than the potential of the fifth power signal provided by the fifth power end when driving the pixels in the second display area to emit light.

[0050] Optionally, when driving the pixels in the second display area to emit light, the potential of the fifth power signal provided by the fifth power end is greater than the potential of the second power signal provided by the second power end.

[0051] Optionally, the shift register unit further comprises:

[0052] a driving enhancement circuit connected between the control node and the second output circuit, and configured to transmit the potential of the control node to the second output circuit after at least one enhancement processing.

[0053] Optionally, the driving enhancement circuit comprises one or a plurality of inverters connected in series.

[0054] Each of the inverters comprises a fourteenth transistor and a fifteenth transistor connected in series between the first power end and the second power end, and the fourteenth transistor is a first type transistor and the fifteenth transistor is a second type transistor.

[0055] Optionally, the second output circuit is connected with the shift output end to be connected with the control node through the first output circuit.

[0056] The second output circuit is configured to control the on-off of the fifth power end and the driving output end and the on-off of the sixth power end and the driving output end in response to the potential of the shift output end.

[0057] Optionally, the second output circuit comprises an eighteenth transistor and a nineteenth transistor.

[0058] The gate of the eighteenth transistor is connected with the shift output end, the first pole of the eighteenth transistor is connected with the fifth power end, and the second pole of the eighteenth transistor is connected with the driving output end; the gate of the nineteenth transistor is connected with the shift output end, the first pole of the nineteenth transistor is connected with the sixth power end, and the second pole of the nineteenth transistor is connected with the driving output end.

[0059] Optionally, the shift register unit further comprises:

[0060] an output enhancement circuit connected between the shift output terminal and the second output circuit, and configured to transmit the potential of the shift output terminal to the second output circuit after at least one enhancement processing.

[0061] Optionally, the output enhancement circuit comprises one or at least two inverters connected in series.

[0062] Each of the inverters comprises a twentieth transistor and a twenty-first transistor connected in series between the first power terminal and the second power terminal, and the twentieth transistor is a first type transistor and the twenty-first transistor is a second type transistor.

[0063] Optionally, the first power terminal to the fourth power terminal and the sixth power terminal are direct current power terminals, and the fifth power terminal is a direct current power terminal or an alternating current power terminal.

[0064] Optionally, the driving output terminal is configured to be connected with a pixel in a display area of a display panel, so as to transmit a driving signal to the pixel to drive the pixel to emit light, and the display area comprises a first display area and a second display area, and a refresh frequency of the first display area is greater than a refresh frequency of the second display area.

[0065] When driving the pixel in the first display area to emit light, a potential of a fifth power signal provided by the fifth power terminal is greater than a potential of a fifth power signal provided by the fifth power terminal when driving the pixel in the second display area to emit light.

[0066] Optionally, when driving the pixel in the second display area to emit light, a potential of a fifth power signal provided by the fifth power terminal is greater than a potential of a second power signal provided by the second power terminal.

[0067] Optionally, in the shift register unit, the first type transistor is a P-type transistor and the second type transistor is an N-type transistor.

[0068] Optionally, the shift register unit further comprises a storage capacitor connected between the first power terminal and the control node.

[0069] Optionally, the shift register unit further comprises a reset circuit connected with a reset signal terminal, the first power terminal and the control node respectively, and configured to control the on-off of the first power terminal and the control node in response to a reset signal provided by the reset signal terminal.

[0070] Optionally, the reset circuit comprises a sixteenth transistor and a seventeenth transistor; a gate of the sixteenth transistor is connected with the reset signal terminal, a first pole of the sixteenth transistor is connected with the first power supply terminal, and a second pole of the sixteenth transistor is connected with a first pole of the seventeenth transistor; a gate of the seventeenth transistor is connected with the reset signal terminal, and a second pole of the seventeenth transistor is connected with the control node.

[0071] In another aspect, a driving method of a shift register unit is provided for driving the shift register unit as described in the above aspect; the method comprises:

[0072] In the first stage, the input circuit controls the first power supply terminal to be disconnected with the control node and controls the second power supply terminal to be connected with the control node in response to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal and the second clock signal provided by the second clock terminal; the first output circuit controls the third power supply terminal to be connected with the shift output terminal and controls the fourth power supply terminal to be disconnected with the shift output in response to the potential of the control node; and the second output circuit controls the fifth power supply terminal to be connected with the driving output terminal and controls the sixth power supply terminal to be disconnected with the driving output in response to the potential of the control node.

[0073] In the second stage, the input circuit controls the first power supply terminal to be connected with the control node and controls the second power supply terminal to be disconnected with the control node in response to the input signal, the first clock signal and the second clock signal; the first output circuit controls the third power supply terminal to be disconnected with the shift output terminal and controls the fourth power supply terminal to be connected with the shift output in response to the potential of the control node; and the second output circuit controls the fifth power supply terminal to be disconnected with the driving output terminal and controls the sixth power supply terminal to be connected with the driving output in response to the potential of the control node.

[0074] Optionally, the first clock terminal is multiplexed as the second clock terminal; the first clock signal provided by the first clock terminal is the same as the second clock signal provided by the second clock terminal.

[0075] Optionally, the shift register unit further comprises a reset circuit connected with a reset signal terminal, the first power supply terminal and the control node respectively, and configured to control the connection and disconnection between the first power supply terminal and the control node in response to a reset signal provided by the reset signal terminal.

[0076] The method comprises a reset stage in which the reset circuit controls the first power supply terminal to be connected with the control node in response to a reset signal provided by the reset signal terminal.

[0077] In yet another aspect, a display driving circuit is provided, which includes a plurality of shift register units cascaded as described in the aspect above.

[0078] Optionally, in the case that the fifth power supply end connected to each of the shift register units is an alternating current power supply end, at least two of the shift register units are connected to different fifth power supply ends.

[0079] In yet another aspect, a display device is provided, which includes a display panel and the display driving circuit as described in the aspect above; the display panel includes a plurality of pixels.

[0080] The display driving circuit is connected to the plurality of pixels via a driving output end and is configured to transmit a driving signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0081] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0082] FIG. 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0083] FIG. 2 is a structural schematic diagram of another shift register unit provided by an embodiment of the present disclosure;

[0084] FIG. 3 is a structural schematic diagram of yet another shift register unit provided by an embodiment of the present disclosure;

[0085] FIG. 4 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present disclosure;

[0086] FIG. 5 is a circuit structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0087] FIG. 6 is a circuit structural schematic diagram of another shift register unit provided by an embodiment of the present disclosure;

[0088] FIG. 7 is a circuit structural schematic diagram of yet another shift register unit provided by an embodiment of the present disclosure;

[0089] FIG. 8 is a local brush division schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0090] FIG. 9 is a flow schematic diagram of a driving method of a shift register unit provided by an embodiment of the present disclosure;

[0091] FIG. 10 is a timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0092] FIG. 11 is a timing simulation diagram of a shift register unit according to an embodiment of the present disclosure;

[0093] FIG. 12 is a timing simulation diagram of another shift register unit according to an embodiment of the present disclosure;

[0094] FIG. 13 is a timing simulation diagram of yet another shift register unit according to an embodiment of the present disclosure;

[0095] FIG. 14 is a local brush driving timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0096] FIG. 15 is a structural diagram of a display driving circuit according to an embodiment of the present disclosure;

[0097] FIG. 16 is a structural diagram of another display driving circuit according to an embodiment of the present disclosure;

[0098] FIG. 17 is a structural diagram of yet another display driving circuit according to an embodiment of the present disclosure;

[0099] FIG. 18 is a structural diagram of a display device according to an embodiment of the present disclosure;

[0100] FIG. 19 is a first structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0101] FIG. 20 is a second structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0102] FIG. 21 is a third structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0103] FIG. 22 is a fourth structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0104] FIG. 23 is a circuit structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0105] FIG. 24 is another circuit structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0106] FIG. 25 is a fifth structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0107] FIG. 26 is another circuit structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0108] FIG. 27 is a sixth structural diagram of a shift register unit according to an embodiment of the present disclosure;

[0109] Figure 28 is another circuit structure of a shift register unit according to an embodiment of the present disclosure;

[0110] Figure 29 is a timing simulation of a shift register unit according to an embodiment of the present disclosure;

[0111] Figure 30 is a connection between a shift register unit and a clock signal line according to an embodiment of the present disclosure;

[0112] Figure 31 is a circuit structure of a shift register unit for local refresh according to an embodiment of the present disclosure;

[0113] Figure 32 is a local refresh driving timing of another shift register unit according to an embodiment of the present disclosure;

[0114] Figure 33 is a local refresh division of another shift register unit according to an embodiment of the present disclosure;

[0115] Figure 34 is a seventh structure of a shift register unit according to an embodiment of the present disclosure;

[0116] Figure 35 is an eighth structure of a shift register unit according to an embodiment of the present disclosure;

[0117] Figure 36 is a ninth structure of a shift register unit according to an embodiment of the present disclosure;

[0118] Figure 37 is a tenth structure of a shift register unit according to an embodiment of the present disclosure;

[0119] Figure 38 is a circuit structure of a shift register unit according to an embodiment of the present disclosure;

[0120] Figure 39 is another circuit structure of a shift register unit according to an embodiment of the present disclosure;

[0121] Figure 40 is an eleventh structure of a shift register unit according to an embodiment of the present disclosure;

[0122] Figure 41 is another circuit structure of a shift register unit according to an embodiment of the present disclosure;

[0123] Figure 42 is a twelfth structure of a shift register unit according to an embodiment of the present disclosure;

[0124] Figure 43 is another circuit structure of a shift register unit according to an embodiment of the present disclosure;

[0125] Figure 44 is a timing simulation of a shift register unit according to an embodiment of the present disclosure;

[0126] FIG. 45 is a schematic diagram of another circuit structure of a shift register unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0127] For the purpose, technical solutions and advantages of the present disclosure to be clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0128] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors (TFTs) or field effect transistors or other devices with the same characteristics. For example, the field effect transistor can be a metal-oxide-semiconductor (MOS) field effect transistor, also known as a MOS transistor. In addition, the transistors used in the embodiments of the present application are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable. In the embodiments of the present application, the source can be referred to as the first pole and the drain can be referred to as the second pole. According to the configuration in the drawings, the middle end of the transistor is the control pole, which can also be referred to as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type transistor and an N-type transistor, wherein the P-type transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential; the N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential. In addition, the plurality of signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent two states of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0129] The embodiments of the present application provide a shift register unit of a hybrid CMOS architecture, which can realize shift output through the combination of NMOS and PMOS, and is also compatible with the local brushing function, can support the demand of local brushing driving, is rich in functions, and has a simple circuit structure and simple driving principle, which is beneficial to the narrow frame design of the display device. Wherein, NMOS refers to an N-type MOS transistor, PMOS refers to a P-type MOS transistor, and CMOS architecture refers to an architecture including NMOS and PMOS.

[0130] FIG. 1 is a structural schematic diagram of a shift register unit according to an embodiment of the present application. As shown in FIG. 1, the shift register unit includes an input circuit 01, a first output circuit 02 and a second output circuit 03.

[0131] The input circuit 01 is connected with the input terminal In, the first clock terminal CK, the second clock terminal CKN, the first power supply terminal V1, the second power supply terminal V2 and the control node PD respectively. The input circuit 01 is configured to control the connection between the first power supply terminal V1 and the control node PD and the connection between the second power supply terminal V2 and the control node PD in response to the input signal provided by the input terminal In, the first clock signal provided by the first clock terminal CK and the second clock signal provided by the second clock terminal CKN. In addition, the first power supply terminal V1 and the second power supply terminal V2 are connected with the control node PD in different time periods respectively.

[0132] Optionally, the first clock signal provided by the first clock terminal CK and the second clock signal provided by the second clock terminal CKN can be inverse clock signals. That is, the potential of the first clock signal and the potential of the second clock signal are opposite in the same time period.

[0133] Based on the above, for example, the input circuit 01 can control the first power supply terminal V1 to be connected with the control node PD and the second power supply terminal V2 to be disconnected from the control node PD when the potential of the input signal provided by the input terminal In is the first potential based on that the potential of the first clock signal provided by the first clock terminal CK is the first potential and the potential of the second clock signal provided by the second clock terminal CKN is the second potential opposite to the first potential, so that the first power signal provided by the first power supply terminal V1 can be transmitted to the control node PD. In addition, the input circuit 01 can control the first power supply terminal V1 to be disconnected from the control node PD and the second power supply terminal V2 to be connected with the control node PD when the potential of the input signal provided by the input terminal In is the second potential based on that the potential of the first clock signal provided by the first clock terminal CK is the second potential and the potential of the second clock signal provided by the second clock terminal CKN is the first potential opposite to the second potential, so that the second power signal provided by the second power supply terminal V2 can be transmitted to the control node PD. The input circuit 01 can control the first power supply terminal V1 and the second power supply terminal V2 to be disconnected from the control node PD when the potential of the input signal provided by the input terminal In is the first potential or the second potential based on that the potential of the first clock signal provided by the first clock terminal CK is the second potential and the potential of the second clock signal provided by the second clock terminal CKN is the first potential opposite to the second potential. That is, the first power supply terminal V1 and the second power supply terminal V2 can be connected with the control node PD in different time periods respectively.

[0134] Optionally, in the embodiment of the present application, the first potential can be a low potential relative to the second potential. That is, the first potential can be a low potential, and the second potential can be a high potential. And, as described above, for an N-type transistor, the high potential can be an effective potential, and the low potential can be an ineffective potential. For a P-type transistor, the low potential can be an effective potential, and the high potential can be an ineffective potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential. On this basis, in combination with the working principle of the input circuit 01 described above, it can be known that the input circuit 01 includes both N-type transistors and P-type transistors.

[0135] Optionally, the first power supply end V1 can provide a first power supply signal with a high potential, and the second power supply end V2 can provide a second power supply signal with a low potential. Correspondingly, in the embodiment of the present application, the first power supply end V1 can also be referred to as an upper pull power supply end VGH, and the second power supply end V2 can also be referred to as a lower pull power supply end VGL. In this way, on the basis that the input circuit 01 controls the first power supply end V1 and the second power supply end V2 to be conductive with the control node PD in different time periods respectively, the potential of the control node PD can be controlled to be a high potential and a low potential in different time periods. Of course, in some other embodiments, the first power supply end V1 can also provide a first power supply signal with a low potential, and the second power supply end V2 can also provide a second power supply signal with a high potential.

[0136] The first output circuit 02 is connected with the control node PD, a third power supply end V3, a fourth power supply end V4 and a shift output end Next respectively. The first output circuit 02 is configured to control the third power supply end V3 and the shift output end Next in response to the potential of the control node PD, and control the fourth power supply end V4 and the shift output end Next. And, the third power supply end V3 and the fourth power supply end V4 are conductive with the control node PD in different time periods respectively.

[0137] For example, when the potential of the control node PD is the first potential, the first output circuit 02 can control the third power supply end V3 to be conductive with the shift output end Next, and control the fourth power supply end V4 to be disconnected with the shift output end Next, so that the third power supply signal provided by the third power supply end V3 can be transmitted to the shift output end Next. When the potential of the control node PD is the second potential, the first output circuit 02 can control the third power supply end V3 to be disconnected with the shift output end Next, and control the fourth power supply end V4 to be conductive with the shift output end Next, so that the fourth power supply signal provided by the fourth power supply end V4 can be transmitted to the shift output end Next. That is, the third power supply end V3 and the fourth power supply end V4 can be conductive with the shift output end Next in different time periods respectively. On this basis, it can also be determined that the first output circuit 02 can include both N-type transistors and P-type transistors.

[0138] Optionally, the third power supply end V3 provides a third power supply signal with a high potential, and the fourth power supply end V4 provides a fourth power supply signal with a low potential. Correspondingly, in the embodiment of the present application, the third power supply end V3 can also be referred to as an upper pull power supply end VGH, and the fourth power supply end V4 can also be referred to as a lower pull power supply end VGL. In this way, based on the control of the first output circuit 02 on the conduction of the third power supply end V3 and the fourth power supply end V4 to the shift output end Next in different time periods, the shift output end Next can output a high potential and a low potential shift signal in different time periods.

[0139] Optionally, the shift output end Next can be connected to the input end In of another shift register unit in cascade to transmit an input signal to the input end In of the other shift register unit, that is, the shift signal output through the shift output end Next can be used as an input signal. For the first shift register unit, as shown in FIG. 1, the input end In can be connected to a separate start signal end ESTV to receive a start signal provided by the start signal end ESTV and output a shift signal through the shift output end Next in response to the start signal, so as to realize cascade driving.

[0140] The second output circuit 03 is connected to the control node PD, the fifth power supply end V5, the sixth power supply end V6 and the drive output end Nout. The second output circuit 03 is configured to control the conduction of the fifth power supply end V5 to the drive output end Nout and the conduction of the sixth power supply end V6 to the drive output end Nout in response to the potential of the control node PD. In addition, the third power supply end V3 and the fourth power supply end V4 are respectively conducted to the control node PD in different time periods.

[0141] For example, when the potential of the control node PD is a first potential, the second output circuit 03 can control the fifth power supply end V5 to be conducted to the drive output end Nout and control the sixth power supply end V6 to be disconnected from the drive output end Nout, so that the fifth power supply signal provided by the fifth power supply end V5 can be transmitted to the drive output end Nout. When the potential of the control node PD is a second potential, the second output circuit 03 can control the fifth power supply end V5 to be disconnected from the drive output end Nout and control the sixth power supply end V6 to be conducted to the drive output end Nout, so that the sixth power supply signal provided by the sixth power supply end V6 can be transmitted to the drive output end Nout. That is, the fifth power supply end V5 and the sixth power supply end V6 can be respectively conducted to the drive output end Nout in different time periods. On this basis, it can also be determined that the second output circuit 03 can include both N-type transistors and P-type transistors.

[0142] Optionally, the fifth power supply end V5 can provide a fifth power supply signal with a high potential, and the sixth power supply end V6 can provide a sixth power supply signal with a low potential. Correspondingly, in the embodiments of the present application, the fifth power supply end V5 can also be referred to as an upper pull power supply end VGH, and the sixth power supply end V6 can also be referred to as a lower pull power supply end VGL. In this way, on the basis that the second output circuit 03 controls the fifth power supply end V5 and the sixth power supply end V6 to be conductive with the driving output end Nout in different time periods respectively, the driving output end Nout can output a driving signal with a high potential and a low potential in different time periods respectively.

[0143] Optionally, the driving output end Nout can be used to connect with a pixel in the display panel, to transmit a required driving signal to the pixel, to drive the pixel to emit light. In addition, the driving output end Nout can be used to connect with a pixel circuit in the pixel, to control the pixel circuit to drive a light emitting element in the pixel to emit light based on the received driving signal.

[0144] For example, the display panel can include a plurality of rows and a plurality of columns of pixels, and the driving output end Nout of each stage of the shift register unit can be connected with a data write transistor included in a pixel circuit in a row of pixels through a gate line Gate, to transmit a gate driving signal to the data write transistor, so that the data write transistor controls a data line Data to transmit a data signal to a driving transistor in the pixel circuit in response to the gate driving signal, to make the driving transistor drive a light emitting element to emit light based on the data signal. The plurality of stages of the shift register unit can transmit the gate driving signal to the plurality of rows of pixels row by row, to scan the pixels to emit light row by row, to realize scan driving. Correspondingly, the gate driving signal is also referred to as a scan signal. In addition, for the scenario in which the potential of the fifth power supply signal provided by the fifth power supply end V5 is a high potential, the data write transistor can be an N-type transistor, and the gate driving signal can be an N-type gate driving signal GateN required by the N-type data write transistor. That is, the shift register unit can realize shift output of GateN. Of course, the type of the driving signal here is only illustrative. For example, in some other embodiments, the driving signal output through the driving output end Nout can also be an emission control signal EM transmitted to an emission control transistor in the pixel circuit.

[0145] Optionally, in some embodiments, the potential of the fifth power signal can include a high potential and a low potential, that is, the fifth power terminal V5 can be an alternating current power terminal with adjustable potential. On this basis, the potential of the fifth power signal can be flexibly adjusted according to the different refresh frequency requirements of different regions in the display panel. For example, for a low-frequency refresh region (also referred to as a low-refresh region), the potential of the fifth power signal can be controlled to be a low potential, so that the second output circuit 03 outputs a driving signal with a low potential to the pixels in the low-refresh region through the driving output terminal Nout. For a high-frequency refresh region (also referred to as a high-refresh region), the potential of the fifth power signal can be controlled to be a high potential, so that the second output circuit 03 outputs a driving signal with a high potential to the pixels in the high-refresh region through the driving output terminal Nout. Thus, the requirements of different refresh frequencies can be flexibly met, and the full-screen local refresh function (also referred to as the local refresh function) is realized, that is, under the control of the shift register unit, different regions in the display panel can display different refresh frequencies, and the driving requirements of full-screen local high and low frequency refresh can be met. Wherein, the high and low of the low-refresh region and the high-refresh region are relative. For example, the refresh frequency of the low-refresh region can be 1 hertz (hz), and the refresh frequency of the high-refresh region can be 120 hz.

[0146] Based on the above example, it can be seen that the shift register unit provided by the embodiments of the present application includes both P-type transistors and N-type transistors, and on the basis of the P-type transistors being PMOS and the N-type transistors being NMOS, the shift register unit can be a hybrid CMOS architecture. In addition, in the shift register unit provided by the embodiments of the present application, the input signal required by the other stage shift register unit is output through the shift output terminal Next and the driving signal required by the pixel circuit is output through the driving output terminal Nout in response to the potential of the same control node PD by different output circuits, that is, the cascade driving and the scan driving can be controlled independently, and the two will not affect each other, so it can be known that the output flexibility and reliability of the shift register unit are better, and the cascade driving can be reliably realized, and the pixel can also be reliably driven to emit light. On this basis, the local refresh function can also be supported by flexibly adjusting the potential of the power signal provided by the power terminal connected to the second output circuit 03, and the function of the shift register unit is relatively rich.

[0147] In summary, the embodiment of the present application provides a shift register unit. In the shift register unit, the input circuit can transmit power signals with different potentials to the control node in different time periods in response to the input signal and the clock signal, and the two output circuits can transmit power signals with different potentials to the connected output terminals in different time periods in response to the potential of the control node. Therefore, it can be determined that the shift register unit includes both P-type transistors and N-type transistors, and the two output circuits can independently output signals to the connected output terminals. On this basis, the potential of the power signal can be flexibly adjusted, so that the driving output terminal of the connected pixel can reliably transmit the required driving signal to the pixel in different refresh frequency regions to support the local brushing function. The shift register unit has a simple structure and rich functions.

[0148] Optionally, FIG. 2 is a structural schematic diagram of another shift register unit provided by the embodiment of the present application. As shown in FIG. 2, the input circuit 01 can include a first input sub-circuit 011 and a second input sub-circuit 012.

[0149] The first input sub-circuit 011 can be connected with the input terminal In, the first power terminal V1, the second power terminal V2, and the first intermediate node N1 respectively. The first input sub-circuit 011 can be used to control the conduction between the first power terminal V1 and the first intermediate node N1, and control the conduction between the second power terminal V2 and the first intermediate node N1 in response to the input signal. Moreover, the first power terminal V1 and the second power terminal V2 can be conducted with the first intermediate node N1 in different time periods respectively.

[0150] For example, when the potential of the input signal is the first potential, the first input sub-circuit 011 can control the first power terminal V1 to be conducted with the first intermediate node N1, and control the second power terminal V2 to be disconnected with the first intermediate node N1, so that the first power signal provided by the first power terminal V1 can be transmitted to the first intermediate node N1. When the potential of the input signal is the second potential, the first input sub-circuit 011 can control the first power terminal V1 to be disconnected with the first intermediate node N1, and control the second power terminal V2 to be conducted with the first intermediate node N1, so that the second power signal provided by the second power terminal V2 can be transmitted to the first intermediate node N1. That is, the first power terminal V1 and the second power terminal V2 can be conducted with the first intermediate node N1 in different time periods respectively. On this basis, it can also be determined that the first input sub-circuit 011 can include both N-type transistors and P-type transistors.

[0151] The second input sub-circuit 012 can be connected with the input terminal In, the first clock terminal CK, the second clock terminal CKN, the first intermediate node N1, the first power supply terminal V1, the second power supply terminal V2 and the control node PD respectively. The second input sub-circuit 012 can be configured to control the first intermediate node N1 and the control node PD to be connected or disconnected in response to the first clock signal, control the first power supply terminal V1 and the control node PD to be connected or disconnected in response to the first clock signal and the input signal, and control the second power supply terminal V2 and the control node PD to be connected or disconnected in response to the second clock signal and the input signal.

[0152] For example, the second input sub-circuit 012 can control the first intermediate node N1 and the control node PD to be connected when the first clock signal is at the first potential, so that the first power supply signal or the second power supply signal transmitted to the first intermediate node N1 can be further transmitted to the control node PD; and can control the first intermediate node N1 and the control node PD to be disconnected when the first clock signal is at the second potential. The second input sub-circuit 012 can control the first power supply terminal V1 and the control node PD to be connected when the first clock signal is at the first potential and the input signal is at the first potential, so that the first power supply signal provided by the first power supply terminal V1 can be transmitted to the control node PD; and can control the first power supply terminal V1 and the control node PD to be disconnected when the first clock signal and / or the input signal is at the second potential. The second input sub-circuit 012 can control the second power supply terminal V2 and the control node PD to be connected when the second clock signal is at the second potential and the input signal is at the second potential, so that the second power supply signal provided by the second power supply terminal V2 can be transmitted to the control node PD; and can control the second power supply terminal V2 and the control node PD to be disconnected when the second clock signal and / or the input signal is at the first potential.

[0153] In this way, the first power supply terminal V1 and the second power supply terminal V2 can be connected with the control node PD in different time periods respectively under the cooperation of the first input sub-circuit 011 and the second input sub-circuit 012, so that the first power supply signal with the high potential and the second power supply signal with the low potential can be output to the control node PD in different time periods to control the potential of the control node PD to be high or low.

[0154] Optionally, FIG. 3 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application. As shown in FIG. 3, the second input sub-circuit 012 can include a first input unit 0121, a second input unit 0122 and a third input unit 0123.

[0155] The first input unit 0121 can be connected with the first clock terminal CK, the first power terminal V1 and the second intermediate node N2 respectively. The first input unit 0121 can be configured to control the first power terminal V1 and the second intermediate node N2 in response to the first clock signal.

[0156] For example, the first input unit 0121 can control the first power terminal V1 and the second intermediate node N2 to be connected when the first clock signal is at the first potential, so that the first power signal provided by the first power terminal V1 can be transmitted to the second intermediate node N2; and can control the first power terminal V1 and the second intermediate node N2 to be disconnected when the first clock signal is at the second potential.

[0157] The second input unit 0122 can be connected with the input terminal In, the second power terminal V2 and the third intermediate node N3 respectively. The second input unit 0122 can be configured to control the second power terminal V2 and the third intermediate node N3 in response to the input signal.

[0158] For example, the second input unit 0122 can control the second power terminal V2 and the third intermediate node N3 to be connected when the input signal is at the second potential, so that the second power signal provided by the second power terminal V2 can be transmitted to the third intermediate node N3; and can control the second power terminal V2 and the third intermediate node N3 to be disconnected when the input signal is at the first potential.

[0159] The third input unit 0123 can be connected with the first clock terminal CK, the second clock terminal CKN, the input terminal In, the first intermediate node N1, the second intermediate node N2, the third intermediate node N3 and the control node PD respectively. The third input unit 0123 can be configured to control the first intermediate node N1 and the control node PD in response to the first clock signal, control the second intermediate node N2 and the control node PD in response to the input signal, and control the third intermediate node N3 and the control node PD in response to the second clock signal.

[0160] For example, the third input unit 0123 can control the first intermediate node N1 to be connected to the control node PD when the first clock signal has the first potential, so that the first power signal or the second power signal transmitted to the first intermediate node N1 can be further transmitted to the control node PD; and can control the first intermediate node N1 to be disconnected from the control node PD when the first clock signal has the second potential. The third input unit 0123 can control the second intermediate node N2 to be connected to the control node PD when the input signal has the first potential, so that the first power signal transmitted to the second intermediate node N2 can be further transmitted to the control node PD; and can control the second intermediate node N2 to be disconnected from the control node PD when the input signal has the second potential. The third input unit 0123 can control the third intermediate node N3 to be connected to the control node PD when the second clock signal has the second potential, so that the second power signal transmitted to the third intermediate node N3 can be further transmitted to the control node PD; and can control the third intermediate node N3 to be disconnected from the control node PD when the second clock signal has the first potential.

[0161] Thus, under the cooperation of the first input unit 0121, the second input unit 0122 and the third input unit 0123, the first power terminal V1 and the second power terminal V2 can be connected to the control node PD in different time periods respectively, so that the first power signal with high potential and the second power signal with low potential can be output to the control node PD in different time periods respectively, to control the potential of the control node PD to be high or low.

[0162] Optionally, FIG. 4 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application. As shown in FIG. 4, the shift register unit can further include a driving enhancement circuit 04.

[0163] The driving enhancement circuit 04 can be connected between the control node PD and the second output circuit 03. The driving enhancement circuit 04 can be configured to transmit the potential of the control node PD to the second output circuit 03 after at least one enhancement processing. The enhancement processing can be, for example, an inversion processing. Of course, to make the potential of the control node PD after the enhancement processing the same as the potential of the control node PD before the enhancement, the driving enhancement circuit 04 can transmit the potential of the control node PD to the second output circuit 03 after an even number of inversion processing.

[0164] It can be understood that, on the basis of also setting the driving enhancement circuit 04, the driving capability of the shift register unit can be enhanced, so that the second output circuit 03 can reliably output the required driving signal to the pixel circuit through the driving output end Nout in response to the potential of the enhanced control node PD, to reliably drive the pixel circuit to drive the light emitting element to emit light. Of course, in some other embodiments, the driving enhancement circuit 04 can also be connected between the control node PD and the first output circuit 02 for the same enhancement effect, to improve the cascaded driving capability of the shift register unit.

[0165] Optionally, on the basis of FIG. 3, FIG. 5 shows a schematic circuit structure diagram of a shift register unit. FIG. 6 shows another schematic circuit structure diagram of a shift register unit. On the basis of FIG. 4, FIG. 7 shows another schematic circuit structure diagram of a shift register unit.

[0166] Optionally, as can be seen with reference to FIGS. 5 to 7 and FIGS. 35 to 43, the first input sub-circuit 011 can include a first transistor T1 and a second transistor T2. The first transistor T1 can be a first type transistor, and the second transistor T2 can be a second type transistor.

[0167] The gate of the first transistor T1 can be connected with the input end In, the first pole of the first transistor T1 can be connected with the first power supply end V1, and the second pole of the first transistor T1 can be connected with the first intermediate node N1.

[0168] The gate of the second transistor T2 can be connected with the input end In, the first pole of the second transistor T2 can be connected with the second power supply end V2, and the second pole of the second transistor T2 can be connected with the first intermediate node N1.

[0169] Optionally, in combination with the foregoing description, in the first type transistor and the second type transistor, one type can be N type, and the other type can be P type. That is, one transistor can be an N type transistor (such as NMOS), and the other transistor can be a P type transistor (such as PMOS).

[0170] For example, on the basis that the first potential is a low potential and the second potential is a high potential, the first type transistor can be a P type transistor, and the second type transistor can be an N type transistor. In some other embodiments, on the basis that the first potential is a high potential and the second potential is a low potential, the first type transistor can be an N type transistor, and the second type transistor can be a P type transistor.

[0171] Optionally, with continuous reference to FIGS. 5-7 and 35-43, the first input unit 0121 can include a third transistor T3. The second input unit 0122 can include a fourth transistor T4. The third input unit 0123 can include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Moreover, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can be first-type transistors (e.g., P-type transistors), and the fourth transistor T4 and the seventh transistor T7 can be second-type transistors (e.g., N-type transistors).

[0172] The gate of the third transistor T3 can be connected with the first clock end CK, the first pole of the third transistor T3 can be connected with the first power end V1, and the second pole of the third transistor T3 can be connected with the second intermediate node N2.

[0173] The gate of the fourth transistor T4 can be connected with the input end In, the first pole of the fourth transistor T4 can be connected with the second power end V2, and the second pole of the fourth transistor T4 can be connected with the third intermediate node N3.

[0174] The gate of the fifth transistor T5 can be connected with the first clock end CK, the first pole of the fifth transistor T5 can be connected with the first intermediate node N1, and the second pole of the fifth transistor T5 can be connected with the control node PD.

[0175] The gate of the sixth transistor T6 can be connected with the input end In, the first pole of the sixth transistor T6 can be connected with the second intermediate node N2, and the second pole of the sixth transistor T6 can be connected with the control node PD.

[0176] The gate of the seventh transistor T7 can be connected with the second clock end CKN, the first pole of the seventh transistor T7 can be connected with the third intermediate node N3, and the second pole of the seventh transistor T7 can be connected with the control node PD.

[0177] As shown in FIGS. 5-7 and 35-43, the input circuit 01 is a shift register part in the shift register unit, which is composed of mixed P-type transistors and N-type transistors, cooperates with clock signals, and realizes shift latching of the high-level scanning signal of the input end In, and stores the latched signal in the control node PD. The storage capacitor C1 is used to ensure the stability of the latched signal. The shift register part provided by the present disclosure is simpler than the conventional latch structure.

[0178] Optionally, as shown in FIGS. 19-28, the first clock end CK is multiplexed as the second clock end CKN, and the first clock end CK and the second clock end CKN input the same clock signal.

[0179] In more detail, the above setting manner is equivalent to setting the third input unit 0123 in the second input sub-circuit 012 can be connected with the first clock end CK, the input end In, the first intermediate node N1, the second intermediate node N2, the third intermediate node N3 and the control node PD respectively. The third input unit 0123 can be used to control the on-off of the first intermediate node N1 and the control node PD in response to the first clock signal, control the on-off of the second intermediate node N2 and the control node PD in response to the input signal, and control the on-off of the third intermediate node N3 and the control node PD in response to the first clock signal.

[0180] For example, the third input unit 0123 can control the first intermediate node N1 and the control node PD to be connected when the potential of the first clock signal is the first potential, so that the first power signal or the second power signal transmitted to the first intermediate node N1 can be further transmitted to the control node PD; and can control the first intermediate node N1 and the control node PD to be disconnected when the potential of the first clock signal is the second potential. The third input unit 0123 can control the second intermediate node N2 and the control node PD to be connected when the potential of the input signal is the first potential, so that the first power signal transmitted to the second intermediate node N2 can be further transmitted to the control node PD; and can control the second intermediate node N2 and the control node PD to be disconnected when the potential of the input signal is the second potential. The third input unit 0123 can control the third intermediate node N3 and the control node PD to be connected when the potential of the first clock signal is the first potential, so that the second power signal transmitted to the third intermediate node N3 can be further transmitted to the control node PD; and can control the third intermediate node N3 and the control node PD to be disconnected when the potential of the first clock signal is the second potential.

[0181] In this way, under the cooperation of the first input unit 0121, the second input unit 0122 and the third input unit 0123, the first power end V1 and the second power end V2 can be connected with the control node PD in different time periods respectively, so as to output the first power signal with high potential and the second power signal with low potential to the control node PD in different time periods, so as to control the potential of the control node PD to be high or low.

[0182] The above setting manner is advantageous to reduce the number of clock signals required by the shift register unit to be connected, and is advantageous to reduce the number of clock signal lines required to be set in the display product when the shift register unit is applied to the display product, and is advantageous to simplify the structure of the display product and narrow the frame width of the display product.

[0183] As shown in FIGS. 29 and 30, in the case that the first clock terminal CK is multiplexed as the second clock terminal CKN, two clock signal lines, i.e., the first clock signal line CK1 and the second clock signal line CK2, can be provided in the display product when the shift register unit is applied to the display product. Meanwhile, the first clock terminal CK of the odd-numbered shift register units (e.g., GOA1 and GOA3) in the cascaded shift register units can be coupled to the first clock signal line CK1, and the first clock terminal CK of the even-numbered shift register units (e.g., GOA2 and GOA4) in the cascaded shift register units can be coupled to the second clock signal line CK2.

[0184] It is worth noting that the duty cycles of the first clock signal provided by the first clock signal line CK1 and the second clock signal provided by the second clock signal line CK2 are not limited.

[0185] Optionally, as shown in FIGS. 21 to 28, the first input unit 0121 can include a third transistor T3. The second input unit 0122 can include a fourth transistor T4. The third input unit 0123 can include a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. In addition, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be first-type transistors (e.g., P-type transistors), and the fourth transistor T4 can be a second-type transistor (e.g., an N-type transistor).

[0186] The gate of the third transistor T3 can be connected to the first clock terminal CK, the first electrode of the third transistor T3 can be connected to the first power terminal V1, and the second electrode of the third transistor T3 can be connected to the second intermediate node N2.

[0187] The gate of the fourth transistor T4 can be connected to the input terminal In, the first electrode of the fourth transistor T4 can be connected to the second power terminal V2, and the second electrode of the fourth transistor T4 can be connected to the third intermediate node N3.

[0188] The gate of the fifth transistor T5 can be connected to the first clock terminal CK, the first electrode of the fifth transistor T5 can be connected to the first intermediate node N1, and the second electrode of the fifth transistor T5 can be connected to the control node PD.

[0189] The gate of the sixth transistor T6 can be connected to the input terminal In, the first electrode of the sixth transistor T6 can be connected to the second intermediate node N2, and the second electrode of the sixth transistor T6 can be connected to the control node PD.

[0190] The gate of the seventh transistor T7 can be connected with the first clock end CK, the first pole of the seventh transistor T7 can be connected with the third intermediate node N3, and the second pole of the seventh transistor T7 can be connected with the control node PD.

[0191] It is worth noting that the gate of the seventh transistor T7 can be connected with the first clock end CK, for controlling the turn-on or turn-off of the seventh transistor T7 in response to the first clock signal provided by the first clock end CK.

[0192] As shown in FIGS. 21-28, the input circuit 01 is a shift register part in the shift register unit, which is composed of mixed P-type transistors and N-type transistors, cooperates with the clock signal, realizes shift latching of the high-level scanning signal of the input end In, and stores in the control node PD. The storage capacitor C1 is used to ensure the stability of the latched signal. The shift register part provided by the present disclosure is simpler than the conventional latch structure.

[0193] It is worth noting that the circuit structure shown in FIGS. 21-28 needs to meet the condition: V_CK < V_VGL1 + Vth@T5&T7, V_VGL1 refers to the low potential of the power signal provided by VGL1, V_CK refers to the potential of the clock signal, and Vth@T5&T7 refers to the minimum value of the threshold voltage of the fifth transistor T5 and the threshold voltage of the seventh transistor T7; so as to ensure that VGL1 can control the node PD through the sufficient writing of the fifth transistor T5 and the seventh transistor T7, and the charging loss of Vth will not be generated.

[0194] Optionally, as can be seen from FIGS. 5-7, the first output circuit 02 can include an eighth transistor T8 and a ninth transistor T9. And the eighth transistor T8 can be a first type transistor (such as a P-type transistor), and the ninth transistor T9 can be a second type transistor (such as an N-type transistor).

[0195] The gate of the eighth transistor T8 can be connected with the control node PD, the first pole of the eighth transistor T8 can be connected with the third power end V3, and the second pole of the eighth transistor T8 can be connected with the shift output end Next.

[0196] The gate of the ninth transistor T9 can be connected with the control node PD, the first pole of the ninth transistor T9 can be connected with the fourth power end V4, and the second pole of the ninth transistor T9 can be connected with the shift output end Next.

[0197] Optionally, with reference to FIG. 5 and FIG. 7, in an embodiment, the second output circuit 03 can include: a tenth transistor T10 and an eleventh transistor T11. And, the tenth transistor T10 can be a first type transistor (e.g., a P-type transistor), and the eleventh transistor T11 can be a second type transistor (e.g., an N-type transistor).

[0198] The gate of the tenth transistor T10 can be connected with the control node PD, the first pole of the tenth transistor T10 can be connected with the fifth power terminal V5, and the second pole of the tenth transistor T10 can be connected with the driving output terminal Nout.

[0199] The gate of the eleventh transistor T11 can be connected with the control node PD, the first pole of the eleventh transistor T11 can be connected with the sixth power terminal V6, and the second pole of the eleventh transistor T11 can be connected with the driving output terminal Nout.

[0200] Optionally, with reference to FIG. 6, in another embodiment, the second output circuit 03 can further include: a twelfth transistor T12 connected in series between the fifth power terminal V5 and the tenth transistor T10, and a thirteenth transistor T13 connected in series between the sixth power terminal V6 and the eleventh transistor T11. And, the twelfth transistor T12 and the tenth transistor T10 can be the same type of transistor (e.g., the first type transistor / P-type transistor), and the thirteenth transistor T13 and the eleventh transistor T11 can be the same type of transistor (e.g., the second type transistor / N-type transistor).

[0201] The gate of the twelfth transistor T12 can be connected with the control node PD, the first pole of the twelfth transistor T12 can be connected with the fifth power terminal V5, and the second pole of the twelfth transistor T12 can be connected with the first pole of the tenth transistor T10.

[0202] The gate of the thirteenth transistor T13 can be connected with the control node PD, the first pole of the thirteenth transistor T13 can be connected with the sixth power terminal V6, and the second pole of the thirteenth transistor T13 can be connected with the first pole of the eleventh transistor T11.

[0203] That is, in an embodiment, as shown in FIG. 5 and FIG. 7, the second output circuit 03 can include one P-type transistor T10 and one N-type transistor T11 of different types. In another embodiment, as shown in FIG. 6, the second output circuit 03 can include two P-type transistors T10&T12 and two N-type transistors T11&T13 of different types, and the two P-type transistors T10&T12 are connected in series, and the two N-type transistors T11&T13 are connected in series. The structure shown in FIG. 6 can also be referred to as a double TFT series architecture.

[0204] It can be understood that in the structure shown in Figure 6, because the double-TFT series architecture is adopted, the leakage problem of the transistor in the second output circuit 03 during the opening process can be effectively reduced, and the effective output of the high / low potential driving signal is ensured. The leakage problem is mainly caused by the rising edge of the driving signal output through the driving output terminal Nout from low to high potential and the falling edge of the driving signal output through the driving output terminal Nout from high to low potential, which causes the collision with the driving signal output through the driving output terminal Nout.

[0205] Alternatively, for the double-TFT series architecture shown in Figure 6, the channel width-length ratio W / L of the tenth transistor T10 and the twelfth transistor T12 in series can be different. And / or, the channel width-length ratio W / L of the eleventh transistor T11 and the thirteenth transistor T13 in series can be different.

[0206] That is, in the layout design, the channel width-length ratio W / L of the two P-type transistors T10&T12 in series can be designed differently. And / or, the channel width-length ratio W / L of the two N-type transistors T11&T13 in series can also be designed differently. In this way, the layout space of the layout can be fully saved, thereby better facilitating the narrow frame design of the display device.

[0207] For example, the channel width-length ratio W / L of the tenth transistor T10 can be greater than the channel width-length ratio W / L of the twelfth transistor T12. That is, among the two P-type transistors T10&T12 in series, the channel width-length ratio W / L of the transistor (i.e., the twelfth transistor T12) directly connected to the fifth power supply terminal V5 can be designed to be relatively small, and the channel width-length ratio W / L of the transistor (i.e., the tenth transistor T10) directly connected to the driving output terminal Nout can be designed to be relatively large. In this way, the output driving capability of the tenth transistor T10 can be ensured, that is, the reliable output of the fifth power supply signal to the driving output terminal Nout through the tenth transistor T10 can be ensured.

[0208] Similarly, the channel width-length ratio W / L of the eleventh transistor T11 can be greater than the channel width-length ratio W / L of the thirteenth transistor T13. That is, among the two N-type transistors T11&T13 in series, the channel width-length ratio W / L of the transistor (i.e., the thirteenth transistor T13) directly connected to the sixth power supply terminal V6 can be designed to be relatively small, and the channel width-length ratio W / L of the transistor (i.e., the eleventh transistor T11) directly connected to the driving output terminal Nout can be designed to be relatively large. In this way, the output driving capability of the eleventh transistor T11 can be ensured, that is, the reliable output of the sixth power supply signal to the driving output terminal Nout through the eleventh transistor T11 can be ensured.

[0209] It can be understood that the above-mentioned double-TFT series connection architecture is designed for the second output circuit 03 outputting a driving signal to a pixel, and the first output circuit 02 for cascade driving can also be designed in the same way.

[0210] Optionally, with reference to FIG. 7, it can be seen that the driving enhancement circuit 04 can include one or a plurality of inverters F in series. That is, as described above, the at least one enhancement process can be at least one inversion process. Each inverter F can include a fourteenth transistor T14 and a fifteenth transistor T15 connected in series between the first power supply end V1 and the second power supply end V2. Moreover, the fourteenth transistor T14 can be a first type transistor (for example, a P-type transistor), and the fifteenth transistor T15 can be a second type transistor (for example, an N-type transistor).

[0211] For example, in the case where the driving enhancement circuit 04 performs an even number of (for example, two) inversion processes, as shown in FIG. 7, the driving enhancement circuit 04 can include two inverters F in series. One inverter F can also be referred to as a set of buffer transistors. Accordingly, the structure shown in FIG. 7 can also be understood as two sets of buffer transistors being added between the control node PD and the second output circuit 03.

[0212] For distinction, in FIG. 7, the inverter F directly connected to the control node PD is identified as F-1, and the fourteenth transistor T14 and the fifteenth transistor T15 included in the inverter F-1 are identified as T14-1 and T15-1, respectively. Moreover, the inverter F directly connected to the second output circuit 03 is identified as F-2, and the fourteenth transistor T14 and the fifteenth transistor T15 included in the inverter F-2 are identified as T14-2 and T15-2, respectively.

[0213] The gate of the fourteenth transistor T14-1 and the gate of the fifteenth transistor T15-1 can be connected with the control node PD, the first electrode of the fourteenth transistor T14-1 can be connected with the first power supply end V1, the first electrode of the fifteenth transistor T15-1 can be connected with the second power supply end V2, the second electrode of the fourteenth transistor T14-1 and the second electrode of the fifteenth transistor T15-1 can be connected with the gate of the fourteenth transistor T14-2 and the gate of the fifteenth transistor T15-2, the first electrode of the fourteenth transistor T14-2 can be connected with the first power supply end V1, the first electrode of the fifteenth transistor T15-2 can be connected with the second power supply end V2, and the second electrode of the fourteenth transistor T14-2 and the second electrode of the fifteenth transistor T15-2 can be connected with the second output circuit 03. For the structure shown in FIG. 5 and FIG. 7, the second electrode of the fourteenth transistor T14-2 and the second electrode of the fifteenth transistor T15-2 can be connected with the gate of the tenth transistor T10 and the gate of the eleventh transistor T11 included in the second output circuit 03. For the structure shown in FIG. 6, the second electrode of the fourteenth transistor T14-2 and the second electrode of the fifteenth transistor T15-2 can be connected with the gate of the tenth transistor T10, the gate of the eleventh transistor T11, the gate of the twelfth transistor T12 and the gate of the thirteenth transistor T13 included in the second output circuit 03.

[0214] Optionally, as shown in FIG. 19 to FIG. 44, the second output circuit 03 is connected with the shift output end Next to be connected with the control node PD through the first output circuit 02; the second output circuit 03 is configured to control the on-off of the fifth power supply end V5 and the driving output end Nout and control the on-off of the sixth power supply end V6 and the driving output end Nout in response to the potential of the shift output end Next.

[0215] For example, the second output circuit 03 can make the fifth power supply end V5 and the sixth power supply end V6 conductive with the driving output end Nout in different time periods under the control of the potential of the shift output end Next. It can also be determined that the second output circuit 03 can include both N-type transistors and P-type transistors.

[0216] For example, the second output circuit 03 includes an eighteenth transistor T18 and a nineteenth transistor T19; the gate of the eighteenth transistor T18 is connected with the shift output terminal Next, the first pole of the eighteenth transistor T18 is connected with the fifth power supply terminal V5, and the second pole of the eighteenth transistor T18 is connected with the drive output terminal Nout; the gate of the nineteenth transistor T19 is connected with the shift output terminal Next, the first pole of the nineteenth transistor T19 is connected with the sixth power supply terminal V6, and the second pole of the nineteenth transistor T19 is connected with the drive output terminal Nout.

[0217] For example, as shown in FIG. 22, FIG. 24, FIG. 27, FIG. 28, FIG. 31, FIG. 37, FIG. 39, FIG. 42 and FIG. 43, the shift register unit further includes an output enhancement circuit 05 connected between the shift output terminal Next and the second output circuit 03, and configured to transmit the potential of the shift output terminal Next to the second output circuit 03 after at least one enhancement processing. It is worth noting that the output enhancement circuit 05 and the second output circuit 03 have a PD2 node therebetween.

[0218] For example, the output enhancement circuit 05 includes one or at least two inverters connected in series; each of the inverters includes a twentieth transistor T20 and a twenty-first transistor T21 connected in series between the first power supply terminal V1 and the second power supply terminal V2; and the twentieth transistor T20 is a first type transistor, and the twenty-first transistor T21 is a second type transistor.

[0219] For example, the first output circuit 02, the second output circuit 03 and the output enhancement circuit 05 jointly constitute an output part, and the output part adopts a mixed CMOS circuit architecture, which can effectively reduce the problem of large leakage current during the opening of the transistor and ensure the effective output of high and low levels.

[0220] Optionally, as shown in FIG. 5 to FIG. 7, FIG. 19 to FIG. 28, FIG. 31, FIG. 34 to FIG. 43, it can also be seen that the shift register unit can further include a storage capacitor C1 connected between the first power supply terminal V1 and the control node PD. The storage capacitor C1 can be used to maintain the potential of the control node PD, so as to ensure that the potential stability of the control node PD is good.

[0221] Optionally, as shown in FIG. 1 to FIG. 7, FIG. 19 to FIG. 28, FIG. 31, FIG. 34 to FIG. 43, it can also be seen that in the embodiment of the present application, the third power supply terminal V3 and the first power supply terminal V1 can be shared, and / or the fourth power supply terminal V4 and the second power supply terminal V2 can be shared. In this way, the number of signal terminals required to be set can be simplified, the wiring is facilitated, and the cost is saved.

[0222] For example, the first power terminal V1 and the third power terminal V3 can be the same pull-up power terminal VGH1, and the fourth power terminal V4 and the second power terminal V2 can be the same pull-down power terminal VGL1.

[0223] Of course, in some other embodiments, the fifth power terminal V5 and the first power terminal V1 can also share the third power terminal V3, i.e., be the same pull-up power terminal VGH1; and / or, the sixth power terminal V6 and the second power terminal V2 can also share the fourth power terminal V4, i.e., be the same pull-down power terminal VGL1. In the embodiments of the present application, the fifth power terminal V5 and the first power terminal V1 can be different power terminals (i.e., not shared), i.e., be different pull-up power terminals VGH2 and VGH1, respectively; and the sixth power terminal V6 and the second power terminal V2 can be different power terminals, i.e., be different pull-down power terminals VGL2 and VGL1, respectively. In this way, the second output circuit 03 can independently transmit the required driving signal to the pixel through the driving output terminal Nout, thereby improving the ability to drive the pixel to emit light, reducing the leakage current, and ensuring reliable driving of the pixel to emit light. In addition, the load of the fifth power terminal V5 and the sixth power terminal V6 can be smaller, and the output of the first output circuit 02 through the shift output terminal Next and the output of the second output circuit 03 through the driving output terminal Nout can not interfere with each other.

[0224] That is, in the embodiments of the present application, double VGH (i.e., VGH1 & VGH2) and double VGL (i.e., VGL1 & VGL2) can be used to power the shift register unit. Or, in some other embodiments, single VGH (i.e., VGH1) and single VGL (i.e., VGL1) can also be used to power the shift register unit.

[0225] Optionally, in the embodiments of the present application, the first power terminal V1 to the fourth power terminal V4 and the sixth power terminal V6 can all be direct current power terminals, and the fifth power terminal V5 can be a direct current power terminal or an alternating current power terminal AC.

[0226] That is, in one embodiment, the first power terminal V1 to the sixth power terminal V6 (e.g., VGH1 & VGH2, and VGL1 & VGL2) can all be direct current power terminals, continuously providing a high-potential power signal or a low-potential power signal.

[0227] In another embodiment, among the first power terminal V1 to the sixth power terminal V6, the fifth power terminal V5 (e.g., VGH2) can be an alternating current power terminal AC, used to provide a high-potential power signal or a low-potential power signal with adjustable potential, and the other power terminals (e.g., VGH1, and VGL1 & VGL2) except the fifth power terminal V5 can all be direct current power terminals, used to continuously provide a high-potential power signal or a low-potential power signal.

[0228] Optionally, as previously described, based on the fifth power terminal V5 being an AC power terminal, the potential of the fifth power signal provided by the fifth power terminal V5 can be flexibly adjusted according to the refresh frequency requirements of different regions in the display panel, so as to adapt to different refresh frequencies required by different regions.

[0229] Optionally, as previously described, the driving output terminal Nout can be used to connect with pixels in the display area of the display panel, for transmitting driving signals to the pixels to drive the pixels to emit light. As can be seen from FIG. 8 and FIG. 33, the display area A can include a first display area A1 and a second display area A2. It can be understood that the display area A can be divided into at least one first display area A1 and at least one second display area A2. For example, FIG. 8 and FIG. 33 schematically show one first display area A1 and two second display areas A2-1 and A2-2.

[0230] The refresh frequency of the first display area A1 can be greater than the refresh frequency of the second display area A2. That is, the first display area A1 can be a high refresh area, and the second display area A2 (e.g., A2-1 and A2-2) can be a low refresh area. For example, the refresh frequency of the first display area A1 can be 120 hz, and the refresh frequency of the second display area A2 can be 1 hz.

[0231] In addition, when driving the pixels in the first display area A1 to emit light, the potential of the fifth power signal provided by the fifth power terminal V5 (i.e., VGH2) can be greater than the potential of the fifth power signal provided by the fifth power terminal V5 when driving the pixels in the second display area A2 to emit light. That is, as shown in FIG. 8 and FIG. 14, when driving the pixels in the high refresh area to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set to a high potential, so that the driving output terminal Nout reliably outputs a driving signal with a high potential to the pixels in the high refresh area; and when driving the pixels in the low refresh area to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set to a low potential (e.g., VGL1, VGL2), so that the driving output terminal Nout reliably outputs a driving signal with a low potential to the pixels in the low refresh area. In this way, the requirements of high frequency refresh and low frequency refresh can be met at the same time.

[0232] Optionally, in some embodiments, the low potential of the power signal provided by VGH2 can also be equal to the low potential of the sixth power signal provided by the sixth power terminal V6 (i.e., VGL2). That is, when driving the pixels in the low refresh area to emit light, the second output circuit 03 can always output a driving signal with a low potential to the pixels in the low refresh area through the driving output terminal Nout.

[0233] It can be understood that, in combination with FIG. 6, taking the fifth power terminal V5 as VGH2 as an example, in the scenario that the potential of the power signal provided by VGH2 is a low potential, that is, the second output circuit 03 controls the fifth power terminal V5 to transmit a low potential fifth power signal to the driving output terminal Nout, it can be considered that the tenth transistor T10 of the P type and the twelfth transistor T12 of the P type are used as pull-down transistors at this time; in the scenario that the potential of the power signal provided by VGH2 is a high potential, that is, the second output circuit 03 controls the fifth power terminal V5 to transmit a high potential fifth power signal to the driving output terminal Nout, it can be considered that the tenth transistor T10 of the P type and the twelfth transistor T12 of the P type are used as pull-up transistors at this time.

[0234] On the basis of this embodiment, when driving the pixels in the second display area A2 to emit light, the potential of the fifth power signal provided by the fifth power terminal V5 can be greater than the potential of the second power signal provided by the second power terminal V2. That is, when driving the pixels in the low brush area to emit light, the low potential of the second power signal provided by the second power terminal V2 can be less than the low potential of the fifth power signal provided by the fifth power terminal V5. For example, on the basis that the fifth power terminal V5 is VGH2 and the second power terminal is VGL1, it can be considered that the low potential of the power signal provided by VGL1 is less than the low potential of the power signal provided by VGH2. Of course, on the basis that the low potential of the power signal provided by VGH2 is equal to the low potential of the power signal provided by VGL2, it can also be considered that the low potential of the power signal provided by VGL1 is less than the low potential of the power signal provided by VGL2.

[0235] It can be understood that, by setting the low potential of the second power signal provided by the second power terminal V2 to be less than the low potential of the fifth power signal provided by the fifth power terminal V5, the input circuit 01 can transmit a power signal with a low potential to the control node PD as low as possible to sufficiently pull down the potential of the control node PD, thereby overcoming the problem that when the potential of the fifth power signal provided by the fifth power terminal V5 is a low potential, that is, the tenth transistor T10 of the P type and the twelfth transistor T12 of the P type are used as pull-down transistors, the tenth transistor T10 and the twelfth transistor T12 do not open sufficiently in response to the low potential of the control node PD.

[0236] For example, when the tenth transistor T10 of the P type and the twelfth transistor T12 of the P type are used as pull-down transistors, taking the first power terminal V1 as VGH1, the second power terminal V2 as VGL1, the fifth power terminal V2 as VGH2, the sixth power terminal V6 as VGL2, and the low potential of the power signal provided by VGH2 being equal to the low potential of the power signal provided by VGL2 as an example, it can be known that the gate-source voltage difference Vgs of the pull-down transistor can satisfy:

[0237] Vgs=V_PD-V_VGL2<Vth@T10 / T12; wherein, V_PD refers to the potential of the control node PD, V_VGL2 refers to the low potential of the power supply signal provided by VGL2, that is, the low potential of the power supply signal provided by VGH2, and Vth@T10 / T12 refers to the minimum value of the threshold voltage Vth of the tenth transistor T10 and the threshold voltage Vth of the twelfth transistor T12.

[0238] Since the low potential of V_PD is the low potential of the power supply signal provided by VGL1, based on the above formula of Vgs, it can be obtained that: V_VGL1<V_VGL2+Vth@T10 / T12; wherein, V_VGL1 refers to the low potential of the power supply signal provided by VGL1.

[0239] That is, in the embodiments of the present application, for the embodiment that the low potential V_VGL1 of the power supply signal provided by VGL1 is less than the low potential V_VGL2 of the power supply signal provided by VGL2, it can be satisfied that: V_VGL1<V_VGL2+Vth@T10 / T12. For example, in some embodiments, V_VGL1 and V_VGL2 can differ by about 3 volts (V).

[0240] Optionally, in some embodiments, the low potential of the first clock signal provided by the first clock terminal CK and / or the low potential of the second clock signal provided by the second clock terminal CKN can also be set to be less than V_VGL2+Vth@T10 / T12 as V_VGL1, so as to ensure that the transistors connected to the first clock terminal CK and the transistors connected to the second clock terminal CKN in the input circuit 01 can be fully turned on, thereby ensuring that the working reliability of the shift register unit is good.

[0241] It can be understood that, in the case of setting the fifth power terminal V5 as an alternating power terminal, also setting the fifth power terminal V5 and the third power terminal V3 not to be shared, can make that when the potential of the fifth power signal provided by the fifth power terminal V5 is switched between the high potential and the low potential, the shift signal output by the first output circuit 02 through the shift output terminal Next will not be affected, that is, the cascade driving will not be affected.

[0242] As shown in FIGS. 31-33, in some embodiments, the fifth power terminal V5 is set as an alternating power terminal, when driving the pixels in the high brush area to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set as a high potential (such as VGH2), so that the high potential driving signal can be reliably output to the pixels in the high brush area through the driving output terminal Nout; and when driving the pixels in the low brush area to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set as a low potential (such as VGL1); at the same time, the potential of the power signal provided by the second power terminal V2 is set as a low potential (such as VGL2).

[0243] In the shift register unit provided by the above embodiment, the fifth power terminal V5 does not affect the step-by-step transmission of the Next signal of the shift output terminal when being switched from VGH2 to VGL1.

[0244] It should be noted that the local brush function needs to be implemented in combination with the low level of the control node PD node, and it is necessary to ensure that VGL1 can be written into the driving output terminal Nout from the eighteenth transistor T18 after the fifth power terminal V5 is switched from VGH2 to VGL1, and the condition V_VGL2 < V_VGL1 + Vth@T18 needs to be met, where V_VGL1 refers to the low potential of the power signal provided by VGL1, V_VGL2 refers to the low potential of the power signal provided by VGL2, and Vth@T18 refers to the threshold voltage of the eighteenth transistor T18. In this way, it can be ensured that VGL1 can be fully written into the driving output terminal Nout after the fifth power terminal V5 is switched from VGH2 to VGL1.

[0245] In the shift register unit provided by the above embodiment, the fifth power terminal V5 is set as an alternating current power terminal AC, so that the local refresh function can be realized according to actual needs, and different refresh frequencies can be realized in different regions.

[0246] As shown in FIGS. 8, 14 and 45, in some embodiments, the fifth power terminal V5 is set as an alternating current power terminal, and when the pixels in the high brush area are driven to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set as a high potential (such as VGH2), so that the high potential driving signal can be reliably output to the pixels in the high brush area through the driving output terminal Nout. When the pixels in the low brush area are driven to emit light, the potential of the power signal provided by the fifth power terminal V5 can be set as a low potential (such as VGL2), and at the same time, the potential of the power signal provided by the second power terminal V2 can be set as a low potential (such as VGL1).

[0247] In the shift register unit provided by the above embodiment, the fifth power terminal V5 does not affect the step-by-step transmission of the Next signal of the shift output terminal when being switched from VGH2 to VGL2.

[0248] It should be noted that the local brush function needs to be implemented in combination with the low level of the control node PD node, and it is necessary to ensure that VGL2 can be written into the driving output terminal Nout from the eighteenth transistor T18 after the fifth power terminal V5 is switched from VGH2 to VGL2, and the condition V_VGL1 < V_VGL2 + Vth@T18 needs to be met, where V_VGL1 refers to the low potential of the power signal provided by VGL1, V_VGL2 refers to the low potential of the power signal provided by VGL2, and Vth@T18 refers to the threshold voltage of the eighteenth transistor T18. In this way, it can be ensured that VGL2 can be fully written into the driving output terminal Nout after the fifth power terminal V5 is switched from VGH2 to VGL2.

[0249] The shift register unit provided by the above embodiment can realize local refresh function according to actual needs by setting the fifth power supply end V5 as an alternating current power supply end AC, and can realize different refresh frequencies in different areas.

[0250] As known from the foregoing, the shift register units shown in FIGS. 5 and 6 each include three parts: an input circuit 01 (also referred to as a shift register part), a first output circuit 02 (also referred to as a transmission unit), and a second output circuit 03 (also referred to as an output unit). The shift register unit shown in FIG. 7 includes the above three parts and further includes a driving enhancement circuit 04 (also referred to as an enhancement unit). As can be further known from FIGS. 5 to 7:

[0251] The shift register part can include four P-type transistors and three N-type transistors, belonging to a mixed P-type+N-type TFT architecture. In combination with clock signals provided by the first clock end CK and the second clock end CKN, the shift register part can shift and latch an input signal provided by the input end In, and store the input signal in a control node PD, with the storage capacitor C1 ensuring the stability of the latch. The shift register part belongs to a key architecture, and as can be seen, it has a simple structure and requires fewer devices to be set.

[0252] The transmission unit can include one P-type transistor and one N-type transistor, similar to a group of diodes. The transmission function of the group of diodes can be used to further transmit the signal shifted and latched to the control node PD to the input end In of other stages of the cascaded shift register unit, to realize cascaded output.

[0253] In one embodiment, as shown in FIGS. 5 and 7, the output unit can include one P-type transistor and one N-type transistor. In another embodiment, as shown in FIG. 6, the output unit can include two P-type transistors in series and two N-type transistors in series. This structure can reduce leakage and ensure reliable output of the required driving signal to the pixel.

[0254] The enhancement unit can include one or a plurality of inverters F in series. Each inverter F can include one P-type transistor and one N-type transistor, equivalent to one buffer tube.

[0255] That is, the shift register unit shown in FIG. 5 includes 6 P-type transistors, 5 N-type transistors and 1 capacitor, and belongs to a 11T1C architecture shift register unit. The shift register unit shown in FIG. 6 includes 7 P-type transistors, 6 N-type transistors and 1 capacitor, and belongs to a 13T1C architecture shift register unit. The shift register unit shown in FIG. 7 includes 8 P-type transistors, 7 N-type transistors and 1 capacitor, and belongs to a 15T1C architecture shift register unit. Of course, the design is not limited to the above structures. In addition, the structures shown in FIGS. 5 to 7 are driven by independent two groups of clock signals (clock signals provided by CK and CKN respectively) and independent two groups of power supply signals (two groups of power supply signals provided by VGH1 / VGL1 and VGH2 / VGL2 respectively), and the shift output terminal Next and the drive output terminal Nout are independent of each other, the input signal required by the input terminal In of the other stage shift register unit in the cascade is transmitted through the shift output terminal Next, and the drive signal required by the pixel circuit is transmitted through the drive output terminal Nout. The structure of the shift register unit provided by the embodiment of the present application is simple and has relatively rich functions.

[0256] In summary, the embodiment of the present application provides a shift register unit. In the shift register unit, the input circuit can transmit different potential power supply signals to the control node in different time periods in response to the input signal and the clock signal, and the two output circuits can transmit different potential power supply signals to the connected output terminals in different time periods in response to the potential of the control node. Therefore, it can be determined that the shift register unit includes P-type transistors and N-type transistors. In addition, the two output circuits can independently output signals to the connected output terminals. On this basis, the potential of the power supply signal can be flexibly adjusted, so that the drive signal with the required potential can be reliably transmitted to the pixels in different refresh frequency regions through the connected pixel drive output terminal to support the local brushing function. The structure of the shift register unit is simple and has rich functions.

[0257] In some embodiments, as shown in FIGS. 25 to 28 and FIGS. 40 to 43, the shift register unit further includes a reset circuit 07 connected with a reset signal terminal CX, the first power supply terminal V1 and the control node PD respectively, and configured to control the on-off of the first power supply terminal V1 and the control node PD in response to the reset signal provided by the reset signal terminal CX.

[0258] Exemplarily, the reset circuit 07 comprises a sixteenth transistor T16 and a seventeenth transistor T17; the gate of the sixteenth transistor T16 is connected with the reset signal end CX, the first pole of the sixteenth transistor T16 is connected with the first power supply end V1, and the second pole of the sixteenth transistor T16 is connected with the first pole of the seventeenth transistor T17; the gate of the seventeenth transistor T17 is connected with the reset signal end CX, and the second pole of the seventeenth transistor T17 is connected with the control node PD.

[0259] Exemplarily, in the reset stage, the reset circuit 07 controls the first power supply end V1 and the control node PD to be turned on in response to the reset signal provided by the reset signal end CX.

[0260] In the power-on process of the shift register unit, the reset signal end CX and the first power supply end V1 are powered on first, so that the reset circuit 07 controls the electrical connection between the first power supply end V1 and the control node PD to be turned on, which can ensure that the control node PD has a high potential in the power-on process of the shift register unit, so as to make the twentieth transistor T20, the eighteenth transistor T18 and the eighth transistor T8 controlled by the control node PD be turned off, avoid the connection of VGH1 and VGL1 and the connection of VGH2 and VGL2 at the moment of starting, and thus ensure that VGH1, VGL1, VGH2 and VGL2 maintain the estimated output potential before being powered on, prevent the shift register unit from working abnormally, and avoid the occurrence of large current during power-on. After the power-on of the shift register unit is completed, the reset signal end CX controls the electrical connection between the first power supply end V1 and the control node PD to be turned off.

[0261] In some embodiments, as shown in FIG. 28 and FIG. 29, the shift register unit comprises 10 P-type transistors, 5 N-type transistors and 1 capacitor. Taking the connection of the first clock end CK with the first clock signal line CK1 as an example, the working process of the shift register with this circuit structure is described in detail as follows:

[0262] In the reset stage: the reset signal end CX is written with a low potential, so as to ensure that the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, the discharge reset of the control node PD is completed, and the control node PD is ensured to be in a high potential state before other signals are powered on, so as to prevent the occurrence of output noise in the power-on of the shift register unit.

[0263] In stage T01, the input signal provided by the input terminal In (i.e., the start signal terminal NSTV) can be at a high potential, the first clock signal provided by the first clock terminal CK can be at a high potential, the P-type first transistor T1 and the P-type sixth transistor T6 can be controlled to be turned off, and the N-type second transistor T2 and the N-type fourth transistor T4 can be controlled to be turned on. At this time, the first intermediate node N1 and the third intermediate node N3 can be written with a low potential power signal, and the potential of the second intermediate node N2 and the potential of the control node PD can be maintained at the high potential before stage T01.

[0264] In stage T02, the first clock signal provided by the first clock terminal CK can be at a low potential, the seventh transistor T7 is controlled to be turned on, and the control node PD continues to be written with a low potential. In this stage, the eighth transistor T8 is turned on to complete the signal output of the shift output terminal Next, and the twenty-first transistor T21 and the eighteenth transistor T18 are turned on to transmit a high potential driving signal to the pixel circuit through the driving output terminal Nout.

[0265] In stage T03, the input signal provided by the input terminal In can be at a low potential, the second transistor T2 and the fourth transistor T4 are controlled to be turned off, and the first transistor T1 and the sixth transistor T6 are controlled to be turned on to pull up the N1 node potential. At this time, the first clock signal controls the third transistor T3 and the fifth transistor T5 to be turned off, the potential of the control node PD can be maintained at the low potential before stage T03, the potential of the second intermediate node N2 and the potential of the third intermediate node N3 can also be maintained at a low potential, for example, for a time length of 1 horizontal scanning period (i.e., 1H), the shift output terminal NEXT and the driving output terminal Nout continue to output a 1H high potential VGH2.

[0266] In stage T04, the first transistor T1 and the sixth transistor T6 are controlled to be turned on, the first clock signal provided by the first clock terminal CK can be at a low potential first, the first clock signal controls the third transistor T3 and the fifth transistor T5 to be turned on, and the high level starts to write the control node PD. In this stage, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, the shift output terminal Next outputs VGL1, and the twentieth transistor T20 and the nineteenth transistor T19 are turned on to complete the output of a scanning signal.

[0267] As shown in FIG. 29, at this stage T04, the potential of the first intermediate node N1, the potential of the second intermediate node N2, and the potential of the third intermediate node N3 can all be high potentials, and the potential of the control node PD can be a high potential. On this basis, the potential of the shift signal output through the shift output terminal Next and the potential of the driving signal output through the driving output terminal Nout can all be low potentials. After that, the stage T04 can be repeatedly executed. The falling edges of the shift signal and the driving signal output by the shift register unit provided in the embodiments of the present application are all stepless, and the output reliability is better.

[0268] The shift register provided in the above embodiments can meet the driving requirements of the existing GateN GOA, and can also be used as an EM GOA. The falling edge of the output driving signal is stepless, and the driving capability is stronger than that of the conventional GOA. The shift register provided in the above embodiments adopts a hybrid CMOS circuit architecture, realizes the shift output of GateN, is also compatible with the local brushing function, can support the driving requirements of the local brushing circuit, has a simpler circuit architecture, uses fewer transistors to realize the corresponding functions, and has more advantages in realizing a narrow frame compared with the prior art.

[0269] In some embodiments, as shown in FIGS. 43 and 44, the shift register unit includes 9 P-type transistors, 6 N-type transistors, and 1 capacitor. The working process of the shift register with this circuit structure is described in detail as follows:

[0270] At the reset stage: the reset signal end CX writes a low potential, ensures that the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, and completes the discharge reset of the control node PD. Before the other signals are powered on, the control node PD is ensured to be in a high potential state, so as to prevent abnormal output noise of the shift register unit after power-on.

[0271] At the stage T01: the potential of the input signal provided by the input end In (i.e., the on signal end NSTV) can be a high potential, and the potential of the first clock signal provided by the first clock end CK can be a high potential. The first transistor T1 and the sixth transistor T6 can be controlled to be both turned off, the third transistor T3 and the fifth transistor T5 can be controlled to be turned off, the second transistor T2 and the fourth transistor T4 can be controlled to be both turned on, at this time, the first intermediate node N1 and the third intermediate node N3 can be written with a low potential power signal, and the potential of the control node PD can be maintained as the high potential before the stage T01.

[0272] In stage T02, the potential of the second clock signal provided by the second clock terminal CKN can be high, to control the seventh transistor T7 to be turned on, the potential of the first clock signal provided by the first clock terminal CK can be low, to control the fifth transistor T5 to be turned on, and to control the node PD to continuously write a low potential, in this stage, the eighth transistor T8 is turned on to complete the signal output of the shift output terminal Next, and the twenty-first transistor T21 and the eighteenth transistor T18 are turned on to transmit the high potential driving signal from the driving output terminal Nout to the pixel circuit.

[0273] In stage T03, the potential of the input signal provided by the input terminal In can be low, to control the second transistor T2 and the fourth transistor T4 to be both turned off, and to control the first transistor T1 and the sixth transistor T6 to be both turned on, to pull up the potential of the N1 node, at this time, the first clock signal controls the third transistor T3 and the fifth transistor T5 to be turned off, the potential of the node PD can be maintained as the low potential before stage T03, the potential of the second intermediate node N2 and the potential of the third intermediate node N3 can also be maintained as low, for example, the time length of 1 horizontal scanning period (i.e., 1H), the shift output terminal Next and the driving output terminal Nout continuously output a 1H high potential VGH2.

[0274] In stage T04, the first transistor T1 and the sixth transistor T6 are controlled to be turned on, the potential of the first clock signal provided by the first clock terminal CK can be low first, the first clock signal controls the third transistor T3 and the fifth transistor T5 to be turned on, and the high level starts to write the control node PD, the control node PD completes a shift rising from low level to high level, in this stage, the eighth transistor T8 is turned off, the ninth transistor T9 is turned on, to control the shift output terminal Next to output VGL1, and the twentieth transistor T20 and the nineteenth transistor T19 are turned on to complete the output of the scanning signal.

[0275] As shown in FIG. 44, in this stage T04, the potential of the first intermediate node N1, the potential of the second intermediate node N2 and the potential of the third intermediate node N3 can all be high, and the potential of the control node PD can be high. On this basis, the potential of the shift signal output through the shift output terminal Next and the potential of the driving signal output through the driving output terminal Nout can all be low. Then, this stage T04 can be repeatedly executed. The falling edges of the shift signal and the driving signal output by the shift register unit provided in the embodiments of the present application are all stepless, and the output reliability is good.

[0276] The shift register provided by the above embodiments can meet the driving requirements of the existing GateN GOA, can also be used as an EM GOA, the falling edge of the output driving signal is stepless, and the driving capability is stronger than that of a conventional GOA; the shift register provided by the above embodiments adopts a mixed CMOS circuit architecture, realizes the shift output of GateN, is also compatible with the local brushing function, can support the driving requirements of the local brushing circuit, the circuit architecture is simpler, fewer transistors are used to realize the corresponding functions, and the existing technology is more advantageous for realizing a narrow frame.

[0277] The embodiments of the present application also provide a driving method of a shift register unit, which is used for driving the shift register unit shown in any one of FIGS. 1 to 7. As shown in FIG. 9, the method comprises the following steps:

[0278] In step 901, in the first stage, the input circuit controls the first power supply end to be disconnected with the control node and controls the second power supply end to be connected with the control node in response to the input signal provided by the input end, the first clock signal provided by the first clock end and the second clock signal provided by the second clock end; the first output circuit controls the third power supply end to be connected with the shift output end and controls the fourth power supply end to be disconnected with the shift output in response to the potential of the control node; and the second output circuit controls the fifth power supply end to be connected with the driving output end and controls the sixth power supply end to be disconnected with the driving output in response to the potential of the control node.

[0279] In step 902, in the second stage, the input circuit controls the first power supply end to be connected with the control node and controls the second power supply end to be disconnected with the control node in response to the input signal, the first clock signal and the second clock signal; the first output circuit controls the third power supply end to be disconnected with the shift output end and controls the fourth power supply end to be connected with the shift output in response to the potential of the control node; and the second output circuit controls the fifth power supply end to be disconnected with the driving output and controls the sixth power supply end to be connected with the driving output in response to the potential of the control node.

[0280] Optionally, taking the structure shown in FIG. 6 and the first potential as a low potential and the second potential as a high potential as an example, FIG. 10 shows a working timing diagram of a shift register unit, and FIG. 11 correspondingly shows a simulation diagram of the working timing diagram shown in FIG. 10. In combination with FIGS. 10 and 11, the driving principle of the shift register unit is described as follows:

[0281] (1) In stage T01, the input signal provided by the input terminal In (i.e., the enable signal terminal ESTV) can be at a high potential, the first clock signal provided by the first clock terminal CK can be at a high potential, and the second clock signal provided by the second clock terminal CKN can be at a low potential. Accordingly, the first transistor T1 of the P type and the sixth transistor T6 of the P type can be controlled to be turned off, the second transistor T2 of the N type and the fourth transistor T4 of the N type can be controlled to be turned on, and the third transistor T3 of the P type, the fifth transistor T5 of the P type, and the seventh transistor T7 of the N type can be controlled to be turned off. In this way, the second power supply terminal V2 (i.e., the pull-down power supply terminal VGL1) is connected to the first intermediate node N1 and the third intermediate node N3, the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH1) is disconnected from the first intermediate node N1 and the second intermediate node N2, and the first intermediate node N1, the second intermediate node N2, and the third intermediate node N3 are disconnected from the control node PD. Further, the low potential power signal provided by the pull-down power supply terminal VGL1 is transmitted to the first intermediate node N1 through the turned-on second transistor T2 and to the third intermediate node N3 through the turned-on fourth transistor T4. That is, in stage T01, the low potential power signal can be written to the first intermediate node N1 and the third intermediate node N3, and the potential of the second intermediate node N2 and the potential of the control node PD can be maintained at the high potential before stage T01.

[0282] On the basis that the potential of the control node PD is at a high potential, the eighth transistor T8 of the P type, the tenth transistor T10 of the P type, and the twelfth transistor T12 of the P type can be controlled to be turned off, and the ninth transistor T9 of the N type, the eleventh transistor T11 of the N type, and the thirteenth transistor T13 of the N type can be controlled to be turned on. In this way, the fourth power supply terminal V4 (i.e., the pull-down power supply terminal VGL1) is connected to the shift output terminal Next, the third power supply terminal V3 (i.e., the pull-up power supply terminal VGH1) is disconnected from the shift output terminal Next, the sixth power supply terminal V6 (i.e., the pull-down power supply terminal VGL2) is connected to the drive output terminal Nout, and the fifth power supply terminal V5 (i.e., the pull-up power supply terminal VGH2) is disconnected from the drive output terminal Nout. Further, the low potential power signal provided by the pull-down power supply terminal VGL1 is transmitted to the shift output terminal Next through the turned-on ninth transistor T9, and the low potential power signal provided by the pull-down power supply terminal VGL2 is transmitted to the drive output terminal Nout through the turned-on thirteenth transistor T13 and the turned-on eleventh transistor T11 in sequence. That is, in stage T01, the low potential input signal can be transmitted to the input terminal In of the other stage shift register unit in the cascade through the shift output terminal Next, and the low potential drive signal can be transmitted to the pixel circuit through the drive output terminal Nout.

[0283] That is, in combination with FIG. 10 and FIG. 11, in this stage T01, the potential of the first intermediate node N1 and the potential of the third intermediate node N3 can both be low potentials, and the potential of the second intermediate node N2 and the potential of the control node PD can both be high potentials. On this basis, the potential of the shift signal output through the shift output terminal Next and the potential of the drive signal output through the drive output terminal Nout can both be low potentials.

[0284] (2) In the stage T02, the potential of the input signal provided by the input terminal In (i.e., the enable signal terminal ESTV) can be a high potential, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, and the potential of the second clock signal provided by the second clock terminal CKN can be a high potential. Correspondingly, the P-type first transistor T1 and the P-type sixth transistor T6 can both be controlled to be turned off, the N-type second transistor T2 and the N-type fourth transistor T4 can both be controlled to be turned on, and the P-type third transistor T3, the P-type fifth transistor T5 and the N-type seventh transistor T7 can all be controlled to be turned on. In this way, the second power terminal V2 (i.e., the pull-down power terminal VGL1) can be made to be connected to the first intermediate node N1 and the third intermediate node N3, the first intermediate node N1 and the third intermediate node N3 can be made to be connected to the control node PD, the first power terminal V1 (i.e., the pull-up power terminal VGH1) can be made to be connected to the second intermediate node N2, the first power terminal V1 can be made to be disconnected from the first intermediate node N1, and the second intermediate node N2 can be made to be disconnected from the control node PD. Further, the low potential power signal provided by the pull-down power terminal VGL1 can be made to be transmitted to the first intermediate node N1 through the turned-on second transistor T2 and to the third intermediate node N3 through the turned-on fourth transistor T4, the high potential power signal provided by the pull-up power terminal VGH1 can be made to be transmitted to the second intermediate node N2 through the turned-on third transistor T3, the low potential power signal transmitted to the first intermediate node N1 can be made to be further transmitted to the control node PD through the turned-on fifth transistor T5, and the low potential power signal transmitted to the third intermediate node N3 can be made to be further transmitted to the control node PD through the turned-on seventh transistor T7. That is, in this stage T02, the low potential power signal can be continued to be written to the first intermediate node N1 and the third intermediate node N3, the low potential power signal can be controlled to be further written to the control node PD, and the high potential power signal can be written to the second intermediate node N2.

[0285] On the basis that the potential of the control node PD is a low potential, the P-type eighth transistor T8, the P-type tenth transistor T10 and the P-type twelfth transistor T12 can be controlled to be all turned on, and the N-type ninth transistor T9, the N-type eleventh transistor T11 and the N-type thirteenth transistor T13 can be controlled to be all turned off. In this way, the third power supply end V3 (i.e., the pull-up power supply end VGH1) can be connected with the shift output end Next, the fourth power supply end V4 (i.e., the pull-down power supply end VGL1) can be disconnected with the shift output end Next, the fifth power supply end V5 (i.e., the pull-up power supply end VGH2) can be connected with the drive output end Nout, and the sixth power supply end V6 (i.e., the pull-down power supply end VGL2) can be disconnected with the drive output end Nout. Further, the high potential power supply signal provided by the pull-up power supply end VGH1 can be transmitted to the shift output end Next through the turned-on eighth transistor T8, and the high potential power supply signal provided by the pull-up power supply end VGH2 can be transmitted to the drive output end Nout through the turned-on twelfth transistor T12 and the tenth transistor T10 in sequence. That is, in the stage T02, the high potential input signal can be transmitted to the input end In of the other stage shift register unit in the cascade through the shift output end Next, and the high potential drive signal can be transmitted to the pixel circuit through the drive output end Nout.

[0286] That is, in combination with FIG. 10 and FIG. 11, in the stage T02, the potential of the first intermediate node N1 and the potential of the third intermediate node N3 can be both low potentials, the potential of the second intermediate node N2 can be a high potential, and the potential of the control node PD can be a low potential. On this basis, the potential of the shift signal output through the shift output end Next and the potential of the drive signal output through the drive output end Nout can be both high potentials.

[0287] (3) In stage T03, the input signal provided by the input terminal In (i.e., the enable signal terminal ESTV) can be at a low potential, the first clock signal provided by the first clock terminal CK can be at a high potential, and the second clock signal provided by the second clock terminal CKN can be at a low potential. Accordingly, the P-type first transistor T1 and the P-type sixth transistor T6 can be controlled to be turned on, the N-type second transistor T2 and the N-type fourth transistor T4 can be controlled to be turned off, and the P-type third transistor T3, the P-type fifth transistor T5 and the N-type seventh transistor T7 can be controlled to be turned off. In this way, the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH1) can be connected to the first intermediate node N1, the second intermediate node N2 can be connected to the control node PD, the first power supply terminal V1 can be disconnected from the second intermediate node N2, the second power supply terminal V2 (i.e., the pull-down power supply terminal VGL1) can be disconnected from the first intermediate node N1 and the third intermediate node N3, and the first intermediate node N1 and the third intermediate node N3 can be disconnected from the control node PD. Further, the high potential power supply signal provided by the pull-up power supply terminal VGH1 can be transmitted to the first intermediate node N1 through the turned-on first transistor T1. That is, in stage T03, the high potential power supply signal can be written to the first intermediate node N1, the potential of the control node PD can be maintained at the low potential before stage T03, and the potentials of the second intermediate node N2 and the third intermediate node N3 can also be maintained at the low potential, for example, for a time length of 1 horizontal scanning period (i.e., 1H).

[0288] On the basis that the potential of the control node PD is a low potential, the P-type eighth transistor T8, the P-type tenth transistor T10 and the P-type twelfth transistor T12 can be controlled to be all turned on, and the N-type ninth transistor T9, the N-type eleventh transistor T11 and the N-type thirteenth transistor T13 can be controlled to be all turned off. In this way, the third power supply end V3 (i.e., the pull-up power supply end VGH1) can be connected with the shift output end Next, the fourth power supply end V4 (i.e., the pull-down power supply end VGL1) can be disconnected with the shift output end Next, the fifth power supply end V5 (i.e., the pull-up power supply end VGH2) can be connected with the drive output end Nout, and the sixth power supply end V6 (i.e., the pull-down power supply end VGL2) can be disconnected with the drive output end Nout. Further, the high potential power supply signal provided by the pull-up power supply end VGH1 can be transmitted to the shift output end Next through the turned-on eighth transistor T8, and the high potential power supply signal provided by the pull-up power supply end VGH2 can be transmitted to the drive output end Nout through the turned-on twelfth transistor T12 and the tenth transistor T10 in sequence. That is, in the stage T03, the high potential input signal can be transmitted to the input end In of the other stage cascaded shift register unit through the shift output end Next, and the high potential drive signal can be transmitted to the pixel circuit through the drive output end Nout.

[0289] That is, in combination with FIG. 10 and FIG. 11, in the stage T03, the potential of the first intermediate node N1 can be a high potential, the potential of the second intermediate node N2 and the potential of the third intermediate node N3 can be both low potentials, and the potential of the control node PD can be a low potential. On the basis, the potential of the shift signal output through the shift output end Next and the potential of the drive signal output through the drive output end Nout can be both high potentials.

[0290] (4) In stage T04, the input signal provided by the input terminal In (i.e., the enable signal terminal ESTV) can be at a low potential, the first clock signal provided by the first clock terminal CK can first be at a low potential, and the second clock signal provided by the second clock terminal CKN can first be at a high potential. Accordingly, the P-type first transistor T1 and the P-type sixth transistor T6 can be controlled to be turned on, the N-type second transistor T2 and the N-type fourth transistor T4 can be controlled to be turned off, and the P-type third transistor T3, the P-type fifth transistor T5 and the N-type seventh transistor T7 can be controlled to be turned on. In this way, the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH1) can be connected to the first intermediate node N1 and the second intermediate node N2, and the first intermediate node N1, the second intermediate node N2 and the third intermediate node N3 can be connected to the control node PD, while the second power supply terminal V2 (i.e., the pull-down power supply terminal VGL1) can be disconnected from the first intermediate node N1 and the third intermediate node N3. Further, the high potential power signal provided by the pull-up power supply terminal VGH1 can be transmitted to the first intermediate node N1 through the turned-on first transistor T1, and to the second intermediate node N2 through the turned-on third transistor T3, and the high potential power signal transmitted to the first intermediate node N1 can be further transmitted to the control node PD through the turned-on fifth transistor T5, and the high potential power signal transmitted to the second intermediate node N2 can be further transmitted to the control node PD through the turned-on sixth transistor T6. That is, in stage T04, the high potential power signal can be written to the first intermediate node N1 and the second intermediate node N2, and the high potential power signal can be further written to the control node PD, so that the potential of the control node PD is shifted and raised from a low potential to a high potential once, and the potential of the third intermediate node N3 can be at a high potential.

[0291] On the basis that the potential of the control node PD is a high potential, the P-type eighth transistor T8, the P-type tenth transistor T10 and the P-type twelfth transistor T12 can be controlled to be all turned off, and the N-type ninth transistor T9, the N-type eleventh transistor T11 and the N-type thirteenth transistor T13 can be controlled to be all turned on. In this way, the fourth power supply end V4 (i.e., the pull-down power supply end VGL1) can be connected to the shift output end Next, the third power supply end V3 (i.e., the pull-up power supply end VGH1) can be disconnected from the shift output end Next, the sixth power supply end V6 (i.e., the pull-down power supply end VGL2) can be connected to the drive output end Nout, and the fifth power supply end V5 (i.e., the pull-up power supply end VGH2) can be disconnected from the drive output end Nout. Further, the low potential power supply signal provided by the pull-down power supply end VGL1 can be transmitted to the shift output end Next through the turned-on ninth transistor T9, and the low potential power supply signal provided by the pull-down power supply end VGL2 can be transmitted to the drive output end Nout through the turned-on thirteenth transistor T13 and the turned-on eleventh transistor T11 in sequence. That is, in this stage T04, the low potential input signal can be transmitted to the input end In of the other stage shift register unit in the cascade through the shift output end Next, and the low potential drive signal can be transmitted to the pixel circuit through the drive output end Nout.

[0292] That is, in combination with FIG. 10 and FIG. 11, in this stage T04, the potential of the first intermediate node N1, the potential of the second intermediate node N2 and the potential of the third intermediate node N3 can all be high potentials, and the potential of the control node PD can be a high potential. On this basis, the potential of the shift signal output through the shift output end Next and the potential of the drive signal output through the drive output end Nout can both be low potentials. Then, this stage T04 can be repeatedly executed. It can be seen from FIG. 10 and FIG. 11 that the falling edges of the shift signal and the drive signal output by the shift register unit provided in the embodiments of the present application are both stepless, and the output reliability is better.

[0293] Based on the above description, it can be known that the stage T02 and the stage T03 can correspond to the first stage shown in FIG. 9, and the stage T01 and the stage T04 can correspond to the second stage shown in FIG. 9.

[0294] Optionally, based on FIG. 10 and FIG. 11, FIG. 12 and FIG. 13 also schematically show the signal simulation timing diagrams output by the shift output Next and the driven output Nout of the cascaded 4-stage shift register unit under the control of input signals with different widths. The width of the input signal can refer to the time length of the input signal in the active potential (e.g., high potential). FIG. 12 shows a width of 4H, and FIG. 13 shows a width of 14H. In FIG. 12 and FIG. 13, the shift output Next of the cascaded 4-stage shift register unit is respectively identified as Next<1>, Next<2>, Next<3> and Next<4>, and the driven output Nout is respectively identified as Nout<1>, Nout<2>, Nout<3> and Nout<4>.

[0295] As can be seen from FIG. 12 and FIG. 13, under the control of input signals with different widths, the shift register unit can output signals with corresponding widths through the shift output Next and the driven output Nout, respectively. Thus, the signal width of the input signal can be flexibly adjusted according to the requirements, so as to output signals with the required width through the shift output Next and the driven output Nout, respectively. For example, the driven output Nout can be supported to output N-type gate drive signals GateN of even stages. Further, the high-frequency PWM driving requirements can be met.

[0296] Optionally, as can be known from the foregoing, the shift register unit provided by the embodiments of the present application can also support the local brushing function. Based on this, taking the structure shown in FIG. 8 as an example, FIG. 14 schematically shows a local brushing timing diagram based on FIG. 10.

[0297] First, as can be seen from FIG. 8, the display area A of the display panel shown therein is divided into one first display area A1 and two second display areas A2-1 and A2-2, that is, three areas, wherein the refresh frequency of the two second display areas A2-1 and A2-2 is 1hz, and the refresh frequency of the first display area A1 is 120hz. That is, the two second display areas A2-1 and A2-2 are low brushing areas, and the first display area A1 is a high brushing area.

[0298] Secondly, based on FIG. 8, it can be further seen from FIG. 14 that for the high-brush area (e.g., the first display area A1), the fifth power supply end V5 (i.e., the pull-up power supply end VGH2) can continuously provide the fifth power supply signal of high potential, so that the driving output end Nout outputs the driving signal of high potential. For the low-brush area (e.g., the second display areas A2-1 and A2-2), the fifth power supply signal provided by the fifth power supply end V5 can be switched from high potential to low potential, such as being switched to the low potential of the power supply signal provided by the pull-down power supply end VGL2, so that the driving output end Nout continuously outputs the driving signal of low potential. That is, as shown in FIG. 8 and FIG. 14, the shift register unit can output the driving signal of low potential to the second display areas A2-1 and A2-2 of the low-brush area through the driving output end Nout, and output the driving signal of high potential to the first display area A1 of the high-brush area, control the pixels in the second display areas A2-1 and A2-2 to emit light in response to the driving signal of low potential, and control the pixels in the first display area A1 to emit light in response to the driving signal of high potential, so as to realize low-frequency refresh and high-frequency refresh.

[0299] It can be understood that in FIG. 14, Nout<1> can refer to the driving output end Nout of the first-stage shift register unit connected to the first row of pixels; Next<1> can refer to the shift output end Next of the first-stage shift register unit connected to the first row of pixels; Next <n>Next N can be a shift output terminal of the Nth shift register unit connected with the Nth row of pixels; Nout N+1 can be a driving output terminal of the N+1th shift register unit connected with the N+1th row of pixels; Next N+1 can be a shift output terminal of the N+1th shift register unit connected with the N+1th row of pixels. N can be an integer greater than 0 and less than the number of rows of pixels.

[0300] It can also be understood that, since the driving method of the shift register unit can have substantially the same technical effects as the shift register unit described in the foregoing embodiments, for the purpose of brevity, the technical effects of the driving method of the shift register unit are not described again here.

[0301] In some embodiments, the first clock terminal CK is multiplexed as the second clock terminal CKN; the first clock signal provided by the first clock terminal CK is the same as the second clock signal CKN provided by the second clock terminal.

[0302] In some embodiments, the shift register unit further comprises a reset circuit 07 connected with a reset signal terminal CX, the first power supply terminal V1 and the control node PD respectively, and configured to control the on-off of the first power supply terminal V1 and the control node PD in response to a reset signal provided by the reset signal terminal CX; the method comprises: in the reset stage, the reset circuit 07 controls the first power supply terminal V1 and the control node PD to be turned on in response to the reset signal provided by the reset signal terminal CX.

[0303] Embodiments of the present application also provide a display driving circuit. As shown in FIG. 15, the display driving circuit comprises a plurality of shift register units (i.e., GOA units) connected in cascade, as shown in any one of FIGS. 1 to 7.

[0304] It can be understood that, as shown in the foregoing description and FIG. 15, each GOA unit is connected with the input terminal In of other GOA units connected in cascade through the shift output terminal Next, and the input terminal In of the first GOA unit GOA(1) can be connected with the enable signal terminal ESTV to realize cascade driving. The driving output terminal Nout of each GOA unit can be connected with pixels in a display panel to realize scan driving. In addition, each GOA unit can be connected with the clock terminal CK and the clock terminal CKN respectively. Furthermore, in the power supply scenario of double VGH and double VGL, each GOA unit can be connected with two pull-up power supply terminals VGH1 and VGH2 and two pull-down power supply terminals VGL1 and VGL2 respectively.

[0305] It can be understood that in the case that the GOA unit transmits the N-type gate drive signal GateN through the driving output end Nout, the GOA unit can also be referred to as a GateN GOA unit, and the display driving circuit including the GateN GOA unit can also be referred to as a gate driving circuit.

[0306] Optionally, in the case that the fifth power supply end V5 (i.e., the pull-up power supply end VGH2) connected to each GOA unit is an alternating current power supply end, at least two GOA units can be connected to different fifth power supply ends V5. That is, a plurality of groups of VGH2 can be provided for connection of a plurality of cascaded GOA units, and it is not limited to two groups of VGH2 or three groups of VGH2. In this way, compared with the case shown in FIG. 15 in which one group of VGH2 is provided for connection of a plurality of GOA units, the voltage drop of the power supply signal provided by each group of VGH2 can be reduced, so that the GOA units connected to different VGH2 can reliably receive the power supply signal provided by VGH2. That is, multiple groups of VGH2 can ensure the output integrity of the driving signal and meet the requirements of the local brushing function.

[0307] For example, referring to FIG. 16, two groups of VGH2 (1) and VGH2 (2) are provided in the display driving circuit shown in FIG. 16; and referring to FIG. 17, three groups of VGH2 (1), VGH2 (2) and VGH2 (3) are provided in the display driving circuit shown in FIG. 17. In addition, it can also be seen from FIGS. 16 and 17 that a plurality of groups of VGH2 can be alternately connected to a plurality of GOA units. For example, in FIG. 16, every four GOA units are taken as one group of GOA units, and the adjacent two groups of GOA units are alternately connected to the two groups of VGH2 (1) and VGH2 (2) provided one by one. In FIG. 17, every six GOA units are taken as one group of GOA units, and the adjacent three groups of GOA units are alternately connected to the three groups of VGH2 (1), VGH2 (2) and VGH2 (3) provided one by one. The GOA units shown in FIGS. 16 and 17 are all GateN GOA units.

[0308] Of course, the above examples are only illustrative. For example, the number of GOA units connected to each group of VGH2 can not be limited, and the number of groups of VGH2 provided can not be limited. In some other embodiments, VGH2 is also not limited to being provided in multiple groups, and CK and / or CKN can also be provided in multiple groups.

[0309] It can be understood that the display driving circuit can have substantially the same technical effects as the shift register unit described in the foregoing embodiments, and therefore the technical effects of the display driving circuit will not be described again for the purpose of brevity.

[0310] The display device provided by the embodiments of the present application also includes the display panel 10 and the display driving circuit 00 as shown in any one of FIGS. 15 to 17.

[0311] The display panel 10 can include a plurality of pixels (not shown in FIG. 18). The display driving circuit 00 can be connected to the plurality of pixels through the driving output terminal Nout and be configured to transmit a driving signal (e.g., a gate driving signal) to the plurality of pixels to drive the plurality of pixels to emit light.

[0312] Optionally, the display device described in the embodiments of the present application can be any product or component with display function, such as an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, and a liquid crystal display device.

[0313] The AMOLED display device has small power consumption, a wide working temperature range, low cost, high contrast, wide viewing angle, wide color gamut, and thin display panel, and can realize flexible display, so as to gradually become the next generation of display crown. The OLED display device can meet the requirements of high performance and large capacity of display equipment in the current information age, can be used for indoor and outdoor lighting, can be used as wallpaper decoration, can be made into foldable electronic newspapers, and can also be applied to portable electronic products such as mobile phones, tablet computers, and wearable electronic devices.

[0314] It can be understood that the display device can have substantially the same technical effects as the shift register unit described in the foregoing embodiments, and therefore, for the purpose of brevity, the technical effects of the display device are not described again.

[0315] It should be noted that the terms used in some embodiments of the present application are only used to explain the embodiments, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meaning understood by those skilled in the art in the field of the present application.

[0316] For example, the terms "first", "second", or "third" and similar terms used in the patent application specification and claims of the present application do not represent any order, number, or importance, but are only used to distinguish different components.

[0317] Similarly, "one" or "a" and similar terms do not represent a quantity limitation, but represent the existence of at least one.

[0318] The terms "comprise", "comprising", "include", "including" or "contain", "containing" and the like are used in the sense of "including" and / or "comprising" and not by way of "consisting only of".

[0319] The terms "upper", "lower", "left", "right" and the like are used for ease of description to describe the orientation of the components to each other. It is to be understood that the orientation of various components can be changed with respect to each other and the absolute position of the described object can be changed, and the relative positional relationship described can be changed accordingly. "Connected" or "coupled" means electrical connection.

[0320] The term "and / or", means that there are three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0321] The above description is only optional embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.< / n>

Claims

1. A shift register unit, the shift register unit comprising: an input circuit connected with an input terminal, a first clock terminal, a second clock terminal, a first power terminal, a second power terminal and a control node respectively, and configured to control on-off of the first power terminal and the control node, and control on-off of the second power terminal and the control node in response to an input signal provided by the input terminal, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal, and the first power terminal and the second power terminal are turned on with the control node in different time periods respectively; a first output circuit connected with the control node, a third power terminal, a fourth power terminal and a shift output terminal respectively, and configured to control on-off of the third power terminal and the shift output terminal, and control on-off of the fourth power terminal and the shift output terminal in response to a potential of the control node, and the third power terminal and the fourth power terminal are turned on with the control node in different time periods respectively; a second output circuit connected with the control node, a fifth power terminal, a sixth power terminal and a driving output terminal respectively, and configured to control on-off of the fifth power terminal and the driving output terminal, and control on-off of the sixth power terminal and the driving output terminal in response to a potential of the control node, and the third power terminal and the fourth power terminal are turned on with the control node in different time periods respectively.

2. The shift register cell of claim 1, wherein, the input circuit comprises: a first input sub-circuit connected with the input terminal, the first power terminal, the second power terminal and a first intermediate node respectively, and configured to control on-off of the first power terminal and the first intermediate node, and control on-off of the second power terminal and the first intermediate node in response to the input signal, and the first power terminal and the second power terminal are turned on with the first intermediate node in different time periods respectively; a second input sub-circuit connected with the input terminal, the first clock terminal, the second clock terminal, the first intermediate node, the first power terminal, the second power terminal and the control node respectively, and configured to control on-off of the first intermediate node and the control node in response to the first clock signal, control on-off of the first power terminal and the control node in response to the first clock signal and the input signal, and control on-off of the second power terminal and the control node in response to the second clock signal and the input signal.

3. The shift register cell of claim 2, wherein, the first input sub-circuit comprises: a first transistor and a second transistor; and the first transistor is a first type transistor, and the second transistor is a second type transistor; a gate of the first transistor is connected with the input terminal, a first pole of the first transistor is connected with the first power terminal, and a second pole of the first transistor is connected with the first intermediate node; a gate of the second transistor is connected with the input terminal, a first pole of the second transistor is connected with the second power terminal, and a second pole of the second transistor is connected with the first intermediate node.

4. The shift register cell of claim 2, wherein, the second input sub-circuit comprises: The first input unit is connected with the first clock terminal, the first power terminal and the second intermediate node respectively, and is configured to control the on-off of the first power terminal and the second intermediate node in response to the first clock signal. The second input unit is connected with the input terminal, the second power terminal and the third intermediate node respectively, and is configured to control the on-off of the second power terminal and the third intermediate node in response to the input signal. The third input unit is connected with the first clock terminal, the second clock terminal, the input terminal, the first intermediate node, the second intermediate node, the third intermediate node and the control node respectively, and is configured to control the on-off of the first intermediate node and the control node in response to the first clock signal, control the on-off of the second intermediate node and the control node in response to the input signal, and control the on-off of the third intermediate node and the control node in response to the second clock signal.

5. The shift register cell of claim 4, wherein, The first input unit comprises a third transistor, the second input unit comprises a fourth transistor, the third input unit comprises a fifth transistor, a sixth transistor and a seventh transistor, and the third transistor, the fifth transistor and the sixth transistor are first type transistors, and the fourth transistor and the seventh transistor are second type transistors. The gate of the third transistor is connected with the first clock terminal, the first pole of the third transistor is connected with the first power terminal, and the second pole of the third transistor is connected with the second intermediate node. The gate of the fourth transistor is connected with the input terminal, the first pole of the fourth transistor is connected with the second power terminal, and the second pole of the fourth transistor is connected with the third intermediate node. The gate of the fifth transistor is connected with the first clock terminal, the first pole of the fifth transistor is connected with the first intermediate node, and the second pole of the fifth transistor is connected with the control node. The gate of the sixth transistor is connected with the input terminal, the first pole of the sixth transistor is connected with the second intermediate node, and the second pole of the sixth transistor is connected with the control node. The gate of the seventh transistor is connected with the second clock terminal, the first pole of the sixth transistor is connected with the third intermediate node, and the second pole of the sixth transistor is connected with the control node.

6. The shift register cell of claim 4, wherein, The first clock terminal is multiplexed as the second clock terminal, and the first clock terminal and the second clock terminal input the same clock signal.

7. The shift register cell of claim 6, wherein, The first input unit comprises a third transistor, the second input unit comprises a fourth transistor, the third input unit comprises a fifth transistor, a sixth transistor and a seventh transistor, and the third transistor, the fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the fourth transistor is a second type transistor. The gate of the third transistor is connected with the first clock terminal, the first pole of the third transistor is connected with the first power terminal, and the second pole of the third transistor is connected with the second intermediate node. A gate of the fourth transistor is connected with the input end, a first electrode of the fourth transistor is connected with the second power supply end, and a second electrode of the fourth transistor is connected with the third intermediate node; A gate of the fifth transistor is connected with the first clock end, a first electrode of the fifth transistor is connected with the first intermediate node, and a second electrode of the fifth transistor is connected with the control node; A gate of the sixth transistor is connected with the input end, a first electrode of the sixth transistor is connected with the second intermediate node, and a second electrode of the sixth transistor is connected with the control node; A gate of the seventh transistor is connected with the first clock end, a first electrode of the seventh transistor is connected with the third intermediate node, and a second electrode of the seventh transistor is connected with the control node.

8. The shift register cell of claim 1, wherein, The first output circuit comprises an eighth transistor and a ninth transistor; the eighth transistor is a first type transistor, and the ninth transistor is a second type transistor; A gate of the eighth transistor is connected with the control node, a first electrode of the eighth transistor is connected with the third power supply end, and a second electrode of the eighth transistor is connected with the shift output end; A gate of the ninth transistor is connected with the control node, a first electrode of the ninth transistor is connected with the fourth power supply end, and a second electrode of the ninth transistor is connected with the shift output end.

9. The shift register cell of any of claims 1 to 7, wherein, The third power supply end is shared with the first power supply end, and / or the fourth power supply end is shared with the second power supply end.

10. The shift register cell of claim 1, wherein, The second output circuit comprises a tenth transistor and an eleventh transistor; the tenth transistor is a first type transistor, and the eleventh transistor is a second type transistor; A gate of the tenth transistor is connected with the control node, a first electrode of the tenth transistor is connected with the fifth power supply end, and a second electrode of the tenth transistor is connected with the drive output end; A gate of the eleventh transistor is connected with the control node, a first electrode of the eleventh transistor is connected with the sixth power supply end, and a second electrode of the eleventh transistor is connected with the drive output end.

11. The shift register cell of claim 10, wherein, The second output circuit further comprises a twelfth transistor connected in series between the fifth power supply end and the tenth transistor, and a thirteenth transistor connected in series between the sixth power supply end and the eleventh transistor; the twelfth transistor and the tenth transistor are transistors of the same type, and the thirteenth transistor and the eleventh transistor are transistors of the same type; A gate of the twelfth transistor is connected with the control node, a first electrode of the twelfth transistor is connected with the fifth power supply end, and a second electrode of the twelfth transistor is connected with a first electrode of the tenth transistor; A gate of the thirteenth transistor is connected with the control node, a first electrode of the thirteenth transistor is connected with the sixth power supply end, and a second electrode of the thirteenth transistor is connected with a first electrode of the eleventh transistor.

12. The shift register cell of claim 11, wherein, The channel width-length ratio of the tenth transistor and the twelfth transistor connected in series is different. And / or, a channel width-length ratio of the eleventh transistor and the thirteenth transistor connected in series is different.

13. The shift register cell of claim 12, wherein, A channel width-length ratio of the tenth transistor is greater than a channel width-length ratio of the twelfth transistor. A channel width-length ratio of the eleventh transistor is greater than a channel width-length ratio of the thirteenth transistor.

14. The shift register cell of claim 10, wherein, The shift register unit further comprises: A driving enhancement circuit connected between the control node and the second output circuit, and configured to transmit the potential of the control node to the second output circuit after at least one enhancement processing.

15. The shift register cell of claim 14, wherein, The driving enhancement circuit comprises one or a plurality of inverters connected in series. Each of the inverters comprises a fourteenth transistor and a fifteenth transistor connected in series between the first power supply terminal and the second power supply terminal, and the fourteenth transistor is a first type transistor and the fifteenth transistor is a second type transistor.

16. The shift register cell of claim 1, wherein, The second output circuit is connected with the shift output terminal to connect with the control node through the first output circuit. The second output circuit is configured to control the on-off of the fifth power supply terminal and the driving output terminal and the on-off of the sixth power supply terminal and the driving output terminal in response to the potential of the shift output terminal.

17. The shift register cell of claim 16, wherein, The second output circuit comprises an eighteenth transistor and a nineteenth transistor. The gate of the eighteenth transistor is connected with the shift output terminal, the first electrode of the eighteenth transistor is connected with the fifth power supply terminal, and the second electrode of the eighteenth transistor is connected with the driving output terminal; the gate of the nineteenth transistor is connected with the shift output terminal, the first electrode of the nineteenth transistor is connected with the sixth power supply terminal, and the second electrode of the nineteenth transistor is connected with the driving output terminal.

18. The shift register cell of claim 16, wherein, The shift register unit further comprises: An output enhancement circuit connected between the shift output terminal and the second output circuit, and configured to transmit the potential of the shift output terminal to the second output circuit after at least one enhancement processing.

19. The shift register cell of claim 18, wherein, The output enhancement circuit comprises one or at least two inverters connected in series. Each of the inverters comprises a twentieth transistor and a twenty-first transistor connected in series between the first power supply terminal and the second power supply terminal, and the twentieth transistor is a first type transistor and the twenty-first transistor is a second type transistor.

20. The shift register cell of any of claims 10 to 19, wherein, The first power supply terminal to the fourth power supply terminal and the sixth power supply terminal are direct current power supply terminals, and the fifth power supply terminal is a direct current power supply terminal or an alternating current power supply terminal.

21. The shift register cell of claim 20, wherein, The driving output terminal is configured to be connected with pixels in a display area of a display panel to transmit driving signals to the pixels to drive the pixels to emit light, and the display area comprises a first display area and a second display area, and a refresh frequency of the first display area is greater than a refresh frequency of the second display area. The potential of the fifth power supply signal provided by the fifth power supply terminal when driving the pixels in the first display area to emit light is greater than the potential of the fifth power supply signal provided by the fifth power supply terminal when driving the pixels in the second display area to emit light.

22. The shift register cell of claim 21, wherein, When driving the pixels in the second display area to emit light, the potential of the fifth power supply signal provided by the fifth power supply end is greater than the potential of the second power supply signal provided by the second power supply end.

23. The shift register cell of any of claims 3 to 8, 10 to 15, 19, wherein, In the shift register unit, the first type of transistor is a P-type transistor, and the second type of transistor is an N-type transistor.

24. The shift register cell of any one of claims 1 to 7, wherein, The shift register unit further comprises a storage capacitor connected between the first power supply end and the control node.

25. The shift register cell of any one of claims 1 to 7, wherein, The shift register unit further comprises: A reset circuit connected to the reset signal end, the first power supply end and the control node, and configured to control the on-off of the first power supply end and the control node in response to a reset signal provided by the reset signal end.

26. The shift register cell of claim 25, wherein, The reset circuit comprises a sixteenth transistor and a seventeenth transistor. The gate of the sixteenth transistor is connected to the reset signal end, the first electrode of the sixteenth transistor is connected to the first power supply end, and the second electrode of the sixteenth transistor is connected to the first electrode of the seventeenth transistor; the gate of the seventeenth transistor is connected to the reset signal end, and the second electrode of the seventeenth transistor is connected to the control node.

27. A driving method of a shift register unit, for driving the shift register unit as claimed in any one of claims 1 to 26; the method comprising: In the first stage, the input circuit controls the first power supply end and the control node to be disconnected, and controls the second power supply end and the control node to be connected, in response to the input signal provided by the input end, the first clock signal provided by the first clock end and the second clock signal provided by the second clock end; the first output circuit controls the third power supply end and the shift output end to be connected, and controls the fourth power supply end and the shift output to be disconnected, in response to the potential of the control node; and the second output circuit controls the fifth power supply end and the driving output end to be connected, and controls the sixth power supply end and the driving output to be disconnected, in response to the potential of the control node. In the second stage, the input circuit controls the first power supply end and the control node to be connected, and controls the second power supply end and the control node to be disconnected, in response to the input signal, the first clock signal and the second clock signal; the first output circuit controls the third power supply end and the shift output end to be disconnected, and controls the fourth power supply end and the shift output to be connected, in response to the potential of the control node; and the second output circuit controls the fifth power supply end and the driving output end to be disconnected, and controls the sixth power supply end and the driving output to be connected, in response to the potential of the control node.

28. The driving method of the shift register unit according to claim 27, wherein The first clock end is multiplexed as the second clock end; the first clock signal provided by the first clock end is the same as the second clock signal provided by the second clock end.

29. The driving method of the shift register unit according to claim 27 or 28, wherein, The shift register unit further comprises a reset circuit connected to the reset signal end, the first power supply end and the control node, and configured to control the on-off of the first power supply end and the control node in response to a reset signal provided by the reset signal end; The method comprises: In a reset stage, the reset circuit controls the first power supply end and the control node to be conductive in response to a reset signal provided by the reset signal end.

30. A display drive circuit, the display drive circuit comprising: A plurality of shift register units as claimed in any one of claims 1 to 26 connected in cascade.

31. The display driver circuit of claim 30, wherein, In the case where the fifth power supply end connected to each of the shift register units is an alternating current power supply end, at least two of the shift register units are connected to different fifth power supply ends.

32. A display device comprising: A display panel, and a display driving circuit as claimed in claim 30 or 31; The display panel comprises a plurality of pixels. The display driving circuit is connected to the plurality of pixels via a driving output end and is configured to transmit driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

Images