Micro-ring modulation light engine based on glass substrate packaging and manufacturing method thereof

Abstract

The invention relates to a micro-ring modulation light engine based on glass substrate packaging and a manufacturing method thereof, and the light engine comprises a glass substrate which is provided with a first plate surface and a second plate surface; the micro-ring modulation optical chip and the electric chip are respectively mounted on the first plate surface through a first connecting structure, and the optical chip and the electric chip are electrically connected through an electric interconnection structure formed in the glass substrate; the engine substrate is electrically connected with the second board surface through a second connecting structure, so that the micro-ring modulation optical chip and the electric chip are electrically communicated with an external circuit; and the optical coupling element is optically coupled to the optical port of the optical chip. In the invention, the glass substrate is used as an adapter plate to connect the photoelectric chip and the engine substrate, so that the micro-ring modulation optical chip and the electric chip can be integrated on the glass substrate in a high-density manner through a packaging technology, and the problems of high I / O quantity and high-bandwidth electric interconnection between the micro-ring modulation optical chip and the driving chip can be well solved; the integration level and the photoelectron interconnection density which are far higher than those of a traditional packaging scheme are achieved; through high-density integration, extremely high bandwidth density is realized in an extremely small packaging size, and dual requirements of a CPO / NPO optical engine on extreme performance and compact space occupation can be met.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology, specifically relating to a micro-ring modulation optical engine based on glass substrate packaging and its fabrication method. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence, cloud computing, and big data centers, the bandwidth and power consumption requirements for internal data exchange are increasing exponentially. The interface rate and density of traditional pluggable optical modules are gradually reaching physical limits. Their pluggable nature leads to higher power consumption and bottlenecks in gold finger density, which have become key factors restricting the performance improvement of next-generation data center networks. Against this backdrop, co-packaged optics (CPO) and near-packaged optics (NPO) technologies have emerged. By physically integrating the optical engine with the network switching chip, they significantly shorten the electrical interconnect distance, thereby achieving ultra-high bandwidth while effectively reducing system power consumption and latency. Under the OIF protocol framework, the physical characteristics and dimensions of the CPO optical engine are defined, imposing stringent requirements on the packaging space. Micro-ring modulators (MRMs), as small, low-power, and easily integrated optoelectronic modulation elements, are considered one of the ideal choices for building next-generation CPO / NPO optical engines. However, transforming the potential of micro-ring modulators into practically usable high-performance products still faces significant packaging challenges:

[0003] (1) Inconsistency between integration density and size: In order to achieve high bandwidth, the optical engine needs to integrate multiple channels of micro-ring modulators and their corresponding driving amplifier chips; traditional packaging solutions (such as flip-chip bonding based on organic substrates) have limited interconnection density, making it difficult to achieve high-density integration of a large number of high-bandwidth electrical interconnects between micro-ring chips and driving chips while maintaining small size.

[0004] (2) Performance and cost balance: Currently, 2.5D packaging is the mainstream advanced solution for high-density interconnects, but it usually uses silicon interposers. Although silicon interposers have excellent performance, they are expensive to manufacture, and their semiconductor characteristics introduce additional radio frequency losses and parasitic effects, which pose a challenge to the integrity of high-frequency electrical signals and limit the improvement of overall system performance.

[0005] (3) Bandwidth density bottleneck: Existing packaging solutions based on organic substrates or silicon interposers are difficult to break through the bandwidth density limit within a limited packaging size. Summary of the Invention

[0006] This invention relates to a micro-ring modulation optical engine based on glass substrate encapsulation and its fabrication method, which can at least solve some of the defects of the prior art.

[0007] This invention relates to a micro-ring modulation optical engine based on glass substrate encapsulation, comprising:

[0008] A glass substrate having a first surface and a second surface;

[0009] An optical chip and an electrical chip are respectively mounted on the first board surface through a first connection structure, and the optical chip and the electrical chip are also electrically connected through an electrical interconnect structure formed in the glass substrate; the optical chip is a micro-ring modulation chip.

[0010] The engine substrate is electrically connected to the second board surface through a second connection structure, thereby enabling the optical chip and the electrical chip to be electrically connected to an external circuit.

[0011] An optical coupling element is optically coupled to the optical port of the optical chip.

[0012] As one embodiment, the glass substrate includes a substrate core layer, a first substrate augmentation layer and a second substrate augmentation layer formed on both sides of the substrate core layer, the outer surface of the first substrate augmentation layer being configured as the first plate surface, the outer surface of the second substrate augmentation layer being configured as the second plate surface, and the electrical interconnection structure being formed in the first substrate augmentation layer.

[0013] As one embodiment, the optical chip and the electrical chip are respectively formed with vertical interconnect vias in the core layer of the substrate. One end of the vertical interconnect via is electrically connected to the first connection structure through an interconnect line formed in the first substrate layer, and the other end is electrically connected to the second connection structure through an interconnect line formed in the second substrate layer.

[0014] As one embodiment, both the first substrate addition layer and the second substrate addition layer are multilayer structures, and the number of multilayers and the residual copper ratio of the two are symmetrically distributed relative to the substrate core layer.

[0015] As one embodiment, the first connection structure is a bump interconnect structure, the second connection structure is a solder ball interconnect structure, and the size of the solder ball in the second connection structure is larger than the size of the bump in the first connection structure.

[0016] As one embodiment, the electrical interconnect structure includes radio frequency transmission lines fabricated in the glass substrate.

[0017] As one implementation method, there are multiple electrical chips, and each electrical chip is symmetrically distributed with respect to the central axis of the optical chip.

[0018] As one implementation, the optical port of the optical chip extends beyond the edge of the glass substrate and is end-face coupled to the optical coupling element.

[0019] As one embodiment, the micro-ring modulation optical engine further includes a heat dissipation cover plate, which is located on the side of the electrical chip away from the glass substrate, and the gap between the heat dissipation cover plate and the electrical chip is filled with thermally conductive adhesive.

[0020] The present invention also relates to a method for fabricating the micro-ring modulated optical engine as described above, comprising:

[0021] Fabrication of glass substrates;

[0022] Optical chips and electrical chips are mounted on the first board surface to obtain a primary package.

[0023] Connect the primary package to the engine base plate;

[0024] The optical coupling element and the optical chip are optically coupled.

[0025] The present invention has at least the following beneficial effects:

[0026] In this invention, a glass substrate is used as an adapter to connect the optoelectronic chip and the engine substrate. This allows for high-density integration of the optical chip and the electrical chip on the glass substrate through packaging technology. This effectively solves the problem of high I / O quantity and high-bandwidth electrical interconnection between optical chips, especially micro-ring modulation optical chips and driver chips, achieving an integration level and optoelectronic interconnection density far exceeding traditional packaging solutions. Through this high-density integration, extremely high bandwidth density is achieved within a very small package size, which can meet the dual requirements of extreme performance and compact space occupation of the CPO / NPO optical engine under the next-generation OIF protocol framework.

[0027] The aforementioned glass substrate possesses excellent high-frequency radio frequency characteristics (such as low loss and low parasitic capacitance), lower cost, and superior optical flatness. While reducing the overall packaging manufacturing cost, it provides superior high-frequency electrical signal transmission integrity compared to silicon interposers, effectively improving the overall performance of the optical engine.

[0028] By leveraging the excellent thermal stability and designability of glass substrates, the thermal management path of the package can be optimized, effectively dissipating the heat generated during the operation of the electronic chip, reducing the performance drift of the optical chip caused by temperature fluctuations, thereby improving the long-term operational stability and reliability of the optical engine.

[0029] This invention provides a flexible and scalable packaging architecture that is not only suitable for specific optoelectronic combinations (such as the combination of micro-ring modulation optical chips and driver chips), but also serves as a general platform to support the integration of more chips in the future. Moreover, it can directly package and connect ASIC chips and optical engines using a large-size glass substrate, eliminating the redundancy of engine substrates and packaging substrates, and providing a reliable hardware foundation for the large-scale application of CPO / NPO technology.

[0030] This invention creatively solves the contradiction between performance, cost, size and reliability in high-density optoelectronic device integration through the unique technical approach of "glass substrate + 2.5D packaging", and promotes the practical application of co-packaging optical technology. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the overall packaging of the optical engine provided in an embodiment of the present invention;

[0033] Figure 2 This is a side view of the packaging structure of the light engine provided in an embodiment of the present invention;

[0034] Figure 3 This is a top view of the packaging structure of the light engine provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram showing the packaging details of the optical engine provided in an embodiment of the present invention;

[0036] Figure 5 A schematic diagram showing the optical coupling details of the optical engine provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the installation structure of the heat dissipation cover provided in an embodiment of the present invention;

[0038] Figures 7-9 A flowchart illustrating the manufacturing process of a light engine provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] like Figures 1-4 This invention provides a light engine based on a glass substrate 400 package, comprising:

[0041] The glass substrate 400 has a first plate surface and a second plate surface;

[0042] The optical chip 100 and the electrical chip are respectively mounted on the first board surface through the first connection structure, and the optical chip 100 and the electrical chip are also electrically connected through the electrical interconnection structure formed in the glass substrate 400.

[0043] The engine substrate 600 is electrically connected to the second board surface through a second connection structure, thereby enabling the optical chip 100 and the electrical chip to be electrically connected to an external circuit.

[0044] Optical coupling element 800 is optically coupled to the optical port of optical chip 100.

[0045] As a preferred option, the aforementioned optical chip 100 adopts a micro-ring modulation chip, whose optical integration per unit area is much greater than that of the MZM modulator chip (up to 50 times or more), and its bandwidth density is not less than 3000Gb / s / mm. This makes the optical chip 100 very small in size, greatly reducing the overall package size and effectively addressing the space constraints in CPO / NPO optical engines. At the same time, the small chip size can effectively avoid the stress problems caused by substrate warping of large chips.

[0046] The aforementioned glass substrate 400 serves as an adapter board connecting the optoelectronic chip and the engine substrate 600. It has advantages such as a small coefficient of thermal expansion, good rigidity, anti-warping, good radio frequency performance (such as low loss and low parasitic capacitance), and low cost. It can effectively meet the packaging requirements of small bumps and the high bandwidth requirements of products. While reducing the overall packaging manufacturing cost, it provides high-frequency electrical signal transmission integrity that is superior to that of silicon interposers, effectively improving the overall performance of the optical engine.

[0047] The aforementioned engine substrate 600 is preferably made of an organic substrate, generally using a low dielectric loss material (such as FR4). To improve circuit density, SAP process is preferably used to fabricate the circuitry. The top of the engine substrate 600, excluding the pads for soldering to the glass substrate 400, houses a chipset (e.g., including MCU, DCDC, AFE, ADC / DAC, and resistors, capacitors, inductors, etc.). The bottom of the engine substrate 600 (i.e., the side furthest from the glass substrate 400) can be connected to the electrical interface of the packaging substrate 130 via BGA, LGA, PGA, or other packaging methods, and is packaged with the ASIC chip on the same packaging substrate 130.

[0048] In one embodiment, such as Figure 4The first connection structure is a bump interconnect structure. Copper pillars 501 and solder caps 502 are formed on both the optical chip 100 and the electrical chip to form bumps. Furthermore, nickel metal is plated between the copper pillars 501 and the solder caps 502 to prevent electromigration failure. Corresponding pads are designed on the glass substrate 400, including but not limited to forming a first UBM layer 405 on the first surface of the glass substrate 400. The bumps (copper pillars 501 and solder caps 502) on the optical chip 100 / electrical chip are soldered to the first UBM layer 405 on the glass substrate 400 to form the above-mentioned bump interconnect structure. The soldering process can be reflow soldering, thermoforming, or ultrasonic soldering.

[0049] Furthermore, such as Figure 4 In the first connection structure, the bottom filling adhesive 503 is also used to cover the bump interconnect area. Generally, the adhesive is filled between the optical chip 100 / electrical chip and the glass substrate 400, which can increase the welding stability and relieve local stress.

[0050] In one embodiment, such as Figure 4 The second connection structure is a solder ball interconnect structure. Specifically, solder balls 406 can be fabricated on the second plate surface of the glass substrate 400, and a second UBM layer 601 can be fabricated on the engine substrate 600. The solder balls 406 on the glass substrate 400 are soldered to the second UBM layer 601 on the engine substrate 600 to form the above-mentioned solder ball interconnect structure. The soldering process can be reflow soldering or hot press soldering, etc.

[0051] Furthermore, such as Figure 4 In the second connection structure, the solder ball 406 is larger than the bump size in the first connection structure; for example, the diameter of the solder ball 406 is larger than the height of the bump. A high-density, small-size bump interconnect structure is used between the optoelectronic chip and the glass substrate 400, which can better adapt to the stress environment between the optoelectronic chip and the glass substrate 400. Simultaneously, it allows for a large number of interconnect points to be arranged within a unit area, thus physically supporting the connection requirements of massive parallel high-speed channels between the optical chip 100 and multiple driver / amplifier chips 700, facilitating the realization of high bandwidth requirements for the product. A low-density, large-size solder ball interconnect structure is used between the glass substrate 400 and the engine substrate 600. The larger solder volume and height provide stronger elastic deformation capability, effectively absorbing stress like a spring, preventing solder joint fatigue cracking, and reliably resisting the large difference in thermal expansion coefficients between the glass substrate 400 and the engine substrate 600, greatly improving the long-term reliability of the aforementioned optical engine under harsh conditions such as high-temperature operation and temperature cycling.

[0052] In one embodiment, the solder balls 406 in the second connection structure use C4 or BGA solder balls, which have a large size and are able to resist the large difference in the coefficient of thermal expansion between the glass substrate 400 and the engine substrate 600.

[0053] In one embodiment, such as Figure 4 The glass substrate 400 includes a substrate core layer 401, a first substrate augmentation layer 402 and a second substrate augmentation layer 403 formed on both sides of the substrate core layer 401. The outer surface of the first substrate augmentation layer 402 is configured as the first plate surface, and the outer surface of the second substrate augmentation layer 403 is configured as the second plate surface. The electrical interconnection structure is formed in the first substrate augmentation layer 402.

[0054] Preferably, the substrate core layer 401 is made of low dielectric constant glass; the first substrate addition layer 402 and the second substrate addition layer 403 can both be made of low dielectric loss materials, such as ABF, PP, etc.

[0055] In one embodiment, such as Figure 4 Vertical interconnect vias 4011 are formed in the core layer 401 of the substrate, respectively, for the optical chip 100 and the electrical chip. One end of the vertical interconnect via 4011 is electrically connected to the first connection structure through an interconnect line 404 formed in the first substrate layer 402, and the other end is electrically connected to the second connection structure through an interconnect line 404 formed in the second substrate layer 403.

[0056] Preferably, both the first substrate addition layer 402 and the second substrate addition layer 403 are multilayer structures, which facilitates the fabrication of the interconnect lines 404; wherein, to improve product yield, the number of layers should be minimized as much as possible. In one embodiment, the interconnect lines 404 in the first substrate addition layer 402 and the second substrate addition layer 403 are fabricated using SAP or MSAP processes; the number of routing layers of the interconnect lines 404 can be designed according to factors such as the number and complexity of routing lines; the seed layer for circuit fabrication is generally fabricated using electroless plating or ion implantation processes.

[0057] For the aforementioned vertical interconnect via 4011, preferably, it is fabricated by first drilling holes in the substrate core layer 401 and then filling the holes with copper. Laser-induced etching can be used for drilling, and the hole shape is determined based on RF simulation evaluation. Generally, the hole walls should be as vertical as possible to ensure impedance continuity, and the hole wall roughness should be as low as possible. For copper filling, preferably, a seed layer is first fabricated on the hole sidewalls. Generally, electroless plating or ion implantation processes are used to bond Cu ions to the hole walls, followed by electroplating to fill with copper. Depending on RF performance requirements, either full Cu filling or a plugging process can be used.

[0058] In the above structure, a reliable connection between the optoelectronic chip and the engine substrate 600 is achieved, while linewidth and spacing at the micron or even submicron level are realized. This allows a massive number of parallel differential signal traces to be integrated within the limited area of ​​the glass substrate 400, making it easier to meet the high bandwidth requirements of the product.

[0059] In the above structure, the inherent characteristics of the glass substrate 400—low dielectric constant and low loss—combined with the aforementioned low-roughness vias and precision circuitry, provide a low-loss, low-crosstalk transmission environment for high-frequency radio frequency signals.

[0060] More preferably, the number of layers and the residual copper ratio of the first substrate add-on layer 402 and the second substrate add-on layer 403 are symmetrically distributed relative to the substrate core layer 401. This ensures stress balance on both sides of the glass substrate 400. The symmetrical add-on structure design and good stress management ensure low warpage and high flatness of the glass substrate 400 during thermal cycling, thereby ensuring the long-term reliability of the flip chip solder joints on it and stable optical alignment with optical coupling elements (such as fiber array 801).

[0061] The electrical interconnection structure between the optical chip 100 and the electrical chip includes, but is not limited to, the fabrication of a radio frequency transmission line 407 in the glass substrate 400 (e.g., the first substrate addition layer 402 described above). Further, one or more radio frequency circuit matching elements 200 are disposed on the radio frequency transmission line of this electrical interconnection structure. The radio frequency circuit matching elements 200 can be capacitors and / or inductors, forming a differential radio frequency network; preferably, small-sized (≤0.2*0.2*0.4mm) ultra-high bandwidth capacitors / inductors are used. Based on the above structure, using the glass substrate 400 as an intermediary platform, the optical chip 100 and the electrical chip are directly connected via radio frequency lines, physically achieving a sub-millimeter level ultra-short interconnection distance. This enables high-speed inter-chip interconnection with extremely short paths and ultra-low losses. Combined with the inherent low dielectric loss characteristics of glass materials, this fundamentally minimizes path loss and delay in signal transmission, providing core support for achieving a total bandwidth and ultra-high bandwidth density in the Tb / s range. The 407 RF transmission lines integrate capacitors and inductors 200 to form a near-chip impedance matching and filtering network, which can achieve precise impedance matching, minimize signal reflection between the chip driver and the load, and ensure efficient signal power transmission.

[0062] In one embodiment, such as Figures 1-3 There are multiple electrical chips, and each electrical chip is symmetrically distributed with respect to the central axis of the optical chip 100. This ensures that the RF trace distances of different channels are consistent and effectively reduces the difference in local packaging stress. For fragile materials such as glass substrate 400, the use of symmetrical trace design also reduces the risk of breakage during manufacturing and cutting.

[0063] Preferably, such as Figures 1-3 The electrical chip includes a driver chip 300 and an amplifier chip 700. To minimize the distance between the optical chip 100 and the electrical chip, the driver chip 300 and the amplifier chip 700 are arranged in a front-to-back configuration (the driver chip 300 is located on the side of the amplifier chip 700 closer to the optical coupling element 800). Further, as... Figure 1 and Figure 3 There are multiple driver chips 300, which are symmetrically distributed with respect to the central axis of the optical chip 100; there are multiple amplifier chips 700, which are symmetrically distributed with respect to the central axis of the optical chip 100.

[0064] In one embodiment, such as Figure 5 The optical port 104 of the optical chip 100 extends beyond the edge of the glass substrate 400 and is end-face coupled to the optical coupling element 800. This method can effectively reduce insertion loss and avoid spatial interference between the optical coupling element 800 and the glass substrate 400. Accordingly, the distance between the pin and the optical port 104 must be considered when designing the optical chip 100.

[0065] Preferably, such as Figure 5 The optical coupling element 800 adopts an optical fiber array 801, which is fixed by bonding the upper cover plate 803 and the lower cover plate 802 of the element. The three form an entire element. After optical coupling is completed, the entire element can be fixed on the engine substrate 600 using optical precision adhesive 900.

[0066] Optionally, the optical chip 100 integrates the functions of both the receiver and the transmitter. The optical port array is arranged at the optical port 104 of the optical chip 100. The coupler mode design matches the single-mode fiber, and the fiber array 801 is used for simultaneous transmission and reception coupling.

[0067] In the aforementioned optical engine, power consumption mainly originates from electrical chips (such as driver chip 300 and amplifier chip 700). Below the electrical chips are the glass substrate 400 and the engine substrate 600, which have long heat dissipation paths and low thermal conductivity. Therefore, this embodiment adopts an upward heat dissipation design, specifically: as shown below... Figure 6 The light engine also includes a heat dissipation cover plate 110, which is located on the side of the electrical chip away from the glass substrate 400, and the gap between the heat dissipation cover plate 110 and the electrical chip is filled with thermally conductive adhesive 111.

[0068] The aforementioned heat dissipation cover 110 is made of a high thermal conductivity material such as tungsten copper; the top of the heat dissipation cover 110 can be connected to the housing of the light engine for heat dissipation.

[0069] Furthermore, the aforementioned heat dissipation cover 110 can be configured with a bracket to support it on the glass substrate 400. When the bracket is a ring-shaped bracket, it can enclose the electrical chip and even the optical chip 100, thereby further achieving the effect of dust prevention and chip protection. The bracket can be bonded and fixed to the glass substrate 400.

[0070] like Figures 7-9 The present invention also provides a method for manufacturing the above-mentioned light engine, comprising:

[0071] S1, fabricating glass substrate 400;

[0072] Preferably, such as Figure 7 First, a substrate core layer 401 is provided, and vertical interconnect vias 4011 are formed on the substrate core layer 401. Then, a first substrate augmentation layer 402 and a second substrate augmentation layer 403 are formed on both sides of the substrate core layer 401, respectively. The number of layers and residual copper ratio of the first substrate augmentation layer 402 and the second substrate augmentation layer 403 are symmetrically designed with respect to the substrate core layer 401. The number of circuit layers in the substrate augmentation layer is defined according to the circuit complexity. The RF transmission line 407 is designed according to the shortest path rule. The line width, thickness and dielectric layer thickness are defined according to impedance control and RF performance requirements. Then, UBM layers are formed on the surface of the first substrate augmentation layer 402 and the second substrate augmentation layer 403, respectively. After forming the UBM layers, a drought-proof layer is formed on the surface to protect the circuit from moisture corrosion.

[0073] S2, the optical chip 100 and the electrical chip are mounted on the first board to obtain a primary package;

[0074] Preferably, such as Figure 8 After the glass substrate 400 is fabricated, the electrical chips are first mounted on the first board surface. When capacitors and / or inductors are included, they can be mounted simultaneously. Then, the optical chip 100 is mounted. Generally, there are two types of bumps on the bottom of the optical chip 100: C2 bump and Au bump. C2 bump can be mounted together with the electrical chips. Attention should be paid to the risk of contamination of the optical port during soldering volatilization and flux cleaning. When soldering Au bump, care should be taken to ensure that the adhesive 503 filling the bottom of the electrical chip does not contaminate the pad area.

[0075] Furthermore, such as Figure 8 After the optoelectronic chip is mounted, the heat sink cover 110 is installed. A gap for thermal adhesive is left between the heat sink cover 110 and the driver chip 300 and amplifier chip 700. The size of the gap is determined based on a comprehensive evaluation of factors such as thermal simulation, the ideal thickness of the thermal adhesive, and controllable process tolerances. After applying thermal adhesive to the surface of the optoelectronic chip, a cover plate fixing adhesive 900 is applied to a designated area on the surface of the glass substrate 400. Both adhesives are then cured simultaneously by applying pressure and pressing them together.

[0076] S3, connect the primary package to the engine base plate 600;

[0077] Preferably, such as Figure 9 First, balls are placed on the second surface of the glass substrate 400, and then the glass substrate 400 and the engine substrate 600 are welded together. After welding, bottom filler glue can be used for bottom filling.

[0078] Optionally, the bottom of the engine substrate 600 can be electrically connected to the package substrate 130 via a BGA, LGA, PGA, or other packaging method, thereby electrically connecting to an external ASIC chip.

[0079] S4, complete the optical coupling between the optical coupling element 800 and the optical chip 100.

[0080] Preferably, such as Figure 9 After the encapsulation and soldering are completed, the module is powered on. For the transmitting end: after the optical chip 100 is powered on, it thermally modulates the micro-ring and couples the light input from the external light source through the optical coupling element 800 (fiber array 801), while simultaneously receiving the modulated output light. For the receiving end: after the optical chip 100 is powered on, it receives the input light and generates a photocurrent. The light from the external light source is input through the optical coupling element 800 (fiber array 801), and the magnitude of the photocurrent is fed back by the MPD on the chip for coupling and alignment.

[0081] After coupling, optical precision adhesive 900 is applied to the bottom of the optical coupling element 800, followed by dual curing using UV and heat. After curing, the final assembly of the light engine can be performed.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A micro-ring modulation optical engine based on glass substrate encapsulation, characterized in that, include: A glass substrate having a first surface and a second surface; An optical chip and an electrical chip are respectively mounted on the first board surface through a first connection structure, and the optical chip and the electrical chip are also electrically connected through an electrical interconnect structure formed in the glass substrate; the optical chip is a micro-ring modulation chip. The engine substrate is electrically connected to the second board surface through a second connection structure, thereby enabling the optical chip and the electrical chip to be electrically connected to an external circuit. An optical coupling element is optically coupled to the optical port of the optical chip.

2. The micro-ring modulation optical engine as described in claim 1, characterized in that: The glass substrate includes a substrate core layer, a first substrate augmentation layer and a second substrate augmentation layer formed on both sides of the substrate core layer, the outer surface of the first substrate augmentation layer being configured as the first plate surface, the outer surface of the second substrate augmentation layer being configured as the second plate surface, and the electrical interconnection structure being formed in the first substrate augmentation layer.

3. The micro-ring modulation optical engine as described in claim 2, characterized in that: Vertical interconnect vias are formed in the core layer of the substrate for the optical chip and the electrical chip respectively. One end of the vertical interconnect via is electrically connected to the first connection structure through an interconnect line formed in the first substrate layer, and the other end is electrically connected to the second connection structure through an interconnect line formed in the second substrate layer.

4. The micro-ring modulation optical engine as described in claim 2 or 3, characterized in that: Both the first substrate addition layer and the second substrate addition layer are multilayer structures, and the number of multilayers and the residual copper ratio of the two are symmetrically distributed relative to the substrate core layer.

5. The micro-ring modulation optical engine as described in any one of claims 1 to 3, characterized in that: The first connection structure is a bump interconnect structure, the second connection structure is a solder ball interconnect structure, and the size of the solder ball in the second connection structure is larger than the size of the bump in the first connection structure.

6. The micro-ring modulation optical engine as described in claim 1, characterized in that: The electrical interconnect structure includes radio frequency transmission lines fabricated in the glass substrate.

7. The micro-ring modulation optical engine as described in claim 1, characterized in that: There are multiple electrical chips, and each electrical chip is symmetrically distributed with respect to the central axis of the optical chip.

8. The micro-ring modulation optical engine as described in claim 1, characterized in that: The optical port of the optical chip extends beyond the edge of the glass substrate and is coupled to the optical coupling element at its end face.

9. The micro-ring modulation optical engine as described in claim 1, characterized in that: It also includes a heat dissipation cover plate, which is located on the side of the electrical chip away from the glass substrate, and the gap between the heat dissipation cover plate and the electrical chip is filled with thermally conductive adhesive.

10. The method for fabricating a micro-ring modulated optical engine as described in any one of claims 1 to 9, characterized in that, include: Fabrication of glass substrates; Optical chips and electrical chips are mounted on the first board surface to obtain a primary package. Connect the primary package to the engine base plate; The optical coupling element and the optical chip are optically coupled.

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