Processor synchronization system and electronic device
By inserting lightweight single opcode markers into processor instructions and utilizing hardware synchronization networks to achieve implicit responses, the problem of instruction cycle penalties and state access delays caused by explicit synchronization point insertion by the compiler is solved, thereby improving system determinism.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOFFETT AI TECHNOLOGY SHENZHEN CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-24
AI Technical Summary
In the design of multi-unit processor architectures with the same instruction set, the compiler needs to explicitly insert synchronization point marking instructions, which leads to instruction cycle penalties and off-chip state access, affecting system determinism.
Dependencies across execution engines are declared by inserting lightweight single opcode markers into instructions, and implicit responses are achieved using hardware synchronization networks, eliminating explicit state access operations and off-chip state access.
It significantly improves system determinism, realizes the transformation of the synchronization mechanism from explicit software scheduling to implicit hardware response, and reduces instruction cycle penalties and state access latency.
Smart Images
Figure CN122086639B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuits, and in particular to digital system design, multiprocessor synchronization systems, and especially to processor synchronization systems and electronic devices. Background Technology
[0002] In the design of multi-unit processor architecture with the same instruction set, the compiler still needs to explicitly insert synchronization point marking instructions in the code flow. The compiler must generate a sequence of synchronization instructions that includes complete logic such as state management, condition judgment and resource coordination. Summary of the Invention
[0003] This disclosure provides a processor synchronization system and an electronic device.
[0004] According to one aspect of this disclosure, a processor synchronization system is provided, comprising: a plurality of execution engines, each execution engine configured to execute an instruction stream, the instruction stream including a synchronization marker instruction, the synchronization marker instruction being a single opcode marker used to indicate dependencies across execution engines; a plurality of synchronization control modules corresponding one-to-one with the plurality of execution engines, each of the plurality of synchronization control modules being embedded in a corresponding execution engine, each synchronization control module being configured to generate a synchronization request signal or a synchronization event signal based on the current state of the corresponding execution engine in response to the execution engine corresponding to the synchronization control module executing the synchronization marker instruction; and an engine The inter-engine synchronization module is coupled to multiple execution engines to receive synchronization request signals and synchronization event signals generated by multiple synchronization control modules in the multiple execution engines. Based on the generated synchronization request signals and synchronization event signals, when a dependency is detected to be satisfied, a synchronization completion signal is returned to the corresponding execution engine. The synchronization request signal is used to instruct the execution engine that generated the synchronization request signal to request synchronization with at least one of the multiple execution engines. The synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, thereby releasing the synchronization requests of other execution engines that depend on the execution engine that generated the synchronization event signal.
[0005] In some embodiments, the synchronization flag instruction includes a first type of synchronization flag instruction and a second type of synchronization flag instruction. The first type of synchronization flag instruction is used to indicate that one of the multiple execution engines needs to request synchronization from at least one other execution engine among the multiple execution engines. The second type of synchronization flag instruction is used to indicate that one of the multiple execution engines needs to provide an event for synchronization to at least one other execution engine among the multiple execution engines. The synchronization control module is further configured to: generate a synchronization request signal in response to the first type of synchronization flag instruction; and generate a synchronization event signal in response to the second type of synchronization flag instruction.
[0006] In some embodiments, the inter-engine synchronization module includes an event and request processing unit, which includes: a request recording circuit configured to record multiple synchronization request signals initiated by execution engines that have not yet been satisfied, to form a request matrix; an event recording circuit configured to record multiple synchronization event signals initiated by execution engines that have not yet been responded to, to form an event matrix; and a matching circuit configured to perform a bitwise comparison between the transpose of the request matrix and the event matrix, and when the comparison result indicates that a matching synchronization request signal and a synchronization event signal exist, determine that the synchronization request signal is satisfied and generate a corresponding synchronization completion signal.
[0007] In some embodiments, the request matrix is an M×M matrix, where M is the number of execution engines, and the value of each element in the request matrix represents the number of incomplete synchronization requests between the execution engine represented by the corresponding row and the execution engine represented by the corresponding column; the event matrix is an M×M matrix, and the value of each element in the event matrix represents the number of unprocessed synchronization events provided by the execution engine represented by the corresponding row to the execution engine represented by the corresponding column.
[0008] In some embodiments, the event recording circuit is further configured to send a pause signal to the corresponding execution engine when the number of synchronization events corresponding to any of the plurality of execution engines exceeds a preset threshold, so as to pause the execution engine from sending synchronization event signals.
[0009] In some embodiments, the synchronization control module includes a state machine configured to switch between multiple states in response to the type of synchronization flag instruction and the internal state of the execution engine. These states include: an idle state, indicating that the execution engine corresponding to the synchronization control module has no instructions to execute; a running state, indicating that the execution engine corresponding to the synchronization control module is executing instructions normally; a waiting-for-interruption state, used to pause instruction execution after a synchronization request signal is issued, waiting for a synchronization completion signal; a self-synchronization pause state, used to pause instruction execution while executing a self-synchronization instruction, waiting for internal data writing to complete; and an event pause state, used to pause instruction execution when preparing to send a synchronization event signal but due to backpressure from the inter-engine synchronization module.
[0010] In some embodiments, the processor synchronization system further includes: one or more processors, each processor including multiple execution engines; and an inter-processor synchronization module coupled to the inter-engine synchronization modules of the multiple processors; wherein, the inter-engine synchronization module of any processor is configured to send a processor synchronization request signal to the inter-processor synchronization module after collecting synchronization requests from all execution engines within its processor, and to return a synchronization completion signal to the corresponding execution engine after receiving a processor synchronization completion signal returned by the inter-processor synchronization module.
[0011] According to another aspect of this disclosure, a processor synchronization method is provided. The processor includes multiple execution engines. The method includes: when any execution engine in the multiple execution engines executes a synchronization marker instruction during the execution of an instruction stream, generating a synchronization request signal or a synchronization event signal based on the current state of the execution engine, wherein the synchronization marker instruction is a single opcode marker used to indicate a dependency relationship across execution engines; sending the synchronization request signal or the synchronization event signal to an inter-engine synchronization module; the inter-engine synchronization module detecting whether the dependency relationship is satisfied based on the received synchronization request signal and the synchronization event signal; when the dependency relationship is detected to be satisfied, returning a synchronization completion signal to the corresponding execution engine so that the corresponding execution engine can continue to execute subsequent instructions, wherein the synchronization request signal is used to indicate that the execution engine that generated the synchronization request signal requests to synchronize with at least one of the multiple execution engines, and the synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, thereby releasing the synchronization requests of other execution engines that depend on the execution engine that generated the synchronization event signal.
[0012] According to another aspect of this disclosure, an electronic device is provided, including a processor synchronization system as described above.
[0013] According to one or more embodiments of this disclosure, by inserting lightweight single opcode markers into instructions to serve only as metadata carriers declaring cross-execution engine dependencies, not only are the instruction cycle penalties and all explicit state access operations of traditional synchronization eliminated, but the system determinism is also significantly improved by eliminating off-chip state access, providing key guarantees for real-time computing scenarios and realizing the transformation of the synchronization mechanism from software explicit scheduling to hardware implicit response.
[0014] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description
[0015] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.
[0016] Figure 1 This is a block diagram illustrating a processor synchronization system according to an exemplary embodiment.
[0017] Figure 2 This is a block diagram illustrating an inter-engine synchronization module of a processor synchronization system according to an exemplary embodiment.
[0018] Figure 3This is a schematic diagram illustrating a processor synchronization system according to an exemplary embodiment.
[0019] Figure 4 This is a schematic diagram illustrating the inter-engine synchronization module of a processor synchronization system according to an exemplary embodiment.
[0020] Figure 5 This is a schematic diagram illustrating the request matrix and event matrix of a processor synchronization system according to an exemplary embodiment.
[0021] Figure 6 This is a schematic diagram illustrating the circuit implementation of an event and request processing unit in a processor synchronization system according to an exemplary embodiment.
[0022] Figure 7 This is a schematic diagram illustrating the state machine of a processor synchronization system according to an exemplary embodiment.
[0023] Figure 8 This is a schematic diagram illustrating the workflow of an example processor synchronization system according to an exemplary embodiment.
[0024] Figure 9 This is a schematic diagram illustrating a specific synchronization control module of a processor synchronization system according to an exemplary embodiment.
[0025] Figure 10 This is a flowchart illustrating a processor synchronization method according to an exemplary embodiment. Detailed Implementation
[0026] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0027] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.
[0028] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.
[0029] In the design of multi-unit processor architectures with the same instruction set, the traditional approach requires the compiler to generate a sequence of synchronization instructions that includes complete logic such as state management, conditional judgment, and resource coordination. In traditional architectures, the compiler is forced to generate dozens of instructions for each synchronization point, including explicit state storage, polling loops, and lock release operations. These instructions not only consume up to 30% of instruction cycles, but also introduce difficult-to-debug latency problems due to storing state data in off-chip memory.
[0030] The embodiments of this disclosure provide a processor synchronization system that, by inserting lightweight single opcode markers into instructions to serve only as metadata carriers declaring cross-execution engine dependencies, not only eliminates the instruction cycle penalty and all explicit state access operations of traditional synchronization, but also significantly improves system determinism by eliminating off-chip state access, providing key guarantees for real-time computing scenarios and realizing the transformation of the synchronization mechanism from software explicit scheduling to hardware implicit response.
[0031] Figure 1 This is a block diagram illustrating a processor synchronization system 100 according to an exemplary embodiment.
[0032] like Figure 1As shown, this disclosure proposes a processor synchronization system 100, including: a plurality of execution engines 110, each execution engine being configured to execute an instruction stream, the instruction stream containing a synchronization marker instruction, the synchronization marker instruction being a single opcode marker used to indicate dependencies across execution engines; a plurality of synchronization control modules 112 corresponding one-to-one with the plurality of execution engines 110, each synchronization control module being embedded in its corresponding execution engine, each synchronization control module being configured to generate a synchronization request signal or a synchronization event signal based on the current state of the corresponding execution engine in response to the execution engine corresponding to the synchronization control module executing the synchronization marker instruction; and an inter-engine synchronization module. 120, the inter-engine synchronization module 120 is coupled to multiple execution engines 110 to receive synchronization request signals and synchronization event signals generated by multiple synchronization control modules 112 among the multiple execution engines 110, and based on the generated synchronization request signals and synchronization event signals, when a dependency is detected to be satisfied, returns a synchronization completion signal to the corresponding execution engine, wherein the synchronization request signal is used to indicate that the execution engine that generated the synchronization request signal requests to synchronize with at least one of the multiple execution engines, and the synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, so as to release the synchronization requests of other execution engines that depend on the execution engine that generated the synchronization event signal.
[0033] In the example, single opcode markers are used only to declare cross-execution engine dependencies and do not include any synchronization implementation code. When the program execution flow reaches these single opcode markers, the hardware synchronization network will be automatically activated.
[0034] Therefore, by inserting lightweight single opcode markers into instructions to serve only as metadata carriers declaring dependencies across execution engines, not only are the instruction cycle penalties and all explicit state access operations of traditional synchronization eliminated, but the system determinism is also significantly improved by eliminating off-chip state access, providing key guarantees for real-time computing scenarios and realizing the transformation of the synchronization mechanism from explicit software scheduling to implicit hardware response.
[0035] In the example, command dispatch and scheduling within each execution engine can be accomplished by an Rvv (RISC-V Vector Extension).
[0036] In the example, a single opcode flag can include opcode sync and opcode condition, where sync can include 2 bits and condition can include M bits, where M is the number of corresponding execution engines.
[0037] In some embodiments, the synchronization flag instruction includes a first type of synchronization flag instruction and a second type of synchronization flag instruction. The first type of synchronization flag instruction is used to indicate that one of the multiple execution engines needs to request synchronization from at least one other execution engine among the multiple execution engines. The second type of synchronization flag instruction is used to indicate that one of the multiple execution engines needs to provide an event for synchronization to at least one other execution engine among the multiple execution engines. The synchronization control module is further configured to: generate a synchronization request signal in response to the first type of synchronization flag instruction; and generate a synchronization event signal in response to the second type of synchronization flag instruction.
[0038] In the example, `sync` can include the following opcodes: 2'b00, representing an engine synchronization event (which can be represented as an Engine Sync Event or SYNC EVENT); 2'b01, representing an engine synchronization request (which can be represented as an Engine Sync Request or SYNC REQUEST); 2'b10, representing a processor synchronization request (which can be represented as a PE Sync Request or SYNCPE); and 2'b11, representing a synchronization event notification RVV (which can be represented as a Sync Event notify RVV or SYNCRVV). Additionally, `condition` is used to indicate the corresponding engine required for the synchronization request signal and the synchronization event signal. For example, Bit 0 indicates whether engine 0 needs to be executed, and Bit M-1 indicates whether engine M-1 needs to be executed. Alternatively, Bit 0 being 0 indicates that engine 0 needs to be executed, and Bit 0 being 1 indicates that engine 0 does not need to be executed.
[0039] Specifically, when sync == 2'b01 and condition == 0, it means that the execution engine needs to synchronize itself (which can be represented as SYNC SELF STALL), and needs to ensure that all data before this instruction is written to the processor's shared cache; when sync == 2'b01 and condition != 0, it means that the execution engine needs to synchronize with the execution engine corresponding to condition. This execution engine will wait until all the corresponding execution engines provide events and the inter-engine synchronization module 120 returns a synchronization completion signal (done) indicating that synchronization is complete before executing the subsequent instructions; when sync == 2'b00 and condition != 0, it means that the synchronization event (sync) (event) The execution engine needs to provide an event to the execution engine corresponding to the condition to release the synchronization request of the corresponding execution engine; when sync==2'b11, it means that the execution engine needs to notify Rvv, and no condition needs to be set; when sync==2'b10, it means that the processor requests to synchronize with other processors. All execution engines in the processor send synchronization requests to the inter-engine synchronization module 120. After the inter-engine synchronization module 120 collects them, it reports to the inter-processor synchronization module. Execution stops before the upper-level inter-processor synchronization module returns that synchronization is complete, and no condition needs to be set.
[0040] Figure 2 This is a block diagram illustrating the inter-engine synchronization module 120 of a processor synchronization system 100 according to an exemplary embodiment.
[0041] refer to Figure 2 In some embodiments, the inter-engine synchronization module 120 includes an event and request processing unit 121, which includes: a request recording circuit 122 configured to record multiple synchronization request signals initiated by execution engines that have not yet been satisfied, to form a request matrix; an event recording circuit 123 configured to record multiple synchronization event signals initiated by execution engines that have not yet been responded to, to form an event matrix; and a matching circuit 124 configured to perform a bitwise comparison between the transpose of the request matrix and the event matrix, and when the comparison result indicates that there is a matching synchronization request signal and a synchronization event signal, determine that the synchronization request signal is satisfied and generate a corresponding synchronization completion signal.
[0042] Therefore, by directly connecting the condition detection circuit to the execution unit, the synchronization state is eliminated in the transistor-level signal transmission, completely avoiding instruction execution overhead. The preset conditions associated with the flag are monitored in real time by a dedicated combinational logic circuit. Once the condition is detected to be met, a zero-cycle delay synchronization release mechanism is immediately triggered through the hardware signal path. The entire process is completely independent of the processor instruction pipeline, realizing the transformation of the synchronization mechanism from explicit software scheduling to implicit hardware response.
[0043] In some embodiments, the processor synchronization system 100 further includes: one or more processors, each processor including multiple execution engines; and an inter-processor synchronization module coupled to the inter-engine synchronization modules of the multiple processors; wherein, the inter-engine synchronization module of any processor is configured to send a processor synchronization request to the inter-processor synchronization module after collecting synchronization requests from all execution engines within its processor, and to return a synchronization completion signal to the corresponding execution engine after receiving a processor synchronization completion signal returned by the inter-processor synchronization module.
[0044] Figure 3 This is a schematic diagram illustrating a processor synchronization system 100 according to an exemplary embodiment.
[0045] refer to Figure 3 The processor synchronization system 100 may include an inter-processor synchronization module 301, a first processor 310, a second processor 320, and a third processor 330, etc., and the specific number of processors is not limited. The first processor 310 may include a first inter-engine synchronization module 311, a first instruction dispatch and scheduling unit 312, a first execution engine 313, a second execution engine 314, and a third execution engine 315, etc., and the specific number of execution engines is not limited. Similarly, the second processor 320 may include a second inter-engine synchronization module 321, a second instruction dispatch and scheduling unit 322, a fourth execution engine 323, a fifth execution engine 324, and a sixth execution engine 325, etc., and the third processor 330 may include a third inter-engine synchronization module 331, a third instruction dispatch and scheduling unit 332, a seventh execution engine 333, an eighth execution engine 334, and a ninth execution engine 335, etc.
[0046] In the example, execution engines 313-315, 323-325, or 333-335 are configured to execute instruction streams issued by corresponding instruction distribution and scheduling units 312, 322, or 332; inter-engine synchronization modules 311, 321, or 331 are coupled to the corresponding execution engines 313-315, 323-325, or 333-335 to receive synchronization request signals and / or synchronization event signals generated by multiple synchronization control modules in multiple execution engines 313-315, 323-325, or 333-335, and return synchronization completion signals to the corresponding execution engines 313-315, 323-325, or 333-335 based on the generated synchronization request signals and / or synchronization event signals.
[0047] In the example, the inter-engine synchronization modules 311, 321, or 331 of any processor 310, 320, or 330 are configured to send a processor synchronization request to the inter-processor synchronization module 301 after collecting synchronization requests from all execution engines 313-315, 323-325, or 333-335 within its processor, and then return a synchronization completion signal to the corresponding execution engine after receiving a processor synchronization completion signal from the inter-processor synchronization module 301.
[0048] In the example, the first instruction dispatch and scheduling unit 312, the second instruction dispatch and scheduling unit 322, or the third instruction dispatch and scheduling unit 332 can be Rvv, used to dispatch and schedule instructions to various execution engines.
[0049] In the example, if any execution engine does not respond for a long time (or if a row in the request matrix does not respond for a long time), the corresponding inter-engine synchronization module 311, 321 or 331 sends a timeout signal to the corresponding instruction distribution and scheduling unit 312, 322 or 332.
[0050] Figure 4 This is a schematic diagram illustrating the inter-engine synchronization module 311 of the processor synchronization system 100 according to an exemplary embodiment.
[0051] refer to Figure 4 The inter-engine synchronization module 311 may include an event and request processing unit 410 and a processor synchronization unit 420.
[0052] In the example, the event and request processing unit 410 is used to implement synchronization between engines, while the processor synchronization unit 420 is used to implement synchronization between processors.
[0053] In the example, the processor synchronization unit 420 maintains an M-bit vector, which is set to 1 when it receives the processor synchronization request signal 1 from the corresponding execution engine; when all bits are 1 (representing that all synchronization requests inside the processor have been collected), it generates a processor synchronization request signal to the upper-level inter-processor synchronization module 301 and waits until it returns a processor synchronization completion signal indicating successful synchronization before generating a synchronization completion signal and sending it to each execution engine to achieve synchronization between processors.
[0054] Figure 5 This is a schematic diagram illustrating the request matrix 510 and event matrix 520 of a processor synchronization system 100 according to an exemplary embodiment.
[0055] In the example, the event and request processing unit 410 may include a request recording circuit configured to record multiple synchronization request signals initiated by the execution engines that have not yet been satisfied, to form a request matrix 510; and an event recording circuit configured to record multiple synchronization event signals initiated by the execution engines that have not yet been responded to, to form an event matrix 520.
[0056] In some embodiments, the request matrix is an M×M matrix, where M is the number of execution engines, and the value of each element in the request matrix represents the number of incomplete synchronization requests between the execution engine represented by the corresponding row and the execution engine represented by the corresponding column; the event matrix is an M×M matrix, and the value of each element in the event matrix represents the number of unprocessed synchronization events provided by the execution engine represented by the corresponding row to the execution engine represented by the corresponding column.
[0057] refer to Figure 5 The working principle of the event and request processing unit 410 is explained below: The event and request processing unit 410 generates a request matrix through the request recording circuit based on the synchronization request signals generated by multiple execution engines. The value of each element in the request matrix can represent the number of times the request from the execution engine represented by the corresponding row and the synchronization of the execution engine represented by the corresponding column have not been completed.
[0058] For example, in request matrix 510, the synchronization request source (the execution engine that issues the synchronization request signal) may include engines 0-4 (i.e., M is 5), where the first row represents the synchronization request signal from engine 0, and the fourth column of the first row is 1, indicating that engine 0 is waiting for engine 3 to provide an event.
[0059] The event and request processing unit 410 generates an event matrix through the event recording circuit based on the synchronous event signals generated by multiple execution engines. The value of each element in the event matrix can represent the number of unprocessed synchronous events provided by the execution engine represented by the corresponding row to the execution engine represented by the corresponding column.
[0060] For example, in event matrix 520, the synchronous event source (the execution engine that issues the synchronous event signal) can include engines 0-4 (i.e., M is 5), where the fourth row represents the synchronous event signal from engine 3, and the first column of the fourth row is 1, indicating that engine 3 needs to provide an event to engine 0.
[0061] The event and request processing unit 410 also includes a matching circuit 124. The matching circuit 124 is configured to perform a bitwise comparison between the request matrix and the transpose of the event matrix, and when the comparison result indicates that a matching synchronization request signal and a synchronization event signal exist, determine that the synchronization request signal is satisfied and generate a corresponding synchronization completion signal.
[0062] For example, in the transpose 530 of request matrix 510 and event matrix 520, the transposes of the request matrix and event matrix are compared positionally (e.g., using an AND gate). If the corresponding position results are consistent, it indicates that the corresponding execution engines are the same (e.g., Figure 5 If engine 0 and engine 3 in the code successfully synchronize, the numbers at both positions are decremented by one, and a synchronization completion signal is returned to the two execution engines that requested synchronization (e.g., ...). Figure 5 In the example of Engine 0 and Engine 3, a 1 in the row indicates that the synchronization request for the corresponding engine has been released, and a 1 in the column indicates that the synchronization event for the corresponding engine has been completed. In this case, the synchronization request for Engine 0 has been released, and the synchronization event for Engine 3 has been completed.
[0063] Figure 6 This is a schematic diagram illustrating the circuit implementation of the event and request processing unit 121 of a processor synchronization system according to an exemplary embodiment.
[0064] In some examples, since subsequent instructions will not be executed after an execution engine requests synchronization with other execution engines, the synchronization request condition (sync reqcondition) provided to each execution engine can be based on the request matrix generated by the request recording circuit. The event matrix generated by the event recording circuit includes an event counter (which can be abbreviated as event cnt) corresponding to each execution engine.
[0065] When the corresponding execution engine provides events ( Figure 6 The event condition is entered into the counter. When src 0 indicates that it comes from execution engine 0, the event counter is incremented by 1. When the corresponding sync reqcondition bit is 1 and the corresponding event counter event cnt is not 0, it means that the bit is successfully synchronized. If every bit of the sync reqcondition of the execution engine is successfully synchronized, the execution engine is successfully synchronized, returns the corresponding synchronization completion signal to the execution engine, and decrements the corresponding event counter by 1.
[0066] In the example, the event logging circuit is also configured to send a pause signal (event fullflag, also known as a backpressure signal) to the corresponding execution engine when the number of synchronous events corresponding to any of the multiple execution engines exceeds a preset threshold, so as to pause the execution engine from sending synchronous event signals.
[0067] Figure 7 This is a schematic diagram illustrating the state machine 700 of a processor synchronization system 100 according to an exemplary embodiment.
[0068] refer to Figure 7According to some embodiments, the synchronization control module 112 includes a state machine 700, which is configured to switch between multiple states in response to the type of synchronization flag instruction and the internal state of the execution engine. The multiple states include: an idle state 710, indicating that the execution engine corresponding to the synchronization control module 112 has no instructions to execute; a running state 720, indicating that the execution engine corresponding to the synchronization control module 112 is executing instructions normally; a waiting interrupt state 730, used to suspend instruction execution after issuing a synchronization request signal and wait for a synchronization completion signal; a self-synchronization pause state 740, used to suspend instruction execution when executing a self-synchronization instruction and wait for internal data writing to be completed; and an event pause state 750, used to suspend instruction execution when preparing to send a synchronization event signal but due to back pressure from the inter-engine synchronization module 120.
[0069] In some embodiments, when the state machine is in a waiting interrupt state 730, a self-synchronization pause state 740, or an event pause state 750, it pulls the instruction fetch pause signal o_cmd_fifo_stall high to pause instruction fetching of the execution engine 903 corresponding to the synchronization control module 112.
[0070] exist Figure 7 In this context, "buffer empty" indicates that the instruction cache (cmd FIFO) within the execution engine is empty, and "glb doneresponse" is the response from the processor's internal shared memory. "Event FIFO full" is a pause signal, indicating that there are bits in the event matrix within the current execution engine that cannot be received due to a full counter. The instruction fetch pause signal "o_cmd_fifo_stall" is a control signal output from the synchronization control module to the instruction cache (cmd FIFO) of the execution engine, used to control the instruction fetch behavior of the execution engine.
[0071] In the example, the execution engine is in idle state (IDLE) 710, indicating that there are currently no instructions to execute. In this state, the output is that the instruction fetch pause signal o_cmd_fifo_stall is not high, and the execution engine pauses instruction fetching automatically because cmd fifo is empty; when the input instruction is SYNC RVV, an empty write signal is sent to the global buffer (GLB) 912; when the input instruction is the synchronization event SYNC_EVENT, an empty write signal is sent to the global buffer 912. The idle state update includes: maintaining the state when a reset signal is received, or when the last-level instruction cache cmd FIFO of the execution engine is empty; entering the running state 720 when the current instruction is not a synchronization instruction SYNC or SYNC RVV; entering the waiting interrupt state 730 when the current instruction is a synchronization request SYNC REQUEST and condition != 0 (the execution engine needs to synchronize with other execution engines), or when the processor synchronizes SYNC PE (the execution engine needs to initiate processor synchronization), waiting for the engine synchronization module 120 to inform that the synchronization is complete; entering the self-synchronization pause state 740 when the current instruction is a synchronization request SYNC REQUEST and condition == 0 (the execution engine needs to synchronize with itself), waiting for all its data to be written to the global cache 912; entering the event pause state 750 when the current instruction is a synchronization event SYNC EVENT and the corresponding event flag event flag is high (Event FIFO full), and preparing to provide event information to the engine synchronization module 120.
[0072] In the example, the execution engine is in RUN state 720, indicating that the execution engine is in normal operation. At this time, the output o_cmd_fifo_stall is pulled low, allowing the execution engine to fetch instructions; when the input is SYNC RVV, a null write signal is sent to global buffer 912; when the input is the SYNC EVENT synchronization event, a null write signal is sent to global buffer 912. The status updates of running state 720 include: maintaining running state 720 when the current instruction is not a SYNC instruction, SYNC RVV, or a SYNC EVENT and the corresponding event flag is low; entering IDLE 710 when the last-level cmd FIFO of the execution engine is empty; entering interrupt waiting state 730 when the current instruction is a SYNC REQUEST and condition != 0 (the execution engine needs to synchronize with other execution engines), or when the instruction is a SYNC PE (the execution engine needs to initiate processor synchronization), waiting for the engine synchronization module 120 to notify that the synchronization is complete; entering self-synchronization pause state 740 when the current instruction is a SYNC REQUEST and condition == 0 (the execution engine needs to synchronize with itself), waiting for all data of the execution engine to be written to the global cache 912; entering event pause state 750 when the current instruction is a SYNC EVENT and the corresponding event flag is high (Event FIFO full), and preparing to provide event information to the engine synchronization module 120.
[0073] In the example, the execution engine is in the Waiting for Interrupt (WFI) state 730, indicating that the execution engine has stopped fetching and decoding, waiting for the inter-engine synchronization module 120 to notify it that synchronization is complete (i.e., a synchronization completion signal). At this time, the output o_cmd_fifo_stall is pulled high, pausing the execution engine's instruction fetching; when requesting synchronization with other execution engines, it sends the signal o_engine_sync_request (the target execution engine for which synchronization is requested) and the signal o_engine_sync_request_valid (valid signal); when requesting synchronization with the processor, it sends the signal o_pe_sync_request_valid (valid signal). The state updates of the Waiting for Interrupt state 730 include: when receiving the synchronization completion signal (Sync Done) returned by the inter-engine synchronization module 120 and the execution engine's instruction cache is not empty (~buffer empty), it enters the running state 720; when receiving the synchronization completion signal returned by the inter-engine synchronization module 120 and the execution engine's instruction cache is empty (buffer empty), it enters the idle state 710; when no synchronization completion signal (~Sync Done) is received, it remains in the Waiting for Interrupt state 730.
[0074] In the example, the execution engine is in a self-synchronizing paused state (SYNC_SELF_STALL) 740, indicating that the execution engine needs to pause to synchronize with itself, waiting for all its internal data to be written to the Global Buffer (GLB) 912 (sending a doone signal to the GLB for empty writes, and then receiving a doone response signal from the GLB). In this state, output may include pulling o_cmd_fifo_stall high to pause instruction fetching; and sending a doone request for empty writes to the GLB. The state update of the self-synchronizing paused state 740 may include: when receiving the doone response signal (glb doneresponse) from the GLB, if the execution engine's instruction cache is not empty (~buffer empty), it enters the running state 720; if it is empty (buffer empty), it enters the idle state 710; if no doone response signal (~glb doneresponse) is received, the self-synchronizing paused state 740 is maintained.
[0075] In the example, the execution engine is in the event-paused state (EVENT_STALL) 750, indicating that the execution engine is paused because the counter of the inter-engine synchronization module 120 is full. It is preparing to send a synchronization event to the inter-engine synchronization module 120, requiring that all internal data has been written to the GLB at this time (sending a completed write signal "done" to the GLB, and then receiving a completed response signal "done rsp" from the GLB). In this state, the output can be o_cmd_fifo_stall pulled high to pause the execution engine's instruction fetching. The update of the event pause state 750 can include entering the running state 720 when the event FIFO buffer of the inter-engine synchronization module 120 is not full (~Event FIFO full), indicating that the inter-engine synchronization module 120 can receive, and the instruction buffer of the execution engine is not empty (~buffer empty); and entering the idle state 710 when the event FIFO of the inter-engine synchronization module 120 is full (Event FIFO full), indicating that the inter-engine synchronization module 120 cannot receive, and maintaining the event pause state 750.
[0076] Figure 8 This is a schematic diagram illustrating the workflow of an example of a processor synchronization system 100 according to an exemplary embodiment.
[0077] refer to Figure 8 Taking the synchronization of two execution engines within the processor as an example, the specific synchronization process includes the following steps: In step 801, Rvv, as an example instruction distribution and scheduling unit, sends instructions to execution engine 0 and execution engine 1. Execution engine 0 receives a task set including the Sync0 event instruction, which indicates that execution engine 0 has completed execution. Execution engine 1 receives a task set including the Sync 1 SyncBit_Engine0 instruction, which indicates that the execution of execution engine 1 depends on the completion status of execution engine 0. In step 802, execution engine 0 begins to execute the received instructions and enters Run state 720; In step 803, execution engine 1 begins to execute the received instructions and enters Run state 720; In step 804, it is determined whether execution engine 0 has executed the Sync0 event instruction, indicating that its task has been completed. If so, proceed to step 806; otherwise, return to step 802. In step 805, it is determined whether execution engine 1 has executed the Sync 1 SyncBit_Engine0 instruction. This instruction indicates that execution engine 1 depends on execution engine 0 to complete its execution. If so, proceed to step 807; otherwise, return to step 803. In step 806, execution engine 0 sends a synchronization event signal to inter-engine synchronization module 120, which is used to notify inter-engine synchronization module 120 that execution engine 0 has completed task execution; In step 807, execution engine 1 sends a synchronization request signal to inter-engine synchronization module 120 to request synchronization with execution engine 0; In step 808, after receiving the synchronization event signal sent by execution engine 0, the inter-engine synchronization module 120 records the execution completion status of execution engine 0; In step 809, after sending the synchronization request, execution engine 1 enters the interrupt waiting state 730, suspends the execution of subsequent instructions, and waits for the response from the inter-engine synchronization module 120; In step 810, when the inter-engine synchronization module 120 receives the synchronization event signal sent by the execution engine 1, it determines whether the execution completion event of the execution engine 0 exists. If the event of the execution engine 0 exists, it means that the execution engine 0 has completed execution and proceeds to step 812; otherwise, it proceeds to step 811. In step 811, the inter-engine synchronization module 120 waits for the synchronization event signal sent by the execution engine 0; In step 812, the inter-engine synchronization module 120 sends a synchronization complete signal (Sync Done) to the execution engine 0, notifying the execution engine 1 that it can continue to perform subsequent operations; In step 813, after engine 1 receives the Sync Done signal sent by the inter-engine synchronization module 120, it ends the WFI state 730, enters the Run state 720, and continues to execute subsequent instructions; and In step 814, after transmitting the Sync Done signal, the inter-engine synchronization module 120 will clear the event record of the executing engine 0 in order to process subsequent synchronization requests.
[0078] Figure 9 This is a schematic diagram illustrating the synchronization control module 112 of the processor synchronization system 100 according to an exemplary embodiment.
[0079] refer to Figure 9 The synchronization control module 112 is embedded in the execution engine 903. The execution engine 903 may include a command buffer (CMD Buffer) 906 for fetching instructions (IF), a first first-in-first-out memory (FIFO) 907 for receiving instruction first-in-first-out stop instructions and sending decode instructions, a decoder 908 and (multiple) IP cores 909 for decoding instructions (ID) and executing instructions (EXCUTE), an interrupt generator 904 for sending instruction distribution and scheduling synchronization signals to the instruction distribution and scheduling unit 901 (e.g., it may be Rvv), and FIFOs for writing channels 0 to N (only the second FIFO 910 and the third FIFO 911 are shown in the figure).
[0080] The specific control flow of the synchronization control module 112 is as follows: The execution engine 903 transmits the latest fetched instruction and the empty signal of the instruction cache to the synchronization control module 112. When the synchronization control module 112 generates an empty write request for the global buffer (GLB) 912 due to an instruction (e.g., SYNC EVENT, SYNC SELF STALL, and SYNC RVV), it generates corresponding information to insert into the decoding instruction and execution (ID&EXECUTE) stage of the execution engine 903, and executes it down the pipeline with the execution engine 903. The number of flags sent to the GLB port corresponds to the number of write paths. When all corresponding GLB ports return a write success signal (write response), the synchronization control module 112 returns an instruction distribution and scheduling synchronization signal to the RVV interrupt, or a synchronization event signal to the inter-engine synchronization module 120, or a self-synchronization signal to the synchronization control module 112 to indicate a jump state.
[0081] It should be understood that, Figures 3 to 9 These are all for illustrative purposes, not for limiting purposes. For example, the structure of the processor synchronization system 100 may not be... Figure 3 and Figure 4 The structure of the example in the text.
[0082] Figure 10 This is a flowchart illustrating a processor synchronization method according to an exemplary embodiment.
[0083] refer to Figure 10 The processor synchronization method 1000 may include the following steps: S1002, when a synchronization flag instruction is executed during the instruction stream execution process of any of the multiple execution engines, a synchronization request signal or a synchronization event signal is generated according to the current state of the execution engine, wherein the synchronization flag instruction is a single opcode flag used to indicate a dependency relationship across execution engines; S1004, the synchronization request signal or the synchronization event signal is sent to the inter-engine synchronization module; S1006, the inter-engine synchronization module detects whether the dependency relationship is satisfied based on the received synchronization request signal and the synchronization event signal; and S1008, when the dependency relationship is detected to be satisfied, a synchronization completion signal is returned to the corresponding execution engine so that the corresponding execution engine can continue to execute subsequent instructions, wherein the synchronization request signal is used to indicate that the execution engine that generated the synchronization request signal requests to synchronize with at least one of the multiple execution engines, and the synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, so as to release the synchronization requests of other execution engines that depend on the execution engine that generated the synchronization event signal.
[0084] The aforementioned processor synchronization method 1000 operation can be combined with Figure 1 The operation of the processor synchronization system 100 is the same, so details of its various aspects will not be repeated here.
[0085] According to one aspect of this disclosure, an electronic device is also provided, including the processor synchronization system of any of the embodiments described above.
[0086] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.
[0087] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.
[0088] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.
[0089] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).
[0090] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.
[0091] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.
[0092] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.
[0093] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.
Claims
1. A processor synchronization system, characterized in that, The processor synchronization system includes: Multiple execution engines, each configured to execute an instruction stream, the instruction stream containing synchronization marker instructions, the synchronization marker instructions being single opcode markers used to indicate dependencies across execution engines; Multiple synchronization control modules, each corresponding to one of the plurality of execution engines, are embedded within their respective execution engines. Each synchronization control module is configured to generate a synchronization request signal or a synchronization event signal based on the current state of the corresponding execution engine in response to the execution engine executing the synchronization flag instruction. An inter-engine synchronization module, coupled to the plurality of execution engines, receives synchronization request signals and synchronization event signals generated by the plurality of synchronization control modules in the plurality of execution engines. Based on the generated synchronization request signals and synchronization event signals, when the dependency relationship is detected to be satisfied, it returns a synchronization completion signal to the corresponding execution engine. The synchronization request signal is used to instruct the execution engine that generated the synchronization request signal to request synchronization with at least one of the plurality of execution engines. The synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, thereby releasing synchronization requests from other execution engines that depend on the execution engine that generated the synchronization event signal. The synchronization flag instruction includes a first type of synchronization flag instruction and a second type of synchronization flag instruction. The first type of synchronization flag instruction is used to indicate that one of the plurality of execution engines needs to request synchronization from at least one of the plurality of execution engines. The second type of synchronization flag instruction is used to indicate that one of the plurality of execution engines needs to provide an event for synchronization to at least one of the plurality of execution engines. The synchronization control module is further configured to: In response to the first type of synchronization flag instruction, the synchronization request signal is generated; and The synchronization event signal is generated in response to the second type of synchronization flag instruction.
2. The system according to claim 1, characterized in that, The inter-engine synchronization module includes an event and request processing unit, which includes: The request recording circuit is configured to record the synchronization request signals initiated by the plurality of execution engines that have not yet been satisfied, in order to form a request matrix; An event logging circuit is used to record synchronous event signals initiated by the multiple execution engines that have not yet been responded to, in order to form an event matrix; and, The matching circuit is configured to perform a bitwise comparison between the request matrix and the transpose of the event matrix, and when the comparison result indicates that a matching synchronization request signal and a synchronization event signal exist, determine that the synchronization request signal is satisfied and generate a corresponding synchronization completion signal.
3. The system according to claim 2, characterized in that, The request matrix is an M×M matrix, where M is the number of the plurality of execution engines. The value of each element in the request matrix represents the number of times the execution engine in the corresponding row requests synchronization with the execution engine in the corresponding column. The event matrix is an M×M matrix, where the value of each element in the event matrix represents the number of unprocessed synchronization events provided by the execution engine in the corresponding row to the execution engine in the corresponding column.
4. The system according to claim 2, characterized in that, The event recording circuit is further configured to send a pause signal to the corresponding execution engine when the number of synchronization events corresponding to any of the plurality of execution engines exceeds a preset threshold, so as to pause the execution engine from sending synchronization event signals.
5. The system according to any one of claims 1 to 4, characterized in that, The synchronization control module includes a state machine configured to switch between multiple states in response to the type of the synchronization flag instruction and the internal state of the execution engine, the multiple states including: The idle state indicates that the execution engine corresponding to the synchronization control module has no instructions to execute; The running status indicates that the execution engine corresponding to the synchronization control module is executing instructions normally; The waiting interruption state is used to pause instruction execution after the synchronization request signal is issued, and wait for the synchronization completion signal; The self-synchronization pause state is used to pause instruction execution during the execution of self-synchronization instructions, waiting for internal data to be written completely; and... The event pause state is used to pause instruction execution when the synchronization event signal is about to be sent but is paused due to back pressure from the inter-engine synchronization module.
6. The system according to claim 5, characterized in that, The state machine, in the waiting interrupt state, the self-synchronization pause state, or the event pause state, pulls high the instruction fetch pause signal to pause instruction fetching of the execution engine corresponding to the synchronization control module.
7. The system according to claim 6, characterized in that, Also includes: One or more processors, each processor including the plurality of execution engines; as well as, Inter-processor synchronization module, coupled to an inter-engine synchronization module for multiple processors; In this configuration, the inter-engine synchronization module of any processor is configured to send a processor synchronization request signal to the inter-processor synchronization module after collecting synchronization requests from all execution engines within its processor, and to return a synchronization completion signal to the corresponding execution engine after receiving a processor synchronization completion signal from the inter-processor synchronization module.
8. A processor synchronization method, characterized in that, The processor includes multiple execution engines, and the method includes: When a synchronization flag instruction is executed during the execution of the instruction stream in any of the plurality of execution engines, a synchronization request signal or a synchronization event signal is generated according to the current state of the execution engine. The synchronization flag instruction is a single opcode flag used to indicate dependencies across execution engines. Send the synchronization request signal or synchronization event signal to the inter-engine synchronization module; The inter-engine synchronization module detects whether the dependency relationship is satisfied based on the received synchronization request signal and synchronization event signal; and When the dependency is detected to be satisfied, a synchronization completion signal is returned to the corresponding execution engine, so that the corresponding execution engine can continue to execute subsequent instructions. The synchronization request signal is used to instruct the execution engine that generated the synchronization request signal to request synchronization with at least one of the plurality of execution engines. The synchronization event signal is used to indicate that the execution engine that generated the synchronization event signal has completed execution, thereby releasing synchronization requests from other execution engines that depend on the execution engine that generated the synchronization event signal. The synchronization flag instruction includes a first type of synchronization flag instruction and a second type of synchronization flag instruction. The first type of synchronization flag instruction is used to indicate that one of the plurality of execution engines needs to request synchronization from at least one of the plurality of execution engines. The second type of synchronization flag instruction is used to indicate that one of the plurality of execution engines needs to provide an event for synchronization to at least one of the plurality of execution engines. In response to the execution engine corresponding to the synchronization control module executing the synchronization flag instruction, generating the synchronization request signal or the synchronization event signal according to the current state of the corresponding execution engine further includes: In response to the first type of synchronization flag instruction, the synchronization request signal is generated; and The synchronization event signal is generated in response to the second type of synchronization flag instruction.
9. An electronic device, characterized in that, Includes the processor synchronization system according to any one of claims 1 to 7.