Shift register, gate drive circuit, array substrate and display device

Abstract

This disclosure provides a shift register, a gate driving circuit, an array substrate, and a display device, relating to the field of display technology, to improve the stability of the output waveform of the shift register. The shift register includes a first input circuit, a second input circuit, a first output circuit, and an output control circuit. Under the control of a first clock signal terminal, the first input circuit transmits an input signal from a signal input terminal to a first node. Under the control of a voltage at a third node, the second input circuit transmits a signal from a second clock signal terminal to a second node. The first output circuit transmits a signal from the second clock signal terminal to a signal output terminal, and also transmits a signal from a first voltage signal terminal to a signal output terminal. Under the control of a control signal terminal, the output control circuit transmits a second voltage signal from the second voltage signal terminal to the second node or the signal output terminal. This application is used for image display.

Description

[0001] This application is a divisional application of the patent application filed on August 1, 2023, with application number 202310961260.4, entitled "Shift Register, Gate Drive Circuit, Array Substrate and Display Device". Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, an array substrate, and a display device. Background Technology

[0003] Gate driving circuits are an important component of display devices. A gate driving circuit may include multiple cascaded shift registers, each of which can be electrically connected to a line in the display device. The gate driving circuit can sequentially input scan signals to multiple lines (such as gate lines or enable signal lines) in the display device, enabling the display device to display an image.

[0004] In related technologies, during the process of the gate driving circuit providing signals to the gate line, the voltage of the gate line fluctuates (e.g., voltage drop), resulting in poor stability of the output waveform of the gate driving circuit. This can cause data to be written to the sub-pixel incorrectly or fail to write, thus affecting the display quality. Summary of the Invention

[0005] This disclosure provides a shift register, a gate driving circuit, an array substrate, and a display device to improve the stability of the output waveform of the shift register.

[0006] On the one hand, a shift register is provided. The shift register includes a first input circuit, a second input circuit, a control circuit, a first output circuit, and an output control circuit.

[0007] The first input circuit is coupled to a signal input terminal, a first clock signal terminal, and a first node. The first input circuit is configured to transmit an input signal from the signal input terminal to the first node under the control of a first clock signal from the first clock signal terminal.

[0008] The second input circuit is coupled to a second clock signal terminal, a second node, and a third node. The second input circuit is configured to transmit a second clock signal from the second clock signal terminal to the second node under the control of the voltage of the third node.

[0009] The first output circuit is coupled to the first node, the second node, the first voltage signal terminal, the second clock signal terminal, and the signal output terminal. The first output circuit is configured to transmit a second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node, and to transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node.

[0010] The output control circuit is coupled to the second voltage signal terminal and the control signal terminal, and is also coupled to the second node or the signal output terminal. The output control circuit is configured to transmit the second voltage signal from the second voltage signal terminal to the second node or the signal output terminal under the control of the control signal from the control signal terminal.

[0011] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal, and the second node. Of the voltage signals received by the first voltage signal terminal and the second voltage signal terminal, one is the operating voltage when the transistor is turned on, and the other is the non-operating voltage when the transistor is turned off.

[0012] In some embodiments, the output control circuit includes a ninth transistor, the first terminal of which is electrically connected to the second voltage signal terminal, the second terminal of which is electrically connected to the second node, and the third terminal of which is electrically connected to the control signal terminal.

[0013] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal, and the signal output terminal. The voltage signals received by the first voltage signal terminal and the second voltage signal terminal are the same.

[0014] In some embodiments, the output control circuit includes a ninth transistor, the first terminal of which is electrically connected to the second voltage signal terminal, the second terminal of which is electrically connected to the signal output terminal, and the third terminal of which is electrically connected to the control signal terminal.

[0015] In some embodiments, the first input circuit includes a first transistor, a first terminal of which is electrically connected to the signal input terminal, a second terminal of which is electrically connected to the first node, and a third terminal of which is electrically connected to the first clock signal terminal. And / or, the second input circuit includes a second transistor and a first capacitor. The first terminal of the second transistor is electrically connected to the second clock signal terminal, the second terminal of which is electrically connected to the second node, and the third terminal of which is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the second clock signal terminal, and the second plate of the first capacitor is electrically connected to the third node.

[0016] In some embodiments, the first output circuit includes a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor. The first terminal of the seventh transistor is electrically connected to the second clock signal terminal, the second terminal of the seventh transistor is electrically connected to the signal output terminal, and the third terminal of the seventh transistor is electrically connected to the first node. The first terminal of the eighth transistor is electrically connected to the first voltage signal terminal, the second terminal of the eighth transistor is electrically connected to the signal output terminal, and the third terminal of the eighth transistor is electrically connected to the second node. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the signal output terminal. The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first voltage signal terminal.

[0017] In some embodiments, the shift register further includes control circuitry coupled to the first node, the second node, the third node, and the first voltage signal terminal. The control circuitry is configured to transmit a first voltage signal from the first voltage signal terminal to the second node and the third node under the control of a voltage from the first node, and to transmit the first voltage signal from the first voltage signal terminal to the first node under the control of a voltage from the second node.

[0018] In some embodiments, the control circuit includes a first control sub-circuit and a second control sub-circuit. The first control sub-circuit is coupled to the first node, the second node, and the first voltage signal terminal. The first control sub-circuit is configured to transmit a first voltage signal from the first voltage signal terminal to the first node under the control of the voltage of the second node. The second control sub-circuit is coupled to the first node, the second node, the third node, and the first voltage signal terminal. The second control sub-circuit is configured to transmit the first voltage signal from the first voltage signal terminal to the second node and the third node under the control of the voltage of the first node.

[0019] In some embodiments, the first control sub-circuit is further coupled to the second clock signal terminal, and the first control sub-circuit includes a third transistor and a fourth transistor. The first terminal of the third transistor is electrically connected to the first voltage signal terminal, the second terminal of the third transistor is electrically connected to the first node, and the third terminal of the third transistor is electrically connected to the second node. The first terminal of the fourth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the fourth transistor is electrically connected to the first node, and the third terminal of the fourth transistor is electrically connected to the second clock signal terminal.

[0020] And / or, the second control sub-circuit includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is electrically connected to the first voltage signal terminal, the second terminal of the fifth transistor is electrically connected to the third node, and the third terminal of the fifth transistor is electrically connected to the first node. The first terminal of the sixth transistor is electrically connected to the first voltage signal terminal, the second terminal of the sixth transistor is electrically connected to the second node, and the third terminal of the sixth transistor is electrically connected to the first node.

[0021] As can be seen from the above, the shift register provided in this embodiment has a voltage signal output at the signal output terminal at any stage, that is, there is no floating stage of the gate line. This can improve the stability of the output waveform of the shift register, improve the anti-interference stability of the shift register, reduce the risk of data miswriting or write failure of sub-pixels, and thus improve the display quality.

[0022] On the other hand, a gate driving circuit is provided. The gate driving circuit includes a plurality of cascaded first shift registers, wherein the first shift register is a shift register as described in any of the above embodiments.

[0023] In some embodiments, except for the last stage first shift register, in every two adjacent stages of first shift registers, the control signal terminal of the previous stage first shift register is coupled to the signal output terminal of the next stage first shift register.

[0024] In some embodiments, the gate driving circuit further includes a second shift register, which includes a first input circuit, a second input circuit, a control circuit, and a first output circuit. The signal input terminal of the second shift register is connected to the signal output terminal of the last stage first shift register, and the control signal terminal of the last stage first shift register is connected to the signal output terminal of the second shift register.

[0025] In another aspect, an array substrate is provided. The array substrate has a display area and a peripheral area located at least on one side of the display area. The array substrate includes a substrate and a gate driving circuit as described in any of the above embodiments, the gate driving circuit being disposed on the substrate and located in the peripheral area.

[0026] In some embodiments, the array substrate further includes a first voltage signal line and a second voltage signal line. The first voltage signal line is disposed on the side of the gate driving circuit away from the display area. The second voltage signal line overlaps with the gate driving circuit and divides the first shift register of the gate driving circuit into a first circuit and a second circuit, wherein the first circuit is further away from the display area than the second circuit. The first circuit includes a first input circuit, a second input circuit, a control circuit, and an output control circuit. The second circuit includes a first output circuit.

[0027] In some embodiments, the control circuit includes a first control sub-circuit and a second control sub-circuit. The array substrate also includes a first active pattern. The first active pattern includes a first straight line segment, a second straight line segment, a third straight line segment, and a fourth straight line segment. The first and third straight line segments are both substantially parallel to the first voltage signal line, and the first straight line segment is closer to the first voltage signal line than the third straight line segment. The second and fourth straight line segments are both substantially perpendicular to the first voltage signal line.

[0028] The first straight segment includes a first part and a second part, which are located on opposite sides of the second straight segment. The ends of the second, third, and fourth straight segments are connected sequentially, and the third straight segment and the first part are located on the same side of the second straight segment.

[0029] The active layer of the transistors included in the first control sub-circuit is located in the second portion. Of the transistors included in the second control sub-circuit, the active layer of a portion of the transistors is located in the first portion, and the active layer of another portion of the transistors is located in the third straight segment.

[0030] In some embodiments, the output control circuit is coupled to a second voltage signal terminal, a control signal terminal, and a second node. The array substrate further includes a first gate line, a second gate line, and a second active pattern.

[0031] The first gate line is substantially perpendicular to the first voltage signal line. The first gate line overlaps with the second portion and is connected to the second control sub-circuit and the first output circuit. The second gate line is substantially perpendicular to the first voltage signal line. The second gate line is connected to the first voltage signal line and the first output circuit.

[0032] The second active pattern is substantially parallel to the first voltage signal line and is located between the first gate line and the second gate line. One end of the second active pattern is connected to the first gate line, and the other end is connected to the second voltage signal line. The active layer of the transistors included in the output control circuit is located on the second active pattern.

[0033] In some embodiments, the array substrate further includes a second clock signal line, a third gate line, a first connection line, and a first cascade line. The second clock signal line is disposed on the side of the gate driving circuit away from the display area and is substantially parallel to the first voltage signal line.

[0034] The third gate line is substantially perpendicular to the first voltage signal line. One end of the third gate line is connected to the second clock signal line, and the other end overlaps with the second portion. The first connecting line is connected to the end of the fourth straight segment away from the third straight segment, and also to the end of the third gate line away from the first voltage signal line.

[0035] In two adjacent shift registers, one end of the first connecting line overlaps with the second active pattern of the previous shift register, and the other end passes between the first connecting line and the second voltage signal line to connect to the signal output terminal of the next shift register.

[0036] In some embodiments, the first cascade line includes a fourth gate line and a second connecting line, the fourth gate line being located between the first gate line and the second gate line. One end of the fourth gate line overlaps with the second active pattern, and the other end is connected to the second connecting line. The second connecting line is connected to the fourth gate line and the signal output terminal of the next-stage shift register.

[0037] In some embodiments, the output control circuit is coupled to a second voltage signal terminal, a control signal terminal, and a signal output terminal. The array substrate further includes a first gate line, a second gate line, and a second active pattern.

[0038] The first gate line is substantially perpendicular to the first voltage signal line. The first gate line overlaps with the second portion and is connected to the second control sub-circuit and the first output circuit. The second gate line is substantially perpendicular to the first voltage signal line. The second gate line is connected to the first voltage signal line and the first output circuit.

[0039] The second active pattern is substantially perpendicular to the first voltage signal line and is located between the first gate line and the second gate line. One end of the second active pattern is connected to the signal output terminal, and the other end is connected to the first voltage signal line. The active layer of the transistor included in the output control circuit is located on the second active pattern.

[0040] In some embodiments, the array substrate further includes a second clock signal line, a third gate line, a first connection line, and a first cascade line. The second clock signal line is disposed on the side of the gate driving circuit away from the display area and is substantially parallel to the first voltage signal line.

[0041] The third gate line is substantially perpendicular to the first voltage signal line. One end of the third gate line is connected to the second clock signal line, and the other end overlaps with the second portion. The first connecting line is connected to the end of the fourth straight segment away from the third straight segment, and also to the end of the third gate line away from the first voltage signal line.

[0042] In two adjacent shift registers, one end of the first cascade line overlaps with the second active pattern of the shift register of the previous stage, and the other end passes between the first connecting line and the second voltage signal line to connect to the second active pattern and signal output terminal of the next stage.

[0043] In some embodiments, the first cascade line includes a fourth gate line and a second connecting line. The fourth gate line is located between the first gate line and the second gate line. One end of the fourth gate line overlaps with the second active pattern, and the other end crosses another first cascade line and connects to the second connecting line. The second connecting line connects to the fourth gate line and the signal output terminal of the next-stage shift register.

[0044] In some embodiments, the end of the first connecting line that connects to the fourth straight segment is further away from the first voltage signal line than the end that connects to the third gate line.

[0045] In another aspect, a display device is provided. The display device includes an array substrate as described in any of the above embodiments.

[0046] The beneficial effects of the gate driving circuit, array substrate, and display device provided in this disclosure are the same as those of the shift register provided in the above-described technical solutions, and will not be repeated here. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0048] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 This is a structural diagram of another display device according to some embodiments; Figure 3 for Figure 1 A sectional view along section line AA'; Figure 4 This is a structural diagram of a display panel according to some embodiments; Figure 5 for Figure 4 A sectional view along section line BB'; Figure 6 This is a structural diagram of a gate drive circuit according to some embodiments; Figure 7 This is a block diagram of a shift register according to some embodiments; Figure 8 This is a block diagram of another shift register according to some embodiments; Figure 9 for Figure 7 The circuit diagram of the shift register shown is shown below; Figure 10 for Figure 8 The circuit diagram of the shift register shown is shown below; Figure 11 for Figure 9 The timing diagram of the shift register shown; Figure 12 The output voltage of the signal output terminal in the floating stage according to some embodiments of the related technology is compared with the output voltage of the signal output terminal in the corresponding stage according to some embodiments of this disclosure. Figure 13 Here is a circuit diagram of a second shift register according to some embodiments; Figure 14 This is a structural diagram of a shift register on an array substrate according to some embodiments; Figure 15 This is a structural diagram of another shift register of an array substrate according to some embodiments; Figure 16 for Figure 14 and Figure 15 The diagram shows the structure of the semiconductor layer on the array substrate. Figure 17 for Figure 14 The diagram shows the structure of the first gate conductive layer and the second gate conductive layer of the array substrate. Figure 18 for Figure 15 The diagram shows the structure of the first gate conductive layer and the second gate conductive layer of the array substrate. Figure 19 for Figure 14 The diagram shows the structure of the source and drain conductive layers of the array substrate. Figure 20 for Figure 15 The diagram shows the structure of the source and drain conductive layers of the array substrate. Detailed Implementation

[0049] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0052] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0056] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0057] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0058] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., limitations of the measurement system), as used herein, “about,” “approximately,” or “roughly” includes stated values ​​and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0060] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0061] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0062] In this specification, unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that, unless expressly defined herein, terms (e.g., those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted as having an ideal or overly formal meaning.

[0063] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0064] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0065] In the embodiments of this disclosure, the transistor used may be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin film transistors as an example.

[0066] In the embodiments of this disclosure, the third electrode of each thin-film transistor is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second electrodes of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0067] In embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0068] In the embodiments of this disclosure, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0069] In embodiments of this disclosure, "operating voltage" refers to a voltage that enables the operated transistors included therein to conduct; correspondingly, "non-operating voltage" refers to a voltage that does not enable the operated transistors included therein to conduct.

[0070] In embodiments of this disclosure, "low voltage" refers to a voltage that enables the included P-type transistor to conduct but does not enable the included N-type transistor to conduct (i.e., the N-type transistor is turned off); correspondingly, "high voltage" refers to a voltage that enables the included N-type transistor to conduct but does not enable the included P-type transistor to conduct (i.e., the P-type transistor is turned off).

[0071] In the circuits provided in the embodiments of this disclosure, all transistors are P-type transistors, as an example, for illustration.

[0072] like Figure 1 and Figure 2 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0073] For example, the display device 1000 can be any product or component with display function, such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, virtual reality (VR) device, etc.

[0074] For example, such as Figure 1 As shown, the display device 1000 can be a portable display product; for example, the display device 1000 can be... Figure 1 The mobile phone shown. For example, see [link to relevant documentation]. Figure 2 The display device 1000 can be a wearable device; for example, the display device 1000 can be... Figure 2 The watch shown.

[0075] The following uses the aforementioned display device 1000 as an example. Figure 1 The present invention uses a mobile phone as an example to illustrate some embodiments of the present invention, but the implementation of the present invention is not limited thereto.

[0076] In some embodiments, see Figure 3 The display device 1000 includes a display panel 100.

[0077] The display panel 100 includes a light-emitting side and a non-light-emitting side arranged opposite to each other. The light-emitting side is the side of the display panel 100 used for display, i.e. Figure 3 The upper side of the middle.

[0078] For example, such as Figure 3As shown, the above-mentioned display device 1000 may also include a housing 200, a cover plate 300, a circuit board 400, and other electronic components.

[0079] See Figure 3 The cover plate 300 can be a single-layer glass cover plate or can include multiple layers of sub-cover plates stacked together. This embodiment of the present disclosure does not make specific limitations.

[0080] like Figure 3 As shown, the longitudinal section of the housing 200 can be, for example, U-shaped. The display panel 100 and the circuit board 400 are disposed inside the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on the side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the required display signals to the display panel 100.

[0081] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0082] For example, the display panel 100 may be any of the following: an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a micro light-emitting diode display panel, a liquid crystal display panel, a plasma display panel, a field emission display panel, an electrowetting display panel, or an electrophoretic display panel, etc. The embodiments disclosed herein are not specifically limited to these.

[0083] The following describes some embodiments of the present disclosure using the above-mentioned display panel 100 as an example of an organic light-emitting diode display panel. However, the implementation of the present disclosure is not limited to this, and any other display panel 100 can be considered as long as the same technical concept is applied.

[0084] In some embodiments, see Figure 5 The display panel 100 includes an array substrate 110 and an encapsulation layer 120 for encapsulating the array substrate 110. The encapsulation layer 120 can be an encapsulation film or an encapsulation substrate, and the embodiments disclosed herein are not specifically limited thereto.

[0085] In some embodiments, see Figure 4 and Figure 5 The array substrate 110 has a display area A, which is an area for displaying images and is configured to have multiple sub-pixels P.

[0086] For example, see Figure 4 and Figure 5 The array substrate 110 includes a substrate 11 and a plurality of sub-pixels P, which are disposed on the substrate 11 and located in the display area A.

[0087] The substrate 11 mentioned above includes various types, and can be selected and set according to actual needs.

[0088] For example, substrate 11 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc.

[0089] For example, substrate 11 can be a flexible substrate. For example, the flexible substrate can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate, etc.

[0090] The aforementioned sub-pixel P includes a pixel circuit 130 and a light-emitting device 140. Multiple sub-pixels P can be arranged in multiple rows and columns, with each row including multiple sub-pixels P arranged along a first direction X, and each column including multiple sub-pixels P arranged along a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are approximately perpendicular.

[0091] It should be noted that the first direction X is the row direction of the arrangement of multiple sub-pixels P, and the second direction Y is the column direction of the arrangement of multiple sub-pixels P.

[0092] In some embodiments, see Figure 4 The array substrate 110 also has a peripheral region B, which is disposed on at least one side of the display area A. The peripheral region B is an area where no image is displayed and is configured to house the display driving circuit.

[0093] For example, see Figure 4 The array substrate 110 also includes a gate driving circuit 10 and a source driving circuit 20 disposed on the substrate 11 and located in the peripheral region B.

[0094] Among them, see Figure 4 and Figure 6 The gate drive circuit 10 includes multiple cascaded shift registers RS, and one shift register RS ​​can be electrically connected to at least one row of sub-pixels P. For example, one shift register RS ​​is electrically connected to one row of sub-pixels P.

[0095] It should be noted that some shift registers RS (e.g.) Figure 6 The second shift register RS2 in the document can also simply serve as an output cascade signal and not be connected to the sub-pixel P. For details, please refer to the following text. No specific examples will be given in this disclosure.

[0096] Here, multi-stage cascading refers to the situation where, in every two adjacent shift registers RS, the signal input terminal IN of the next-stage shift register RS ​​is coupled to the signal output terminal OT of the previous-stage shift register RS. Specifically, the signal input terminal IN of the first-stage shift register RS ​​is connected to the initialization signal line SL.

[0097] In some embodiments, see Figure 4 The array substrate 110 also includes multiple gate lines GL and multiple data lines DL disposed on the substrate 11.

[0098] In this configuration, multiple gate lines GL extend generally along a first direction X, and each gate line GL can be electrically connected to at least one row of sub-pixels P. Multiple data lines DL extend generally along a second direction Y, and each data line DL can be electrically connected to at least one column of sub-pixels P.

[0099] At this time, a shift register RS ​​in the gate driving circuit 10 can be electrically connected to a row of sub-pixels P through the gate line GL, and the source driving circuit 20 can be electrically connected to a column of sub-pixels P through the data line DL.

[0100] Based on the above, the gate driving circuit 10 can drive each row of sub-pixels P sequentially from one side of the display area A, i.e., single-sided driving. The gate driving circuit 10 can also drive each row of sub-pixels P sequentially from opposite sides of the display area A, i.e., cross-driving. The gate driving circuit 10 can also simultaneously drive each row of sub-pixels P sequentially from opposite sides of the display area A, i.e., dual-sided driving.

[0101] The following describes some embodiments of the present disclosure using the single-sided driving method of the gate driving circuit 10 as an example. However, the implementation of the present disclosure is not limited to this, and any other driving method can be considered as long as the same technical concept is applied.

[0102] In related technologies, during the process of providing signals to the gate line, the gate driving circuit has a floating phase, meaning that the gate driving circuit does not provide any signal to the gate. During this floating phase, the voltage of the gate line is easily disturbed by coupling from other signal lines (such as data lines), causing voltage fluctuations (such as voltage drops) in the gate line. This affects the stability of the output waveform of the entire gate driving circuit, leading to data miswriting or write failure in sub-pixels, thus impacting display quality.

[0103] Based on this, see Figure 7 and Figure 8 The shift register RS ​​provided in some embodiments of this disclosure includes a first input circuit 30, a second input circuit 40, a control circuit 50, a first output circuit 60, and an output control circuit 70.

[0104] In some examples, see Figure 7 and Figure 8 The first input circuit 30 is coupled to the signal input terminal IN, the first clock signal terminal CK, and the first node N1. The first input circuit 30 is configured to transmit the input signal from the signal input terminal IN to the first node N1 under the control of the first clock signal from the first clock signal terminal CK.

[0105] For example, such as Figure 9 and Figure 10 As shown, the first input circuit 30 includes a first transistor T1. The first terminal of the first transistor T1 is electrically connected to the signal input terminal IN, the second terminal of the first transistor T1 is electrically connected to the first node N1, and the third terminal of the first transistor T1 is electrically connected to the first clock signal terminal CK.

[0106] In some examples, see Figure 7 and Figure 8 The second input circuit 40 is coupled to the second clock signal terminal CB, the second node N2, and the third node N3. The second input circuit 40 is configured to transmit the second clock signal from the second clock signal terminal CB to the second node N2 under the control of the voltage of the third node N3.

[0107] For example, such as Figure 9 and Figure 10 As shown, the second input circuit 40 includes a second transistor T2 and a first capacitor C1. The first terminal of the second transistor T2 is electrically connected to the second clock signal terminal CB, the second terminal of the second transistor T2 is electrically connected to the second node N2, and the third terminal of the second transistor T2 is electrically connected to the third node N3. The first plate of the first capacitor C1 is electrically connected to the second clock signal terminal CB, and the second plate of the first capacitor C1 is electrically connected to the third node N3.

[0108] In some examples, see Figure 7 and Figure 8 The control circuit 50 is coupled to the first node N1, the second node N2, the third node N3, and the first voltage signal terminal VGH. The control circuit 50 is configured to transmit a first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 under the control of the voltage from the first node N1, and to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage from the second node N2.

[0109] For example, see Figure 7 and Figure 8 The control circuit 50 includes a first control sub-circuit 51 and a second control sub-circuit 52.

[0110] like Figure 7 and Figure 8 As shown, the first control sub-circuit 51 is coupled to the first node N1, the second node N2, and the first voltage signal terminal VGH. The first control sub-circuit 51 is configured to transmit a first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage of the second node N2.

[0111] For example, such as Figure 9 and Figure 10 As shown, the first control sub-circuit 51 includes a third transistor T3. The first terminal of the third transistor T3 is electrically connected to the first voltage signal terminal VGH, the second terminal of the third transistor T3 is electrically connected to the first node N1, and the third terminal of the third transistor T3 is electrically connected to the second node N2.

[0112] In addition, such as Figure 9 and Figure 10 As shown, the first control sub-circuit 51 can also be coupled to the second clock signal terminal CB. The first control sub-circuit 51 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage of the second node N2 and the second clock signal of the second clock signal terminal CB.

[0113] At this time, as Figure 9 and Figure 10 As shown, the first control sub-circuit 51 also includes a fourth transistor T4. The second terminal of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is electrically connected to the first node N1, thereby making the second terminal of the third transistor T3 electrically connected to the first node N1. The third terminal of the fourth transistor T4 is electrically connected to the second clock signal terminal CB.

[0114] like Figure 7 and Figure 8 As shown, the second control sub-circuit 52 is coupled to the first node N1, the second node N2, the third node N3, and the first voltage signal terminal VGH. The second control sub-circuit 52 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 under the control of the voltage of the first node N1.

[0115] For example, such as Figure 9 and Figure 10As shown, the second control sub-circuit 52 includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is electrically connected to the first voltage signal terminal VGH, the second terminal of the fifth transistor T5 is electrically connected to the third node N3, and the third terminal of the fifth transistor T5 is electrically connected to the first node N1. The first terminal of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH, the second terminal of the sixth transistor T6 is electrically connected to the second node N2, and the third terminal of the sixth transistor T6 is electrically connected to the first node N1.

[0116] In some examples, see Figure 7 and Figure 8 The first output circuit 60 is coupled to a first node N1, a second node N2, a first voltage signal terminal VGH, a second clock signal terminal CB, and a signal output terminal OT. The first output circuit 60 is configured to, under the control of the voltage at the first node N1, transmit a second clock signal from the second clock signal terminal CB to the signal output terminal OT; and, under the control of the voltage at the second node N2, transmit a first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT.

[0117] For example, the first output circuit 60 includes a first output sub-circuit 61 and a second output sub-circuit 62.

[0118] like Figure 7 and Figure 8 As shown, the first output sub-circuit 61 is coupled to the first node N1, the second clock signal terminal CB, and the signal output terminal OT. The first output sub-circuit 61 is configured to transmit the second clock signal from the second clock signal terminal CB to the signal output terminal OT under the control of the voltage of the first node N1.

[0119] For example, such as Figure 9 and Figure 10 As shown, the first output sub-circuit 61 includes a seventh transistor T7 and a second capacitor C2. The first terminal of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the second terminal of the seventh transistor T7 is electrically connected to the signal output terminal OT, and the third terminal of the seventh transistor T7 is electrically connected to the first node N1. The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the signal output terminal OT.

[0120] like Figure 7 and Figure 8 As shown, the second output sub-circuit 62 is coupled to the second node N2, the first voltage signal terminal VGH, and the signal output terminal OT. The second output sub-circuit 62 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT under the control of the voltage of the second node N2.

[0121] For example, such as Figure 9 and Figure 10 As shown, the second output sub-circuit 62 includes an eighth transistor T8 and a third capacitor C3. The first terminal of the eighth transistor T8 is electrically connected to the first voltage signal terminal VGH, the second terminal of the eighth transistor T8 is electrically connected to the signal output terminal OT, and the third terminal of the eighth transistor T8 is electrically connected to the second node N2. The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the first voltage signal terminal VGH.

[0122] In some examples, see Figure 7 and Figure 8 The output control circuit 70 is coupled to the second voltage signal terminal VS and the control signal terminal K, and also coupled to the second node N2 or the signal output terminal OT. The output control circuit 70 is configured to transmit the second voltage signal from the second voltage signal terminal VS to the second node N2 or the signal output terminal OT under the control of the control signal from the control signal terminal K.

[0123] For example, such as Figure 7 As shown, the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the second node N2.

[0124] For example, such as Figure 9 As shown, the output control circuit 70 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is electrically connected to the second voltage signal terminal VS, the second terminal of the ninth transistor T9 is electrically connected to the second node N2, and the third terminal of the ninth transistor T9 is electrically connected to the control signal terminal K.

[0125] Based on this, all transistors are either P-type transistors or N-type transistors. Of the voltage signals received at the first voltage signal terminal VGH and the second voltage signal terminal VS, one is the operating voltage when the transistor is turned on, and the other is the non-operating voltage when the transistor is turned off.

[0126] For example, all transistors are P-type transistors. The first voltage signal received at the first voltage signal terminal VGH is a constant high voltage, and the second voltage signal received at the second voltage signal terminal VS is a constant low voltage, that is, the second voltage signal is less than the first voltage signal.

[0127] For example, such as Figure 8 As shown, the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the signal output terminal OT.

[0128] For example, such as Figure 10As shown, the output control circuit 70 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is electrically connected to the second voltage signal terminal VS, the second terminal of the ninth transistor T9 is electrically connected to the signal output terminal OT, and the third terminal of the ninth transistor T9 is electrically connected to the control signal terminal K.

[0129] Based on this, the voltage signals received at the first voltage signal terminal VGH and the second voltage signal terminal VS are the same. For example, if all transistors are P-type transistors, the voltage signals received at the first voltage signal terminal VGH and the second voltage signal terminal VS are both constant high voltages.

[0130] In some embodiments, see Figure 9 and Figure 10 The shift register RS ​​also includes an isolating sub-circuit 80, which is coupled to the first node N1, the fourth node N4, and the third voltage signal terminal VGL. The first output sub-circuit 61 is coupled to the fourth node N4, that is, the first output sub-circuit 61 is coupled to the first node N1 through the isolating sub-circuit 80.

[0131] The isolator circuit 80 is configured to transmit the voltage from the first node N1 to the fourth node N4 under the control of the third voltage signal from the third voltage signal terminal VGL.

[0132] For example, such as Figure 9 and Figure 10 As shown, the isolator circuit 80 includes a tenth transistor T10. The first terminal of the tenth transistor T10 is electrically connected to the first node N1, the second terminal of the tenth transistor T10 is electrically connected to the third terminal of the seventh transistor T7, and the third terminal of the tenth transistor T10 is electrically connected to the third voltage signal terminal VGL.

[0133] It should be noted that the third voltage signal received at the third voltage signal terminal VGL is a constant operating voltage. For example, if the tenth transistor T10 is a P-type transistor, the third voltage signal received at the third voltage signal terminal VGL is a constant low voltage.

[0134] Figure 11 for Figure 9 The timing diagram of the shift register is shown below. (Followed by...) Figure 9 and Figure 11 The timing of shift registers in some embodiments of this disclosure will be described by way of example.

[0135] like Figure 11 As shown, in the first stage P1, the input signal received by the input signal terminal IN is low voltage, the first clock signal received by the first clock signal terminal CK is low voltage, and the second clock signal received by the second clock signal terminal CB is high voltage. The control signal received by the control signal terminal K is high voltage.

[0136] At this time, combined Figure 9 The first transistor T1 is turned on under the control of the first clock signal at the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1, where the voltage is low. The tenth transistor T10 is turned on, transmitting the low voltage from the first node N1 to the fourth node N4, where the voltage is low. The seventh transistor T7 is turned on under the control of the voltage at the first node N1, transmitting the second clock signal received from the second clock signal terminal CB to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0137] Furthermore, the ninth transistor T9 is turned off under the control of the control signal at the control signal terminal K. Meanwhile, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the voltage at the first node N1, transmitting the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 respectively, thus maintaining the voltages at the second node N2 and the third node N3 at a high voltage. The second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.

[0138] like Figure 11 As shown, in the second stage P2, the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a high voltage, and the second clock signal received by the second clock signal terminal CB is a low voltage. The control signal received by the control signal terminal K is a high voltage.

[0139] At this time, combined Figure 9 The first transistor T1 is turned off under the control of the first clock signal at the first clock signal terminal CK. The first node N1 maintains the voltage of the previous stage, i.e., the low voltage of P1 in the first stage. The fourth node N4 is also at a low voltage. The seventh transistor T7 is turned on under the control of the voltage of the first node N1, transmitting the second clock signal received from the second clock signal terminal CB to the signal output terminal OT. The signal output terminal OT outputs a low voltage.

[0140] Furthermore, the ninth transistor T9 is turned off under the control of the control signal at the control signal terminal K. Meanwhile, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the voltage at the first node N1, transmitting the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 respectively, thus maintaining the voltages at the second node N2 and the third node N3 at a high voltage. The second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.

[0141] like Figure 11As shown, in the third stage P3, the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a low voltage, and the second clock signal received by the second clock signal terminal CB is a high voltage. The control signal received by the control signal terminal K is a low voltage.

[0142] At this time, combined Figure 9 The ninth transistor T9 is turned on under the control of the control signal at the control signal terminal K, transmitting the second voltage signal from the second voltage signal terminal VS to the second node N2, where the second node N2 is at a low voltage. The eighth transistor T8 is turned on, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0143] Furthermore, the first transistor T1 is turned on under the control of the first clock signal at the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1, where the first node N1 is at a high voltage. The tenth transistor T10 is turned on, transmitting the high voltage from the first node N1 to the fourth node N4, where the fourth node N4 is at a high voltage. The seventh transistor T7 is turned off.

[0144] like Figure 11 As shown, in the fourth stage P4, the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a high voltage, and the second clock signal received by the second clock signal terminal CB is a low voltage. The control signal received by the control signal terminal K is a high voltage.

[0145] At this time, combined Figure 9 The ninth transistor T9 is turned off under the control of the control signal at the control signal terminal K. The second transistor T2 is turned on under the control of the second clock signal at the second clock signal terminal CB, transmitting the second clock signal from CB to the second node N2. The second node N2 is at a low voltage. The eighth transistor T8 is turned on, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0146] Furthermore, the first transistor T1 is turned off under the control of the first clock signal at the first clock signal terminal CK, and the third transistor T3 is turned on under the control of the second node N2. The fourth transistor T4 is turned on under the control of the second clock signal at the second clock signal terminal CB. The first voltage signal at the first voltage signal terminal VGH is transmitted to the first node N1, so that the voltage of the first node N1 is kept at a high voltage, and the voltage of the fourth node N4 is high. The seventh transistor T7 is turned off.

[0147] like Figure 11As shown, in the fifth stage P5, the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a low voltage, and the second clock signal received by the second clock signal terminal CB is a high voltage. The control signal received by the control signal terminal K is a high voltage.

[0148] At this time, combined Figure 9 The ninth transistor T9 is turned off under the control of the control signal at the control signal terminal K, and the second transistor T2 is turned on and off under the control of the second clock signal at the second clock signal terminal CB. The second node N2 maintains the voltage of the previous stage, i.e., the low voltage of P4 in the fourth stage. The eighth transistor T8 is turned on under the control of the voltage at the second node N2, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0149] Furthermore, the first transistor T1 is turned on under the control of the first clock signal at the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1. The first node N1 is at a high voltage, while the fifth transistor T5 and the sixth transistor T6 are turned off. The fourth node N4 is at a high voltage. The seventh transistor T7 is turned off.

[0150] As can be seen from the above, the shift register RS ​​provided in this embodiment has a voltage signal output at the signal output terminal OT at any stage, that is, there is no floating stage for the gate line GL. This can improve the stability of the output waveform of the shift register RS, improve the anti-interference stability of the shift register RS, reduce the risk of data miswriting or write failure of sub-pixel P, and thus improve the display quality.

[0151] Figure 12 This is a simulation comparison diagram of the output voltage of the signal output terminal in the floating stage according to some embodiments of the related technology, and the output voltage of the signal output terminal in the corresponding stage according to some embodiments of this disclosure.

[0152] according to Figure 12 As is known in related technologies, the signal output terminal OT of the shift register RS ​​experiences a voltage drop of 1.2V from other signal lines (such as the data line DL). In this application, the voltage drop at the signal output terminal OT of the shift register RS ​​is 0.5V, which is 0.7V lower than that in related technologies. Therefore, this application can significantly improve the stability of the output waveform of the shift register RS, enhance the anti-interference stability of the shift register RS, reduce the risk of data miswriting or write failure in sub-pixel P, and thus improve display quality.

[0153] In some embodiments of the present disclosure, the gate drive circuit 10 is provided, see [reference]. Figure 4 and Figure 6The multi-stage cascaded shift register RS ​​includes a first shift register RS1, which is the shift register RS1 of any of the above embodiments. Each stage of the first shift register RS1 can, for example, be connected to a row of sub-pixels P.

[0154] In some embodiments, see Figure 6 Except for the last stage first shift register RS1, in every two adjacent stages of the first shift register RS1, the control signal terminal K of the previous stage's first shift register RS1 is coupled to the signal output terminal OT of the next stage's first shift register RS1. With this configuration, the control signal terminal K does not require a separate signal line, simplifying circuit design.

[0155] In some embodiments, such as Figure 6 and Figure 13 As shown, the gate drive circuit 10 further includes a second shift register RS2, which includes a first input circuit 30, a second input circuit 40, a control circuit 50, and a first output circuit 60. That is, the second shift register RS2 does not include the aforementioned output control circuit 70.

[0156] It should be noted that the second shift register RS2 may also include an isolating sub-circuit 80. The structures of the first input circuit 30, the second input circuit 40, the control circuit 50, the first output circuit 60, and the isolating sub-circuit 80 can be referred to above, and will not be repeated here in the embodiments of this disclosure.

[0157] The signal input terminal IN of the second shift register RS2 is connected to the signal output terminal OT of the last stage first shift register RS1, and the control signal terminal K of the last stage first shift register RS1 is connected to the signal output terminal OT of the second shift register RS2.

[0158] It should be understood that the output signal terminal OT of the second shift register RS2 has a floating phase. Based on this, in some embodiments of this disclosure, the signal output terminal OT of the second shift register RS2 is not connected to the sub-pixel P, and the signal output terminal OT of the second shift register RS2 only provides a control signal to the control signal terminal K of the previous stage first shift register RS1.

[0159] See Figure 14 and Figure 15 The array substrate 110 provided in some embodiments of this disclosure also includes a first voltage signal line VL1 and a second voltage signal line VL2, both of which extend approximately along the second direction Y.

[0160] It should be noted that the first voltage signal line VL1 is configured to provide a constant high voltage, and the second voltage signal line VL2 is configured to provide a constant low voltage.

[0161] Among them, such as Figure 4 , Figure 14 and Figure 15 As shown, the first voltage signal line VL1 is located on the side of the gate driving circuit 10 away from the display area A. The second voltage signal line VL2 overlaps with the gate driving circuit 10 and divides the first shift register RS1 of the gate driving circuit 10 into a first circuit 500 and a second circuit 600. The first circuit 500 is further away from the display area A than the second circuit 600.

[0162] At this time, as Figure 6 , Figure 14 and Figure 15 As shown, the first voltage signal terminal VGH is connected to the first voltage signal line VL1, the second voltage signal terminal VS is connected to either the first voltage signal line VL1 or the second voltage signal line VL2, and the third voltage signal terminal VGL is connected to the second voltage signal line VL2.

[0163] In some embodiments, see Figure 14 and Figure 15 The array substrate 110 also includes a first clock signal line CL1, a second clock signal line CL2, and an initialization signal line SL. The first clock signal line CL1, the second clock signal line CL2, and the initialization signal line SL all extend approximately along the second direction Y, that is, they are approximately parallel to the first voltage signal line VL1.

[0164] It should be noted that there can be multiple first clock signal lines CL1 and second clock signal lines CL2. Figure 14 , Figure 15 , Figure 19 and Figure 20 The example only uses one first clock signal line CL1 and one second clock signal line CL2, and the embodiments disclosed herein are not limited to this.

[0165] Among them, see Figure 4 , Figure 14 and Figure 15 The first clock signal line CL1, the second clock signal line CL2, and the initialization signal line SL are located on the side of the gate drive circuit 10 away from the display area A.

[0166] For example, such as Figure 4 , Figure 14 and Figure 15 As shown, the first clock signal line CL1, the second clock signal line CL2, and the initialization signal line SL can be arranged sequentially away from the first voltage signal line VL1.

[0167] At this time, as Figure 6 , Figure 14 and Figure 15 As shown, the first clock signal terminal CK is connected to the first clock signal line CL1, the second clock signal terminal CB is connected to the second clock signal line CL2, and the signal input terminal IN of the first stage first shift register RS ​​is connected to the initialization signal line SL.

[0168] In some embodiments, see Figure 16 The array substrate 110 also includes a first active pattern 21, a second active pattern 22, a third active pattern 23, a fourth active pattern 24 and a fifth active pattern 25.

[0169] In some examples, such as Figure 16 As shown, the first active pattern 21 includes a first straight line segment 211, a second straight line segment 212, a third straight line segment 213, and a fourth straight line segment 214.

[0170] Among them, such as Figure 14 , Figure 15 and Figure 16 As shown, the first straight line segment 211 and the third straight line segment 213 are both approximately parallel to the first voltage signal line VL1, and the first straight line segment 211 is closer to the first voltage signal line VL1 than the third straight line segment 213. The second straight line segment 212 and the fourth straight line segment 214 are both approximately perpendicular to the first voltage signal line VL1.

[0171] In addition, such as Figure 16 As shown, the first straight segment 211 includes a first part 2111 and a second part 2112. The first part 2111 and the second part 2112 are located on opposite sides of the second straight segment 212. The ends of the second straight segment 212, the third straight segment 213 and the fourth straight segment 214 are connected in sequence, and the third straight segment 213 and the first part 2111 are located on the same side of the second straight segment 212.

[0172] See Figure 9 , Figure 14 and Figure 16 The active layers of the transistors included in the first control sub-circuit 51 are located in the second portion 2112 of the first straight line segment 211 in the first active pattern 21. For example, the active layers of the third transistor T3 and the fourth transistor T4 are located in the second portion 2112 of the first straight line segment 211 in the first active pattern 21.

[0173] See Figure 9 , Figure 14 and Figure 16In the second control sub-circuit 52 mentioned above, the active layers of some transistors are located in the first part 2111 of the first straight line segment 211 in the first active pattern 21, and the active layers of other transistors are located in the third straight line segment 213. For example, the active layer of the fifth transistor T5 is located in the first part 1211, and the active layer of the sixth transistor T6 is located in the third straight line segment 213.

[0174] See Figure 9 , Figure 14 and Figure 16 The active layer of the transistors included in the second input circuit 40 is located in the fourth straight segment 214. For example, the active layer of the second transistor T2 is located in the fourth straight segment 214.

[0175] In some examples, such as Figure 14 and Figure 16 As shown, the second active pattern 22 can be located on the side of the first active pattern 21 away from the first voltage signal line VL1.

[0176] At this time, refer to Figure 9 , Figure 14 and Figure 16 The active layer of the transistors included in the output control circuit 70 is located in the second active pattern 22. For example, the active layer of the ninth transistor T9 is located in the second active pattern 22.

[0177] In some examples, such as Figure 9 , Figure 14 and Figure 16 As shown, the third active pattern 23 is located on the side of the first active pattern 21 closest to the first voltage signal line VL1. The third active pattern 23 can be approximately parallel to the first voltage signal line VL1.

[0178] At this time, the active layer of the transistors included in the first input circuit 30 is located in the third active pattern 23. For example, the active layer of the first transistor T1 is located in the third active pattern 23.

[0179] In some examples, such as Figure 9 , Figure 14 and Figure 16 As shown, the fourth active pattern 24 is located on the side of the second voltage signal line VL2 away from the first voltage signal line VL1. The fourth active pattern 24 can be approximately parallel to the first voltage signal line VL1.

[0180] At this time, the active layer of the transistors included in the aforementioned isolator circuit 80 is located in the fourth active pattern 24. For example, the active layer of the tenth transistor T10 is located in the fourth active pattern 24.

[0181] In some examples, such as Figure 9 , Figure 14 and Figure 16 As shown, the fifth active pattern 25 is located on the side of the fourth active pattern 24 away from the first voltage signal line VL1. The fifth active pattern 25 may include a plurality of sub-active patterns spaced apart along the first direction X.

[0182] At this time, the active layers of the transistors included in the first output circuit 60 are located in the fifth active pattern 25. For example, the active layers of the seventh transistor T7 and the eighth transistor T8 are located in the fifth active pattern 25.

[0183] In some embodiments, see Figure 14 , Figure 15 , Figure 17 and Figure 18 The array substrate 110 also includes a first gate line 31, a second gate line 32, a third gate line 33, a fourth gate line 34, a fifth gate line 35, a sixth gate line 36, a seventh gate line 37, an eighth gate line 38, a ninth gate line 39, a tenth gate line 41, and an eleventh gate line 42.

[0184] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the first gate line 31 is approximately perpendicular to the first voltage signal line VL1. The first gate line 31 overlaps with the second portion 2112 of the first straight line segment 211 in the first active pattern 21, and is connected to the second control sub-circuit 52 and the first output circuit 60.

[0185] For example, such as Figure 9 , Figure 14 and Figure 17 As shown, the first gate line 31 overlaps with the second portion 2112 of the first straight line segment 211 in the first active pattern 21 to form the third transistor T3. It is connected to the connection node (second node N2) of the second transistor T2 and the sixth transistor T6, and to the third terminal of the eighth transistor T8.

[0186] Among them, such as Figure 9 , Figure 14 and Figure 17 As shown, the array substrate 110 may further include a first plate and a second plate of a third capacitor C3, the first plate and the second plate at least partially overlapping. The first gate line 31 is also connected to the first plate of the third capacitor C3.

[0187] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the second gate line 32 is approximately perpendicular to the first voltage signal line VL1. The second gate line 32 is connected to the first voltage signal line VL1 and the first output circuit 60.

[0188] For example, such as Figure 9, Figure 14 and Figure 17 As shown, the second gate line 32 is connected to the first voltage signal line VL1, and is also connected to the first terminal of the eighth transistor T8.

[0189] Among them, such as Figure 9 , Figure 14 and Figure 17 As shown, the array substrate 110 may further include a first plate and a second plate of a third capacitor C3, the first plate and the second plate at least partially overlapping. The second gate line 32 is also connected to the second plate of the third capacitor C3.

[0190] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the third gate line 33 is approximately perpendicular to the first voltage signal line VL1. The third gate line 33 is located between the first gate line 31 and the second gate line 32. One end of the third gate line 33 is connected to the second clock signal line CL2, and the other end overlaps with the second part 2112 of the first straight line segment 211 in the first active pattern 21, forming the fourth transistor T4.

[0191] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the fourth gate line 34 is located between the first gate line 31 and the second gate line 32. The fourth gate line 34 overlaps with the second active pattern 22 to form the ninth transistor T9.

[0192] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the fifth gate line 35 is approximately perpendicular to the first voltage signal line VL1. The fifth gate line 35 is located on the side of the first gate line 31 away from the second gate line 32, and one end of the fifth gate line 35 is connected to the first clock signal line CL1, while the other end overlaps with the third active pattern 23 to form the first transistor T1.

[0193] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the sixth gate line 36 is approximately parallel to the first voltage signal line VL1. The sixth gate line 36 is located on the side of the fifth gate line 35 away from the first voltage signal line VL1, and overlaps with the fourth straight line segment 214 to form the second transistor T2.

[0194] Among them, such as Figure 9 , Figure 14 and Figure 17As shown, the array substrate 110 may further include a first plate and a second plate of the first capacitor C1, the first plate and the second plate at least partially overlapping. The sixth gate line 36 is also connected to the second plate of the first capacitor C1.

[0195] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the seventh gate line 37 overlaps with the first part 2111 of the first straight line segment 211 and the third straight line segment 213 in the first active pattern 21, respectively, to form the fifth transistor T5 and the sixth transistor T6.

[0196] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, one end of the eighth gate line 38 is connected to the second voltage signal line VL2, and the other end overlaps with the fourth active pattern to form the tenth transistor T10.

[0197] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the ninth gate line 39 overlaps with the fifth active pattern 25 to form the seventh transistor T7.

[0198] Among them, such as Figure 9 , Figure 14 and Figure 17 As shown, the array substrate 110 may further include a first plate and a second plate of the second capacitor C2, the first plate and the second plate at least partially overlapping. The ninth gate line 39 is also connected to the first plate of the second capacitor C2.

[0199] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the tenth gate line 41 is connected to the first gate line 31 and overlaps with the fifth active pattern 25 to form the eighth transistor T8.

[0200] Among them, such as Figure 9 , Figure 14 and Figure 17 As shown, the array substrate 110 may further include a first plate and a second plate of the third capacitor C3, the first plate and the second plate at least partially overlapping. The tenth gate line 41 is also connected to the first plate of the third capacitor C3.

[0201] In some examples, such as Figure 9 , Figure 14 and Figure 17 As shown, the eleventh gate line 42 is connected to the second pole of the seventh transistor T7 and the eighth transistor T8, and extends between the first voltage signal line VL1 and the second voltage signal line VL2.

[0202] In some embodiments, see Figure 14 , Figure 15 , Figure 19 and Figure 20 The array substrate 110 also includes a first connection line 71, a second connection line 72, a third connection line 73, a fourth connection line 74, a fifth connection line 75, a sixth connection line 76, a seventh connection line 77, an eighth connection line 78, a ninth connection line 79, a tenth connection line 81, and an eleventh connection line 82.

[0203] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the first connection line 71 is connected to the first terminal of the second transistor T2 and the third terminal of the fourth transistor T4. That is, the first connection line 71 is connected to the end of the fourth straight segment 214 away from the third straight segment 213, and to the end of the third gate line 33 away from the first voltage signal line VL1.

[0204] It should be noted that the first connecting line 71 is connected to the first plate of the first capacitor C1.

[0205] At this time, as Figure 14 , Figure 17 and Figure 19 As shown, the array substrate 110 may further include a first capacitor C1 and a twelfth gate line 43, the twelfth gate line 43 being connected to the first connection line 71 and the first electrode of the seventh transistor T7. The first connection line 71 may also be connected to the first electrode of the first capacitor C1.

[0206] Here, the end of the first connecting line 71 that connects to the fourth straight segment 214 is further away from the first voltage signal line VL1 than the end that connects to the third gate line 33. This arrangement increases the distance between the first connecting line 71 and the second voltage signal line VL2, which is beneficial for the configuration of the output control circuit 70.

[0207] In some examples, such as Figure 14 , Figure 17 and Figure 19 As shown, the second connection line 72 is connected to the fourth gate line 34 and the next stage shift register RS ​​(see...). Figure 6 ) signal output terminal OT (see Figure 6 The second connection line 72 can be connected at one end to the fourth gate line 34, and at the other end to the next stage shift register RS ​​(see [link to shift register]). Figure 6 The eleventh gate line 42 extends to the portion between the first voltage signal line VL1 and the second voltage signal line VL2.

[0208] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the third connection line 73 is connected to the second terminal of the first transistor T1 and the third terminal of the fifth transistor T5 and the sixth transistor T6. That is, one end of the third connection line 73 can be connected to the third active pattern 23, and the other end can be connected to the seventh gate line 37.

[0209] In some examples, such as Figure 14 , Figure 17 and Figure 19 As shown, the fourth connection line 74 is connected to the third terminal of the fifth transistor T5 and the sixth transistor T6, and the second terminal of the fourth transistor T4. That is, one end of the fourth connection line 74 can be connected to the seventh gate line 37, and the other end can be connected to the second part 2112 of the first straight line segment 211 in the first active pattern 21, away from the first part 2111 of the first straight line segment 211 in the first active pattern 21.

[0210] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the fifth connecting line 75 is connected to the second electrode of the fifth transistor T5 and the second plate of the first capacitor C1. That is, one end of the fifth connecting line 75 can be connected to the first part 2111 of the first straight line segment 211 in the first active pattern 21, away from the second part 2112 of the first straight line segment 211 in the first active pattern 21, and the other end can be connected to the second plate of the first capacitor C1.

[0211] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the sixth connection line 76 is connected to the second terminals of the second transistor T2 and the sixth transistor T6, and the third terminal of the third transistor T3 and the eighth transistor T8. That is, one end of the sixth connection line 76 can be connected to the inflection point of the third straight segment 213 and the fourth straight segment 214, and the other end can be connected to the first gate line 31.

[0212] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the seventh connection line 77 is connected to the second terminal of the tenth transistor T10 and the third terminal of the seventh transistor T7. That is, one end of the seventh connection line 77 can be connected to the fourth active pattern 24, and the other end can be connected to the ninth gate line 39.

[0213] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the eighth connection line 78 is connected to the first stage of the tenth transistor T10, the third stage of the fifth transistor T5, and the third stage of the sixth transistor T6. That is, one end of the eighth connection line 78 can be connected to the fourth active pattern 24, and the other end can be connected to the seventh gate line 37.

[0214] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the ninth connection line 79 is connected to the second plate of the third capacitor C3 and the first plate of the eighth transistor T8. That is, one end of the ninth connection line 79 is connected to the second plate of the third capacitor C3, and the other end is connected to the fifth active pattern 25.

[0215] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the tenth connection line 81 is connected to the first terminal and the second clock signal line CL2 of the seventh transistor T7. At this time, the array substrate 110 may also include a twelfth gate line 43, which is connected to the first connection line 71 and the tenth connection line 81.

[0216] In some examples, such as Figure 14 , Figure 16 , Figure 17 and Figure 19 As shown, the eleventh connection line 82 is connected to the second plate of the second capacitor C2, the second electrode of the seventh transistor T7, and the second electrode of the eighth transistor T8, forming the signal output terminal OT. At this time, the aforementioned eleventh gate line 42 is connected to the eleventh connection line 82.

[0217] In some embodiments, such as Figure 9 and Figure 14 As shown, the above-mentioned output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the second node N2.

[0218] Based on this, refer to Figure 14 , Figure 16 and Figure 17 The second active pattern 22 is approximately parallel to the first voltage signal line VL1. Furthermore, one end of the second active pattern 22 is connected to the first gate line 31, and the other end is connected to the second voltage signal line VL2.

[0219] Here, as Figure 14 , Figure 16 , Figure 17 and Figure 19As shown, the array substrate 110 may further include a twelfth connection line 83, the second active pattern 22 is connected to the twelfth connection line 83, and the twelfth connection line 83 is electrically connected to the first gate line 31, thereby making the second active pattern 22 electrically connected to the first gate line 31.

[0220] The array substrate 110 may further include a first cascade line 90. In two adjacent shift registers RS, one end of the first cascade line 90 overlaps with the second active pattern 22 of the previous shift register RS, and the other end passes between the first connection line 71 and the second voltage signal line VL2 and is connected to the signal output terminal OT of the next shift register RS.

[0221] At this time, the first cascade line 90 includes the second connection line 72 and the fourth gate line 34, and the second connection line 72 is connected to the fourth gate line 34 and the signal output terminal OT of the shift register RS ​​of the next stage.

[0222] In other embodiments, see Figure 10 and Figure 15 The output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the signal output terminal OT.

[0223] Based on this, refer to Figure 15 and Figure 16 The second active pattern 22 is approximately perpendicular to the first voltage signal line VL1. Furthermore, one end of the second active pattern 22 is connected to the signal output terminal OT (see [reference]). Figure 10 The other end is connected to the first voltage signal line VL1.

[0224] The array substrate 110 may further include a first cascade line 90. In two adjacent shift registers RS, one end of the first cascade line 90 overlaps with the second active pattern 22 of the previous shift register RS, and the other end passes through the first connection line 71 and the second voltage signal line VL2 to connect to the signal output terminal OT of the next shift register RS.

[0225] At this time, as Figure 15 , Figure 16 , Figure 18 and Figure 20 As shown, the first cascade line 90 includes the aforementioned second connecting line 72 and fourth gate line 34. One end of the fourth gate line 34 overlaps with the second active pattern 22, and the other end crosses over another first cascade line 90 and connects to the second connecting line 72. The second connecting line 72 is connected to the fourth gate line 34 and the signal output terminal OT of the next stage shift register RS.

[0226] Based on the above routing design, along the first direction X, the width of the first shift register RS1 is approximately equal to the width of the second shift register RS2. That is, the gate drive circuit 10 can add an output control circuit 70 while keeping the width of the first direction X unchanged, thereby improving the anti-interference stability of the gate drive circuit 10, reducing the risk of data miswriting or write failure of the sub-pixel P, and thus improving the display quality.

[0227] For example, when the radial dimension of the sub-pixel P is at most 110μm~120μm, the width of the gate drive circuit 10 along the first direction X is 380μm~390μm.

[0228] Figure 5 for Figure 4 A sectional view along section line BB'. (See below for details.) Figure 5 The present disclosure provides a schematic description of the film layers in which each trace in the array substrate 110 is located, but the embodiments of the present disclosure are not limited thereto.

[0229] like Figure 5 As shown, along a direction perpendicular to and away from the substrate 11, the array substrate 110 includes a semiconductor layer ACT, a gate insulating layer GI, a first gate conductive layer GT1, a first interlayer insulating layer ILD1, a second gate conductive layer GT2, a second interlayer insulating layer ILD2, a source / drain conductive layer SD, and a planarization layer PLN, which are sequentially disposed on the substrate 11.

[0230] See Figure 5 and Figure 16 The first active pattern 21, the second active pattern 22, the third active pattern 23, the fourth active pattern 24 and the fifth active pattern 25 are located in the semiconductor layer ACT.

[0231] See Figure 5 , Figure 17 and Figure 18 The first gate line 31, the third gate line 33, the fourth gate line 34, the fifth gate line 35, the sixth gate line 36, the seventh gate line 37, the eighth gate line 38, the ninth gate line 39, the tenth gate line 41, the eleventh gate line 42, and the twelfth gate line 43 are located in the first gate conductive layer GT1. The second gate line 32 is located in the second gate conductive layer GT2.

[0232] See Figure 5 , Figure 19 and Figure 20 The first connection line 71, the second connection line 72, the third connection line 73, the fourth connection line 74, the fifth connection line 75, the sixth connection line 76, the seventh connection line 77, the eighth connection line 78, the ninth connection line 79, the tenth connection line 81, the eleventh connection line 82 and the twelfth connection line 83 are located in the source and drain conductive layer SD.

[0233] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized by, An array substrate having a display area and a peripheral area at least on one side of the display area, the array substrate comprising: a substrate; a gate driving circuit disposed on one side of the substrate and located in the peripheral area; a first voltage signal line disposed on one side of the substrate; the first voltage signal line being electrically connected with the gate driving circuit; a first active pattern disposed on one side of the substrate; the first active pattern comprising a first straight segment, a second straight segment and a third straight segment; the first straight segment and the third straight segment being substantially parallel to the first voltage signal line, and the first straight segment being closer to the first voltage signal line than the third straight segment; the second straight segment being substantially perpendicular to the first voltage signal line; the first straight segment comprising a first portion and a second portion, the first portion and the second portion being located on opposite sides of the second straight segment; and the third straight segment and the first portion being located on the same side of the second straight segment; the end of the second straight segment and the end of the third straight segment being connected.

2. The array substrate of claim 1, wherein, Further comprising a second voltage signal line, the second voltage signal line being electrically connected with the gate driving circuit; the first voltage signal line and the second voltage signal line extending substantially along a second direction.

3. The array substrate of claim 1, wherein, The first voltage signal line is disposed on the side of the gate driving circuit away from the display area, and the second voltage signal line overlaps the gate driving circuit.

4. The array substrate of claim 1, wherein, Further comprising a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line being electrically connected with the gate driving circuit respectively, and the first clock signal line and the second clock signal line extending substantially along the second direction.

5. The array substrate of claim 1, wherein, Further comprising a third active pattern, the third active pattern being located on the side of the first active pattern close to the first voltage signal line; the third active pattern being substantially parallel to the first voltage signal line.

6. The array substrate of claim 1, wherein, The gate driving circuit comprises a shift register, the shift register comprising: a control circuit comprising a first control sub-circuit, the active layer of the transistor included in the first control sub-circuit being located in the first active pattern.

7. The array substrate of claim 6, wherein, The first control sub-circuit comprises a third transistor and a fourth transistor, the active layer of the third transistor and the fourth transistor being located in the first straight segment.

8. The array substrate of claim 1, wherein, The gate driving circuit comprises a shift register, the shift register comprising: a control circuit comprising a second control sub-circuit, the second control sub-circuit being coupled with a first node and a second node; the active layer of the transistor included in the second control sub-circuit being located in the first active pattern.

9. The array substrate of claim 8, wherein, Among the transistors included in the second control sub-circuit, the active layer of a part of the transistors is located in the third straight segment.

10. The array substrate of claim 7, wherein, Further comprising: a first gate conductive layer located on the side of the first active pattern away from the substrate; a first gate line being substantially perpendicular to the first voltage signal line; the orthogonal projection of the first gate line on the substrate overlaps the orthogonal projection of the second portion of the first straight segment in the first active pattern on the substrate; the first gate line being located in the first gate conductive layer.

11. The array substrate of claim 10, wherein, The first gate line overlaps the second portion of the first straight segment in the first active pattern to form the third transistor.

12. The array substrate of claim 1, wherein, The gate drive circuit comprises a shift register, and the shift register comprises: The first output circuit is coupled with the first node, the second node, a first voltage signal terminal, the second clock signal terminal and a signal output terminal; the first output circuit is configured to transmit a second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node, and transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node; the active layer of a transistor comprised in the first output circuit is located on the fifth active pattern. The first output circuit comprises a second capacitor, a first plate and a second plate of the second capacitor at least partially overlap, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the signal output terminal.

13. The array substrate of claim 1, wherein, The gate drive circuit comprises a shift register, and the shift register comprises: The first output circuit is coupled with the first node, the second node, a first voltage signal terminal, the second clock signal terminal and a signal output terminal; the first output circuit is configured to transmit a second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node, and transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node; the active layer of a transistor comprised in the first output circuit is located on the fifth active pattern. The first output circuit further comprises a third capacitor, a first plate and a second plate of the third capacitor at least partially overlap, the first plate of the third capacitor is electrically connected with the second node, and the second plate of the third capacitor is electrically connected with the first voltage signal terminal.

14. The array substrate of claim 1, wherein, Further comprising a fourth active pattern and a fifth active pattern, the fifth active pattern is located on a side of the fourth active pattern away from the first voltage signal line; The gate drive circuit comprises a shift register, and the shift register comprises: The first output circuit is coupled with the first node, the second node, a first voltage signal terminal, the second clock signal terminal and a signal output terminal; the first output circuit is configured to transmit a second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node, and transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node; the active layer of a transistor comprised in the first output circuit is located on the fifth active pattern.

15. The array substrate of claim 1, wherein, In a direction perpendicular to the substrate and away from the substrate, the array substrate comprises, in sequence, a semiconductor layer, a gate insulating layer, a first gate conductive layer, a first interlayer insulating layer, a second gate conductive layer, a second interlayer insulating layer and a source-drain conductive layer on the substrate.

16. The array substrate of claim 15, wherein, Further comprising a third active pattern, a fourth active pattern and a fifth active pattern, the third active pattern is located on a side of the first active pattern close to the first voltage signal line; the fifth active pattern is located on a side of the fourth active pattern away from the first voltage signal line; The first active pattern, the third active pattern, the fourth active pattern, and the fifth active pattern are located in the semiconductor layer.

17. The array substrate of claim 1, wherein, The gate drive circuit includes a shift register, which includes: A control circuit is coupled to a first node, a second node, a third node, and a first voltage signal terminal; the control circuit is configured to transmit a first voltage signal from the first voltage signal terminal to the second node and the third node under the control of a voltage from the first node; and to transmit a first voltage signal from the first voltage signal terminal to the first node under the control of a voltage from the second node.

18. The array substrate of claim 17, wherein, The control circuit includes a first control sub-circuit, which includes a third transistor and a fourth transistor. The first terminal of the third transistor is electrically connected to the first voltage signal terminal, the second terminal of the third transistor is electrically connected to the first node, and the third terminal of the third transistor is electrically connected to the second node. The first terminal of the fourth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the fourth transistor is electrically connected to the first node, and the third terminal of the fourth transistor is electrically connected to the second clock signal terminal.

19. The array substrate of claim 18, wherein, The shift register also includes: A first output circuit is coupled to the first node, the second node, a first voltage signal terminal, a second clock signal terminal, and a signal output terminal; the first output circuit is configured to transmit a second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node; and to transmit a first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node.

20. A display device comprising: Includes the array substrate as described in any one of claims 1-19.

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