Sparse 4C2+ phase detection autofocus and correlation multiple sampling

Abstract

This disclosure relates to sparse 4C2+ phase detection autofocus and correlated multiple sampling. An arithmetic logic unit includes: a GC-to-binary level; an adder stage; an adder output stage; an adder input latch stage coupled to latch the output of the GC-to-binary level; a feedback multiplexer stage coupled to receive the output of the GC-to-binary level; a latch output multiplexer coupled to receive the output of a first adder input latch, wherein the latch output multiplexer is configured to multiply the output of the first adder input latch by -1 or -2; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of the latch output multiplexer, and a second input of the adder input multiplexer stage is coupled to receive the output of a second adder input latch. The arithmetic logic performs adaptive correlated multiple sampling on image-sensing pixels and performs phase detection autofocus on other pixels.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on May 7, 2024, with application number 202410552807.X and invention title "Sparse 4C2+ Phase Detection Autofocus and Correlation Multiple Sampling". Technical Field

[0003] This disclosure generally relates to image sensors, and specifically, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. Background Technology

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, surveillance cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a growing expectation to enhance their functionality, performance metrics, and the like in as many ways as possible—e.g., resolution, power consumption, dynamic range—through both device architecture design and image acquisition and processing. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher resolution and lower power consumption has spurred further miniaturization and integration of these devices.

[0005] A typical image sensor operates in response to incident image light from an external scene. The image sensor includes a pixel array with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge in the process. The image charge generated by the pixel light can be measured as an analog output image signal on a bit line that varies depending on the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and this image charge is read out as an analog image signal from the bit line and converted into a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit line is coupled to a readout circuit that includes an input stage with analog-to-digital converter (ADC) circuitry to convert those analog image signals from the pixel array into digital image signals. Summary of the Invention

[0006] One aspect of this disclosure relates to an arithmetic logic unit (ALU) comprising: a front-end latch stage coupled to a Gray code (GC) generator to latch a GC output of the GC generator in response to a comparator output; a signal latch stage coupled to a latch output of the front-end latch stage in response to a signal latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC output latched in the signal latch stage; and an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the GC-to-binary representation. The adder stage outputs a binary level, wherein the output of the adder stage is generated in response to the first input and the second input of the adder stage; an adder output stage coupled to receive the output of the adder stage, wherein the adder output stage is configured to divide the output of the adder stage by 1 or 2; and an adder input latch stage coupled to latch the output of the GC to the binary level, wherein the adder input latch stage includes: a first adder input latch configured to latch the output of the GC to the binary level in response to a first adder input latch enable signal. ; and a second adder input latch configured to latch the output of the GC to the binary level in response to a second adder input latch enable signal; a feedback multiplexer stage coupled to receive the output of the GC to the binary level, wherein the feedback multiplexer stage includes: a first feedback multiplexer having a first input coupled to receive the output of the adder output stage and a second input coupled to receive the output of the GC to the binary level; and a second feedback multiplexer having a first input coupled to receive the output of the adder output stage and a second input coupled to receive the output of the GC to the binary level; and a second feedback multiplexer having a first input coupled to receive the output of the adder output stage and a second input coupled to receive the output of the adder output stage. A second input coupled to receive the output of the GC to the binary level; a latch output multiplexer coupled to receive the output of the first adder input latch, wherein the latch output multiplexer is configured to multiply the output of the first adder input latch by -1 or -2; and an adder input multiplexer stage, wherein the first input of the adder input multiplexer stage is coupled to receive the output of the latch output multiplexer, and the second input of the adder input multiplexer stage is coupled to receive the output of the second adder input latch.

[0007] Another aspect of this disclosure relates to a method of operating an arithmetic logic unit (ALU), comprising: configuring Gray code (GC) to a binary level to output a reset signal; configuring a first adder input latch of an adder input latch stage to latch the reset signal in response to a first adder input latch enable signal; configuring the GC to a binary level to output a first data signal; and, upon determining that the ALU is coupled to an image sensing pixel and the first data signal is not saturated—configuring a latch output multiplexer to convert the output of the first adder input latch into a single data signal. The output is multiplied by -2; the adder stage is configured to sum the output of the latch output multiplexer with the first data signal from the GC to binary stage; the second adder input latch of the adder input latch stage is configured to latch the output of the adder stage; the GC to binary stage is configured to output a second data signal; the adder stage is configured to sum the output of the second adder input latch with the second data signal from the GC to binary stage; and the adder output stage is configured to divide the output of the adder stage by 2.

[0008] Another aspect of this disclosure relates to a method of operating an arithmetic logic unit (ALU), comprising: configuring Gray code (GC) to a binary level to output a first reset signal; configuring a second adder input latch of an adder input latch stage to latch the first reset signal in response to a second adder input latch enable signal; configuring the GC to a binary level to output a second reset signal; configuring an adder stage to sum the output of the second adder input latch with the second reset signal from the GC to the binary level; configuring an adder output stage to divide the output of the adder stage by 2; configuring a first adder input latch of the adder input latch stage to latch the output of the adder output stage; and configuring the GC to a binary level to output a first data signal. When it is determined that the ALU is coupled to an image sensing pixel and the first data signal is not saturated—the latch output multiplexer is configured to multiply the output of the first adder input latch by -2; the adder stage is configured to sum the output of the latch output multiplexer with the first data signal from the GC to binary stage; the second adder input latch is configured to latch the output of the adder stage in response to the second adder input latch enable signal; the GC to binary stage is configured to output a second data signal; the adder stage is configured to sum the output of the second adder input latch with the second data signal from the GC to binary stage; and the adder output stage is configured to divide the output of the adder stage by 2. Attached Figure Description

[0009] The following figures illustrate non-limiting and non-exhaustive embodiments of this disclosure, wherein throughout the various views, the same reference numerals refer to the same portions unless otherwise specified.

[0010] Figure 1 This describes an example of an imaging system comprising a pixel array according to the teachings of this disclosure.

[0011] Figure 2 This describes a portion of an example readout circuit that includes a column analog-to-digital converter with a Gray code generator and parallel column arithmetic logic units, according to the teachings of this disclosure.

[0012] Figure 3 This describes the control of pixels during the readout period according to the teachings of this disclosure.

[0013] Figure 4 This describes a portion of an example arithmetic logic unit based on the teachings of this disclosure.

[0014] Figure 5 It is a table illustrating a sequence of instances of operations performed by an instance arithmetic logic unit in accordance with the teachings of this disclosure.

[0015] Figure 6 It is a table illustrating other instance sequences of operations performed by instance arithmetic logic units according to the teachings of this disclosure.

[0016] Figure 7 This describes a portion of another example of an arithmetic logic unit based on the teachings of this disclosure.

[0017] Throughout the various views of the drawings, corresponding reference numerals indicate the corresponding components. Those skilled in the art will understand that the elements in the drawings are for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the various embodiments of this disclosure. Additionally, common but well-understood elements that are useful or necessary in commercially viable embodiments are not typically depicted in order to contribute to a clearer understanding of these different embodiments of this disclosure. Detailed Implementation

[0018] Examples of imaging systems with arithmetic logic units that perform phase-detection autofocus and adaptive correlation multiple sampling are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0019] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of this disclosure. Therefore, the appearance of the phrase "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples in any suitable manner.

[0020] For ease of description, spatial relative terms such as “below,” “below,” “above,” “under,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is rotated or flipped, then an element described as “below,” “under,” or “below” other elements or features will be oriented as “above” other elements or features. Thus, the exemplary terms “below” and “under” may cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, it will be understood that when an element is described as being “between” two other elements, it may be the only element between the two other elements, or there may be one or more intervening elements.

[0021] Throughout this specification, several terms used are employed. These terms take on their ordinary meaning in the field from which they are derived, unless explicitly defined herein or the context in which they are used will clearly suggest otherwise. It should be noted that component names and symbols may be used interchangeably throughout this document (e.g., Si and silicon); however, they have the same meaning.

[0022] As will be discussed, various examples of imaging systems with an arithmetic logic unit that performs phase detection autofocus (PDAF) and adaptive correlated multiple sampling (CMS) are disclosed. PDAF operates by using a first set of one or more photodiodes to detect light from one side, a second set of one or more photodiodes to detect light from the other side, and measuring the phase difference between the two sets of photodiodes to determine the required autofocus for a particular image. Adaptive CMS operates by performing CMS when the benefits of using CMS outweigh the costs, for example, in dark conditions where the signal is weak and random noise from components of the readout circuitry dominates.

[0023] In various instances, an arithmetic logic unit (ALU) includes: a front-end latch stage coupled to a Gray code (GC) generator to latch the GC output of the GC generator in response to a comparator output; a semaphore latch stage coupled to the latch output of the front-end latch stage in response to a semaphore latch enable signal; a GC-to-binary stage coupled to generate a binary representation of the GC output latched in the semaphore latch stage; an adder stage including a first input and a second input, wherein the first input of the adder stage is coupled to receive the output of the GC-to-binary stage, wherein the output of the adder stage is generated in response to the first input and the second input; and an adder output stage coupled to receive the output of the adder stage, wherein the adder output stage is configured to divide the output of the adder stage by 1 or 2. The ALU further includes an adder input latch stage coupled to latch the output of the GC to the binary level. The adder input latch stage includes: a first adder input latch configured to latch the output of the GC to the binary level in response to a first adder input latch enable signal; and a second adder input latch configured to latch the output of the GC to the binary level in response to a second adder input latch enable signal. The ALU further includes a feedback multiplexer stage coupled to receive the output of the GC to the binary level. The feedback multiplexer stage includes: a first feedback multiplexer having a first input coupled to receive the output of the adder output stage and a second input coupled to receive the output of the GC to the binary level; and a second feedback multiplexer having a first input coupled to receive the output of the adder output stage and a second input coupled to receive the output of the GC to the binary level. The ALU further includes: a latch output multiplexer coupled to receive the output of the first adder input latch, wherein the latch output multiplexer is configured to multiply the output of the first adder input latch by -1 or -2; and an adder input multiplexer stage, wherein a first input of the adder input multiplexer stage is coupled to receive the output of the latch output multiplexer, and a second input of the adder input multiplexer stage is coupled to receive the output of the second adder input latch.

[0024] In various instances, a method of operating an ALU includes: configuring Gray code (GC) to a binary level to output a reset signal; configuring a first adder input latch of an adder input latch stage to latch the reset signal in response to a first adder input latch enable signal; and configuring the GC to a binary level to output a first image signal. When it is determined that the ALU is coupled to an image sensing pixel and the first image signal is not saturated, the method further includes configuring a latch output multiplexer to multiply the output of the first adder input latch by -2; configuring an adder stage to sum the output of the latch output multiplexer with the first image signal from the GC to binary stage; configuring a second adder input latch of the adder input latch stage to latch the output of the adder stage; configuring the GC to binary stage to output a second image signal; configuring the adder stage to sum the output of the second adder input latch with the second image signal from the GC to binary stage; and configuring an adder output stage to divide the output of the adder stage by 2.

[0025] To illustrate, Figure 1 An example of an imaging system 100 with readout circuitry 106 according to the teachings of this disclosure is shown. Specifically, Figure 1 The illustrated example describes an imaging system 100, which includes a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn), the pixel units 104 being arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to render images of people, places, objects, etc. In various examples, the pixel circuits P1, P2, ..., Pn include photodiodes configured to provide image data and photodiodes configured to provide PDAF data. In various examples, the photodiodes configured to provide PDAF data may be distributed among the photodiodes configured to provide image data.

[0026] In various instances, the readout circuit 106 may be configured to read out the image signal via the column bit line 112. As will be discussed, in various instances, the readout circuit 106 may include an analog-to-digital converter (ADC) 107 according to the teachings of this disclosure. In such instances, the digital image data value generated by the ADC in the readout circuit 106 may then be received by functional logic 108. The functional logic 108 may simply store the digital image data, or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.).

[0027] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of multiple photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with lighting effects (e.g., flash).

[0028] In one example, the imaging system 100 may be included in a digital camera, mobile phone, laptop computer, endoscope, security camera, or imaging device for automobiles. Furthermore, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting / flash, electrical inputs (keyboard, touchscreen, trackpad, mouse, microphone, etc.), and / or a display. Other hardware may send instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0029] Figure 2 This illustration describes a portion of an example readout circuit 206 comprising a column analog-to-digital converter with a Gray code generator 220 and a parallel column arithmetic logic unit (ALU) 218, according to the teachings of this disclosure. It should be understood that... Figure 2 The readout circuit 206 can be included in, for example Figure 1 The example shown is the readout circuit 106 in the imaging system 100, and the similarly named and numbered elements described above are similarly coupled and function in the following text.

[0030] As in Figure 2 As shown in the example depicted, a portion of the readout circuit 206 includes multiple comparators 216. Each of the multiple comparators 216 is coupled to receive a ramp signal 214, which in one example is a global ramp signal. Each of the multiple comparators 216 is further coupled to a corresponding one of a plurality of column bit lines 212 from the image sensor to receive a corresponding analog image or phase detection autofocus (PDAF) data signal from a column of the image sensor. As shown in the example, the outputs of the multiple comparators 216 are coupled in parallel to a corresponding column ALU 218. Each of the multiple ALUs 218 is also coupled to receive a Gray code (GC) output 222 generated by a shared Gray code (GC) generator 220 as shown. In one example, the GC output 222 generated by the GC generator 220 is a phase-aligned 13-bit Gray code signal.

[0031] In operation, each of the plurality of comparators 216 is coupled to generate a corresponding comparator output in response to a comparison of a corresponding analog image or PDAF data signal received from a corresponding bit line 212 with a ramp signal 214. In one example, a falling edge occurs at the output of the corresponding comparator 216 when the voltage of the ramp signal 214 slopes down to a value equal to or less than the voltage of the analog image or PDAF data signal carried by the corresponding column bit line 212. In this example, when a falling edge occurs at the output of the corresponding comparator 216 coupled to a corresponding column ALU 218, each corresponding column ALU 218 is coupled to sample and hold or latch a 13-bit Gray code signal 222 received from the GC generator 220. In various examples, each column ALU 218 is then configured to perform a Gray code to binary code conversion on the latched GC code signal 222.

[0032] In various instances, column ALU 218 is configured to extract image signals and PDAF signals and store them locally within the column ALU. It should be understood that, according to the teachings of this disclosure, digital power consumption is reduced by extracting and storing the PDAF signals locally within the image signal processor, rather than outside the column ALU 218. In various instances, according to the teachings of this disclosure, column ALU 218 can also be coupled to perform correlated multiple sampling (CMS) or operations in parallel by determining the differences between one or more reset signals and one or more data signals from the corresponding column bit lines 212 to generate normalized digital image signals or PDAF data from the image sensor. In one instance, the digital image or PDAF signal data extracted and stored within column ALU 218 can then be output to the corresponding global readout bit line of readout circuitry 206.

[0033] In one instance, Figure 2 The portion of the readout circuit 206 shown may be one of multiple portions of the readout circuit 206 that are repeated or "stitched together" across columns of the image sensor array. Figure 2 In the example shown, the image signal output from column ALU 218 can therefore be relayed from "right" to "left" through each portion of column ALU 218 of readout circuit 206, and wherein shift register readout 224 is coupled to the first and last columns and distributed between every N columns of the image sensor array to read out image or PDAF data from the image sensor array. For example, in an example of a 48-megapixel sensor array, there are 8,000 columns. In this example, a single GC generator 220 can be shared in every N = 500 columns of the sensor array, such that... Figure 2The total 16x portions of the readout circuit 206 shown are contained between shift register readouts 224 coupled to the first and last columns, and spread out every 500 columns to read out image signal outputs from the sensor array. In other words, the shift readout registers 224 are coupled to corresponding ALUs 218, which are coupled to the first and last columns of the image sensor. Furthermore, the shift registers 224 are coupled to and spread out among multiple ALUs 218 of each of the multiple readout circuits 206 to read out corresponding digital image data signals from the multiple ALUs 218.

[0034] Figure 3 This describes the control of pixel 304 during the readout period according to the teachings of this disclosure. It should be understood that... Figure 3 Pixel 304 can be included in, for example Figure 1 Examples of pixels 104 in the imaging system 100 shown herein, and similarly named and numbered elements described above are similarly coupled and function below.

[0035] In the illustrated embodiment, each pixel 304 includes four photodiodes and four transfer transistors. Each transfer transistor is configured to be controlled by one of six different control signals labeled 1 to 6, as shown in FIG311. Pixel 304 may be an image sensing pixel 304a or a phase detection autofocus (PDAF) pixel 304b. The transfer transistors of the image sensing pixel 304a are configured to be controlled via control signals 1 to 4, while the PDAF pixel 304b is configured to be controlled via control signals 1, 3, 5, and 6. In the illustrated embodiment, the PDAF pixel 304b is located in every three pixels and in every four rows. In other embodiments, different arrangements of the PDAF pixel 304b are possible.

[0036] Referring to the timing diagram of transfer control signals 1 to 4 305a, transfer control signals 5 and 6 305b, and ramp 314, the first ramp signal 315a corresponds to the left PDAF extraction via PDAF pixel 304b in each figure 313. The second ramp signal 315b corresponds to the left and right PDAF extractions of each PDAF pixel 304b in each figure 315. The third ramp signal 315c corresponds to the first image signal readout of each image sensing pixel 304a in each figure 317. The fourth ramp signal 315d corresponds to the second image signal readout of each image sensing pixel 304a in each figure 319. As shown, transfer control signals 1 to 4 305a are pulsed simultaneously before the left PDAF extraction ramp signal 315a and the first image signal ramp signal 315c. The transfer control signals 5 and 6 305b are pulsed simultaneously before the left and right PDAF extraction ramp signals 315b, allowing for partial independent control of the image sensing pixel 304a and the PDAF pixel 304b.

[0037] Figure 4 This description is a portion of an example of an arithmetic logic unit (ALU) 418, based on the teachings of this disclosure. It should be understood that... Figure 4 ALU 418 can be included in, for example Figure 2 The example shown is of one of the ALUs 218 in the readout circuit 206, and similarly named and numbered components described above are similarly coupled and function below. It should also be understood that... Figure 4 The section depicting the ALU 418 illustrates the circuitry for processing one of the bits of the ALU 418. For example, in various instances, it should be noted that each of the plurality of ALUs 418 is coupled to sample and hold or latch the corresponding bit of the received 12-bit Gray code q_gc<11:0> 422 in response to the arrival of the falling edge of the comparator output cmpout 450, in order to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 422 into a binary value.

[0038] To illustrate, Figure 4The example ALU 418 shown includes a front-end latch stage 426 coupled to receive and latch the corresponding bits of the Gray code q_gc<11:0> 422 signal in response to the comparator output cmpout 450. In the illustrated example, each latch of the front-end latch stage 426 has a data input “D” coupled to receive the corresponding bits of the Gray code q_gc<11:0>. The ALU 418 also includes a pulse generator 444 coupled to receive the comparator output cmpout 450 from the corresponding comparator in the column (e.g., comparator 216). In one example, the pulse generator 444 is coupled to generate a front-end latch enable signal 452 in response to the arrival of a falling edge in the comparator output cmpout 450. In one example, the pulse of the front-end latch enable signal 452 is coupled to the enable input of each latch in the front-end latch stage 426.

[0039] In the depicted example, ALU 418 also includes a signal latch stage 428 coupled to the output of front-end latch stage 426. In operation, signal latch stage 428 is coupled to the latch output of front-end latch stage 426 in response to a signal latch enable signal wen_sig 454. As shown in the depicted example, each latch of signal latch stage 428 includes a data input "D" coupled to the "Q" output of the corresponding latch in front-end latch stage 426. Figure 4 The example shown illustrates that ALU 418 also includes a GC-to-binary stage (e.g., G2B) 430, which is coupled to generate a binary representation of the Gray code q_gc<11:0> 422 signal value latched in front-end latch stage 426. In one example, GC-to-binary stage 430 includes a plurality of XOR gates (not shown), each of which has an output coupled to generate a corresponding binary bit and a first input coupled to receive the corresponding “Q” output of the corresponding latch of signal latch stage 428.

[0040] As in Figure 4As illustrated in the example depicted, ALU 418 also includes an adder stage 438 comprising a plurality of full adders, each having a first input coupled via wire 458 to the output of GC-to-binary stage 430 and a second input coupled to the output of adder input multiplexer stage 437, which will be described in more detail below. In operation, the output of adder stage 438 is generated in response to the first input from GC-to-binary stage 430 and the second input from adder input multiplexer stage 437 and is sent to adder output stage 439, which is configured to divide the output of the adder stage by 1 or 2. In one example, the output of adder stage 438 is configured to determine the difference between the value received at the first input of adder input multiplexer stage 437 and the value received at its second input.

[0041] continue Figure 4 In the example depicted, ALU 418 further includes an adder input latch stage 431 coupled to latch the GC to the output of binary stage 430. In one example, adder input latch stage 431 includes a first adder input latch 432a configured to latch the GC to the output of binary stage 430 in response to a first adder input latch enable signal wen_1st 456a. In this example, adder input stage 431 also includes a second adder input latch 432b configured to latch the GC to the output of binary stage 430 in response to a second adder input latch enable signal wen_2nd 456b. In the depicted example, latch output multiplexer 436 is coupled to receive the output of first adder input latch 432a and configured to multiply the output of the first adder input latch by -1 or -2. Alternatively, adder stage 438 can be used to effectively multiply the output of the first adder input latch by -1 or -2.

[0042] ALU 418 may also include a feedback multiplexer stage 433 coupled to receive the output of GC to binary stage 430. In the illustrated example, feedback multiplexer stage 433 includes: a first feedback multiplexer 434 having a first input coupled to receive the output of adder output stage 439 and a second input coupled to receive the output of GC to binary stage 430; and a second feedback multiplexer 435 having a first input coupled to receive the output of adder output stage 439 and a second input coupled to receive the output of GC to binary stage 430. In operation, a first adder input latch 432a is coupled to latch the output of the first feedback multiplexer 434, and a second adder input latch 432b is coupled to latch the output of the second feedback multiplexer 435.

[0043] Figure 4 The example shown in the diagram illustrates that the ALU 418 also includes a data latch stage 442, which is coupled to latch the output of the adder output stage 439. As illustrated in the depicted example, the data latch stage 442 includes a first data latch 440a and a second data latch 440b. As will be discussed in more detail below, the first data latch 440a is configured to latch a phase detection signal from the output of the adder output stage 439 in response to a first data latch enable signal wwl_PDL 464a, and the second data latch 440b is configured to latch an image data signal from the output of the adder output stage 439 in response to a second data latch enable signal wwl_sum 464b. In the illustrated example, the phase detection signal latched in the first data latch 440a and the image data signal latched in the second data latch 440b are output from ALU 418 as output bits rbl<11:0> 447 through output switches rwl_pdl 443a and rwl_cdssig 443b, respectively.

[0044] ALU 418 may also include a determining block 470, which is coupled to receive comparator output cmpout 450 and configured to output at least one of a second adder input latch enable signal wen_2nd 456b, a control signal for latch output multiplexer 436, a control signal for adder input multiplexer stage 437, and a control signal for adder output stage 439. Determining block 470 may include at least one of a saturation circuit 472 configured to saturate a signal (e.g., a PDAF signal, an image signal) and a PDAF circuit 474 configured to determine whether a particular ALU 418 is coupled to a PDAF pixel or an image sensing pixel. (The following text is about...) Figure 4 and 5To describe it further, the determining block 470 can control specific operations performed by the ALU 418 based on whether it is a coupled PDAF pixel or an image sensing pixel and whether the data signal is saturated. In other embodiments, the determining block 470 may be external to the ALU 418.

[0045] Figure 5 This is a table illustrating a sequence of instances of operations performed by an instance arithmetic logic unit according to the teachings of this disclosure. It should be understood that... Figure 5 The operation sequence described herein can be derived from Figure 4 The ALU 418 performs a sequence of operations, and the similarly named and numbered elements described above are similarly coupled and function below.

[0046] like Figure 5 As shown, at least four distinct operation sequences can exist, labeled I, II, III, and IV. The ALU can be configured to be based on a defined block (e.g., Figure 4 The output of the determining block 470 described herein is selected from these different operation sequences. For example, the PDAF circuit 574 may be configured to determine whether a particular ALU is coupled to a PDAF pixel or an image sensing pixel, and the saturation circuit 572 may be configured to determine the saturation of a data signal (e.g., a PDAF signal or an image signal). In other embodiments, the ALU may select a specific operation sequence based on different circuit systems and / or different factors.

[0047] In the illustrated table, regardless of the specific sequence of operations performed by the ALU, the read timing 530 can be configured such that the Gray code (GC) to binary stage sequentially outputs a reset signal (“rst”) following the first ramp, a first data signal (“sig1”) following the second ramp, and a second data signal (“sig2”) following the third ramp. Each of these signals is directly sent to the adder stage via wire 558 carrying the signal last output from the GC to the binary stage, which can be configured to perform at least a portion of the ALU operation 538. Furthermore, regardless of the specific sequence of operations performed by the ALU, the first adder input latch 532a can be configured to latch the reset signal rst until the end of the third ramp. The GC to binary stage is then configured to output the first data signal sig1.

[0048] When it is determined that the ALU is coupled to the image sensing pixel and the first data signal sig1 (i.e., the first image signal for the image sensing pixel) is not saturated, the ALU may execute a first described sequence of operations (“Sequence I”). Because the first data signal sig1 is not saturated, the pixel may be under low-light conditions, and performing CMS may be advantageous. Sequence I includes configuring a latch output multiplexer (e.g., latch output multiplexer 336) to multiply the output of the first adder input latch by -2, configuring an adder input multiplexer stage (e.g., adder input multiplexer stage 337) to output the output of the latch output multiplexer, and configuring an adder stage (e.g., adder stage 338) to sum the output of the latch output multiplexer with the first data signal sig1 from GC to the binary stage. Then, the adder output stage (e.g., adder output stage 339) divides the output of the adder stage by 1, the second feedback multiplexer (e.g., second feedback multiplexer 335) receives the output of the adder output stage, and sequence I further includes configuring the second adder input latch 532b to latch the output of the adder stage from the second feedback multiplexer. At this time, the second adder input latch may have latched sig1-rst-rst. Then, sequence I includes configuring the GC to binary stage to output the second data signal sig2, configuring the adder stage to sum the output of the second adder input latch with the second data signal sig2 from the GC to binary stage, and configuring the adder output stage to divide the output of the adder stage by 2. At this time, the output of the adder output stage may be (sig1+sig2) / 2-rst, and the second data latch 540b may be configured to then latch the output of the adder output stage.

[0049] When it is determined that the ALU is coupled to the image sensing pixel and the first data signal sig1 (i.e., the first image signal for the image sensing pixel) is saturated, the ALU may execute a second described sequence of operations (“Sequence II”). Because the first data signal sig1 is saturated and therefore unreliable, the pixel may be under bright lighting conditions, and CMS should be avoided. Sequence II includes configuring the GC-to-binary stage to output the second data signal sig2, configuring the latch output multiplexer to multiply the output of the first adder input latch by -1, and configuring the adder stage to sum the output of the latch output multiplexer with the second data signal sig2 from the GC-to-binary stage. The adder output stage may be configured to divide the output of the adder stage by 1 to produce sig2-rst. Then, Sequence II may include configuring the second data latch 540b to latch the output of the adder output stage.

[0050] When it is determined that the ALU is coupled to the PDAF pixel and the first data signal sig1 (e.g., the left-hand signal sigL for the PDAF pixel) is not saturated, the ALU may execute the third described operation sequence (“Sequence III”). Because the first data signal sig1 is not saturated, the imaging system may appropriately perform PDAF extraction. Sequence III includes configuring a latch output multiplexer to multiply the output of the first adder input latch by -1, configuring the adder stage to sum the output of the latch output multiplexer with the first data signal sig1 from GC to the binary stage, and configuring the first data latch 540a to latch the output of the adder stage, which may be sig1-rst at this time. Then, sequence III includes configuring the GC to the binary stage to output a second data signal sig2 (e.g., the left and right signals sigL+sigR for PDAF), configuring the adder stage to sum the output of the latch output multiplexer with the second data signal sig2 from the GC to the binary stage, and configuring the second data latch 540b to latch the output of the adder stage, which can be sig2-rst at this time.

[0051] When it is determined that the ALU is coupled to an image sensing pixel and the first data signal sig1 (e.g., the left signal sigL for the PDAF pixel) is saturated, the ALU may execute the fourth described operation sequence (“Sequence IV”). Because the first data signal sig1 is saturated and therefore unreliable, the pixel may be under bright lighting conditions, thus avoiding PDAF execution. Sequence IV includes configuring a latch output multiplexer to multiply the output of the first adder input latch by -1, and configuring the first data latch 540a to latch a PDAF saturation flag, indicating that the signal is not suitable for performing PDAF. Sequence IV also includes configuring the GC to binary stage to output a second data signal sig2 (e.g., the left and right signals sigL+sigR for PDAF), configuring the adder stage to sum the output of the latch output multiplexer with the second data signal sig2 from the GC to binary stage, and configuring the second data latch 540b to latch the output of the adder stage, which may be sig2-rst at this time.

[0052] By executing one of sequences I, II, III, and IV, the same ALU can perform adaptive CMS (“Signal CMS”) using signals from image sensing pixels and adaptive PDAF using signals from PDAF pixels, without requiring an additional ALU, each of which is suitable for performing a specific sequence.

[0053] Figure 6 This is a table illustrating other instance sequences of operations performed by the instance arithmetic logic unit according to the teachings of this disclosure. It should be understood that... Figure 6 The operation sequence described herein can be derived from Figure 4 The ALU 418 performs a sequence of operations, and the similarly named and numbered elements described above are similarly coupled and function below.

[0054] like Figure 6 As shown, at least four distinct operation sequences can exist, labeled I, II, III, and IV. The ALU can be configured to be based on a defined block (e.g., Figure 4 The output of the determining block 470 described herein is selected from these different operation sequences. For example, the PDAF circuit 674 may be configured to determine whether a particular ALU is coupled to a PDAF pixel or an image sensing pixel, and the saturation circuit 672 may be configured to determine the saturation of a data signal (e.g., a PDAF signal or an image signal). In other embodiments, the ALU may select a specific operation sequence based on different circuit systems and / or different factors.

[0055] In the illustrated table, regardless of the specific sequence of operations performed by the ALU, the read timing 630 can be configured such that the Gray code (GC) to binary stage sequentially outputs a first reset signal (“rst1”) following the first ramp, a second reset signal (“rst2”) following the second ramp, a first data signal (“sig1”) following the third ramp, and a second data signal (“sig2”) following the fourth ramp. Each of these signals is sent directly to the adder stage via wire 558 carrying the signal finally output from the GC to the binary stage, and the adder stage can be configured to perform at least a portion of the ALU operation 638. Furthermore, regardless of the specific sequence of operations performed by the ALU, the second adder input latch 632b can be configured to latch the first reset signal rst1, the GC-to-binary stage can be configured to output the second reset signal rst2, the adder stage can be configured to sum the output of the second adder input latch 632b with the second reset signal rst2, the adder output stage can be configured to divide the output of the adder stage by 2, and the first adder input latch 632a can be configured to latch the output of the adder output stage, which can be (rst1+rst2) / 2 at this time. Then, the GC-to-binary stage can be configured to output the first data signal sig1.

[0056] When it is determined that the ALU is coupled to the image sensing pixel and the first data signal sig1 (i.e., the first image signal for the image sensing pixel) is not saturated, the ALU may execute the first described operation sequence (“Sequence I”). Because the first data signal sig1 is not saturated, the pixel may be under low-light conditions, and performing CMS may be advantageous. Sequence I includes configuring a latch output multiplexer to multiply the output of the first adder input latch by -2, configuring an adder stage to sum the output of the latch output multiplexer with the first data signal sig1 from the GC to the binary stage, and configuring the second adder input latch 632b to latch the output of the adder stage. Sequence I also includes configuring the GC to the binary stage to output a second data signal sig2, configuring the adder stage to sum the output of the second adder input latch 632b with the second data signal sig2 from the GC to the binary stage, and configuring the adder output stage to divide the output of the adder stage by 2. At this time, the output of the adder output stage can be (sig1+sig2-rst1-rst2) / 2, and the second data latch 640b can be configured to latch the output of the adder output stage.

[0057] When it is determined that the ALU is coupled to the image sensing pixel and the first data signal sig1 (i.e., the first image signal for the image sensing pixel) is saturated, the ALU may execute the second described operation sequence (“Sequence II”). Because the first data signal sig1 is saturated and therefore unreliable, the pixel may be under bright lighting conditions, and CMS should be avoided. Sequence II includes configuring a latch output multiplexer to multiply the output of the first adder input latch 632a by -1, configuring the GC to binary stage to output the second data signal sig2, and configuring the adder stage to sum the output of the first adder input latch 632a with the second data signal sig2 from the GC to binary stage to produce sig2-rst, where rst is the average of the first and second reset signals (i.e., (rst1+rst2) / 2). Then, Sequence II may include configuring a second data latch 640b to latch the output of the adder stage.

[0058] When it is determined that the ALU is coupled to the PDAF pixel and the first data signal sig1 (e.g., the left-hand signal sigL for the PDAF pixel) is not saturated, the ALU may execute the third described operation sequence (“Sequence III”). Because the first data signal sig1 is not saturated, the imaging system may appropriately perform PDAF extraction. Sequence III includes configuring a latch output multiplexer to multiply the output of the first adder input latch 632a by -1, configuring the adder stage to sum the output of the latch output multiplexer with the first data signal sig1 from GC to the binary stage, and configuring the first data latch 640a to latch the output of the adder stage. Subsequently, sequence III includes configuring the GC to the binary stage to output a second data signal sig2 (e.g., the left and right signals sigL+sigR for PDAF), configuring the adder stage to sum the output of the latch output multiplexer with the second data signal sig2 from the GC to the binary stage, and configuring the second data latch 640b to latch the output of the adder stage, which may be sig2-rst at this time.

[0059] When it is determined that the ALU is coupled to an image sensing pixel and the first data signal sig1 (e.g., the left signal sigL for the PDAF pixel) is saturated, the ALU may execute the fourth described operation sequence (“Sequence IV”). Because the first data signal sig1 is saturated and therefore unreliable, the pixel may be under bright lighting conditions, thus avoiding PDAF execution. Sequence IV includes configuring a latch output multiplexer to multiply the output of the first adder input latch 632a by -1, and configuring the first data latch 640a to latch a PDAF saturation flag, indicating that the signal is not suitable for PDAF execution. Sequence IV also includes configuring the GC to binary stage to output a second data signal sig2 (e.g., the left and right signals sigL+sigR for PDAF), configuring the adder stage to sum the output of the latch output multiplexer with the second data signal sig2 from the GC to binary stage, and configuring the second data latch 640b to latch the output of the adder stage, which may be sig2-rst at this time.

[0060] By executing one of sequences I, II, III, and IV, the same ALU can perform adaptive CMS (“true CMS”) using signals from image sensing pixels and adaptive PDAF using signals from PDAF pixels, without requiring an additional ALU, each of which is suitable for performing a specific sequence.

[0061] Figure 7 This describes a portion of another example of the teachings of this disclosure, arithmetic logic unit 718. It should be understood that... Figure 7 ALU 718 can be included in, for example Figure 2The example shown is of one of the ALUs 218 in the readout circuit 206, and similarly named and numbered components described above are similarly coupled and function below. It should also be understood that... Figure 7 The section depicting the ALU 718 illustrates the circuitry for processing one of the bits of the ALU 718. For example, in various instances, it should be noted that each of the plurality of ALUs 718 is coupled to sample and hold or latch the corresponding bit of the received 12-bit Gray code q_gc<11:0> 722 in response to the arrival of the falling edge of the comparator output cmpout 750, so as to perform analog-to-digital conversion by converting the latched 12-bit Gray code q_gc<11:0> 722 into a binary value.

[0062] To illustrate, Figure 7 The example ALU 718 shown includes a front-end latch stage 726 coupled to receive and latch the corresponding bits of the Gray code q_gc<11:0> 722 signal in response to a comparator output cmpout 750. In the illustrated example, each latch of the front-end latch stage 726 has a data input “D” coupled to receive the corresponding bits of the Gray code q_gc<11:0>. The ALU 718 also includes a pulse generator 744 coupled to receive the comparator output cmpout 750 from the corresponding comparator in the column (e.g., comparator 216). In one example, the pulse generator 744 is coupled to generate a front-end latch enable signal 752 in response to the arrival of a falling edge in the comparator output cmpout 750. In one example, the pulse of the front-end latch enable signal 752 is coupled to the enable input of each latch in the front-end latch stage 726.

[0063] In the depicted example, ALU 718 also includes a signal latch stage 728 coupled to the output of front-end latch stage 726. In operation, signal latch stage 728 is coupled to the latch output of front-end latch stage 726 in response to a signal latch enable signal wen_sig 754. As shown in the depicted example, each latch of signal latch stage 728 includes a data input "D" coupled to the "Q" output of the corresponding latch in front-end latch stage 726. Figure 7The example shown illustrates that the ALU 718 also includes a GC-to-binary stage (e.g., G2B) 730, which is coupled to generate a binary representation of the Gray code q_gc<11:0> 722 signal value latched in the front-end latch stage 726. In one example, the GC-to-binary stage 730 includes a plurality of XOR gates (not shown), each of which has an output coupled to generate a corresponding binary bit and a first input coupled to receive the corresponding “Q” output of the corresponding latch of the signal latch stage 728.

[0064] As in Figure 7 As illustrated in the example depicted, the ALU 718 also includes an adder stage 738 comprising a plurality of full adders, each having a first input coupled via wire 758 to the output of the GC-to-binary stage 730 and a second input coupled to the output of the adder input multiplexer stage 737, which will be described in more detail below. In operation, the output of the adder stage 738 is generated in response to the first input from the GC-to-binary stage 730 and the second input from the adder input multiplexer stage 737 and is sent to an adder output stage 739, which is configured to divide the output of the adder stage by 1 or 2. In one example, the output of the adder stage 738 is configured to determine the difference between the value received at the first input of the adder input multiplexer stage 737 and the value received at its second input.

[0065] continue Figure 7In the example depicted, ALU 718 further includes an adder input latch stage 731 coupled to latch the GC to the output of binary stage 730. In one example, adder input latch stage 731 includes a first adder input latch 732a configured to latch the GC to the output of binary stage 730 in response to a first adder input latch enable signal wen_1st 756a. In the same example, adder input stage 731 also includes a second adder input latch 732b configured to latch the GC to the output of binary stage 730 in response to a second adder input latch enable signal wen_2nd 756b. Adder input stage 731 may further include a third adder input latch 732c, which is configured to latch GC to the output of binary stage 730 in response to a third adder input latch enable signal wen_3rd 756c. The third adder input latch 732c may be configured to latch a low conversion gain (LCG) signal, enabling ALU 718 to perform double conversion gain (DCG) calculations. A third input of adder input multiplexer stage 737 may be coupled to receive the output of the third adder input latch 732c.

[0066] In the depicted example, latch output multiplexer 736 is coupled to receive the output of first adder input latch 732a and configured to multiply the output of the first adder input latch by -1 or -2. Alternatively, adder stage 738 can be used to effectively multiply the output of the first adder input latch by -1 or -2.

[0067] ALU 718 may also include a feedback multiplexer stage 733 coupled to receive the output of GC to binary stage 730. In the illustrated example, feedback multiplexer stage 733 includes: a first feedback multiplexer 734 having a first input coupled to receive the output of adder output stage 739 and a second input coupled to receive the output of GC to binary stage 730; and a second feedback multiplexer 735 having a first input coupled to receive the output of adder output stage 739 and a second input coupled to receive the output of GC to binary stage 730. In operation, a first adder input latch 732a is coupled to latch the output of the first feedback multiplexer 734, and a second adder input latch 732b is coupled to latch the output of the second feedback multiplexer 735.

[0068] Figure 7The example shown in the diagram illustrates that the ALU 718 also includes a data latch stage 742, which is coupled to latch the output of the adder output stage 739. As illustrated in the depicted example, the data latch stage 742 includes a first data latch 740a, a second data latch 740b, and a third data latch 740c. The first data latch 740a is configured to latch a phase detection signal from the output of the adder output stage 739 in response to a first data latch enable signal wwl_PDL 764a; the second data latch 740b is configured to latch an image data signal from the output of the adder output stage 739 in response to a second data latch enable signal wwl_sum 764b; and the third data latch 740c is configured to latch an LCG image data signal from the output of the adder output stage 739 in response to a third data latch enable signal wwl_LCG 764c. In the illustrated example, the phase detection signal latched in the first data latch 740a and the image data signal latched in the second data latch 740b are output from the ALU 718 as output bits rbl<11:0> 747 via output switches rwl_pdl 743a and rwl_cdssig 743b, respectively.

[0069] ALU 718 may also include a determining block 770, which is coupled to receive comparator output cmpout 750 and configured to output a second adder input latch enable signal wen_2nd 756b, a control signal for latch output multiplexer 736, a control signal for adder input multiplexer stage 737, and a control signal for adder output stage 739. Determining block 770 may include at least one of a saturation circuit 772 configured to saturate a signal (e.g., a PDAF signal, an image signal) and a PDAF circuit 774 configured to determine whether a particular ALU 718 is coupled to a PDAF pixel or an image sensing pixel. Similar to the above description... Figure 5 and 6 The detailed operation describes how determining block 770 can control specific operations performed by ALU 718 based on whether a PDAF pixel or an image sensing pixel is coupled and whether the data signal is saturated. In other embodiments, determining block 770 may be external to ALU 718.

[0070] The above description of the illustrative examples in this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to its precise form. As those skilled in the art will recognize, while specific examples of this disclosure have been described herein for illustrative purposes, various modifications are possible within the scope of this disclosure.

[0071] These modifications may be made to this disclosure in light of the detailed description above. The terminology used in the following claims should not be construed as limiting this disclosure to the specific instances disclosed in the specification. Rather, the scope of this disclosure should be determined entirely by the following claims, which should be interpreted according to the established theory of interpretation.

Claims

1. A method for operating an arithmetic logic unit (ALU), the method comprising: Configure Gray code to binary G2B level to output a reset signal; Configure the first adder input latch of the adder input latch stage to latch the reset signal in response to the first adder input latch enable signal; Configure the G2B stage to output a first data signal; and When it is determined that the ALU is coupled to the image sensing pixel and the first data signal is not saturated— Configure a latch output multiplexer to multiply the output of the first adder input latch by -2. Configure the adder stage to sum the output of the latch output multiplexer with the first data signal from the G2B stage. Configure the second adder input latch of the adder input latch stage to latch the output of the adder stage. Configure the G2B stage to output a second data signal. The adder stage is configured to sum the output of the second adder input latch with the second data signal from the G2B stage, and Configure the adder output stage to divide the output of the adder stage by 2.

2. The method of claim 1, further comprising, when determining that the ALU is coupled to an image sensing pixel and the first data signal is not saturated, configuring a second data latch to latch the output of the adder output stage in response to a second data latch enable signal.

3. The method of claim 1, further comprising, upon determining that the ALU is coupled to an image sensing pixel and the first data signal is saturated— Configure the G2B stage to output a second data signal; Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; and The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage.

4. The method of claim 3, further comprising, upon determining that the ALU is coupled to an image sensing pixel and the first data signal is saturated, configuring a second data latch to latch the output of the adder output stage in response to a second data latch enable signal.

5. The method of claim 1, further comprising, when it is determined that the ALU is coupled to a phase detection autofocus (PDAF) pixel and the first data signal is not saturated— Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; The adder stage is configured to sum the output of the latch output multiplexer with the first data signal from the G2B stage; Configure a first data latch to latch the output of the adder stage in response to a first data latch enable signal; Configure the G2B stage to output a second data signal; The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage; and Configure a second data latch to latch the output of the adder stage in response to a second data latch enable signal.

6. The method of claim 1, further comprising, upon determining that the ALU is coupled to a phase detection autofocus (PDAF) pixel and the first data signal is saturated— Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; Configure the first data latch to latch the PDAF saturation flag; Configure the G2B stage to output a second data signal; The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage; and Configure a second data latch to latch the output of the adder stage in response to a second data latch enable signal.

7. A method for operating an arithmetic logic unit (ALU), the method comprising: Configure Gray code to binary G2B level to output the first reset signal; Configure the second adder input latch of the adder input latch stage to latch the first reset signal in response to the second adder input latch enable signal; Configure the G2B stage to output a second reset signal; Configure the adder stage to sum the output of the second adder input latch with the second reset signal from the G2B stage; Configure the adder output stage to divide the output of the adder stage by 2; Configure the first adder input latch of the adder input latch stage to latch the output of the adder output stage; Configure the G2B stage to output a first data signal; and When it is determined that the ALU is coupled to the image sensing pixel and the first data signal is not saturated— Configure a latch output multiplexer to multiply the output of the first adder input latch by -2. The adder stage is configured to sum the output of the latch output multiplexer with the first data signal from the G2B stage. Configure the second adder input latch to latch the output of the adder stage in response to the second adder input latch enable signal. Configure the G2B stage to output a second data signal. The adder stage is configured to sum the output of the second adder input latch with the second data signal from the G2B stage, and Configure the adder output stage to divide the output of the adder stage by 2.

8. The method of claim 7, further comprising, when determining that the ALU is coupled to an image sensing pixel and the first data signal is not saturated, configuring a second data latch to latch the output of the adder output stage in response to a second data latch enable signal.

9. The method of claim 7, further comprising, upon determining that the ALU is coupled to an image sensing pixel and the first data signal is saturated— Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; Configure the G2B stage to output a second data signal; and The adder stage is configured to sum the output of the first adder input latch with the first data signal from the G2B stage.

10. The method of claim 9, further comprising, upon determining that the ALU is coupled to an image sensing pixel and the first data signal is saturated, configuring a second data latch to latch the output of the adder stage in response to a second data latch enable signal.

11. The method of claim 7, further comprising, upon determining that the ALU is coupled to a phase-detection autofocus (PDAF) pixel and the first data signal is not saturated— Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; The adder stage is configured to sum the output of the latch output multiplexer with the first data signal from the G2B stage; Configure a first data latch to latch the output of the adder stage in response to a first data latch enable signal; Configure the G2B stage to output a second data signal; The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage; and Configure a second data latch to latch the output of the adder stage in response to a second data latch enable signal.

12. The method of claim 7, further comprising, upon determining that the ALU is coupled to a phase-detection autofocus (PDAF) pixel and the first data signal is saturated— Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; Configure the first data latch to latch the PDAF saturation flag; Configure the G2B stage to output a second data signal; The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage; and Configure a second data latch to latch the output of the adder stage in response to a second data latch enable signal.

13. The method of claim 7, further comprising configuring the first adder input latch to latch the average value of the first reset signal and the second reset signal.

14. The method of claim 7, further comprising configuring the PDAF circuitry of the ALU to determine whether the ALU is coupled to the image sensing pixel or the phase detection autofocus PDAF pixel.

15. A method for operating an arithmetic logic unit (ALU), the method comprising: Receives the comparator output generated in response to the comparison between the analog signal from the column line and the ramp signal; In response to the falling edge in the comparator output, a front-end latch enable signal is generated; In response to the front-end latch enable signal, the Gray code output from the Gray code generator is latched in the front-end latch stage; In response to a signal latch enable signal, the output of the front-end latch stage is latched in the signal latch stage; The latched Gray code output is converted to a binary representation using the Gray code to binary G2B level. Determine whether the ALU is coupled to an image sensing pixel or a phase detection autofocus (PDAF) pixel; and Based at least in part on the determination, one of the associated multiple sampling operation and the phase detection autofocus operation is selectively performed.

16. The method of claim 15, further comprising using a saturation circuit of the ALU to determine whether the data signal is saturated.

17. The method of claim 16, wherein selectively performing the correlated multiple sampling operation comprises, when determining that the ALU is coupled to the image sensing pixel and the data signal is not saturated, performing the following operations: Configure a latch output multiplexer to multiply the output of the first adder input latch by -2; Configure the adder stage to sum the output of the latch output multiplexer with the first data signal from the G2B stage; Configure a second adder input latch to latch the output of the adder stage; The adder stage is configured to sum the output of the second adder input latch with the second data signal from the G2B stage; and Configure the adder output stage to divide the output of the adder stage by 2.

18. The method of claim 16, wherein selectively performing the phase detection autofocus operation comprises, when determining that the ALU is coupled to the PDAF pixel and the data signal is not saturated, performing the following operations: Configure the latch output multiplexer to multiply the output of the first adder input latch by -1; Configure the adder stage to sum the output of the latch output multiplexer with the first data signal from the G2B stage; Configure a first data latch to latch the output of the adder stage; The adder stage is configured to sum the output of the latch output multiplexer with the second data signal from the G2B stage; and Configure a second data latch to latch the output of the adder stage.

19. The method of claim 15, wherein latching the Gray code output from the Gray code generator comprises latching the Gray code output from a Gray code generator shared in a plurality of column ALUs of the image sensor readout circuit.

20. The method of claim 15, further comprising outputting a digital image data signal or a phase detection signal from the ALU to a shift register for reading via an output switch.

21. The method of claim 15, wherein determining whether the ALU is coupled to the image sensing pixel or the PDAF pixel comprises using PDAF circuitry employing the ALU to determine whether the ALU is coupled to the image sensing pixel or the PDAF pixel.

22. The method of claim 15, further comprising: The output of the adder output stage of the ALU is provided to the first input of the feedback multiplexer stage of the ALU; and The output of the G2B stage is provided to the second input of the feedback multiplexer stage.

23. The method of claim 1, further comprising configuring the front-end latch stage of the ALU to latch Gray code output from the Gray code generator in response to comparator output.

24. The method of claim 1, further comprising configuring a phase detection autofocus (PDAF) circuit of the ALU to determine whether the ALU is coupled to the image sensing pixel or the PDAF pixel.

25. The method of claim 1, further comprising configuring a saturation circuit of the ALU to determine whether the first data signal is saturated.

Images