Arithmetic logic unit register sequencing

Abstract

A graphics processing unit (GPU) [100] orders the provision of operands to a set of operand registers [106], thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) [108], where at least one of the ALUs [116] is configured to perform double precision operations. The GPU also includes a set of operand registers configured to store single precision operands. For a plurality of execution threads requesting double precision operations, the GPU stores corresponding operands at the operand registers. Within a plurality of execution cycles, the GPU orders the transfer of operands from a set of operand registers to a designated double precision operand register. During each execution cycle, a double precision ALU performs a double precision operation using operands stored at the double precision operand register.

Description

Background Technology

[0001] A processor employs one or more processing units specifically designed and configured to perform specified operations on behalf of the processor. For example, some processors employ graphics processing units (GPUs) to perform graphics and vector processing operations. The processor's central processing unit (CPU) provides commands to the GPU, and the GPU's command processor (CP) decodes the commands into one or more operations. The GPU's execution units (such as one or more arithmetic logic units (ALUs)) execute the operations to perform the graphics and vector processing operations. The ALU uses operand registers to store operands for processing. Specifically, when a thread executes at the GPU, the thread stores operands in the operand registers and provides opcodes or other control information to the ALU to control the mathematical operations performed by the ALU using the operands. Using a large number of operand registers allows the GPU to support the simultaneous execution of a relatively large number of threads. However, such a large number of operand registers consumes significant processing resources, including power and circuit area. Attached Figure Description

[0002] This disclosure will be better understood by referring to the accompanying drawings, which will enable those skilled in the art to appreciate its many features and advantages. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 It is a block diagram of a graphics processing unit (GPU) configured to sort the provision of operands from one set of operand registers to another, according to some implementation schemes.

[0004] Figure 2 This illustrates how operands are provided to, according to some implementation schemes. Figure 1 A block diagram of the GPU registers.

[0005] Figure 3 This illustrates some implementation schemes. Figure 1 A block diagram showing the configuration of the GPU's operand registers and the corresponding ALU.

[0006] Figure 4 This illustrates how operands are provided in some implementation schemes. Figure 3 A block diagram of a portion of the example sorting at the operand register.

[0007] Figure 5 This illustrates some implementation schemes. Figure 4 A block diagram of another part of the example sorting.

[0008] Figure 6 This illustrates some implementation schemes. Figure 4A flowchart of another part of the example sorting.

[0009] Figure 7 This illustrates some implementation schemes. Figure 5 A flowchart of another part of the example sorting. Detailed Implementation

[0010] Figures 1 to 7 This illustration illustrates a technique in which a graphics processing unit (GPU) orders operand offerings to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers among processes. The GPU includes multiple arithmetic logic units (ALUs), at least one of which is configured to perform double-precision operations. The GPU also includes a set of operand registers configured to store single-precision operands. For multiple execution threads requesting double-precision operations, the GPU stores the corresponding operands at the operand registers. Within multiple execution loops, the GPU orders the transfer of operands from the set of operand registers to designated double-precision operand registers. During each execution loop, the double-precision ALU performs double-precision operations using the operands stored at the double-precision operand registers. By ordering operand offerings among registers in this manner, the GPU allows multiple processing blocks (e.g., multiple vector shader processors) to share double-precision operand registers, thereby reducing circuit area and power consumption by the operand registers.

[0011] Figure 1 A GPU 100 is illustrated, according to some embodiments, which prioritizes the provision of operands for double-precision mathematical operations. For descriptive purposes, it is assumed that the GPU 100 is part of a processor that executes an instruction set (e.g., a computer program) to perform tasks on behalf of an electronic device. Thus, in different embodiments, the GPU 100 is part of an electronic device such as a desktop computer, laptop computer, server, tablet computer, smartphone, game console, etc. Furthermore, it is assumed that the processor including the GPU 100 includes a central processing unit (CPU) that executes the instruction set.

[0012] GPU 100 is designed and manufactured to perform specified operations on behalf of the CPU. More specifically, GPU 100 performs graphics and vector processing operations on behalf of the CPU. For example, in some implementations, during instruction execution, the CPU generates commands associated with the graphics and vector processing operations. The CPU provides these commands to GPU 100, which uses an instruction processor (not shown) to decode the commands into an instruction set for execution at GPU 100.

[0013] To facilitate instruction execution, GPU 100 includes multiple compute units, such as one or more Single Instruction Multiple Data (SIMD) blocks, each of which is configured as a corresponding thread to perform an operation. In some implementations, the GPU's command processor decodes commands received from the CPU and, based on those commands, generates and schedules multiple sets of threads to be executed at the SIMD block. Each SIMD block includes multiple vector shader processors (VSPs) (e.g., VSPs 102, 103, 104). In some implementations, each SIMD block includes four different VSPs, thereby supporting the simultaneous execution of four different threads. Therefore, assuming each compute unit includes four SIMD blocks, where each SIMD block includes four VSPs, each compute unit supports the simultaneous execution of 16 threads.

[0014] During execution, the thread generates mathematical operations to be performed using the corresponding operands. To support the execution of mathematical operations, the GPU 100 includes a set of operand registers 106 (e.g., operand registers 111, 112) and a set of ALUs 108 (e.g., ALUs 114, 116). The operand registers 106 store operands for mathematical operations, and the ALUs 108 use the stored operands to perform mathematical operations. Specifically, to perform a mathematical operation, the thread stores the corresponding operand in one of the operand registers 106 (as described further below) and provides control information (not shown) to one of the ALUs 108. Based on the control information, the ALU performs the mathematical operation using the stored operands and stores the result in a result register (not shown) for retrieval by the thread.

[0015] It will be understood that, for clarity, each operand register 106 is shown as a single block herein. However, in some implementations, each operand register 106 stores multiple operands. Figure 2 An example is shown here. Figure 2 The operand register 111, which stores operands for the ALU 114, is depicted. In the depicted embodiment, operand register 111 stores three operands for the corresponding thread, which are designated as "A", "B", and "C", respectively.

[0016] return Figure 1It will be understood that the diagram illustrates the sharing of operand register 106 and ALU 108 among VSPs 102-104. However, in other embodiments, one or more of operand registers 106 or one or more of ALUs 108 are dedicated to individual VSPs. Thus, for example, in some embodiments, a subset of operand registers 106 is allocated to VSP 102 and a different subset of operand registers is allocated to VSP 103, such that each VSP cannot use operand registers already allocated to another VSP. Similarly, in some embodiments, a subset of ALU 108 is allocated to VSP 102 and a different subset of ALU 108 is allocated to VSP 103, such that each VSP cannot assign mathematical operations to ALUs already allocated to different VSPs.

[0017] In some implementations, at least some of the different mathematical operations generated by the execution thread are associated with different precisions, thereby indicating the precision level of the corresponding operands. For example, in some implementations, the execution thread generates single-precision mathematical operations and double-precision mathematical operations, wherein the double-precision operands (i.e., the operands used for double-precision operations) are twice the size of the single-precision operands. The size of each subset of operand register 106 is set to store single-precision operands, while the size of each subset of operand register 106 is set to store double-precision operands. In some implementations, and as described in more detail below, while double-precision operands await processing of one or more of 108, the single-precision operand registers in operand register 106 store portions of these operands.

[0018] Each subset of ALU 108 includes a circuitry for performing mathematical operations using operands of the corresponding precision. Thus, for example, ALU 114 includes a circuitry for performing single-precision mathematical operations (using single-precision operands), and ALU 116 includes a circuitry for performing double-precision operations (using double-precision operands). In some implementations, threads executing at GPU 100 are expected to request a relatively high number of single-precision operations and a relatively low number of double-precision operations. Therefore, ALU 108 comprises a higher number of single-precision ALUs and a lower number of double-precision ALUs. Furthermore, operand register 106 comprises a higher number of single-precision operand registers and a lower number of operand registers storing double-precision operands. Figure 3Examples according to some embodiments are shown. In the depicted example, ALU 108 includes 15 single-precision (SP) ALUs and one double-precision ALU. Operand register 106 includes a plurality of single-precision operand registers, wherein a pair of operand registers stores double-precision operands for the double-precision ALU 116, the pair of operand registers being designated as operand registers 321 and 322. In some embodiments, operand register 321 stores the "high" bit or most significant bit of the double-precision operand, and operand register 322 stores the "low" bit or least significant bit of the double-precision operand. In some embodiments, at different times, registers 321 and 322 also store single-precision operands for one or more of the SP ALUs. That is, depending on the precision of the given arithmetic operation being performed, registers 321 and 322 store single-precision operands for processing by one or more SP ALUs (e.g., SP ALU 323), or together store a set of double-precision operands for processing by the DP ALU 116.

[0019] As described above, in many cases, GPU 100 is expected to perform a relatively high number of single-precision operations and a relatively low number of double-precision operations. Therefore, to save the cost of having a dedicated set of double-precision registers for each execution thread, GPU 100 includes an operand ordering control module 110 for controlling the ordering of double-precision operands in destination registers 321 and 322. For illustration, in some embodiments, at least a subset of the operand registers are concatenated, and in response to control signaling from operand ordering control module 110, each operand register receiving the control signal transfers its stored data to another operand register. By controlling the transfer of data between operand registers, operand ordering control module 110 schedules the execution of double-precision operations for multiple threads within multiple execution loops while using a relatively small number of operand registers and double-precision ALU circuitry, thereby saving GPU 100 resources. In some embodiments, operand ordering control module 110 is part of a scheduler (not shown) that schedules thread execution at VSPs 102-104 of GPU 100.

[0020] Figures 4 to 7 Together, we show an example of sorting the double-precision operands provided by GPU 100 opposing registers 321 and 322 according to some implementations. Figures 4 to 7 The example illustrates multiple execution cycles of the GPU 100. In some implementations, each execution cycle corresponds to a single clock cycle (not shown) used to synchronize the computations of the GPU 100. In other implementations, each execution cycle corresponds to multiple clock cycles. Figures 4 to 7For the purposes of this example, it is assumed that VSPs 102-104 execute 16 threads concurrently, each of which needs to perform double-precision arithmetic operations at DP ALU 116. To perform these operations, the GPU utilizes operand registers 430-439, as well as operand registers 321 and 322, in operand register 106. It is assumed that in some implementations, each of operand registers 321, 322, and 430-439 includes independent read and write ports, such that data is read from and written to the operand registers during a single execution loop.

[0021] For illustrative purposes, assume that each execution thread provides a set of double-precision operands for processing at DP ALU 116. As further explained below, each thread provides its corresponding double-precision operand in two parts: a lower part representing the least significant bit of the double-precision operand, and an upper part representing the most significant bit of the double-precision operand. Therefore, assume that each double-precision operand is 64 bits, the upper part of the operand is the 32 most significant bits, and the lower part of the operand is the 32 least significant bits.

[0022] Figure 4 The first two execution loops, designated as loop 0 and loop 1, are shown as examples according to some implementations. During loop 0, the scheduler of GPU 100 schedules the execution of threads 0, 4, 8, and 12 such that the lower portions of the double-precision operands used for these threads (designated 0L, 4L, 8L, and 12L, respectively) are read into operand registers. Specifically, the lower portion operand 4L is stored at operand register 430, the lower portion operand 0L at operand register 433, the lower portion operand 8L at operand register 434, and the lower portion operand 12L at operand register 437. In at least some implementations, each of threads 0, 4, 8, and 12 executes at a different VSP of GPU 100.

[0023] During loop 1, operand sequence control module 110 provides control signaling for transferring data between operand registers. Specifically, operand 0L is transferred from operand register 433 to operand register 321, operand 8L is transferred from operand register 434 to operand register 433, and operand 12L is transferred from operand register 437 to operand register 434.

[0024] Additionally, during loop 1, the upper portions of the double-precision operands used for threads 0, 4, 8, and 12 (specified as 0H, 4H, 8H, and 12H, respectively) are read into subsets of the operand registers. Specifically, the upper portion operand 4H is stored at operand register 432, the upper portion operand 0H is stored at operand register 322, the upper portion operand 8H is stored at operand register 436, and the upper portion operand 12H is stored at operand register 439.

[0025] During loop 1, the 0L and 0H operands are stored in operand registers 321 and 322 and are therefore readily available for processing by the DP ALU 116. Thus, during loop 1, the DP ALU 116 uses the 0L and 0H operands to begin the double-precision operation requested by thread 0. Specifically, the DP ALU 116 concatenates the upper and lower portions of operands A, B, and C based on the 0L and 0H operands and uses the resulting A, B, and C operands for double-precision operations.

[0026] Figure 5 The following two loops of an example sorting operation according to some embodiments are shown, designated as loop 2 and loop 3. During loop 2, the operand order control module 110 provides control signaling for further data transfer between operand registers. Specifically, operand 4L is transferred from operand register 430 to operand register 433, operand 8L from operand register 433 to operand register 321, operand 8H from operand register 436 to operand register 322, and operand 12H from operand register 439 to operand register 436. Thus, during loop 2, operands 8L and 8H are stored in operand registers 321 and 322. Therefore, during loop 2, the DP ALU 116 uses operands 8L and 8H to begin the double-precision operation requested by thread 8.

[0027] During loop 3, similar to the previous two loops, the operand sequence control module 110 provides further control signaling for transferring data between operand registers. Specifically, operand 4L is transferred from operand register 433 to operand register 321, operand 4H is transferred from operand register 432 to operand register 322, and operand 12L is transferred from operand register 434 to operand register 433. Thus, during loop 3, operands 4L and 4H are stored in operand registers 321 and 322, and the DP ALU 116 uses operands 4L and 4H to begin the double-precision operation requested by thread 4.

[0028] Figure 6The following two loops of an example sorting operation according to some embodiments are shown, designated as loop 4 and loop 5. During loop 4, the operand order control module 110 provides control signaling to transfer the last operand from the initial set of operands between operand registers. Specifically, operand 12H is transferred from operand register 436 to operand register 322, and operand 12L is transferred from operand register 433 to operand register 321. Thus, during loop 4, operands 12L and 12H are stored at operand registers 321 and 322. Therefore, during loop 4, the DP ALU 116 uses operands 12L and 12H to begin the double-precision operation requested by thread 12.

[0029] Additionally, during loop 4, the next set of operands to be processed is stored in the operand register. As shown, the lower portions of the double-precision operands used for threads 5, 1, 9, and 13 (specified as 5L, 1L, 9L, and 13L, respectively) are read into the operand register. Specifically, operand 5L is stored at operand register 430, operand 1L at operand register 433, operand 9L at operand register 434, and operand 13L at operand register 437.

[0030] In loop 5, the operand sequence control module 110 provides control signaling for transferring data between operand registers, such that operand 1L is transferred from operand register 433 to operand register 321, operand 9L is transferred from operand register 434 to operand register 433, and operand 13L is transferred from operand register 437 to operand register 434.

[0031] Additionally, during loop 5, the upper portions of the double-precision operands used for threads 5, 1, 9, and 13 (designated as 5H, 1H, 9H, and 13H, respectively) are read into subsets of the operand registers. Specifically, operand 5H is stored at operand register 432, operand 1H at operand register 322, operand 9H at operand register 436, and operand 13H at operand register 439. Therefore, during loop 5, operands 1L and 1H are stored at operand registers 321 and 322 and are thus readily available for processing by the DP ALU 116. Thus, during loop 5, the DP ALU 116 uses operands 1L and 1H to begin the double-precision operation requested by thread 1.

[0032] Figure 7The following three loops of an example sorting operation according to some embodiments are shown, designated as loop 6, loop 7, and loop 8. During loop 6, the operand sequence control module 110 provides control signaling for further data transfer between operand registers. Specifically, operand 5L is transferred from operand register 430 to operand register 433, operand 9L from operand register 433 to operand register 321, operand 9H from operand register 436 to operand register 322, and operand 13 from operand register 439 to operand register 436. Thus, during loop 6, operands 9L and 9H are stored in operand registers 321 and 322. Therefore, during loop 6, the DP ALU 116 uses operands 9L and 9H to begin the double-precision operation requested by thread 9.

[0033] Moving to loop 7, the operand sequence control module 110 provides further control signaling for transferring data between operand registers. Specifically, operand 5L is transferred from operand register 433 to operand register 321, operand 5H is transferred from operand register 432 to operand register 322, and operand 13L is transferred from operand register 434 to operand register 433. Thus, during loop 7, operands 5L and 5H are stored in operand registers 321 and 322, and the DP ALU 116 uses operands 5L and 5H to begin the double-precision operation requested by thread 5.

[0034] Moving to loop 8, operand sequence control module 110 provides control signaling for transferring the last operand of the second set of operands between operand registers. Specifically, operand 13H is transferred from operand register 436 to operand register 322, and operand 12L is transferred from operand register 433 to operand register 321. Therefore, during loop 8, operands 13L and 13H are stored in operand registers 321 and 322, respectively. Thus, during loop 8, DP ALU 116 uses operands 13L and 13H to begin the double-precision operation requested by thread 13.

[0035] Additionally, during loop 8, the next set of operands to be processed is stored in the operand register. As shown, the lower portions of the double-precision operands used for threads 6, 2, 10, and 14 (specified as 6L, 2L, 9L, and 14L, respectively) are read into the operand register. Specifically, operand 6L is stored at operand register 430, operand 2L at operand register 433, operand 10L at operand register 434, and operand 14L at operand register 437.

[0036] In some implementations, GPU 100 continues to order the operands provided to and between the operand registers in a manner similar to the illustrated loops 0-8, to process operands for the remaining threads (including threads 2, 3, 6, 7, 10, 11, 14, and 15). Therefore, GPU 100 supports double-precision operations for each of the 16 concurrently executing threads using a single set of double-precision operand registers shared between VSPs 102-104. GPU 100 is thus able to support double-precision operations with a relatively small set of operand registers, thereby saving processor resources such as area and power.

[0037] In some implementations, a method includes: receiving a plurality of operands for processing at a first arithmetic logic unit (ALU) for a plurality of threads executing at a processing unit; storing the plurality of operands at a plurality of registers; and, within a plurality of execution loops, ordering the provision of the plurality of operands from the plurality of registers to a first operand register for processing at the ALU. In one aspect, the ordering includes: during a first execution loop, storing a first portion of a first operand among the plurality of operands at the first operand register; and during a second execution loop, transferring a first portion of a second operand among the plurality of operands from the first register to the first operand register. In another aspect, the ordering further includes: during the first execution loop, storing a second portion of the first operand at a second register among the plurality of registers; and during the second execution loop, transferring the second portion of the first operand to a second operand register for processing at the ALU.

[0038] In another aspect, the method includes: during the second execution loop, reading the first operand from the first operand register and the second operand register at the ALU. In another aspect, the first operand is a double-precision operand, and each of the plurality of registers is configured to store a single-precision operand. In another aspect, the sorting further includes: during the second execution loop, transferring a first portion of the third operand from the second register of the plurality of registers to the first register of the plurality of registers. In another aspect, the sorting further includes: during the third execution loop, transferring the first portion of the third operand from the first register of the plurality of registers to the first operand register. In yet another aspect, the sorting further includes: during the second execution loop, transferring a first portion of the fourth operand from the third register of the plurality of registers to the second register of the plurality of registers.

[0039] In some embodiments, a processor includes: a processing unit including an arithmetic logic unit (ALU) for executing a plurality of corresponding threads, the plurality of threads executing to generate a plurality of operands for processing at the ALU; a plurality of registers configured to store the plurality of operands; and a sequence control module configured to order the provision of the plurality of operands from the plurality of registers to a first operand register for processing at the ALU within a plurality of execution loops. In one aspect, the ordering includes: during a first execution loop, storing a first portion of a first operand of the plurality of operands at the first operand register; and during a second execution loop, transferring a first portion of a second operand of the plurality of operands from the first register of the plurality of registers to the first operand register.

[0040] In one aspect, the sorting further includes: during the first execution loop, storing a second portion of the first operand in a second register among the plurality of registers; and during the second execution loop, transferring the second portion of the first operand to a second operand register for processing at the ALU. In another aspect, the ALU is configured to: during the second execution loop, read the first operand from both the first operand register and the second operand register for processing. In yet another aspect, the first operand is a double-precision operand, and each of the plurality of registers is configured to store a single-precision operand.

[0041] In one aspect, the sorting further includes: during the second execution loop, transferring a first portion of the third operand from a second register of the plurality of registers to a first register of the plurality of registers. In another aspect, the sorting further includes: during the third execution loop, transferring the first portion of the third operand from the first register of the plurality of registers to the first operand register. In yet another aspect, the sorting further includes: during the second execution loop, transferring a first portion of the fourth operand from a third register of the plurality of registers to a second register of the plurality of registers.

[0042] In some implementations, a graphics processing unit (GPU) includes: a plurality of shader processors for executing corresponding plurality of threads, the plurality of threads executing to generate a plurality of operands; an arithmetic logic unit (ALU); a plurality of registers configured to store the plurality of operands; and a sequence control module configured to order the provision of the plurality of operands from the plurality of registers to a first operand register for processing at the ALU within a plurality of execution loops. In one aspect, the ordering includes: during a first execution loop, storing a first portion of a first operand among the plurality of operands at the first operand register; and during a second execution loop, transferring a first portion of a second operand among the plurality of operands from the first register to the first operand register. In another aspect, the ordering further includes: during the first execution loop, storing a second portion of the first operand at a second register among the plurality of registers; and during the second execution loop, transferring the second portion of the first operand to a second operand register for processing at the ALU. In another aspect, the ALU is configured to read the first operand from the first operand register and the second operand register for processing during the second execution cycle.

[0043] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software includes instructions and certain data that, when executed by the one or more processors, control the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium includes one or more of the following: for example, disk or optical disk storage devices, solid-state storage devices such as flash memory, cache memory, random access memory (RAM), or one or more other non-volatile memory devices. In various embodiments, the executable instructions stored on the non-transitory computer-readable storage medium are represented in source code, assembly language code, object code, or other instruction formats that are interpreted or executable by the one or more processors.

[0044] Note that not all of the activities or elements described in the general description above are required, and a particular activity or device may not be necessary. Furthermore, one or more other activities or elements may be performed in addition to the described activities and elements. The order in which the activities are listed is not necessarily the order in which they are performed. Moreover, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and figures are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0045] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that make any benefit, advantage, or solution to a problem apparent or more obvious should not be construed as key, necessary, or essential features of any or all claims. Furthermore, those skilled in the art, benefiting from the teachings herein, will understand that the specific embodiments disclosed above are merely illustrative and the disclosed subject matter may be modified and practiced in different but equivalent ways. No limitation is intended to be made on the details of the constructions or designs shown herein, other than those described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above may be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Thus, the protection sought herein is as set forth in the appended claims.

Claims

1. A method, the method comprising: For multiple threads executing at the processing unit, multiple operands are received for processing at the arithmetic logic unit (ALU); The plurality of operands are stored in a plurality of registers, the size of which is set to store single-precision operands; as well as Within multiple execution loops, the plurality of operands are ordered to be provided from the plurality of registers to a first operand register for processing at the ALU, the size of the first operand register being set to store double-precision operands.

2. The method of claim 1, wherein the sorting comprises: During the first execution loop, a first portion of the first operand of the plurality of operands is stored at the first operand register; as well as During the second execution cycle, a first portion of the second operand among the plurality of operands is transferred from the first register among the plurality of registers to the first operand register.

3. The method of claim 2, wherein the sorting further comprises: During the first execution loop, the second portion of the first operand is stored in the second register among the plurality of registers; as well as During the second execution cycle, the second portion of the first operand is transferred to the second operand register for processing at the ALU.

4. The method of claim 3, further comprising: During the second execution cycle, the first operand is read from the first operand register and the second operand register at the ALU.

5. The method of claim 2, wherein the first operand is a double-precision operand.

6. The method of claim 2, wherein the sorting further comprises: During the second execution loop, the first portion of the third operand is transferred from the second register of the plurality of registers to the first register of the plurality of registers.

7. The method of claim 6, wherein the sorting further comprises: During the third execution cycle, the first portion of the third operand is transferred from the first register of the plurality of registers to the first operand register.

8. The method of claim 6, wherein the sorting further comprises: During the second execution cycle, the first portion of the fourth operand is transferred from the third register of the plurality of registers to the second register of the plurality of registers.

9. A processor, the processor comprising: The processing unit includes an arithmetic logic unit (ALU), which is used to execute multiple threads to generate multiple operands for processing at the ALU. Multiple registers, the size of which is set to store single-precision operands and configured to store the multiple operands; as well as A sequence control module is configured to sort the plurality of operands from the plurality of registers to a first operand register for processing at the ALU within a plurality of execution loops, the size of the first operand register being set to store double-precision operands.

10. The processor of claim 9, wherein the sequence control module is configured to order the provision of the plurality of operands by: During the first execution loop, a first portion of the first operand of the plurality of operands is stored at the first operand register; and During the second execution cycle, a first portion of the second operand among the plurality of operands is transferred from the first register among the plurality of registers to the first operand register.

11. The processor of claim 10, wherein the sequence control module is configured to order the provision of the plurality of operands by: During the first execution loop, the second portion of the first operand is stored in the second register among the plurality of registers; and During the second execution cycle, the second portion of the first operand is transferred to the second operand register for processing at the ALU.

12. The processor of claim 11, wherein the ALU is configured to: During the second execution loop, the first operand is read from the first operand register and the second operand register for processing.

13. The processor of claim 10, wherein the first operand is a double-precision operand.

14. The processor of claim 10, wherein the sequence control module is configured to order the provision of the plurality of operands by: During the second execution loop, the first portion of the third operand is transferred from the second register of the plurality of registers to the first register of the plurality of registers.

15. The processor of claim 14, wherein the sequence control module is configured to order the provision of the plurality of operands by: During the third execution cycle, the first portion of the third operand is transferred from the first register of the plurality of registers to the first operand register.

Images