Semiconductor structure and its fabrication method, memory system, electronic device

Abstract

This application provides a semiconductor structure and its fabrication method, a memory system, and an electronic device, relating to the field of semiconductor chip technology, and aims to reduce the size of semiconductor structures. The semiconductor structure provided in this application includes a silicon substrate and a plurality of transistors spaced apart on the silicon substrate. An isolation structure is provided between two adjacent transistors. The isolation structure includes a first insulating layer, a conductive layer, and a second insulating layer. The first insulating layer is disposed between the silicon substrate and the conductive layer, and the conductive layer is disposed between the first and second insulating layers. When the transistors are in operation, electrons in the transistors are less likely to pass through the conductive layer in the isolation structure located between two adjacent transistors, enhancing the isolation effect between the two adjacent transistors. Therefore, under the premise of the same isolation effect, the isolation structure in the semiconductor structure provided in this application has a smaller size, thereby reducing the size of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] In a semiconductor structure, there are multiple transistors located on the same plane. A shallow trench isolation (STI) of a certain size is required between two adjacent transistors to prevent leakage between them. However, the size of the shallow trench isolation limits the size of the entire semiconductor structure, making it difficult to reduce the size of the semiconductor structure. Summary of the Invention

[0003] Embodiments of this application provide a semiconductor structure and its fabrication method, a storage system, and an electronic device, with the aim of reducing the size of the semiconductor structure.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] On one hand, embodiments of this application provide a semiconductor structure including a silicon substrate, a plurality of transistors, and a plurality of isolation structures. The transistors are disposed on the silicon substrate, the plurality of transistors are spaced apart, and an isolation structure is provided between two adjacent transistors. The isolation structure includes a first insulating layer, a conductive layer, and a second insulating layer. The first insulating layer is disposed between the silicon substrate and the conductive layer, and the conductive layer is disposed between the first insulating layer and the second insulating layer.

[0006] In some embodiments, the first insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion being in contact with one of two adjacent transistors, the second insulating portion being in contact with the other of two adjacent transistors, and the end of the first insulating portion near the silicon substrate being connected to the end of the second insulating portion near the silicon substrate; the conductive layer includes a first conductive portion and a second conductive portion, the first conductive portion covering the first insulating portion, the second conductive portion covering the second insulating portion, and the end of the first conductive portion near the silicon substrate being connected to the end of the second conductive portion near the silicon substrate.

[0007] In some embodiments, the first insulating layer further includes a third insulating portion located between the silicon substrate and the first insulating portion and the second insulating portion. The third insulating portion contacts the silicon substrate located between two adjacent transistors. The end of the first insulating portion near the silicon substrate is connected to the third insulating portion, and the end of the second insulating portion near the silicon substrate is also connected to the third insulating portion. The conductive layer further includes a third conductive portion covering the third insulating portion. The third conductive portion is located between the first conductive portion and the second conductive portion. The end of the first conductive portion near the silicon substrate is connected to the third conductive portion, and the end of the second conductive portion near the silicon substrate is also connected to the third conductive portion.

[0008] In some embodiments, the silicon substrate has a first side and a second side opposite to each other, the transistor and the isolation structure are both disposed on the first side, and the distance from the conductive layer to the second side is less than the distance from the transistor to the second side.

[0009] In some embodiments, the semiconductor structure further includes a conductive structure and a contact structure. The conductive structure and the transistor are both disposed on the same side of the silicon substrate, and the conductive structure is connected to the isolation structure. The contact structure is located on the side of the conductive structure away from the silicon substrate and is connected to the conductive structure. The contact structure is configured as a reference potential.

[0010] In some embodiments, the conductive structure is located on the same side of the plurality of transistors.

[0011] In some embodiments, a plurality of transistor arrays are provided; the plurality of isolation structures include a plurality of first isolation structures and a plurality of second isolation structures, the first isolation structures being located between two adjacent transistors in the row direction and the second isolation structures being located between two adjacent transistors in the column direction, the extension direction of the conductive structures being the same as the extension direction of the first isolation structures, and the first isolation structures being connected to the conductive structures through the second isolation structures.

[0012] On the other hand, embodiments of this application also provide a method for fabricating a semiconductor structure, including:

[0013] Provide silicon substrates;

[0014] An isolation trench is formed on the silicon substrate;

[0015] An isolation structure is formed in an isolation trench. The formation of the isolation structure includes the sequential formation of a first insulating layer, a conductive layer, and a second insulating layer. The first insulating layer is located between the silicon substrate and the conductive layer, and the conductive layer is located between the first insulating layer and the second insulating layer.

[0016] Transistors are formed on a silicon substrate, with the transistors located between two adjacent isolation structures.

[0017] In some embodiments, the formed isolation groove includes two sidewalls;

[0018] Forming the first insulating layer includes forming a first insulating portion and a second insulating portion on the two sidewalls, respectively.

[0019] Forming a conductive layer includes forming a first conductive portion covering a first insulating portion and a second conductive portion covering a second insulating portion.

[0020] In some embodiments, the formed isolation trench also includes a bottom wall;

[0021] Forming the first insulating layer also includes forming a third insulating portion on the bottom wall;

[0022] The formation of the conductive layer also includes forming a third conductive portion that covers the third insulating portion.

[0023] In some embodiments, the semiconductor structure fabrication method further includes:

[0024] An isolation structure is formed simultaneously with a conductive structure. The formed isolation structure is connected to the conductive structure, and all the formed isolation structures are located on the same side of the conductive structure.

[0025] A contact hole is formed, and a contact structure is formed within the contact hole. The formed contact structure is connected to the conductive structure.

[0026] In some embodiments, forming an isolation groove includes forming a first isolation groove and a second isolation groove that are interconnected, wherein the second isolation groove extends along a row direction and the first isolation groove extends along a column direction.

[0027] The formation of the isolation structure includes forming a first isolation structure in a first isolation groove and forming a second isolation structure in a second isolation groove, wherein the first isolation structure and the second isolation structure are connected.

[0028] In another aspect, embodiments of this application also provide a storage system, including a semiconductor structure and a controller, wherein the semiconductor structure is as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0029] In another aspect, embodiments of this application also provide an electronic device, including the storage system described above.

[0030] It is understood that the beneficial effects that the semiconductor structure fabrication method, storage system and electronic device provided in the above embodiments of this application can achieve can be referred to the beneficial effects of the semiconductor structure in the above text, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0032] Figure 1 This is a schematic diagram of the semiconductor structure in the embodiments of this application. Figure 1 ;

[0033] Figure 2 This is a schematic diagram of the semiconductor structure in the embodiments of this application. Figure 2 ;

[0034] Figure 3 This is a schematic diagram of the semiconductor structure in the embodiments of this application. Figure 3 ;

[0035] Figure 4 This is a top view of the semiconductor structure in an embodiment of this application;

[0036] Figure 5 This is a schematic flowchart of the semiconductor structure fabrication method in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of the structure after the mask plate is formed in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of the structure after the isolation groove is formed in the embodiment of this application. Figure 1 ;

[0039] Figure 8 This is a schematic diagram of the structure after the isolation groove is formed in the embodiment of this application. Figure 2 ;

[0040] Figure 9 This is a top view of the embodiment of this application after the isolation groove has been formed;

[0041] Figure 10 This is a schematic diagram of the structure after the initial first insulating layer is formed in the embodiments of this application. Figure 1 ;

[0042] Figure 11 This is a schematic diagram of the structure after the initial first insulating layer is formed in the embodiments of this application. Figure 2 ;

[0043] Figure 12 This is a schematic diagram of the structure after the initial conductive layer is formed in the embodiments of this application. Figure 1 ;

[0044] Figure 13 This is a schematic diagram of the structure after the initial conductive layer is formed in the embodiments of this application. Figure 2 ;

[0045] Figure 14 This is a schematic diagram of the structure after the conductive layer is formed in the embodiments of this application;

[0046] Figure 15 This is a schematic diagram of the structure after the second insulating layer is formed in an embodiment of this application;

[0047] Figure 16 This is a top view of the isolation structure formed in the embodiments of this application;

[0048] Figure 17 This is a schematic diagram of the structure after the transistor is formed in an embodiment of this application;

[0049] Figure 18 This is a schematic diagram of the structure after the third insulating layer is formed in an embodiment of this application;

[0050] Figure 19 This is a schematic diagram of the structure after the contact hole is formed in an embodiment of this application;

[0051] Figure 20 This is a schematic diagram of the structure after the contact structure is formed in the embodiments of this application;

[0052] Figure 21 This is a block diagram of a storage system according to some embodiments;

[0053] Figure 22 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0054] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0055] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0057] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content of this document.

[0059] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0060] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] Please refer to Figure 1 This application provides a semiconductor structure 200 including a plurality of transistors 210 located on the same plane and a silicon substrate 220. The transistors 210 are disposed on one side surface of the silicon substrate 220, and the plurality of transistors 210 are spaced apart. An isolation structure 230, namely shallow trench isolation (STI), is provided between two adjacent transistors 210 to prevent leakage between adjacent transistors 210. It is understood that the isolation structure 230 is located between two adjacent transistors 210, and since there are multiple transistors 210, there are also multiple isolation structures 230. The isolation structure 230 can be formed of insulating oxide, and the size of the isolation structure 230 in the arrangement direction of the two transistors 210 depends on the operating voltage of the transistors 210. In embodiments where the operating voltage of the transistors 210 is constant, the size of the isolation structure 230 is difficult to reduce, which limits the size of the entire semiconductor structure 200.

[0066] In the above embodiments, transistor 210 may include at least one of NMOS (N-Metal-Oxide-Semiconductor) transistor and PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0067] In an embodiment where transistor 210 is an NMOS transistor, the semiconductor structure 200 includes a P-type doped silicon substrate 220 and a plurality of NMOS transistors. The NMOS transistors are formed on one side surface of the P-type doped silicon substrate 220, and an isolation structure 230 is provided between two adjacent NMOS transistors. Each NMOS transistor includes a source 211, a drain 212, and a gate 213. Two spaced-apart, highly doped N+ regions can be formed on the P-type doped silicon substrate 220 as the source 211 and drain 212 of the NMOS transistor. Exemplarily, the arrangement direction of the source 211 and drain 212 of the same NMOS transistor is the same as the arrangement direction of two adjacent NMOS transistors. The gate 213 is located between the source 211 and drain 212 and is spaced apart from the P-type doped silicon substrate 220. Exemplarily, a gate dielectric layer formed of insulating oxide is provided between the gate 213 and the P-type doped silicon substrate 220.

[0068] In an embodiment where transistor 210 is a PMOS transistor, the semiconductor structure 200 includes an N-type doped silicon substrate 220 and a plurality of PMOS transistors. The PMOS transistors are formed on one side surface of the N-type doped silicon substrate 220, and an isolation structure 230 is provided between adjacent PMOS transistors. Each PMOS transistor includes a source, a drain, and a gate. Two spaced-apart, highly doped P+ regions can be formed on the N-type doped silicon substrate 220 as the source and drain of the PMOS transistor. Exemplarily, the arrangement direction of the source and drain of the same PMOS transistor is the same as the arrangement direction of two adjacent PMOS transistors. The gate is located between the source and drain and is spaced apart from the N-type doped silicon substrate 220. Exemplarily, a gate dielectric layer formed of insulating oxide is provided between the gate and the N-type doped silicon substrate 220.

[0069] In both embodiments described above, regardless of whether transistor 210 is an NMOS transistor or a PMOS transistor, for the source 211, drain 212, and gate 213 of the same transistor 210, the semiconductor structure 200 further includes a lead-out structure 240. The lead-out structure 240 may include a first lead-out structure 241, a second lead-out structure 242, and a third lead-out structure 243. The first lead-out structure 241 is connected to the source 211, the second lead-out structure 242 is connected to the drain 212, and the third lead-out structure 243 is connected to the gate 213. In some embodiments, the semiconductor structure 200 further includes multiple metal wirings 250. The first lead-out structure 241, the second lead-out structure 242, and the third lead-out structure 243 are respectively connected to different metal wirings 250 to respectively realize the lead-out of the source 211, drain 212, and gate 213 of transistor 210.

[0070] Reference Figure 2 and Figure 3In some embodiments, the isolation structure 230 includes a first insulating layer 231, a conductive layer 232, and a second insulating layer 233. The first insulating layer 231 is disposed between the silicon substrate 220 and the conductive layer 232, and the conductive layer 232 is disposed between the first insulating layer 231 and the second insulating layer 233. The first insulating layer 231 and the second insulating layer 233 include insulating materials, such as insulating oxides, silicon nitride (SiN), etc. The conductive layer 232 may include conductive materials, such as titanium nitride (TiN), tungsten (W), etc.

[0071] Reference Figure 2 In some embodiments, the first insulating layer 231 includes a first insulating portion 2311 and a second insulating portion 2312. Since the isolation structure 230 is located between two adjacent transistors 210, the first insulating layer 231 contacts one of the two adjacent transistors 210, and the second insulating portion 2312 contacts the other of the two adjacent transistors 210. The end of the first insulating portion 2311 near the silicon substrate 220 is connected to the end of the second insulating portion 2312 near the silicon substrate 220. The first insulating layer 231 may cover one of the transistors 210 and a portion of the silicon substrate 220 below it, and the second insulating layer 233 may cover the other transistor 210 and a portion of the silicon substrate 220 below it. This makes the connection point of the first insulating portion 2311 and the second insulating portion 2312 closer to the lower surface of the silicon substrate 220 relative to the transistor 210, thereby ensuring that the conductive layer 232 located between the first insulating layer 231 and the second insulating layer 233 is completely located between the two adjacent transistors 210 in the thickness direction of the silicon substrate 220.

[0072] In the above embodiment, the conductive layer 232 includes a first conductive portion 2321 and a second conductive portion 2322. The first conductive portion 2321 covers the first insulating portion 2311, and the second conductive portion 2322 covers the second insulating portion 2312. One end of the first conductive portion 2321 near the silicon substrate 220 is connected to one end of the second conductive portion 2322 near the silicon substrate 220. In a cross-section parallel to the thickness direction of the silicon substrate 220, the first conductive portion 2321 and the second conductive portion 2322 of the conductive layer 232 are V-shaped. For example, the silicon substrate 220 has a first surface 221 and a second surface 222 facing each other. The transistor 210 and the isolation structure 230 are both disposed on the first surface 221 of the silicon substrate 220. The distance from the conductive layer 232 (the connection between the first conductive portion 2321 and the second conductive portion 2322) to the second surface 222 is less than the distance from the transistor 210 to the second surface 222.

[0073] Reference Figure 3In other embodiments, the first insulating layer 231 includes a first insulating portion 2311, a second insulating portion 2312, and a third insulating portion 2313. Similarly, the first insulating layer 231 contacts one of two adjacent transistors 210, the second insulating portion 2312 contacts the other of the two adjacent transistors 210, and the third insulating portion 2313 is closer to the lower surface of the silicon substrate 220 relative to the transistors 210. This ensures that the conductive layer 232 located between the first insulating layer 231 and the second insulating layer 233 is completely positioned between the two adjacent transistors 210 in the thickness direction of the silicon substrate 220. One end of the first insulating portion 2311 near the silicon substrate 220 is connected to the third insulating portion 2313, and the other end of the second insulating portion 2312 near the silicon substrate 220 is also connected to the third insulating portion 2313.

[0074] In the above embodiment, the conductive layer 232 includes a first conductive portion 2321 and a second conductive portion 2322, as well as a third conductive portion 2323. The third conductive portion 2323 covers the third insulating portion 2313 and is located between the first conductive portion 2321 and the second conductive portion 2322. The end of the first conductive portion 2321 near the silicon substrate 220 is connected to the third conductive portion 2323, and the end of the second conductive portion 2322 near the silicon substrate 220 is also connected to the third conductive portion 2323. In a cross-section parallel to the thickness direction of the silicon substrate 220, the first conductive portion 2321, the second conductive portion 2322, and the third conductive layer 232 of the conductive layer 232 are U-shaped. For example, the silicon substrate 220 has a first surface 221 and a second surface 222 opposite to each other. The transistor 210 and the isolation structure 230 are both disposed on the first surface 221 of the silicon substrate 220. The distance from the conductive layer 232 (third conductive part 2323) to the second surface 222 is less than the distance from the transistor 210 to the second surface 222.

[0075] The semiconductor structure 200 provided in this application includes a silicon substrate 220 and a plurality of transistors 210 spaced apart on the silicon substrate 220. An isolation structure 230 is provided between two adjacent transistors 210. The isolation structure 230 includes a first insulating layer 231, a conductive layer 232, and a second insulating layer 233. The first insulating layer 231 is disposed between the silicon substrate 220 and the conductive layer 232, and the conductive layer 232 is disposed between the first insulating layer 231 and the second insulating layer 233. When the transistors 210 are in the working state, electrons in the transistors 210 are less likely to pass through the conductive layer 232 in the isolation structure 230 located between two adjacent transistors 210, thereby enhancing the isolation effect of the isolation structure 230 between two adjacent transistors 210. Therefore, under the premise of having the same isolation effect, the isolation structure 230 in the semiconductor structure 200 provided in this application embodiment has a smaller size, thereby reducing the size of the semiconductor structure 200.

[0076] Reference Figure 2 and Figure 3 In some embodiments, the semiconductor structure 200 further includes a conductive structure 260 and a contact structure 270. The conductive structure 260 is connected to the isolation structure 230, and the contact structure 270 is connected to the conductive structure 260. The contact structure 270 is configured as a reference potential, meaning that the conductive structure 260 connected to the contact structure 270 also has a reference potential, thereby enabling the isolation structure 230 connected to the conductive structure 260 to have a reference potential. Exemplarily, the contact structure 270 can be grounded or connected to a negative voltage. In embodiments where the isolation structure 230 is grounded or connected to a negative voltage, the isolation effect of the isolation structure 230 on two adjacent transistors 210 can be further enhanced. Therefore, while maintaining the same isolation effect, the isolation structure 230 can have a smaller size, thereby reducing the size of the semiconductor structure 200.

[0077] In the above embodiments, the conductive structure 260 and the isolation structure 230 can be formed using the same fabrication process, making the conductive structure 260 and the isolation structure 230 have the same shape. The conductive structure 260 and the transistor 210 are both disposed on the same side of the silicon substrate 220, and the contact structure 270 is located on the side of the conductive structure 260 facing away from the silicon substrate 220. In embodiments where the semiconductor structure 200 includes a lead-out structure 240, the contact structure 270 and the lead-out structure 240 can be formed using the same fabrication process.

[0078] In some embodiments, the conductive structure 260 is located on the same side of the plurality of transistors 210, such that the plurality of isolation structures 230 located between the transistors 210 are all located on the same side of the conductive structure 260. In embodiments where the contact structure 270 is connected to the conductive structure 260, the contact structure 270 is located at the edge of the entire semiconductor structure 200 to facilitate the setting of the contact structure 270.

[0079] Reference Figure 4In the above embodiments, the multiple isolation structures 230 are divided into multiple first isolation structures 2301 and multiple second isolation structures 2302. Multiple transistors 210 are arrayed. The first isolation structure 2301 is located between two adjacent transistors 210 in the row direction and extends along the column direction of the multiple transistors 210. The second isolation structure 2302 is located between two adjacent transistors 210 in the column direction and extends along the row direction of the multiple transistors 210. The first isolation structure 2301 extending along the column direction and the second isolation structure 2302 extending along the row direction are connected to form an array region. In some embodiments, each region of the array contains only one transistor 210; in other embodiments, each region of the array contains at least two transistors 210, with the source 211 and drain 212 of each transistor 210 arranged along the row direction, and the at least two transistors 210 in the same region arranged along the column direction.

[0080] In the embodiment where the conductive structure 260 is located on the same side of the plurality of transistors 210, the extension direction of the conductive structure 260 is the same as the extension direction of the first isolation structure 2301, both extending along the column direction; the plurality of first isolation structures 2301 are all located on the same side of the conductive structure 260, and the plurality of isolation structures 230 and the conductive structure 260 are spaced apart in the row direction. The second isolation structure 2302 extends along the row direction and is connected to the plurality of first isolation structures 2301 and the conductive structure 260, so that the first isolation structure 2301 is connected to the conductive structure 260 through the second isolation structure 2302. It can be understood that the first isolation structure 2301, the second isolation structure 2302, and the conductive structure 260 all have the same potential.

[0081] This application also provides a method for fabricating a semiconductor structure 200, which can be used to fabricate the semiconductor structure 200 in the above embodiments. (Referring to...) Figure 5 This manufacturing method may include steps S100-S400.

[0082] S100: Provides a silicon substrate.

[0083] S200: An isolation trench is formed on a silicon substrate.

[0084] In S200, refer to Figures 6 to 8 Before forming the isolation trench 280 on the silicon substrate 220, the fabrication method further includes forming a mask 281 on the silicon substrate 220, which may be formed by depositing silicon nitride (SiN).

[0085] Before forming the mask 281, an oxide layer 282 can be formed on the silicon substrate 220, so that the oxide layer 282 is located between the mask 281 and the silicon substrate 220, which can reduce the stress between the mask 281 and the silicon substrate 220.

[0086] Reference Figure 7 and Figure 8 A portion of the mask 281 is removed to form mask holes 283, and a portion of the silicon substrate 220 is removed according to the mask holes 283 to form isolation trenches 280. Multiple isolation trenches 280 can be formed, and the multiple isolation trenches 280 are arranged at intervals.

[0087] Meanwhile, by removing part of the silicon substrate 220 according to the mask hole 283, a lead-out trench 284 can also be formed, and the lead-out trench 284 is arranged at intervals with multiple isolation trenches 280.

[0088] Depending on the size of the mask aperture 283 and the depth to which the silicon substrate 220 is removed, isolation trenches 280 with different structures can be formed. In some embodiments, the formed isolation trench 280 includes two sidewalls 2811; in other embodiments, the formed isolation trench 280 includes two sidewalls 2811 and a bottom wall 2812. It should be noted that the structure and size of the lead-out trench 284 are the same as those of the isolation trench 280.

[0089] Please refer to Figure 9 The formation of the isolation groove 280 includes forming a plurality of first isolation grooves 2801 and a plurality of second isolation grooves 2802. The manufacturing method of the first isolation groove 2801 is the same as that of the second isolation groove 2802, so the depths of the first isolation grooves 2801 and the second isolation grooves 2802 are the same. The first isolation grooves 2801 extend along the column direction, and the second isolation grooves 2802 extend along the row direction. The plurality of first isolation grooves 2801 are spaced apart along the row direction, and the plurality of second isolation grooves 2802 are spaced apart along the column direction. The first isolation grooves 2801 and the second isolation grooves 2802 are interconnected.

[0090] The extension direction of the lead-out groove 284 is the same as that of the first isolation groove 2801, and the multiple first isolation grooves 2801 are located on the same side of the lead-out groove 284. For example, the lead-out groove 284 can be located on the left or right side of all the first isolation grooves 2801. The second isolation groove 2802 can connect the multiple first isolation grooves 2801 and the lead-out groove 284.

[0091] S300: An isolation structure is formed in an isolation trench. The formation of the isolation structure includes the sequential formation of a first insulating layer, a conductive layer, and a second insulating layer. The first insulating layer is located between the silicon substrate and the conductive layer, and the conductive layer is located between the first insulating layer and the second insulating layer.

[0092] In S300, refer to Figure 10and Figure 11 First, an oxide layer 231 is formed by depositing oxide on the isolation trench 280. This includes depositing insulating oxide within the isolation trench 280 to form an initial first insulating layer 2310, which covers the inner wall of the isolation trench 280 and the mask plate 281. The portion of the initial first insulating layer 2310 covering the inner wall of the isolation trench 280 is ultimately retained to form the final first insulating layer 231. In an embodiment where the formed isolation trench 280 includes two sidewalls 2811, forming the first insulating layer 231 includes forming a first insulating portion 2311 and a second insulating portion 2312 on the two sidewalls 2811, respectively. In an embodiment where the formed isolation trench 280 includes two sidewalls 2811 and a bottom wall 2812, forming the first insulating layer 231 includes forming a first insulating portion 2311 and a second insulating portion 2312 on the two sidewalls 2811, and forming a third insulating portion 2313 on the bottom wall 2812.

[0093] Reference Figure 12 and Figure 13 Then, a conductive layer 232 is formed on the initial first insulating layer 2310, including depositing a conductive material (TiN, W, etc.) within the isolation trench 280 to form the initial conductive layer 2320, which covers the initial first insulating layer 2310. Ultimately, a portion of the initial conductive layer 2320 covering the first insulating layer 2310 is retained, wherein the portion of the initial conductive layer 2320 located within the isolation trench 280 forms the conductive layer 232. In embodiments where forming the first insulating layer 231 includes forming a first insulating portion 2311 and a second insulating portion 2312 on two sidewalls 2811 respectively, forming the conductive layer 232 includes forming a first conductive portion 2321 covering the first insulating portion 2311 and forming a second conductive portion 2322 covering the second insulating portion 2312. In an embodiment where forming the first insulating layer 231 includes forming a first insulating portion 2311 and a second insulating portion 2312 on two sidewalls 2811 and forming a third insulating portion 2313 on the bottom wall 2812, forming the conductive layer 232 includes forming a first conductive portion 2321 covering the first insulating portion 2311, forming a second conductive portion 2322 covering the second insulating portion 2312, and forming a third conductive portion 2323 covering the third insulating portion 2313.

[0094] While the conductive layer 232 is being formed, a portion of the initial conductive layer 2320 located within the lead-out groove 284 forms a conductive structure 260. The conductive layer 232 is connected to the conductive structure 260.

[0095] Reference Figure 14 In the above steps, during the process of forming the conductive layer 232 by removing part of the initial conductive layer 2320, the height of the conductive layer 232 in the isolation groove 280 can be adjusted as needed so that the final isolation structure 230 achieves the required isolation effect.

[0096] Reference Figure 15 After the conductive layer 232 is formed, an insulating oxide is deposited to form a second insulating layer 233. The second insulating layer 233 fills the isolation trench 280, so that the formed conductive layer 232 is located between the first insulating layer 231 and the second insulating layer 233. The first insulating layer 231, the conductive layer 232, and the second insulating layer 233 form an isolation structure 230.

[0097] Reference Figure 16 The isolation structure 230 is formed by forming a first isolation structure 2301 in a first isolation groove 2801 and a second isolation structure 2302 in a second isolation groove 2802, and the first isolation structure 2301 and the second isolation structure 2302 are connected.

[0098] S400: A transistor is formed on a silicon substrate, with the transistor located between two adjacent isolation structures.

[0099] In S400, refer to Figure 16 and Figure 17 Forming a transistor 210 on a silicon substrate 220 includes removing the mask 281 and oxide layer 282 covering the silicon substrate 220, and then performing operations such as doping on the silicon substrate 220 to form a transistor 210 between two adjacent isolation structures 230. Multiple transistors 210 can be formed in the regions defined by multiple first isolation structures 2301 and multiple second isolation structures 2302, with the multiple transistors 210 in the same region spaced apart along the extending direction of the first isolation structure 2301.

[0100] Reference Figure 18 After transistor 210 is formed, insulating oxide can be deposited to form a third insulating layer 234, which covers transistor 210, isolation structure 230, and conductive structure 260. The material used to form the third insulating layer 234 is the same as that used to form the second insulating layer 233, and there is no clear boundary between the second insulating layer 233 and the third insulating layer 234.

[0101] Reference Figure 19 and Figure 20 The manufacturing method further includes forming a contact hole 285 on a portion of the second insulating layer 233 and the third insulating layer 234 covering the conductive structure 260, with one end of the contact hole 285 exposing the conductive structure 260; then filling the contact hole 285 with conductive material to form a contact structure 270, which is connected to the conductive structure 260.

[0102] While forming the contact hole 285, a lead-out hole 286 can also be formed on a portion of the second insulating layer 233 and the third insulating layer 234 covering the transistor 210, exposing the transistor 210; then, conductive material is filled into the lead-out hole 286 to form a lead-out structure 240. For simplified illustration, as shown... Figure 20 As shown, Figure 1 The first lead-out structure 241 connected to the source 211 of transistor 210, the second lead-out structure 242 connected to the drain 212 of transistor 210, and the third lead-out structure 243 connected to the gate 213 of transistor 210 are schematically referred to as lead-out structure 240.

[0103] Please refer to Figure 21 and Figure 22 Some embodiments of this application also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the semiconductor structure 200 as described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0104] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0105] In some embodiments, refer to Figure 21 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0106] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0107] In other embodiments, reference is made to Figure 22 The storage system 1000 includes a controller 20 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0108] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0109] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0110] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0111] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0112] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0113] Some embodiments of this application also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0114] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a silicon substrate; a plurality of transistors disposed on the silicon substrate, the plurality of transistors being spaced apart; a plurality of isolation structures, one of the isolation structures being disposed between two adjacent transistors; wherein the isolation structure comprises a first insulating layer, a conductive layer, and a second insulating layer, the first insulating layer being disposed between the silicon substrate and the conductive layer, and the conductive layer being disposed between the first insulating layer and the second insulating layer.

2. The semiconductor structure of claim 1, wherein, The first insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion being in contact with one of the two adjacent transistors, and the second insulating portion being in contact with the other of the two adjacent transistors, and an end of the first insulating portion close to the silicon substrate being connected to an end of the second insulating portion close to the silicon substrate. The conductive layer comprises a first conductive portion and a second conductive portion, the first conductive portion covering the first insulating portion, and the second conductive portion covering the second insulating portion, and an end of the first conductive portion close to the silicon substrate being connected to an end of the second conductive portion close to the silicon substrate.

3. The semiconductor structure of claim 2, wherein, The first insulating layer further comprises a third insulating portion, the third insulating portion being disposed between the silicon substrate and the first insulating portion and the second insulating portion, the third insulating portion being in contact with the silicon substrate between the two adjacent transistors, an end of the first insulating portion close to the silicon substrate being connected to the third insulating portion, and an end of the second insulating portion close to the silicon substrate also being connected to the third insulating portion. The conductive layer further comprises a third conductive portion, the third conductive portion covering the third insulating portion, the third conductive portion being disposed between the first conductive portion and the second conductive portion, an end of the first conductive portion close to the silicon substrate being connected to the third conductive portion, and an end of the second conductive portion close to the silicon substrate also being connected to the third conductive portion.

4. The semiconductor structure according to any of claims 1 to 3, characterized in that The silicon substrate has opposite first and second faces, the transistors and the isolation structures are disposed on the first face, and the distance from the conductive layer to the second face is less than the distance from the transistors to the second face.

5. The semiconductor structure of any of claims 1-3, wherein the semiconductor structure is a semiconductor-on-insulator structure. The semiconductor structure further comprises a conductive structure and a contact structure, the conductive structure and the transistors are disposed on the same face of the silicon substrate, and the conductive structure is connected to the isolation structures. The contact structure is located on the side of the conductive structure away from the silicon substrate, and the contact structure is connected to the conductive structure, and the contact structure is configured as a reference potential.

6. The semiconductor structure of claim 5, wherein, The conductive structure is located on the same side of the plurality of transistors.

7. The semiconductor structure of claim 6, wherein, The plurality of transistors are arranged in an array, the plurality of isolation structures comprise a plurality of first isolation structures and a plurality of second isolation structures, the first isolation structures are located between two adjacent transistors in a row direction, the second isolation structures are located between two adjacent transistors in a column direction, the extension direction of the conductive structure is the same as the extension direction of the first isolation structures, and the first isolation structures are connected to the conductive structure through the second isolation structures.

8. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure comprises: providing a silicon substrate; forming an isolation groove on the silicon substrate; An isolation structure is formed within the isolation trench. The formation of the isolation structure includes the sequential formation of a first insulating layer, a conductive layer, and a second insulating layer. The first insulating layer is located between the silicon substrate and the conductive layer, and the conductive layer is located between the first insulating layer and the second insulating layer. A transistor is formed on the silicon substrate, the transistor being located between two adjacent isolation structures.

9. The method of manufacturing according to claim 8, wherein, The formed isolation groove includes two sidewalls; Forming the first insulating layer includes forming a first insulating portion and a second insulating portion on the two sidewalls, respectively. Forming the conductive layer includes forming a first conductive portion covering the first insulating portion and a second conductive portion covering the second insulating portion.

10. The method of manufacturing according to claim 9, wherein, The formed isolation groove also includes a bottom wall; Forming the first insulating layer also includes forming a third insulating portion on the bottom wall; The formation of the conductive layer also includes forming a third conductive portion that covers the third insulating portion.

11. A method of manufacture according to any one of claims 8 to 10, wherein, The semiconductor structure fabrication method further includes: A conductive structure is formed simultaneously with the isolation structure, the isolation structure is connected to the conductive structure, and all of the multiple isolation structures are located on the same side of the conductive structure. A contact hole is formed, and a contact structure is formed within the contact hole. The formed contact structure is connected to the conductive structure.

12. The method of making according to any one of claims 8-10, wherein, Forming an isolation groove includes forming a first isolation groove and a second isolation groove that are interconnected, wherein the second isolation groove extends along the row direction and the first isolation groove extends along the column direction; The formation of the isolation structure includes forming a first isolation structure in the first isolation groove and forming a second isolation structure in the second isolation groove, wherein the first isolation structure and the second isolation structure are connected.

13. A storage system, characterized by include: The controller and the semiconductor structure according to any one of claims 1-7, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data.

14. An electronic device, comprising: Including the storage system as described in claim 13.

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