Trench isolation fabrication method and semiconductor structure

Abstract

This invention relates to a method for fabricating trench isolation and a semiconductor structure. In the fabrication method, after forming a linear oxide layer on the inner wall of the trench and before filling the trench, a linear nitride layer is formed along the inner wall of the trench and the surface of the pad nitride layer. Hydrogen plasma treatment is then performed to form a hydrogen-rich layer of at least a partial thickness of the linear nitride layer. When filling the trench with dielectric material, the deposition base surface on the inner wall of the trench is consistent with the deposition base surface outside the trench, resulting in a more balanced deposition rate inside and outside the trench. This reduces the risk of voids or seams in the dielectric material inside the trench due to faster deposition outside the trench. Furthermore, during filling the trench with dielectric material and annealing, the hydrogen-rich layer reacts with oxygen in the dielectric material, reducing the degree of substrate oxidation and mitigating linewidth loss in the active region. The semiconductor structure can be formed using the above-described fabrication method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating trench isolation and a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, trench isolation (such as deep trench isolation (DTI) or shallow trench isolation (STI)) and active regions separated by the trench isolation are typically formed in the substrate. Figure 1 This illustrates a commonly used method for fabricating trench isolation systems. (Refer to...) Figure 1 Common trench isolation fabrication methods include: as shown in (a), a pad oxide layer 11 and a pad nitride layer 12 are sequentially formed on the surface of a substrate 10, and a trench T1 extending from the upper surface of the pad nitride layer 12 into the substrate 10 is formed by etching, the trench T1 defining the active area (AA) in the substrate 10; then, as shown in (b), a pull-back process is performed on the pad nitride layer 12 to move the side of the pad nitride layer 12 inward, thereby widening the trench T1 at the opening of the pad nitride layer 12; next, as shown in (c), a linear oxide layer 13 is formed on the inner surface of the trench T1; then, as shown in (d), due to its excellent trench filling capability, a HARP (high aspect ratio) process is used. (High aspect ratio process) Deposit dielectric material 14, which fills trench T1 and is also deposited on pad nitride layer 12; then, as shown in (e), annealing is performed to improve the quality of dielectric material 14; subsequently, as shown in (f), a CMP process is performed to expose the upper surface of pad nitride layer, and the remaining dielectric material 14 fills trench T1 to form trench filling layer. Annealing can then be performed again, as shown in (g).

[0003] Studies have found that in the above-mentioned trench isolation fabrication method, after annealing following the deposition of the deposition medium material 14, the linewidth of the active region is significantly reduced, such as... Figure 1 As shown in (d), before annealing after depositing the dielectric material 14, the linewidth of the active region AA located between the trenches is CD1. After the first annealing, the linewidth of the same active region AA decreases to CD2. After the second annealing, the linewidth of the same active region AA further decreases to CD3, satisfying CD1>CD2>CD3. The linewidth loss due to annealing will cause the active region area to decrease, affecting the flexibility of active region design and the integration density of semiconductor devices. In addition, studies have found that using the above-mentioned existing trench isolation fabrication method, the dielectric material 14 in the trench T1 is prone to voids or seams, such as... Figure 2 The joint 14a shown affects the stability and reliability of the device. Summary of the Invention

[0004] Reference Figure 3 It shows the cross-sectional structure after depositing the medium material 14 in trench T1 using the existing trench isolation fabrication method and undergoing the first annealing. The dashed line indicates the location of the active region AA before annealing. The study found that... Figure 3 Because the dielectric material 14 contains a large amount of oxygen, during the HARP process and annealing, an oxygen-rich environment is formed between the linear oxide layer 13 on the inner wall of trench T1 and the dielectric material 14 in trench T1. This allows a large amount of oxygen to diffuse into the linear oxide layer 13 and further oxidize the substrate silicon below the linear oxide layer 13, resulting in a linewidth loss in the active region AA. In addition, studies have found that the deposition rate of the dielectric material 14 on nitride (such as silicon nitride) and oxide (such as silicon oxide) surfaces is affected. Unlike other methods, the deposition rate on nitride surfaces is faster. In existing trench isolation fabrication methods, before depositing the medium material 14 in trench T1, the deposition surface on the inner wall of trench T1 is a linear oxide layer 13, while the deposition surface outside trench T1 is a pad nitride layer 12. The difference in materials causes the medium material 14 to deposit faster on the pad nitride layer 12 and slower in trench T1. This can easily lead to the medium material 14 sealing the trench T1 before it is fully filled, resulting in voids or seams (such as...). Figure 2 (as shown in the image)

[0005] In order to fabricate trench isolation in a substrate and improve the problems of active region linewidth loss after depositing dielectric material in the trench and annealing, as well as the easy generation of voids or seams in the dielectric material in the trench, the present invention provides a method for fabricating trench isolation and a semiconductor structure.

[0006] On one hand, the present invention provides a method for manufacturing trench isolation, the method comprising:

[0007] A pad oxide layer and a pad nitride layer are stacked on the upper surface of the substrate;

[0008] The pad nitride layer, the pad oxide layer, and the substrate are etched to form a trench extending from the upper surface of the pad nitride layer into the substrate, the trench defining an active region in the substrate;

[0009] A linear oxide layer is formed on the inner wall of the trench;

[0010] A linear nitriding layer is formed along the inner wall of the trench and the surface of the pad nitriding layer;

[0011] The linear nitride layer is subjected to hydrogen plasma treatment to form a hydrogen-rich layer with at least a portion of its thickness.

[0012] The trench is filled with a medium material; and

[0013] Perform the first annealing process.

[0014] Optionally, after the hydrogen plasma treatment and before filling the trench with a dielectric material, the fabrication method further includes:

[0015] An oxidation process is performed to form a first oxide coating layer on the surface of the hydrogen-rich layer.

[0016] Optionally, the oxidation treatment includes oxygen plasma treatment or treatment under an oxidizing atmosphere.

[0017] Optionally, before performing the first annealing process, the dielectric material further covers the outside of the trench; after completing the first annealing process, the manufacturing method further includes:

[0018] A planarization process is performed to expose the upper surface of the nitrided pad layer, and the remaining dielectric material fills the trench with its upper surface flush with the upper surface of the nitrided layer; and

[0019] Perform the second annealing process.

[0020] Optionally, the linear nitride layer is formed using an ALD process.

[0021] Optionally, the first annealing process is steam annealing.

[0022] Optionally, the linear nitriding layer is formed entirely as the hydrogen-rich layer, and the hydrogen-rich layer is adjacent to the linear oxide layer; or, a portion of the linear nitriding layer is formed as the hydrogen-rich layer, and the remaining thickness of the linear nitriding layer is further included between the hydrogen-rich layer and the linear oxide layer.

[0023] On the other hand, the present invention provides a semiconductor structure, the semiconductor structure comprising:

[0024] A substrate having trenches formed therein, the trenches extending from the upper surface of the substrate into the substrate, the trenches defining an active region in the substrate;

[0025] A linear stack is formed on the inner wall of the trench, the linear stack including a linear oxide layer covering the inner wall of the trench and an oxide capping layer formed on the side of the linear oxide layer away from the inner wall of the trench; and

[0026] The trench is filled with a medium that covers the linear stack and fills the trench.

[0027] Optionally, the linear stack further includes a linear nitride layer between the linear oxide layer and the oxide capping layer, wherein the linear oxide layer, the linear nitride layer and the oxide capping layer form an ONO structure.

[0028] Optionally, in the linear stack, the thickness of the linear oxide layer is The thickness of the linear nitride layer is The thickness of the oxide coating is

[0029] In the trench isolation fabrication method provided by this invention, after forming a linear oxide layer on the inner wall of the trench and before filling with dielectric material, a linear nitride layer is formed along the inner wall of the trench and the surface of the pad nitride layer. The linear nitride layer is then subjected to hydrogen plasma treatment to form a hydrogen-rich layer of at least a portion of its thickness. When filling the trench with dielectric material, the deposition base surface on the inner wall of the trench is consistent with the deposition base surface outside the trench, resulting in a more balanced deposition rate of dielectric material inside and outside the trench. Compared with the prior art, this reduces the risk of voids or seams in the dielectric material inside the trench due to faster deposition outside the trench. Furthermore, when filling the trench with dielectric material and performing subsequent annealing processes, oxygen in the dielectric material diffuses towards the linear oxide layer and is first consumed by the hydrogen-rich layer, thereby reducing oxygen diffusion to the linear oxide layer and the active substrate below it. This reduces the degree of substrate oxidation during filling the trench with dielectric material and subsequent annealing processes, mitigating linewidth loss in the active region. Furthermore, the hydrogen-rich layer reacts with oxygen to form oxides. That is, at least a portion of the linear nitride layer formed before hydrogen plasma treatment can be transformed into an oxide capping layer between the linear oxide layer and the trench filling medium in subsequent processes, which can reduce the stress impact of the linear nitride layer on the active region. Moreover, by reasonably setting the thickness of the linear nitride layer and the hydrogen plasma treatment conditions, the linear nitride layer can be completely transformed into an oxide capping layer after the medium material is filled in the trench and annealed. This results in the final product having virtually no linear nitride layer, which can further reduce the stress impact of the linear nitride layer on the active region.

[0030] In the semiconductor structure provided by the present invention, a linear stack is formed on the inner wall of the trench. The linear stack includes a linear oxide layer and an oxide capping layer. The oxide capping layer helps to block the diffusion of oxygen in the dielectric material to the linear oxide layer and the active region substrate below it during the formation of the filling dielectric in the trench and the subsequent annealing process, so that the substrate is less oxidized and the linewidth loss of the active region is reduced. Attached Figure Description

[0031] Figure 1 This is a cross-sectional schematic diagram of an existing trench isolation fabrication method.

[0032] Figure 2 This is a cross-sectional schematic diagram showing the formation of voids in the medium material within the trench when using existing trench isolation fabrication methods.

[0033] Figure 3 yes Figure 1 The diagram in (e) shows the reduction in the linewidth of the active region.

[0034] Figure 4 This is a schematic flowchart of the trench isolation fabrication method according to an embodiment of the present invention.

[0035] Figure 5 This is a cross-sectional schematic diagram of a method for manufacturing trench isolation according to an embodiment of the present invention.

[0036] Figure 6 This is a cross-sectional schematic diagram of a method for manufacturing trench isolation according to another embodiment of the present invention.

[0037] Figure 7 This is a cross-sectional schematic diagram of a method for manufacturing trench isolation according to another embodiment of the present invention.

[0038] Figure 8 This is a cross-sectional schematic diagram of a method for manufacturing trench isolation according to another embodiment of the present invention. Detailed Implementation

[0039] The trench isolation fabrication method and semiconductor structure of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the terms "first," "second," etc., used in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms can be replaced where appropriate. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, and are only used to facilitate clarity in illustrating the embodiments of the present invention. Furthermore, spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0040] The following first combines Figures 4 to 8 This invention introduces a method for fabricating trench isolation according to an embodiment of the present invention.

[0041] Reference Figure 4 and Figures 5 to 8 In step (a) of the trench isolation fabrication method according to an embodiment of the present invention, step S1 is performed to stack and form a pad oxide layer 110 and a pad nitride layer 120 on the upper surface of a substrate 100.

[0042] The substrate 100 may be a silicon substrate, germanium (Ge) substrate, germanium-silicon substrate, SOI (Silicon On Insulator) substrate, or GOI (Germanium On Insulator) substrate, or other substrates used in semiconductor manufacturing. In the following embodiments, the substrate 100 is, for example, a silicon substrate, the pad oxide layer 110 is, for example, a silicon oxide layer, and the pad nitride layer 120 is, for example, a silicon nitride layer.

[0043] Reference Figure 4 and Figures 5 to 8 In step S2, the pad nitride layer 120, the pad oxide layer 110, and the substrate 100 are etched to form a trench TR extending from the upper surface of the pad nitride layer 120 into the substrate 100, the trench TR defining an active region AA in the substrate 100.

[0044] The location of the trench TR can be defined using photolithography, and the trench TR, penetrating the pad nitride layer 120, the pad oxide layer 110, and a portion of the substrate 100, can be formed through one or more etching processes. In the following embodiments, the trench TR is, for example, a shallow trench with a depth of approximately 100 nm to 400 nm. In other embodiments, the trench TR may also be a deep trench.

[0045] Reference Figures 5 to 8 Optionally, in (b), the pad nitride layer 120 can be etched back to move the side of the pad nitride layer 120 inward (i.e., move it to the inside of the pad nitride layer 120 so that the area of ​​the pad nitride layer 120 is smaller than the area of ​​the active region AA below). By performing this etch-back process, the opening of the trench TR in the pad nitride layer 120 is widened, and the dielectric material subsequently filled in the trench TR covers the corner of the opening of the trench TR, which helps to reduce the leakage risk of the active region AA.

[0046] Reference Figure 4 and Figures 5 to 8 Following step (c), in step S3, a linear oxide layer 130 is formed on the inner wall of the trench TR. The linear oxide layer 130 is, for example, a silicon oxide layer that covers the surface of the substrate 100 (or active region AA) exposed on the inner wall of the trench TR. The linear oxide layer 130 can be formed using thermal oxidation, RTA (rapid thermal annealing), ISSG (in-situ vapor generation), or other suitable processes. This embodiment, for example, employs the ISSG process.

[0047] Next, refer to Figure 4 and Figures 5 to 8In step (d), step S4 is performed to form a linear nitride layer 140 along the inner wall of the trench TR and the surface of the pad nitride layer 120. The linear nitride layer 140 is, for example, silicon nitride. The linear nitride layer 140 conformally covers the substrate 100. The linear nitride layer 140 can be formed using an ALD (atomic layer deposition) process or other suitable processes. The thickness of the linear nitride layer 140 is, for example, [missing information]. For example,

[0048] Then, refer to Figure 4 and Figures 5 to 8 In step (e), step S5 is performed to treat the linear nitride layer 140 with hydrogen plasma so that the linear nitride layer 140 with at least a partial thickness forms a hydrogen-rich layer 141.

[0049] The hydrogen plasma treatment can be implemented using CVD (chemical vapor deposition) equipment, DE (dry etching) equipment, or dedicated equipment. For example, a remote plasma system (RPS) of a CVD equipment or the in-situ plasma function inside a CVD chamber can be used. The substrate 100 after the linear nitride layer 140 is formed is placed in the equipment chamber, and hydrogen (H2) and a carrier gas (such as nitrogen (N2) or argon (Ar)) are introduced into the chamber. The flow rate of hydrogen is, for example, 1 sccm to 500 sccm. Under appropriate conditions, hydrogen plasma is generated in the chamber, and the hydrogen plasma bombards the surface of the linear nitride layer 140.

[0050] During the aforementioned hydrogen plasma treatment, the hydrogen plasma, particularly the hydrogen radicals within it, enters the linear nitride layer 140 to form a hydrogen-rich layer 141. These hydrogen radicals can react with the linear nitride layer 140. For example, when the linear nitride layer 140 is silicon nitride, the hydrogen radicals can form Si-H bonds with the silicon in the silicon nitride. These Si-H bonds are distributed within the hydrogen-rich layer 141. Within a certain time range, as the hydrogen plasma treatment time increases, the thickness of the hydrogen-rich layer 141 with Si-H bonds gradually increases from the surface to the interior of the linear nitride layer 140. The thickness direction of the hydrogen-rich layer 141 is the same as that of the linear nitride layer 140. By controlling the hydrogen plasma treatment time, the thickness of the hydrogen-rich layer 141 can be controlled to be less than or equal to the thickness of the linear nitride layer 140. In other words, the thickness of the hydrogen-rich layer 141 can be adjusted by changing the process conditions of the hydrogen plasma treatment.

[0051] In some embodiments, such as Figure 5 and Figure 6As shown in (e), by adjusting the process conditions of the hydrogen plasma treatment, the linear nitride layer 140 is integrally formed into a hydrogen-rich layer 141 after hydrogen plasma treatment, and the hydrogen-rich layer 141 is adjacent to the linear oxide layer 130. However, this is not the only embodiment; in other embodiments, by adjusting the process conditions of the hydrogen plasma treatment, such as... Figure 7 and Figure 8 As shown in (e), after hydrogen plasma treatment, a portion of the linear nitride layer 140 is formed into a hydrogen-rich layer 141, and between the formed hydrogen-rich layer 141 and the linear oxide layer 130, there is a remaining thickness of linear nitride layer 140 that has not been converted into the hydrogen-rich layer 141.

[0052] Reference Figure 4 , Figure 5 and Figure 7 (f) and Figure 6 and Figure 8 Following step (g), step S6 is performed to fill the trench TR with dielectric material 150. The HARP process has excellent trench filling performance; therefore, this embodiment of the invention employs the HARP process to fill the trench TR with dielectric material to form trench isolation.

[0053] As an example, in some embodiments, the HARP process (see [reference]) is performed immediately after the formation of the linear nitride layer 140 and the completion of the hydrogen plasma treatment. Figure 5 and Figure 7 In (f) of the diagram, the dielectric material 150 deposited by the HARP process is deposited on the surface of the hydrogen-rich layer 141, which is transformed from the linear nitride layer 140. That is, the hydrogen-rich layer 141 serves as both the HARP deposition base surface within and outside the trench TR. Since the deposition base surface of the HARP-deposited dielectric material 150 is the same at different locations, the deposition rate is essentially consistent. This means that the deposition rate of the dielectric material 150 within the trench TR, at the opening of the trench TR, and outside the trench TR differs very little. This avoids the problem of inconsistent deposition rates due to inconsistent base surfaces inside and outside the trench during HARP deposition in existing technologies. It also reduces the risk of voids or seams in the dielectric material within the trench caused by faster deposition outside the trench, improving the stability and reliability of the semiconductor device to be formed. Simultaneously, during the HARP process, the hydrogen and silicon (such as Si-H bonds) in the hydrogen-rich layer 141 can react with oxygen diffusing towards the silicon substrate 100 to generate silicon oxide, thereby consuming oxygen and preventing the loss of active region AA silicon.

[0054] As an example, in some other embodiments, after forming the linear nitride layer 140 and completing the hydrogen plasma treatment, the HARP process is not performed first, but an oxidation treatment is performed instead (see [reference]). Figure 6 and Figure 8(f) In this process, after forming the first oxide capping layer 142 on the surface of the hydrogen-rich layer 141, the HARP process is then performed (refer to [reference]). Figure 6 and Figure 8 (g)). The oxidation process may include oxygen plasma treatment or treatment under an oxidizing atmosphere. The first oxide capping layer 142 is, for example, silicon oxide. Taking the oxidation process using oxygen plasma treatment as an example, the oxygen plasma treatment is performed, for example, in the same plasma-generating equipment chamber as the above-mentioned hydrogen plasma treatment. For example, an oxidizing gas is introduced into the chamber where the substrate 100 is placed to provide oxygen, and suitable conditions are set to form oxygen plasma. A carrier gas (such as nitrogen (N2) or argon (Ar)) may also be introduced. The oxidizing gas includes, for example, at least one of oxygen, ozone, and nitrogen oxides (N2O). The oxygen plasma is accelerated and bombards the surface of the hydrogen-rich layer. The oxygen can react with the hydrogen and silicon in the hydrogen-rich layer 141 (such as reacting with Si-H bonds), and the oxide formed by the reaction forms the first oxide capping layer 142 on the surface of the hydrogen-rich layer 141. When treating under an oxidizing atmosphere, the above-mentioned oxidizing gas can be introduced into the chamber where the substrate 100 is placed, and by setting appropriate temperature and pressure conditions, the first oxide capping layer 142 is formed on the surface of the hydrogen-rich layer 141. The thickness of the first oxide capping layer 142 is, for example,

[0055] The first oxide capping layer 142 located on the surface of the hydrogen-rich layer 141 may also be formed without special oxidation treatment. For example, in some embodiments, after the linear nitride layer 140 is formed and the hydrogen plasma treatment is completed, before the HARP process, the first oxide capping layer 142 is formed on the surface of the hydrogen-rich layer 141 due to the presence of natural oxidation factors in the air.

[0056] Reference Figure 6 and Figure 8 In step (g), after the oxidation treatment is completed, a HARP process is then performed, depositing the HARP-deposited dielectric material 150 onto the surface of the first oxide capping layer 142. That is, the first oxide capping layer 142 serves as both the HARP deposition base surface within and outside the trench TR. The deposition base surface for the HARP-deposited dielectric material 150 is the same at different locations, resulting in a essentially consistent deposition rate. This means that the deposition rate difference of the dielectric material 150 within the trench TR, at the opening of the trench TR, and outside the trench TR is minimal. This avoids the problem of inconsistent deposition rates due to inconsistent base surfaces inside and outside the trench during HARP deposition in existing technologies, and reduces the risk of voids or seams in the dielectric material within the trench caused by faster deposition outside the trench. The dielectric material 150 is, for example, silicon oxide.

[0057] Reference Figures 5 to 8The dielectric material 150 deposited by the HARP process fills the trench TR and is also deposited outside the trench TR. When the HARP process is completed, the upper surface of the dielectric material 150 is, for example, higher than the upper surfaces of the hydrogen-rich layer 141 and the oxide capping layer 142. The dielectric material 150 located outside the trench can be removed by a planarization process (such as CMP), and an annealing process can be performed before and / or after the planarization to improve the filling quality of the dielectric material 150.

[0058] Reference Figure 4 According to the trench isolation fabrication method of the present invention, after filling the trench TR with medium material 150, step S7 is performed to carry out the first annealing process.

[0059] As an example, a first annealing process is performed before the planarization process is used to remove the dielectric material located outside the trench TR, in order to improve the filling quality of the dielectric material 150. The first annealing process is, for example, steam annealing.

[0060] When the dielectric material 150 is filled into the trench TR and the first annealing process is performed, the interface between the inner wall of the trench TR and the dielectric material 150 is an oxygen-rich environment. In this embodiment of the invention, the dielectric material 150 and the linear oxide layer 130 are not in direct contact; there is at least a hydrogen-rich layer 141 formed by the linear nitride layer 140 between them. Therefore, when oxygen in the dielectric material 150 diffuses towards the linear oxide layer 130, it reacts with hydrogen and silicon in the hydrogen-rich layer 141 and is consumed. This reduces the amount of oxygen diffused into the linear oxide layer 130 and the active region AA of the substrate 100 below it, compared to... Figure 1 The prior art shown can reduce the degree of oxidation of the filling dielectric material 150 in the trench TR and the substrate 100 during annealing, thereby reducing the linewidth loss of the active region AA.

[0061] In addition, when filling the trench TR with dielectric material 150 and performing the first annealing process, the oxygen in the dielectric material 150 will react with the hydrogen-rich layer 141 and be consumed when it diffuses into the active region AA of the substrate 100. For the hydrogen-rich layer 141, the reaction of hydrogen and silicon with oxygen can transform the hydrogen-rich layer 141 into an oxide (such as silicon oxide), thereby forming a second oxide capping layer between the linear oxide layer 130 and the dielectric material 150. Thus, after the first annealing process is completed, at least a portion of the linear nitride layer 140 deposited in step S4 is oxidized, which can reduce the stress effect of the linear nitride layer 140 on the active region AA. In some embodiments, by reasonably setting the thickness of the linear nitride layer 140 and the processing conditions of the hydrogen plasma, the linear nitride layer 140 can be completely transformed into a hydrogen-rich layer 141. After filling the trench TR with dielectric material and undergoing a first annealing process, the hydrogen-rich layer 141 is completely transformed into oxide, thereby making the linear nitride layer 140 basically absent in the final product, which can further reduce the influence of the linear nitride layer 140 on the stress of the active region AA.

[0062] In some embodiments, such as Figure 5 As shown in (g), the linear nitride layer 140 is integrally formed as a hydrogen-rich layer 141. Within the trench TR, the bottom surface of the hydrogen-rich layer 141 is adjacent to the linear oxide layer 130, and the top surface is adjacent to the dielectric material 150. During the deposition of the dielectric material 150 and the first annealing process, the oxygen in the dielectric material 150 diffuses into the active region AA of the substrate 100 and reacts with the hydrogen-rich layer 141, thus reducing the linewidth loss of the active region AA. This is beneficial for the design of the active region AA and improving the integration density of the semiconductor device to be formed. The oxygen diffused into the hydrogen-rich layer 141 during the deposition of the dielectric material 150 and the first annealing process reacts with the hydrogen-rich layer 141, causing the hydrogen-rich layer 141 to transform into a second oxide capping layer 143. Therefore, the second oxide capping layer 143 is located between the dielectric material 150 and the linear oxide layer 130.

[0063] In some embodiments, such as Figure 6As shown in (h), the linear nitride layer 140 is formed as a hydrogen-rich layer 141. Before the HARP process, a first oxide capping layer 142 is formed on the surface of the hydrogen-rich layer 141. Thus, during the HARP process, the first oxide capping layer 142 and the hydrogen-rich layer 141 are spaced between the dielectric material 150 and the linear oxide layer 130 in the trench TR. During the deposition of the dielectric material 150 and the first annealing process, the oxygen in the dielectric material 150 diffuses into the active region AA of the substrate 100 and is blocked by the first oxide capping layer 142, and reacts with the hydrogen-rich layer 141 and is consumed, which can reduce the linewidth loss of the active region AA. Oxygen diffused into the hydrogen-rich layer 141 during the deposition medium material 150 and the first annealing process reacts with the hydrogen-rich layer 141 to form a second oxide capping layer 143 between the linear oxide layer 130 and the first oxide capping layer 142. Thus, the second oxide capping layer 143 and the first oxide capping layer 142 are located between the medium material 150 and the linear oxide layer 130. In these embodiments, both the second oxide capping layer 143 and the first oxide capping layer 142 comprise oxides formed by the oxidation reaction of the hydrogen-rich layer 141, and the second oxide capping layer 143 and the first oxide capping layer 142 can be formed as a single, integral oxide capping layer without a clear boundary.

[0064] In some embodiments, such as Figure 7 As shown in (g), during the aforementioned hydrogen plasma treatment, a portion of the linear nitride layer 140 is formed as a hydrogen-rich layer 141. During the HARP process, within the trench TR, a hydrogen-rich layer 141 and a remaining thickness of linear nitride layer 140 are spaced between the dielectric material 150 and the linear oxide layer 130. During the deposition of the dielectric material 150 and the first annealing process, when oxygen in the dielectric material 150 diffuses into the active region AA of the substrate 100, it reacts with the hydrogen-rich layer 141 and is consumed. On the other hand, the remaining thickness of the linear nitride layer 140 blocks the diffusion of oxygen through the hydrogen-rich layer 141 into the active region AA, which can further reduce the degree of oxidation of the substrate 100 during annealing and reduce the linewidth loss of the active region AA. The reaction of oxygen in the dielectric material 150 with the hydrogen-rich layer 141 can transform the hydrogen-rich layer 141 into a second oxide capping layer 143, thereby creating a second oxide capping layer 143 and a linear nitride layer 140 of remaining thickness between the dielectric material 150 and the linear oxide layer 130.

[0065] In some embodiments, such as Figure 8As shown in (h), during the aforementioned hydrogen plasma treatment, a portion of the linear nitride layer 140 is formed into a hydrogen-rich layer 141. Before the HARP process, a first oxide capping layer 142 is formed on the surface of the hydrogen-rich layer 141. During the HARP process, the first oxide capping layer 142, the hydrogen-rich layer 141, and the remaining thickness of the linear nitride layer 140 are spaced between the dielectric material 150 and the linear oxide layer 130 in the trench TR. When the dielectric material 150 is filled and the first annealing process is performed, the oxygen in the dielectric material 150 diffuses into the active region AA of the substrate 100. On the one hand, it reacts with the hydrogen-rich layer 141 and is consumed. On the other hand, the first oxide capping layer 142 and the remaining thickness of the linear nitride layer 140 block the diffusion of oxygen through the hydrogen-rich layer 141 into the active region AA. This can further reduce the degree of oxidation of the substrate 100 during annealing and reduce the linewidth loss of the active region AA. During the filling of the dielectric material 150 and the first annealing process, oxygen diffuses into the hydrogen-rich layer 141 and reacts with the hydrogen-rich layer 141, transforming the hydrogen-rich layer 141 into a second oxide capping layer 143. Thus, between the dielectric material 150 and the linear oxide layer 130, there is a first oxide capping layer 142, a second oxide capping layer 143, and a linear nitride layer 140 of remaining thickness. The first oxide capping layer 142 and the second oxide capping layer 143 are formed by the reaction of the hydrogen-rich layer 141 with oxygen, and both can be collectively referred to as oxide capping layers.

[0066] Reference Figure 5 (h) in Figure 6 (i) in Figure 7 (h) and Figure 8 As shown in (i), after completing the first annealing process described above, a planarization process can then be performed to expose the upper surface of the pad nitride layer 120. The remaining dielectric material 150 fills the trench TR and its upper surface is flush with the upper surface of the pad nitride layer 120, forming a trench isolation between the active regions AA. The planarization process is, for example, CMP (chemical mechanical polishing).

[0067] In some embodiments, after the planarization process is completed, a second annealing process can be performed to further improve the quality of trench isolation. The second annealing process is, for example, a dry thermal annealing process. During the second annealing process, an oxide capping layer formed by the reaction of a hydrogen-rich layer 141 with oxygen is formed between the dielectric material 150 and the linear oxide layer 130. This oxide capping layer is formed by the aforementioned second oxide capping layer 143 or by the first oxide capping layer 142 and the second oxide capping layer 143. Furthermore, a linear nitride layer 140 may be located between the dielectric material 150 and the linear oxide layer 130, making the substrate 100 of the active region AA less prone to oxidation. Compared to the prior art, the linewidth loss problem of the active region AA can also be improved after the second annealing process.

[0068] Reference Figures 5 to 8 The present invention also relates to a semiconductor structure, the semiconductor structure comprising:

[0069] A substrate 100 has a trench TR formed therein, the trench TR extending from the upper surface of the substrate 100 into the substrate 100, and the trench TR defines an active region AA in the substrate 100.

[0070] A linear stack is formed on the inner wall of a trench TR, the linear stack including a linear oxide layer 130 covering the inner wall of the trench TR and an oxide capping layer formed on the side of the linear oxide layer 130 away from the inner wall of the trench TR.

[0071] The trench is filled with a medium (i.e., medium material 150), which covers the linear stack and fills the trench TR.

[0072] The semiconductor structure can be formed using the trench isolation fabrication method described in the above embodiments. Figures 5 to 8 The medium material 150 is the medium filling the trench.

[0073] In one embodiment, the linear stack is formed by stacking a linear oxide layer 130 and the oxide capping layer, wherein the linear oxide layer 130 and the oxide capping layer are adjacent to each other. The oxide capping layer may include the second oxide capping layer 143 formed by the reaction of the hydrogen-rich layer 141 with oxygen during the first annealing process, as described in the above embodiments, where the medium material 150 is filled in the trench TR. Optionally, the oxide capping layer may further include a first oxide capping layer 142, which is located between the second oxide capping layer 143 and the medium material 150.

[0074] Reference Figure 7 and Figure 8 In some embodiments, in addition to the linear oxide layer 130 and the oxide capping layer, the linear stack may include a linear nitride layer 140 between the linear oxide layer 130 and the oxide capping layer, wherein the linear oxide layer 130, the linear nitride layer 140, and the oxide capping layer form an ONO structure. The oxide capping layer may include the second oxide capping layer 143 formed by the reaction of the hydrogen-rich layer 141 with oxygen during the first annealing process and the filling of the trench TR with the dielectric material 150 described in the above embodiments, and may also include a first oxide capping layer 142 formed before filling the trench TR with the dielectric material 150, wherein the first oxide capping layer 142 is located between the second oxide capping layer 143 and the dielectric material 150.

[0075] As an example, in the linear stack, the thickness of the linear oxide layer 130 is... The thickness of the linear nitride layer 140 is The thickness of the oxide coating is

[0076] In the semiconductor structure described in the above embodiments, the linear stack formed on the inner wall of the trench TR includes a linear oxide layer 130 formed on the inner wall of the trench TR and an oxide capping layer between the linear oxide layer 130 and the trench filling medium. The oxide capping layer helps to isolate oxygen in the dielectric material during the formation of the trench filling medium and subsequent annealing processes, reducing oxygen diffusion to the linear oxide layer 130 and the active region AA substrate 100 below it. This reduces the degree of oxidation of the substrate 100 during the filling dielectric material and subsequent annealing processes, alleviates the linewidth loss of the active region AA, and helps to improve the flexibility of active region design and the integration density of semiconductor devices.

[0077] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and relevant parts can be understood by referring to them.

[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a trench isolation system, characterized in that, include: A pad oxide layer and a pad nitride layer are stacked on the upper surface of the substrate; The pad nitride layer, the pad oxide layer, and the substrate are etched to form a trench extending from the upper surface of the pad nitride layer into the substrate, the trench defining an active region in the substrate; A linear oxide layer is formed on the inner wall of the trench; A linear nitriding layer is formed along the inner wall of the trench and the surface of the pad nitriding layer; The linear nitride layer is subjected to hydrogen plasma treatment to form a hydrogen-rich layer with at least a portion of its thickness. The trench is filled with a medium material; as well as Perform the first annealing process.

2. The manufacturing method as described in claim 1, characterized in that, The fabrication method further includes, after the hydrogen plasma treatment and before the trench is filled with dielectric material: An oxidation process is performed to form a first oxide coating layer on the surface of the hydrogen-rich layer.

3. The manufacturing method as described in claim 2, characterized in that, The oxidation process includes oxygen plasma treatment or treatment under an oxidizing atmosphere.

4. The manufacturing method as described in claim 1, characterized in that, Before performing the first annealing process, the dielectric material is also applied to the outside of the trench. After completing the first annealing process, the manufacturing method further includes: A planarization process is performed to expose the upper surface of the nitrided pad layer, and the remaining dielectric material fills the trench with its upper surface flush with the upper surface of the nitrided layer; and Perform the second annealing process.

5. The manufacturing method as described in claim 1, characterized in that, The linear nitride layer is formed using the ALD process.

6. The manufacturing method as described in claim 1, characterized in that, The first annealing process is steam annealing.

7. The manufacturing method according to any one of claims 1 to 6, characterized in that, The linear nitriding layer is formed entirely as the hydrogen-rich layer, and the hydrogen-rich layer is adjacent to the linear oxide layer; or, a portion of the linear nitriding layer is formed as the hydrogen-rich layer, and the remaining thickness of the linear nitriding layer is also included between the hydrogen-rich layer and the linear oxide layer.

8. A semiconductor structure, characterized in that, include: A substrate having trenches formed therein, the trenches extending from the upper surface of the substrate into the substrate, the trenches defining an active region in the substrate; A linear stack is formed on the inner wall of the trench, the linear stack including a linear oxide layer covering the inner wall of the trench and an oxide capping layer formed on the side of the linear oxide layer away from the inner wall of the trench; as well as The trench is filled with a medium that covers the linear stack and fills the trench.

9. The semiconductor structure as described in claim 8, characterized in that, The linear stack further includes a linear nitriding layer between the linear oxide layer and the oxide capping layer, wherein the linear oxide layer, the linear nitriding layer and the oxide capping layer form an ONO structure.

10. The semiconductor structure as described in claim 9, characterized in that, In the linear stack, the thickness of the linear oxide layer is The thickness of the linear nitride layer is The thickness of the oxide coating is

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