Semiconductor assembly with fingered metal wire layout
By adjusting the regional polarity of the semiconductor substrate and the metal layer structure of the pad, the problems of uneven current conduction and increased parasitic capacitance in traditional semiconductor components are solved, resulting in better current conduction and component performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PANSTAR SEMICONDUCTOR CO LTD
- Filing Date
- 2025-07-04
- Publication Date
- 2026-05-26
Smart Images
Figure CN122094486A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor components, and more particularly to a semiconductor component having a finger-structured metal wire winding layout. Background Technology
[0002] Please refer to Figure 1 and Figure 2 , Figure 1 and Figure 2 These are top and side views of a conventional semiconductor component with a finger-structured metal wire-wound layout. Because conventional semiconductor components (such as diode components, but not limited to them) 1 use a finger-structured metal wire-wound layout, uneven current conduction occurs when current flows from the first pad (e.g., input / output pad) IP1 to the second pad (e.g., ground pad) GP1.
[0003] To improve this uneven current conduction phenomenon, the traditional solution is to set multiple layers of metal PM1~PM2 and NM1~NM2 on the first pad IP1 and the second pad GP1 respectively, such as... Figure 2 As shown. However, since the parasitic capacitance C1 formed between the first pad IP1 and the second pad GP1 is directly proportional to the metal side area of the first pad IP1 and the second pad GP1 relative to each other and inversely proportional to the distance between the first pad IP1 and the second pad GP1, even though the distance between the first pad IP1 and the second pad GP1 is fixed, the increase in the metal side area of the first pad IP1 and the second pad GP1 relative to each other leads to an increase in the parasitic capacitance C1 formed between the first pad IP1 and the second pad GP1, which seriously affects the physical characteristics of the semiconductor device and needs further resolution. Summary of the Invention
[0004] Therefore, the object of the present invention is to provide a semiconductor component with a finger-structured metal winding layout to effectively solve the problems encountered in the prior art.
[0005] To achieve the above objectives, the present invention employs the following technical solution: A semiconductor component with a finger-structured metal winding layout according to the present invention includes a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities. The first pad is disposed on the first region. The first pad comprises multiple layers of metal and has a multilayer height. The second pad is disposed on the second region. The second pad comprises a single layer of metal and has a single-layer height. The multilayer height is greater than the single-layer height, causing the multilayer metal side area of the first pad relative to the second pad to be greater than the single-layer metal side area of the second pad relative to the first pad.
[0006] In one embodiment, the first pad is an input / output pad, and the second pad is a ground pad.
[0007] In one embodiment, the semiconductor substrate is N-type, the first region is P-type, and the second region is N-type. The width of the first region is smaller than the width of the second region, and the width of the multilayer metal of the first pad is smaller than the width of the single layer metal of the second pad.
[0008] In one embodiment, if the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.
[0009] Another preferred embodiment of the present invention is a semiconductor device having a finger-structured metal wire-wound layout. In this embodiment, the semiconductor device includes a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities. The first pad is disposed on the first region. The first pad comprises a single layer of metal and has a single-layer height. The second pad is disposed on the second region. The second pad comprises multiple layers of metal and has multiple-layer heights. The single-layer height is less than the multiple-layer height, such that the single-layer metal side area of the first pad relative to the second pad is less than the multiple-layer metal side area of the second pad relative to the first pad.
[0010] In one embodiment, the first pad is an input / output pad, and the second pad is a ground pad.
[0011] In one embodiment, the semiconductor substrate is N-type, the first region is P-type, and the second region is N-type. The widths of the first region and the second region are equal, and the widths of the single-layer metal of the first pad and the multilayer metal of the second pad are equal.
[0012] In one embodiment, if the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.
[0013] Another preferred embodiment of the present invention is a semiconductor component having a finger-structured metal wire-wound layout. In this embodiment, the semiconductor component includes a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities. The first pad is disposed on the first region. The first pad comprises a single layer of metal and has a single-layer height. The second pad is disposed on the second region. The second pad comprises a single layer of metal and also has a single-layer height. Both the first pad and the second pad have a single-layer height, such that the single-layer metal side area of the first pad relative to the second pad is equal to the single-layer metal side area of the second pad relative to the first pad.
[0014] In one embodiment, the first pad is an input / output pad, and the second pad is a ground pad.
[0015] In one embodiment, the semiconductor substrate is N-type, the first region is P-type, and the second region is N-type. The width of the first region is smaller than the width of the second region, and the width of the monolayer metal of the first pad is smaller than the width of the monolayer metal of the second pad.
[0016] In one embodiment, if the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.
[0017] Compared to prior art, the semiconductor component with a finger-structured metal winding layout proposed in this invention can not only reduce the metal interconnect resistance to effectively improve the uneven current conduction phenomenon, but also reduce the corresponding metal side area between the input / output pad and the ground pad to effectively avoid the increase of metal parasitic capacitance and thus improve the physical characteristics of the semiconductor component. Attached Figure Description
[0018] The drawings presented in this invention are intended to help describe various embodiments of the invention. However, to simplify the drawings and / or highlight what they are meant to represent, known structures and / or components may be depicted in a simplified schematic manner or omitted. Furthermore, the number of components in the drawings may be singular or plural. The drawings presented in this invention are for illustrative purposes only and are not intended to limit the scope of the invention.
[0019] Figure 1 and Figure 2 These are top and side views of a traditional semiconductor component with a finger-structured metal wire winding layout.
[0020] Figures 3 to 4 These are a top view and a side view of a semiconductor component with a finger-shaped metal winding layout according to one specific embodiment of the present invention.
[0021] Figure 5 This is a side view of a semiconductor component with a finger-shaped metal wire winding layout according to another specific embodiment of the present invention.
[0022] Figure 6 This is a side view of a semiconductor component with a finger-shaped metal wire winding layout, according to another specific embodiment of the present invention. [Symbol Explanation] 1: Semiconductor component IP1: First pad GP1: Second pad NS: Semiconductor substrate P+: First region CT: Contact layer PM1: First metal layer of the first pad; VIA: Through-hole layer PM2: Second metal layer of the first pad; C1: Parasitic capacitance; N+: Second region; NM1: First metal layer of the second pad. NM2: Second metal layer of the second pad; d: Distance between the first and second pads; AC: Lateral area of the contact layer; A1: Lateral area of the first metal layer. AV: Side area of the via layer; A2: Side area of the second metal layer; 2: Semiconductor component; IP2: First pad. GP2: Second pad; NM1L: First metal layer of the second pad H1: Height of the contact layer; H2: Height of the first metal layer H3: Height of the through-hole layer; H4: Height of the second metal layer C2: Parasitic capacitance; 3: Semiconductor components IP3: First pad; GP3: Second pad C3: Parasitic capacitance; 4: Semiconductor components IP4: First pad; GP4: Second pad C4: Parasitic capacitance Detailed Implementation
[0023] Any reference to components referred to herein by names such as "first," "second," etc., does not generally limit the number or order of these components. Rather, these names are used herein as a convenient way to distinguish two or more components or instances of components. Therefore, it should be understood that the names "first," "second," etc., in the claims do not necessarily correspond to the same names in the written description. Furthermore, it should be understood that references to first and second components do not imply that only two components can be used or that the first component must precede the second component. The terms "comprising," "including," "having," "containing," etc., as used herein are open-ended, meaning that they include but are not limited to.
[0024] In this invention, the terms "exemplary" and "for example" are used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the invention.
[0025] According to one specific embodiment of the present invention, a semiconductor component has a finger-structured metal wire-wound layout. In practical applications, the semiconductor component may be, for example, a diode component, but is not limited thereto. In this embodiment, the semiconductor component includes at least a semiconductor substrate, a first pad, and a second pad. The semiconductor substrate includes a first region and a second region with different polarities (e.g., P-type and N-type). The first pad is disposed on the first region. The first pad comprises multiple layers of metal and has a multilayer height. The second pad is disposed on the second region. The second pad comprises a single layer of metal and has a single layer height. The multilayer height is greater than the single layer height, such that the multilayer metal side area of the first pad relative to the second pad is greater than the single-layer metal side area of the second pad relative to the first pad.
[0026] Specifically, please refer to Figure 3 and Figure 4 , Figure 3 This is a top view of the semiconductor component 2 with a finger-like metal wire winding layout in this embodiment, and Figure 4 Then it is Figure 3The side view of semiconductor component 2 from point C to point D. Figure 3 As shown, the semiconductor component 2 includes a first pad IP2 and a second pad GP2, and the first pad IP2 and the second pad GP2 form a metal wire winding layout with a finger structure.
[0027] like Figure 4 As shown, semiconductor component 2 includes a semiconductor substrate NS, a first pad IP2, and a second pad GP2. The semiconductor substrate NS includes a first region P+ and a second region N+ with different polarities, and the width of the first region P+ is smaller than the width of the second region N+. In this embodiment, the semiconductor substrate NS can be an N-type substrate, and the first region P+ and the second region N+ can be P-type doped regions and N-type doped regions formed on the surface of the semiconductor substrate NS, respectively, and the width of the P-type doped region is smaller than the width of the N-type doped region, but this is not a limitation.
[0028] The first pad IP2 is disposed on the first region P+ and the second pad GP2 is disposed on the second region N+. In this embodiment, the first pad IP2 can be an input / output pad (e.g., an I / O pad) and the second pad GP2 can be a ground pad (e.g., a groundpad), and the width of the first pad IP2 may be smaller than the width of the second pad GP2, but is not limited thereto.
[0029] The first pad IP2 comprises multiple layers of metal and has a multi-layer height, while the second pad GP2 comprises a single layer of metal and has a single-layer height. The multi-layer height is greater than the single-layer height. In this embodiment, the first pad IP2 disposed on the first region P+ sequentially comprises, from bottom to top, a contact layer CT, a first metal layer PM1, a via layer VIA, and a second metal layer PM2. The contact layer CT is disposed on the first region P+. The first metal layer PM1 is disposed on the contact layer CT. The via layer VIA is disposed on the first metal layer PM1. The second metal layer PM2 is disposed on the via layer VIA. The second pad GP2 disposed on the second region N+ sequentially comprises, from bottom to top, a contact layer CT and a first metal layer NM1L. The contact layer CT is disposed on the second region N+. The first metal layer NM1L is disposed on the contact layer CT. The width of the first metal layer NM1L of the second pad GP2 is greater than the width of the first metal layer PM1 and the second metal layer PM2 of the first pad IP2. The contact layer CT and the via layer VIA are made of a conductive material, such as metal.
[0030] It should be noted that the multilayer height of the first pad IP2 includes the sum of the height H1 of the contact layer CT, the height H2 of the first metal layer PM1, the height H3 of the through-hole layer VIA, and the height H4 of the second metal layer PM2, while the single-layer height of the second pad GP2 only includes the sum of the height H1 of the contact layer CT and the height H2 of the first metal layer NM1L. Therefore, the multilayer height of the first pad IP2 is significantly higher than the single-layer height of the second pad GP2.
[0031] Similarly, the multilayer metal side area of the first pad IP2 relative to the second pad GP2 includes the sum of the side area AC of the contact layer CT, the side area A1 of the first metal layer PM1, the side area AV of the via layer VIA, and the side area A2 of the second metal layer PM2. However, the single-layer metal side area of the second pad GP2 relative to the first pad IP2 only includes the sum of the side area AC of the contact layer CT and the side area A1 of the first metal layer NM1L. Therefore, the multilayer metal side area of the first pad IP2 relative to the second pad GP2 is significantly larger than the single-layer metal side area of the second pad GP2 relative to the first pad IP2.
[0032] Compare this embodiment Figure 4 Compared with previous technologies Figure 2 It will later be known that: the prior art Figure 2 The metal side areas of the first pad IP1 and the second pad GP1 facing each other are equal to the sum of (AC+A1+AV+A2), while in this embodiment... Figure 4 The metal side areas of the first pad IP2 and the second pad GP2 facing each other are only the sum of (AC+A1), which is the case in this embodiment. Figure 4 The metal side areas of the first pad IP2 and the second pad GP2 facing each other are significantly smaller than those of the prior art. Figure 2 The first pad IP1 and the second pad GP1 in the figure have opposite metal side areas. Since the size of the parasitic capacitance formed between the two pads is proportional to the opposite metal side areas of the two pads, this embodiment can achieve the following when the distance between the two pads is fixed: Figure 4 The parasitic capacitance C2 formed between the first pad IP2 and the second pad GP2 in the previous technology will be significantly smaller. Figure 2 The parasitic capacitance C1 formed between the first pad IP1 and the second pad GP1 in the semiconductor component 2 proposed in this invention can effectively reduce the parasitic capacitance formed between its input / output pad and ground pad, thereby effectively solving the problem in the prior art where the increased parasitic capacitance between the input / output pad and the ground pad seriously affects the physical characteristics of the semiconductor component.
[0033] Please refer to Figure 5 , Figure 5 This is a side view of a semiconductor component 3 with a finger-like metal wire winding layout according to another embodiment of the present invention. Figure 5As shown, semiconductor component 3 includes a semiconductor substrate NS, a first pad IP3, and a second pad GP3. The semiconductor substrate NS includes a first region P+ and a second region N+ with different polarities, and the width of the first region P+ is equal to the width of the second region N+. In this embodiment, the semiconductor substrate NS can be an N-type substrate, and the first region P+ and the second region N+ can be P-type doped regions and N-type doped regions formed on the surface of the semiconductor substrate NS, respectively, and the width of the P-type doped region is equal to the width of the N-type doped region, but this is not a limitation.
[0034] The first pad IP3 is disposed on the first region P+ and the second pad GP3 is disposed on the second region N+. In this embodiment, the first pad IP3 can be an input / output pad, the second pad GP3 can be a ground pad, and the width of the first pad IP3 is equal to the width of the second pad GP3, but is not limited thereto.
[0035] The first pad IP3 comprises a single layer of metal and has a single-layer height, while the second pad GP3 comprises multiple layers of metal and has multiple-layer height. In this embodiment, the first pad IP3 disposed on the first region P+ comprises only a contact layer CT and a first metal layer PM1 from bottom to top. The contact layer CT is disposed on the first region P+. The first metal layer PM1 is disposed on the contact layer CT. The second pad GP3 disposed on the second region N+ comprises, from bottom to top, a contact layer CT, a first metal layer NM1, a via layer VIA, and a second metal layer NM2. The contact layer CT is disposed on the second region N+. The metal layer NM1 is disposed on the contact layer CT. The via layer VIA is disposed on the first metal layer PM1. The second metal layer PM2 is disposed on the via layer VIA. The widths of the first metal layer NM1 and the second metal layer NM2 of the second pad GP3 are equal to the width of the first metal layer PM1 of the first pad IP3. The contact layer CT and the via layer VIA are made of a conductive material, such as metal.
[0036] It should be noted that, as Figure 5 As shown, the multilayer height HM of the second pad GP3 includes the sum of the height H1 of the contact layer CT, the height H2 of the first metal layer NM1, the height H3 of the via layer VIA, and the height H4 of the second metal layer NM2. In contrast, the single-layer height of the first pad IP3 only includes the sum of the height H1 of the contact layer CT and the height H2 of the metal layer PM1. Therefore, the multilayer height HM of the second pad GP3 is significantly higher than the single-layer height of the first pad IP3.
[0037] Similarly, the multilayer metal side area of the second pad GP3 relative to the first pad IP3 (equal to the sum of AC+A1+AV+A2) is significantly larger than the single-layer metal side area of the first pad IP3 relative to the second pad GP3 (equal to the sum of AC+A1). This is in comparison to the embodiments described above. Figure 5 Compared with previous technologies Figure 2It will later be known that: the prior art Figure 2 The metal side areas of the first pad IP1 and the second pad GP1 facing each other are equal to the sum of (AC+A1+AV+A2), while in this embodiment... Figure 5 The metal side areas of the first pad IP3 and the second pad GP3 facing each other are only the sum of (AC+A1), which is the case in this embodiment. Figure 5 The metal side areas of the first pad IP3 and the second pad GP3 facing each other are significantly smaller than those of the prior art. Figure 2 The first pad IP1 and the second pad GP1 have opposite metal side areas. Since the parasitic capacitance formed between the two pads is proportional to the opposite metal side areas, this embodiment, with a fixed distance between the two pads, [determines the capacitance]. Figure 5 The parasitic capacitance C3 formed between the first pad IP3 and the second pad GP3 of the semiconductor component 3 will be significantly smaller than that of the prior art. Figure 2 The parasitic capacitance C1 formed between the first pad IP1 and the second pad GP1 of the semiconductor component 1 effectively solves the problem in the prior art where the increased parasitic capacitance between the input / output pad and the ground pad seriously affects the physical characteristics of the semiconductor component.
[0038] Please refer to Figure 6 , Figure 6 This is a side view of a semiconductor component with a finger-like metal wire winding layout according to another embodiment of the present invention. Figure 6 As shown, semiconductor component 4 includes a semiconductor substrate NS, a first pad IP4, and a second pad GP4. The semiconductor substrate NS includes a first region P+ and a second region N+ with different polarities, and the width of the first region P+ is smaller than the width of the second region N+. In this embodiment, the semiconductor substrate NS can be an N-type substrate, and the first region P+ and the second region N+ can be P-type doped regions and N-type doped regions formed on the surface of the semiconductor substrate NS, respectively. The width of the P-type doped region is smaller than the width of the N-type doped region, but this is not a limitation.
[0039] The first pad IP4 is disposed on the first region P+ and the second pad GP4 is disposed on the second region N+. In this embodiment, the first pad IP4 can be an input / output pad, the second pad GP4 can be a ground pad, and the width of the first pad IP4 may be smaller than the width of the second pad GP4, but is not limited thereto.
[0040] Both the first pad IP4 and the second pad GP4 comprise a single layer of metal and have a single-layer height. In this embodiment, the first pad IP4, disposed on the first region P+, sequentially comprises a contact layer CT and a first metal layer PM1 from bottom to top. The contact layer CT is disposed on the first region P+. The first metal layer PM1 is disposed on the contact layer CT. The second pad GP4, disposed on the second region N+, sequentially comprises a contact layer CT and a first metal layer NM1L from bottom to top. The contact layer CT is disposed on the second region N+. The first metal layer NM1L is disposed on the contact layer CT. The width of the first metal layer NM1L of the second pad GP4 is greater than the width of the first metal layer PM1 of the first pad IP4. The contact layer CT is made of a conductive material, such as metal.
[0041] It should be noted that, as Figure 6 As shown, the multilayer height HM of the second pad GP4 includes the sum of the height H1 of the contact layer CT and the height H2 of the first metal layer NM1L, while the single-layer height of the first pad IP4 includes the sum of the height H1 of the contact layer CT and the height H2 of the metal layer PM1. Therefore, the single-layer height HM of the second pad GP4 is equal to the single-layer height of the first pad IP4. Similarly, the single-layer metal side area of the second pad GP4 relative to the first pad IP4 is equal to the single-layer metal side area of the first pad IP4 relative to the second pad GP4 (both are equal to the sum of AC+A1). As can be seen from the description of the foregoing embodiment: This embodiment... Figure 6 The metal side areas of the first pad IP4 and the second pad GP4 in the prior art (equal to the sum of AC+A1) are significantly smaller than those in the prior art. Figure 2 The metal side areas of the first pad IP1 and the second pad GP1 facing each other are equal to the sum of AC + A1 + AV + A2. Since the parasitic capacitance formed between the two pads is proportional to the metal side areas of the two pads facing each other, this embodiment, with a fixed distance between the two pads, [achieves a certain effect]. Figure 6 The parasitic capacitance C4 formed between the first pad IP4 and the second pad GP4 of the semiconductor component 4 will be significantly smaller than that of the prior art. Figure 2 The parasitic capacitance C1 formed between the first pad IP1 and the second pad GP1 of the semiconductor component 1 effectively solves the problem in the prior art where the increased parasitic capacitance between the input / output pad and the ground pad seriously affects the physical characteristics of the semiconductor component.
[0042] The prior description of the invention is provided to enable those skilled in the art to make or practice the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations or embodiments can be combined with or implemented individually without departing from the spirit or scope of the invention. Therefore, the invention is not intended to be limited to the examples described herein, but is accorded the widest scope consistent with the principles and novel features of the invention herein.
Claims
1. A semiconductor component having a finger-like metal wire winding layout, characterized in that... Include: A semiconductor substrate includes a first region and a second region having different polarities; A first pad, disposed on the first region, the first pad comprising multiple layers of metal and having a multi-layer height; and A second pad is disposed on the second region, the second pad comprising a single layer of metal and having a single layer height; Wherein, the height of the multilayer is greater than the height of the single layer, such that the multilayer metal side area of the first pad relative to the second pad is greater than the single-layer metal side area of the second pad relative to the first pad.
2. The semiconductor component as described in claim 1, characterized in that, The first pad is an input / output pad, and the second pad is a grounding pad.
3. The semiconductor component as described in claim 2, characterized in that, The semiconductor substrate is N-type, the first region is P-type, and the second region is N-type, with the first region being smaller than the second region; the multilayer metal of the first pad is smaller than the single-layer metal of the second pad.
4. The semiconductor component as claimed in claim 1, characterized in that, If the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.
5. A semiconductor component having a finger-like metal wire winding layout, characterized in that... Include: A semiconductor substrate includes a first region and a second region having different polarities; A first pad, disposed on the first region, the first pad comprising a single layer of metal and having a single layer height; and A second pad is disposed on the second region, the second pad comprising multiple layers of metal and having a multi-layer height; Wherein, the height of a single layer is less than the height of multiple layers, such that the single-layer metal side area of the first pad relative to the second pad is less than the multi-layer metal side area of the second pad relative to the first pad.
6. The semiconductor component as claimed in claim 5, characterized in that, The first pad is an input / output pad, and the second pad is a grounding pad.
7. The semiconductor component as claimed in claim 6, characterized in that, The semiconductor substrate is N-type, the first region is P-type, and the second region is N-type. The first region and the second region are of equal size, and the single-layer metal of the first pad and the multilayer metal of the second pad are of equal size.
8. The semiconductor component as claimed in claim 5, characterized in that, If the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.
9. A semiconductor component having a finger-like metal wire winding layout, characterized in that... Include: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region having different polarities; A first pad, disposed on the first region, the first pad comprising a single layer of metal and having a single layer height; and A second pad is disposed on the second region, the second pad comprising a single layer of metal and also having the single layer height; Both the first pad and the second pad have the single-layer height, such that the single-layer metal side area of the first pad relative to the second pad is equal to the single-layer metal side area of the second pad relative to the first pad.
10. The semiconductor component as claimed in claim 9, characterized in that, The first pad is an input / output pad, and the second pad is a grounding pad.
11. The semiconductor component as claimed in claim 10, characterized in that, The semiconductor substrate is N-type, the first region is P-type, and the second region is N-type. The first region is smaller than the second region, and the monolayer metal of the first pad is smaller than the monolayer metal of the second pad.
12. The semiconductor component as claimed in claim 9, characterized in that, If the distance between the first pad and the second pad is fixed, the parasitic capacitance between the first pad and the second pad is proportional to the side area of the single-layer metal.