Three-dimensional stacked packaging substrate device and manufacturing method

Abstract

The invention provides a three-dimensional stacked packaging substrate device and a manufacturing method, and relates to the technical field of semiconductor packaging, and the three-dimensional stacked packaging substrate device comprises a substrate which is a multi-layer stacked substrate; a drop point area corresponding to the vertical interconnection terminal is provided with a backflow channel, and the backflow channel comprises a grounding via hole array or a grounding metal ring surrounding the drop point area and is used for providing a continuous reference loop for a high-speed signal transmitted through the vertical interconnection terminal. Providing a core plate, carrying out multi-layer lamination, and manufacturing a backflow channel in a corresponding vertical interconnection terminal drop point area; manufacturing blind holes or micro holes in the substrate to realize interlayer interconnection; the substrate is divided into a high-speed digital area, an analog / radio frequency area and a power supply area according to functions for partition wiring, and the ground plane of each partition is kept continuous; a decoupling device is arranged at the near end of the vertical interconnection drop point or the chip power supply inlet. The system has the beneficial effects that low reflection, low jitter and low bit error rate of high-speed signal transmission are realized, and the electromagnetic compatibility and the working reliability of the system are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically, to a three-dimensional stacked packaging substrate device and its manufacturing method. Background Technology

[0002] As integrated circuits develop towards higher density and miniaturization, 3D stacked packaging technologies (such as POP packaging and SiP packaging) effectively improve system integration and space utilization by stacking multiple chips or packages vertically. In this 3D stacked structure, high-speed signal transmission is achieved between upper and lower packages via vertical interconnect terminals such as metal pillars and solder balls, placing higher demands on the signal integrity and power integrity of the substrate. However, most existing 3D stacked packaging substrates adopt traditional two-dimensional planar wiring schemes, and the high-speed signal layer lacks a continuous reference plane, resulting in impedance discontinuities and excessively large return loop areas. At the same time, the lack of dedicated return channels around the vertical interconnect terminals leads to increased parasitic inductance and severe electromagnetic leakage. In addition, the power distribution network lacks low-impedance design, making it difficult to suppress switching noise and ground bounce noise.

[0003] To address these issues, existing technologies typically employ simple methods such as increasing the number of decoupling capacitors, thickening the copper layer, or increasing the number of substrate layers. However, these methods not only increase package size and cost but also fail to fundamentally solve the problems of discontinuous return paths and electromagnetic compatibility in high-frequency signal transmission. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional stacked packaging substrate device and manufacturing method to improve the above-mentioned problems. To achieve the above objective, the technical solution adopted by this invention is as follows: In a first aspect, this application provides a three-dimensional stacked packaging substrate device, comprising: an upper package and a lower package, wherein the lower package includes a substrate, at least one lower chip, and vertical interconnect terminals for realizing interconnection between the upper and lower layers; characterized in that the substrate is a multilayer stacked substrate, including at least a first signal layer, a first ground reference layer, a first power layer, and a second ground reference layer. The first signal layer and the first ground reference layer are arranged adjacent to each other, and the first power layer and the second ground reference layer are arranged adjacent to each other to form a power-ground plane pair. The landing area corresponding to the vertical interconnect terminal is provided with a return channel, which includes an array of ground vias or a ground metal ring surrounding the landing area, for providing a continuous reference loop for high-speed signals transmitted through the vertical interconnect terminal.

[0005] This invention relates to the field of semiconductor packaging and substrate interconnect technology, and particularly to a multilayer substrate wiring and reflow optimization structure and fabrication method suitable for three-dimensional stacked POP / SiP packages. The substrate of the lower package adopts a multilayer stacked design, including at least a signal layer, a ground reference layer, and a power layer. By arranging high-speed signal layers between adjacent reference planes to form a stripline / microstrip structure with ground plane, and setting ground vias and reflow channels around the metal pillars / solder ball landing points, the vertical interconnect between the upper and lower packages electrically forms a transmission path with low parasitic inductance and controllable impedance. Furthermore, the power distribution network of the substrate suppresses switching noise, crosstalk, and electromagnetic radiation through paired stacking of power and ground layers, near-end placement of locally decoupling devices, and zoned power supply / zoned grounding. Compared with traditional substrate solutions that primarily use two-dimensional planar traces and have discontinuous reference planes, this invention significantly improves the signal integrity and power integrity of high-speed interconnects, reduces the reflow loop area, and enhances the working margin and reliability of system-in-package.

[0006] In summary, among the technical solutions provided above, in some possible implementations, the substrate adopts a six-layer stack, which includes, in sequence along the thickness direction: a first signal layer, a first ground reference layer, a first power layer, a second signal layer, a second ground reference layer, and a third signal layer; The first signal layer and the first ground reference layer are adjacent to form a microstrip structure with ground, and the second signal layer is sandwiched between the first power layer and the second ground reference layer to form a stripline structure.

[0007] In summary of the above-mentioned technical solutions, in some possible implementations, a high-speed differential pair is arranged in the first signal layer. The high-speed differential pair adopts equal-length and equal-spacing wiring, and grounding wires are provided on both sides or ground via stitching is adopted.

[0008] In summary, among the technical solutions provided above, in some possible implementations, the high-speed differential pair achieves interlayer interconnection through micropores or blind holes during interlayer switching, and no unconnected through-hole residual piles are formed in the layer switching transition area.

[0009] In summary, in some possible implementations, the grounding via array is evenly distributed circumferentially along the landing point area, the signal landing point of the vertical interconnect terminal is located at the center, and the grounding via array and the vertical interconnect terminal together constitute a quasi-coaxial or coaxial vertical interconnect structure to form a high-speed transmission channel with low parasitic inductance and resistance to electromagnetic interference.

[0010] In summary, in some possible implementations, the return channel further includes a grounding metal ring disposed below the landing area. The grounding metal ring is electrically connected to the first grounding reference layer and / or the second grounding reference layer through multiple grounding vias to form a three-dimensional shielding structure.

[0011] In summary, in some possible implementations, the substrate is functionally divided into a high-speed digital area, an analog / RF area, and a power supply area, with the ground plane within each area remaining continuous; equipotential connections are achieved between different areas through single-point connections or controlled impedance bridging.

[0012] In summary, among the technical solutions provided above, in some possible implementations, each partition adopts a partitioned power supply and partitioned grounding design, the power supply-ground plane is independently arranged and tightly coupled in each partition, and the power networks between different partitions are connected by controlled impedance bridging or single-point grounding.

[0013] In summary, in some possible implementations, the substrate has decoupling devices arranged near the vertical interconnect landing point or the chip power supply input. The decoupling devices include surface-mount capacitors and / or embedded capacitor layers. The decoupling devices work together with the power-ground plane to reduce the impedance of the power distribution network.

[0014] Secondly, this application provides a method for fabricating a three-dimensional stacked packaging substrate device, comprising the following steps: A core board is provided and multi-layer stacked and laminated to form a substrate comprising at least a first signal layer, a first ground reference layer, a first power layer and a second ground reference layer, wherein the first signal layer is controlled to be adjacent to the first ground reference layer and the first power layer is controlled to be adjacent to the second ground reference layer to form a power-ground plane pair; A return current channel is created in the corresponding vertical interconnect terminal landing area. A grounding via array is formed by laser drilling and electroplating filling around the landing point, or by etching process to form a grounding metal ring. Blind vias or microvias are fabricated on the substrate to achieve interlayer interconnection, and the drilling depth is controlled to eliminate via piles. The substrate is divided into high-speed digital area, analog / RF area and power area according to function and the wiring is partitioned. The ground plane of each partition is kept continuous, and the equipotential connection between different partitions is achieved by single-point connection or controlled impedance bridging. Decoupling devices are placed near the vertical interconnect landing point or the chip power input, so that the decoupling devices and the power-ground plane pair work together to form a low-impedance power distribution network.

[0015] The beneficial effects of this invention are as follows: This invention provides a three-dimensional stacked packaging substrate device and manufacturing method, aiming to solve the technical problems of poor signal integrity, insufficient power integrity, and poor electromagnetic compatibility in existing three-dimensional stacked packages during high-speed interconnection. By constructing a multi-layer stacked substrate, high-speed signal layers are arranged between adjacent reference planes to form striplines or microstrip structures with ground planes. Return channels composed of ground via arrays or ground metal rings are set around the vertical interconnect terminal landing points to form a quasi-coaxial transmission structure, thereby shortening the return path and reducing parasitic inductance. Simultaneously, by configuring power-ground plane pairs and using near-end decoupling devices to construct a low-impedance power distribution network, and by adopting a partitioned power supply and partitioned grounding design, noise coupling between different functional domains is effectively suppressed. This invention achieves low reflection, low jitter, and low bit error rate in high-speed signal transmission without significantly increasing the package size, thus improving the electromagnetic compatibility and operational reliability of the system.

[0016] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the three-dimensional stacked POP / SiP packaging structure described in an embodiment of the present invention; Figure 2 This is a schematic diagram of the multilayer substrate stack structure described in an embodiment of the present invention; Figure 3 This is a schematic diagram of the return flow barrier and ground via array at the landing point of the vertical interconnect terminal as described in this embodiment of the invention; Figure 4 This is a schematic diagram illustrating the low-impedance PDN formed by the power-to-ground plane pair and the near-end decoupling device in an embodiment of the present invention. Figure 5 This is a schematic diagram of the functional partitioning of the substrate as described in an embodiment of the present invention.

[0019] Icons: 11-Upper package, 12-Metal pillar / Vertical interconnect, 13-Molding compound / Package, 14-Adapter substrate, 15-Lower package, 16-Solder ball series, 21-L1 signal layer, 22-L2 ground layer, 23-L3 power layer, 24-L4 signal layer, 25-L5 ground layer, 26-L6 signal layer / pad layer, 27-Ground via, 28-Blind / buried via or microvia, 31-Ground via enclosure, 32- Signal vertical interconnect, 33-Controlled return path, 34-GND layer, 35-PWR / GND reference layer, 41-Power layer, 42-Decoupling capacitor, 43-Power supply via, 44-Ground via, 45-Shortest loop to reduce PDN impedance, 46-Ground layer, 51-Upper lead bonding area, 52-Center array interconnect area, 53-Left lead bonding area, 54-Right lead bonding area, 55-Lower lead bonding area. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Example 1: like Figure 1-5 As shown, this embodiment provides a three-dimensional stacked packaging substrate device, including: an upper package 11 and a lower package 15. The lower package 15 includes a transition substrate 14, at least one lower chip, and metal pillars / vertical interconnects 12 for realizing the interconnection between the upper and lower layers. The transition substrate 14 is a multilayer stacked substrate, including at least an L1 signal layer 21, an L2 ground layer 22, an L3 power layer 23, and an L5 ground layer 25. Among them, the L1 signal layer 21 and the L2 ground layer 22 are arranged adjacent to each other, and the L3 power layer 23 and the L5 ground layer 25 are arranged adjacent to each other to form a power-ground plane pair; the landing area corresponding to the metal pillar / vertical interconnect 12 is provided with a return path control 33, which includes a ground via fence 31 or a grounding metal ring surrounding the landing area, for providing a continuous reference loop for high-speed signals transmitted through the metal pillar / vertical interconnect 12.

[0023] Specifically, the adapter substrate 14 adopts a six-layer stack structure, which includes, in sequence along the thickness direction: L1 signal layer 21, L2 ground layer 22, L3 power layer 23, L4 signal layer 24, L5 ground layer 25 and L6 signal layer / pad layer 26. Among them, the L1 signal layer 21 and the L2 ground layer 22 are adjacent to form a microstrip structure, and the L4 signal layer 24 is sandwiched between the L3 power layer 23 and the L5 ground layer 25 to form a stripline structure.

[0024] Specifically, high-speed differential pairs are arranged in the L1 signal layer 21 or L4 signal layer 24. The high-speed differential pairs are wired with equal length and equal spacing, and grounding wires are provided on both sides or ground vias 27 are used for stitching.

[0025] Specifically, the high-speed differential pair achieves interlayer interconnection through blind / buried holes or micro-holes 28 during interlayer switching, and no unconnected through-hole residual piles are formed in the layer switching transition area.

[0026] Specifically, the ground via fence 31 is evenly distributed circumferentially along the landing point area, and the signal landing point of the metal pillar / vertical interconnect 12 is located in the central array interconnect area 52. The ground via fence 31 and the metal pillar / vertical interconnect 12 together constitute a quasi-coaxial or coaxial vertical interconnect structure to form a high-speed transmission channel with low parasitic inductance and resistance to electromagnetic interference.

[0027] Specifically, the return path control 33 also includes a GND layer 34 or a grounding metal ring disposed below the landing area. The GND layer 34 is electrically connected to the L2 ground layer 22 and / or the L5 ground layer 25 through multiple ground vias 27 to form a three-dimensional shielding structure.

[0028] Specifically, the adapter substrate 14 is functionally divided into a high-speed digital area, an analog / RF area, and a power supply area, and the PWR / GND reference layer 35 in each area remains continuous; different areas are connected at the same potential through single-point connection or controlled impedance bridging.

[0029] Specifically, each zone adopts a zoned power supply and zoned grounding design. The power supply and ground planes are arranged independently and tightly coupled in each zone. The power networks between different zones are connected by controlled impedance bridging or single-point grounding.

[0030] Specifically, the adapter substrate 14 has decoupling capacitors 42 arranged near the metal pillar / vertical interconnect 12 landing point or the chip power supply input. The decoupling capacitors 42 include surface-mount capacitors and / or embedded capacitor layers. The decoupling capacitors 42 work together with the power-ground plane to reduce the power distribution network impedance.

[0031] This embodiment focuses on the functional partitioning design and power integrity optimization scheme of the adapter substrate 14. The top surface of the adapter substrate 14 is divided into three functional areas: a high-speed digital area, an analog RF area, and a power area, corresponding to the central array interconnect area 52, the left lead bonding area 53 / right lead bonding area 54, and the upper lead bonding area 51 / lower lead bonding area 55, respectively. The PWR / GND reference layer 35 within each partition remains continuous and intact to avoid interruption; equipotential connections are achieved between different partitions through single-point connections or controlled impedance bridging. Specifically, a narrow bridge connection with a small resistor in series is used between the high-speed digital area and the analog RF area to block the propagation path of high-frequency noise and reduce the interference of digital switching noise on analog signals.

[0032] Each zone employs an independent power-ground plane pair design. The high-speed digital zone uses L3 power layer 23 and L5 ground layer 25 to form a power-ground plane pair, while the analog RF zone uses an independent power layer 41 and ground layer 46. The power zone uses a fourth power layer and a fourth ground reference layer. The power layer 41 and ground layer 46 of each zone are tightly coupled through a thin dielectric layer to reduce distributed inductance and achieve zoned power supply and zoned grounding. Vertical interconnects 32 are used to realize signal transmission between different layers.

[0033] At the metal pillar / vertical interconnect 12 landing points and chip power supply entry points, embedded capacitor layers are used as decoupling capacitors 42. These embedded capacitor layers are made of high-dielectric-constant ceramic material and are directly integrated between the power layer 41 and ground layer 46 via a parallel-plate capacitor structure, forming a distributed capacitor network. Compared to surface-mount capacitors, embedded capacitor layers have lower equivalent series inductance and wider bandwidth response, and can work synergistically with the power-ground plane pair to maintain low power distribution network impedance over a wide frequency range. Power vias 43 and ground vias 44 are used to implement vertical interconnects for power and ground, and the shortest loop reduces PDN impedance 45, optimizing the impedance characteristics of the power distribution network.

[0034] During the fabrication of the adapter substrate 14, core boards for each functional area are first prepared separately. After precise alignment, lamination is performed to ensure accurate alignment of the power layer 41 and ground layer 46 in each zone. Subsequently, blind / buried vias or microvias 28 are fabricated in each zone using laser drilling technology to achieve interlayer interconnection. Finally, a controlled impedance bridging structure is fabricated at the boundary between zones to complete the integration of the functional zones and the low-impedance power distribution network. This design effectively isolates noise coupling between different functional domains and improves the system's operational stability in mixed-signal environments.

[0035] Example 3: This embodiment provides a method for fabricating a three-dimensional stacked packaging substrate device, including the following steps: A core board is provided and multi-layer stacked and pressed to form a transition substrate 14 comprising at least an L1 signal layer 21, an L2 ground layer 22, an L3 power layer 23 and an L5 ground layer 25, wherein the L1 signal layer 21 is adjacent to the L2 ground layer 22 and the L3 power layer 23 is adjacent to the L5 ground layer 25 to form a power-ground plane pair. In the corresponding metal column / vertical interconnect 12 landing area, a return path control 33 is made, and a ground via fence 31 is formed by laser drilling and electroplating filling around the landing point, or by etching process to form GND layer 34 or ground metal ring. Blind / buried vias or microvias 28 are fabricated on the adapter substrate 14 to achieve interlayer interconnection, and the drilling depth is controlled to eliminate through-hole residual piles; The adapter board 14 is divided into high-speed digital area, analog / RF area and power area according to function and is routed in the partition. The PWR / GND reference layer 35 of each partition is kept continuous, and the equipotential connection between different partitions is achieved by single-point connection or controlled impedance bridging. Decoupling capacitors 42 are placed near the metal pillar / vertical interconnect 12 or near the chip power supply input, so that the decoupling capacitors 42 and the power-ground plane work together to form a low-impedance power distribution network.

[0036] It is understood that this embodiment provides a specific method for manufacturing a three-dimensional stacked packaging substrate device, which is applicable to high-frequency and high-speed three-dimensional stacked packaging applications, and specifically includes the following steps: Step 1: Fabrication and lamination of multilayer stacked substrates Glass fiber reinforced epoxy resin with low dielectric constant (approximately 3.5) and low loss factor was selected as the substrate to prepare L1 signal layer 21 core board, L2 ground layer 22 copper foil, L3 power layer 23 core board, and L5 ground layer 25 copper foil, respectively. The thickness of L1 signal layer 21 core board was controlled at 0.1 mm, and its surface was covered with 18 μm thick low profile copper foil; the thickness of L3 power layer 23 core board was 0.2 mm, and it was copper-clad on both sides. The layers were stacked in the following order from top to bottom: L1 signal layer 21, L2 ground layer 22, prepreg (0.09 mm thick), L3 power layer 23, prepreg (0.09 mm thick), and L5 ground layer 25. A vacuum hot press was used for lamination, controlling the pressing temperature within the range of 180 to 200 degrees Celsius, maintaining the pressure at 30 to 40 kg / cm², and holding the heat and pressure for 90 minutes to ensure thorough bonding between the layers. After lamination, a six-layer stacked substrate is formed, in which the L1 signal layer 21 and the L2 ground layer 22 are closely adjacent to form a ground microstrip structure, and the L3 power layer 23 and the L5 ground layer 25 are separated only by a prepreg to form a power-ground plane pair. The vertical spacing between the two is controlled within 0.09 mm to obtain low distributed inductance characteristics.

[0037] Step 2: Creating the Reflux Channel After determining the landing points of the metal pillars / vertical interconnects 12 (copper pillars with a diameter of 0.25 mm in this embodiment) on the surface of the adapter substrate 14, a ring-shaped hole is drilled around the landing points using an ultraviolet laser drilling device. Eight through-holes with a radius of 0.35 mm are drilled evenly around the center of the landing point, with a hole diameter of 0.1 mm and a depth penetrating from the L1 signal layer 21 to the L5 ground layer 25. Subsequently, the hole walls are metallized using chemical copper plating and electroplating processes, with the electroplated copper layer thickness controlled at 20 to 25 micrometers, forming a ground via enclosure 31. For power area landing points requiring enhanced shielding, an additional etching process is used to create a ring-shaped GND layer 34 on the L3 power layer 23 or L5 ground layer 25 below the landing point. The GND layer 34 has a width of 0.15 mm and is electrically connected to the adjacent reference layer through multiple ground vias 27 with a diameter of 0.15 mm, collectively forming a layered shielded return path control 33.

[0038] Step 3: Fabrication of Interlayer Interconnection for Low-Residual Pile To address the requirements of high-speed differential pair interlayer interconnection, a combined CO2 laser and UV laser drilling process is used to fabricate blind / buried vias or microvias 28. First, a CO2 laser is used to remove surface resin, followed by precise drilling with a UV laser terminating at the target layer. The drilling depth is strictly controlled so that the bottom of the blind / buried via or microvia 28 terminates precisely at the copper foil on the L4 signal layer 24, preventing residual spikes extending into the L6 signal layer / pad layer 26. After drilling, the vias undergo desmearing, chemical copper plating, and pulsed electroplating for filling. The filler copper is flush with the surface copper layer to ensure impedance continuity of high-frequency signals during interlayer transitions. For areas with multiple layers, buried vias are used for inner-layer interconnection. The buried vias are positioned away from directly beneath high-speed signal lines to minimize impact on signal transmission.

[0039] Step 4: Functional Zone Cabling Process The top surface of the adapter substrate 14 is divided into three functional regions: a high-speed digital region located at the center of the adapter substrate 14 (corresponding to the central array interconnect region 52), an analog RF region located at the left edge (corresponding to the left lead bonding region 53) or the right edge (corresponding to the right lead bonding region 54) of the adapter substrate 14, and a power region located at the upper edge (corresponding to the upper lead bonding region 51) or the lower edge (corresponding to the lower lead bonding region 55) of the adapter substrate 14. Within the high-speed digital region, the PWR / GND reference layer 35 remains intact and continuous. High-speed differential pair traces are arranged on the L4 signal layer 24 with a line width of 0.1 mm and a line spacing of 0.15 mm, with 0.2 mm wide grounding guards on both sides. Sensitive RF lines are arranged within the analog RF region, and its PWR / GND reference layer 35 is independent of the high-speed digital region. A single-point connection is used at the boundary between the two zones: a 0.3 mm diameter ground via 27 is placed in the boundary area as the sole electrical connection point, and a 10-ohm surface-mount resistor is connected in series between this ground via 27 and the PWR / GND reference layer 35 of the high-speed digital zone to form a controlled impedance bridge, blocking the direct coupling path of high-frequency noise. A power distribution network is arranged within the power supply zone, and the power layers 41 of each zone are connected by narrow bridges, 0.3 mm wide and 1 mm long, to limit noise propagation.

[0040] Step 5: Integration and Layout of Decoupling Devices Within a 0.5 mm radius around the metal pillar / vertical interconnect 12 landing point, multiple 0201-sized ceramic capacitors are arranged using surface mount technology as decoupling capacitors 42. The capacitance values ​​are selected in combinations of 0.1 μF and 1 μF, respectively for decoupling high-frequency and low-frequency noise. Directly below the chip power supply input, an embedded capacitor technology is used, sandwiching a 0.02 mm thick high-dielectric-constant ceramic film (dielectric constant approximately 50) between the L3 power layer 23 and the L5 ground layer 25. An interdigital capacitor structure is formed through photolithography etching, with a capacitance value of approximately 10 nanofarads, creating a high-low pairing with the surface mount capacitors. The decoupling capacitors 42 are connected to the power layer 41 and ground layer 46 via conductive adhesive or soldering, forming a low-impedance power distribution network. Testing shows that at a frequency of 1 GHz, the impedance of the power distribution network can be controlled below 0.5 ohms, effectively meeting the transient power supply requirements of the upper-layer chip.

[0041] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0043] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A three-dimensional stacked packaging substrate device, comprising: The upper package and the lower package, wherein the lower package includes a substrate, at least one lower chip, and vertical interconnect terminals for realizing interconnection between the upper and lower layers; characterized in that the substrate is a multilayer stacked substrate, including at least a first signal layer, a first ground reference layer, a first power layer, and a second ground reference layer. The first signal layer and the first ground reference layer are arranged adjacent to each other, and the first power layer and the second ground reference layer are arranged adjacent to each other to form a power-ground plane pair. The landing area corresponding to the vertical interconnect terminal is provided with a return channel, which includes an array of ground vias or a ground metal ring surrounding the landing area, for providing a continuous reference loop for high-speed signals transmitted through the vertical interconnect terminal.

2. The three-dimensional stacked packaging substrate device according to claim 1, characterized in that, The substrate adopts a six-layer stack structure, which includes, in sequence along the thickness direction: a first signal layer, a first ground reference layer, a first power layer, a second signal layer, a second ground reference layer, and a third signal layer; The first signal layer and the first ground reference layer are adjacent to form a microstrip structure with ground, and the second signal layer is sandwiched between the first power layer and the second ground reference layer to form a stripline structure.

3. The three-dimensional stacked packaging substrate device according to claim 1, characterized in that, The first signal layer contains high-speed differential pairs. The high-speed differential pairs are wired with equal length and spacing, and grounding wires or ground via stitching are provided on both sides of them.

4. The three-dimensional stacked packaging substrate device according to claim 3, characterized in that, The high-speed differential pair achieves interlayer interconnection through micropores or blind holes during interlayer switching, and no unconnected through-hole residual piles are formed in the layer switching transition area.

5. The three-dimensional stacked packaging substrate device according to claim 1, characterized in that, The grounding via array is evenly distributed circumferentially along the landing point area, and the signal landing point of the vertical interconnect terminal is located at the center. The grounding via array and the vertical interconnect terminal together form a quasi-coaxial or coaxial vertical interconnect structure to form a high-speed transmission channel with low parasitic inductance and resistance to electromagnetic interference.

6. The three-dimensional stacked packaging substrate device according to claim 5, characterized in that, The return channel also includes a grounding metal ring disposed below the landing area. The grounding metal ring is electrically connected to the first grounding reference layer and / or the second grounding reference layer through multiple grounding vias to form a three-dimensional shielding structure.

7. The three-dimensional stacked packaging substrate device according to claim 1, characterized in that, The substrate is functionally divided into a high-speed digital area, an analog / RF area, and a power supply area, with the ground plane within each area remaining continuous; different areas are connected at the same potential through single-point connection or controlled impedance bridging.

8. The three-dimensional stacked packaging substrate device according to claim 7, characterized in that, Each zone adopts a zoned power supply and zoned grounding design. The power supply and ground planes are independently arranged and tightly coupled in each zone. The power networks between different zones are connected by controlled impedance bridging or single-point grounding.

9. The three-dimensional stacked packaging substrate device according to claim 7, characterized in that, The substrate has decoupling devices arranged near the vertical interconnect landing point or the chip power supply input. The decoupling devices include surface-mount capacitors and / or embedded capacitor layers. The decoupling devices work together with the power-ground plane to reduce the impedance of the power distribution network.

10. A method for manufacturing a three-dimensional stacked packaging substrate apparatus as claimed in any one of claims 1-9, characterized in that, Includes the following steps: A core board is provided and multi-layer stacked and laminated to form a substrate comprising at least a first signal layer, a first ground reference layer, a first power layer and a second ground reference layer, wherein the first signal layer is controlled to be adjacent to the first ground reference layer and the first power layer is controlled to be adjacent to the second ground reference layer to form a power-ground plane pair; A return current channel is created in the corresponding vertical interconnect terminal landing area. A grounding via array is formed by laser drilling and electroplating filling around the landing point, or by etching process to form a grounding metal ring. Blind vias or microvias are fabricated on the substrate to achieve interlayer interconnection, and the drilling depth is controlled to eliminate via piles. The substrate is divided into high-speed digital area, analog / RF area and power area according to function and the wiring is partitioned. The ground plane of each partition is kept continuous, and the equipotential connection between different partitions is achieved by single-point connection or controlled impedance bridging. Decoupling devices are placed near the vertical interconnect landing point or the chip power input, so that the decoupling devices and the power-ground plane pair work together to form a low-impedance power distribution network.

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