Brake unit failure detection method, brake unit system, brake unit failure detection device, and electronic device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGXI ABC ELECTRIC CO LTD
- Filing Date
- 2026-03-05
- Publication Date
- 2026-05-29
Smart Images
Figure CN122109913A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of brake fault detection technology for frequency converters, and in particular to a brake unit fault detection method, brake unit system, brake unit fault detection device, and electronic equipment. Background Technology
[0002] In the field of variable frequency speed control technology, the braking unit, as a crucial component of the frequency converter, directly affects the safe operation of the entire transmission system. When the motor is decelerating or undergoing potential energy load release, the braking unit controls the switching of the braking resistor to dissipate regenerative energy as heat, thereby preventing overvoltage faults caused by excessive DC bus voltage. However, in practical applications, the braking unit and its core component, the braking resistor, operate under harsh conditions of high voltage and high current for extended periods, making them highly susceptible to faults such as short circuits, open circuits, or performance degradation. Failure to detect these faults promptly and accurately can not only weaken the system's braking capability but also potentially lead to serious safety accidents.
[0003] Existing methods for detecting brake unit faults largely rely on simple threshold judgments. For example, they determine overcurrent or short circuit by detecting the current flowing through the braking resistor or the voltage drop across the IGBT. However, these methods often require additional current sensors or complex isolation detection circuits in the main circuit, increasing system cost and design complexity. Furthermore, their detection accuracy is easily affected by environmental factors such as temperature and stray parameters. In addition, some software logic-based detection schemes typically only perform static self-tests when the system is powered on, failing to monitor the dynamic performance of the brake unit in real time during normal inverter operation. This results in delayed fault detection, hindering timely warnings and handling in the early stages of a fault.
[0004] Therefore, how to achieve online and accurate detection of short-circuit faults in braking units, especially braking resistors, without excessively relying on additional hardware costs has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] This application provides a method for detecting brake unit faults, a brake unit, a brake unit fault detection device, and an electronic device to solve the problems mentioned in the background art.
[0006] In a first aspect, this application provides a method for detecting brake unit faults, comprising the following steps: The power-on time is preset to t1, the rated DC bus voltage V0 of the inverter is obtained, the first reference voltage V1 and the second reference voltage V2 are preset, and the DC bus voltage Vdc is continuously sampled. During the power-on phase of the inverter, the power-on start signal is acquired, and timing begins according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, timing stops, and the time t0 is recorded. Compare the time t0 with the set time t1; if t0 < t1, the braking unit is determined to be operating normally; if t0 > t1, the braking unit is determined to be short-circuited. During normal operation of the frequency converter, changes in the motor state controlled externally cause the DC bus voltage to rise. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If a braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops, and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the frequency converter, timing stops, and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3. Determine whether |Kb-Kr|<ε holds true, where ε is the tolerance error; if true, the braking unit is determined to be short-circuited; if false, the braking unit is determined to be operating normally.
[0007] In one implementation, after determining whether |Kb-Kr|<ε holds true, where ε is the tolerance error; and if true, determining the short-circuit fault of the braking unit, the method further includes: A slope threshold K1 is preset, where K1 is 5-10 times the average recovery slope under normal conditions; If Kb>K1 and Kr>K1, then the braking unit is determined to be short-circuited; otherwise, the braking unit is determined to be operating normally.
[0008] In one implementation, during the normal operation of the frequency converter, changes in the externally controlled motor state cause the DC bus voltage to rise. Timing begins when the DC bus voltage Vdc first reaches the first reference voltage V1. If a braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. Timing stops when the DC bus voltage Vdc drops to the second reference voltage V2, and time t2 is recorded to obtain the braking slope Kb = (V1 - V2) / t2. If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is not completely consumed by the braking resistor, the DC bus voltage Vdc, which has decreased to the second reference voltage V2, will continue to rise to the first reference voltage V1. At this time, after the braking resistor is connected to the DC bus circuit, the braking slope Kb can still be collected and calculated, and this process repeats. If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is completely consumed by the braking resistor, the DC bus voltage Vdc will not rise to the first reference voltage V1 again, and the system will enter the next detection step.
[0009] Secondly, this application also proposes a braking unit system employing the braking unit fault detection method described above, wherein the braking unit includes... The voltage sampling circuit is connected to the DC bus of the frequency converter and is used to acquire a sampling signal that reflects the DC bus voltage Vdc. A reference voltage generating circuit is connected to the DC bus via a pre-stepping circuit to generate a first reference voltage V1 and a second reference voltage V2. A comparison control circuit, connected to the voltage sampling circuit and the reference voltage generating circuit respectively, is used to output a status signal to the controller based on the comparison result of the sampled signal with the first and second reference voltages, so that the controller executes the method steps of any one of claims 1 to 3.
[0010] In one specific implementation, the voltage sampling circuit includes resistors R1 and R2 connected in series with the positive and negative terminals of the DC bus, and the two ends of resistor R2 are used to output the sampling voltage. The reference voltage generating circuit includes resistors R4, R5, and R6 connected in series at the output of the pre-step-down circuit, and an adjustable voltage regulator DZ2 connected in parallel across resistors R5 and R6. The adjustable voltage regulator DZ2 has a reference terminal connected between resistors R5 and R6 to obtain the second reference voltage V2. The comparison control circuit includes a comparator, a pull-up resistor, and a resistor R7. The positive input terminal of the comparator is used to receive the sampled voltage. The negative input terminal of the comparator is used to receive the stable DC voltage generated by the reference voltage generation circuit. One end of the pull-up resistor is connected to the level signal output terminal of the comparator, and the other end is connected to the output terminal of the pre-buck circuit for powering the reference voltage generation circuit and the comparison control circuit. The two ends of the resistor R7 are respectively connected to the level signal output terminal and the positive input terminal of the comparator. The resistor R7 is used for positive feedback hysteresis of the comparator to generate the first reference voltage V1.
[0011] In one specific implementation, the pre-step-down circuit includes resistors R3 and Zener diode DZ1 connected in series with the positive and negative terminals of the DC bus, and the Zener diode DZ1 is connected in parallel with the reference voltage generating circuit; the other end of the pull-up resistor is connected to the cathode of the Zener diode DZ1.
[0012] In one specific implementation, the pre-step-down circuit further includes a capacitor C2, which is connected in parallel with the Zener diode DZ1.
[0013] In one specific implementation, the resistor voltage divider circuit further includes a capacitor C1, which is connected in parallel with the resistor R2.
[0014] In one specific implementation, the braking unit further includes a braking module, which includes a push-pull amplifier circuit, an IGBT, and a freewheeling diode; The gate of the IGBT is connected to the output terminal of the push-pull amplifier circuit, the emitter of the IGBT is connected to the negative terminal of the DC bus voltage, the collector of the IGBT is connected to the anode of the freewheeling diode, the cathode of the freewheeling diode is connected to the positive terminal of the DC bus voltage, and the braking resistor is connected in parallel between the positive terminal of the DC bus voltage and the collector of the IGBT.
[0015] Thirdly, this application also proposes a brake unit fault detection device for implementing the method described above, including... The parameter setting and acquisition module presets the power-on time t1, acquires the rated DC bus voltage V0 of the inverter, presets the first reference voltage V1 and the second reference voltage V2, and continuously samples the DC bus voltage Vdc. The first processing module acquires the power-on start signal during the power-on phase of the inverter and starts timing according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, the timing stops and the time t0 is recorded. The first judgment module compares the time t0 with the set time t1; if t0 < t1, it determines that the braking unit is operating normally; if t0 > t1, it determines that the braking unit has a short circuit fault. The second processing module, during the normal operation of the inverter, causes the DC bus voltage to rise due to changes in the externally controlled motor state. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If the braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the inverter, timing stops and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3. The second judgment module determines whether |Kb-Kr|<ε is true, where ε is the allowable error; if true, the braking resistor is short-circuited, and the braking unit is determined to be short-circuited.
[0016] Fourthly, this application also proposes an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the braking unit fault detection method as described above.
[0017] This application provides a method for detecting brake unit faults, a brake unit, a brake unit fault detection device, and an electronic device, wherein: Firstly, this method enables online monitoring and fault early warning throughout the entire lifecycle of the braking unit. Specifically, by acquiring the inherent DC bus voltage signal of the frequency converter, and comparing the charging time t0 with the preset power-on time t1 during the frequency converter's power-on phase, it can quickly identify whether a braking resistor is abnormally connected to the DC bus circuit, thus diagnosing short-circuit faults in the braking unit at the very beginning of equipment startup. Simultaneously, this method continuously monitors DC bus voltage fluctuations during the normal operation of the frequency converter, achieving real-time tracking of the braking unit's dynamic performance and significantly improving system operational safety.
[0018] Furthermore, by introducing slope comparison logic during the normal operation of the frequency converter, the accuracy of fault identification is significantly improved, effectively avoiding misjudgments. Specifically, this method uses the braking slope Kb and recovery slope Kr, and determines whether the braking resistor is short-circuited based on whether the absolute value of their difference is less than the allowable error ε. When the braking resistor is short-circuited, it is equivalent to a fixed load connected to the bus, causing the voltage rise and fall mechanisms to be dominated by the charging and discharging characteristics of the bus capacitor. Therefore, Kb and Kr tend to be close in value.
[0019] Furthermore, this method requires no additional hardware sensors, making it cost-effective and easy to implement for engineering applications. The method relies entirely on continuous sampling of the DC bus voltage Vdc, a parameter typically readily available in frequency converters. Moreover, the braking unit circuit defined in this application has a simple and low-cost structure, generating trigger signals solely through hardware logic, without relying on complex software algorithms. This means that this method can be directly upgraded or modified based on existing braking hardware, significantly improving the product's intelligent fault diagnosis level without significantly increasing material costs. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic flowchart illustrating the braking unit fault detection method provided in this application embodiment; Figure 2 The circuit control schematic diagram of the braking unit system provided in the embodiments of this application; Figure 3 A schematic circuit diagram of the braking unit provided in the embodiments of this application; Figure 4 A schematic block diagram of the structure of the braking unit fault detection device provided in the embodiments of this application; Figure 5 This is a schematic block diagram of the structure of an electronic device provided in an embodiment of this application.
[0022] Label Explanation: 21. Voltage sampling circuit; 22. Pre-step-down circuit; 23. Reference voltage generation circuit; 24. Comparison control circuit; 25. Braking module; 251. Push-pull amplifier circuit; 252. IGBT; 253. Freewheeling diode; 100. Braking unit fault detection device; 110. Parameter setting and acquisition module; 120. First processing module; 130. First judgment module; 140. Second processing module; 150. Second judgment module. Detailed Implementation
[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0025] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0026] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0027] This application provides a method for detecting brake unit faults, a brake unit system, a brake unit fault detection device 100, and an electronic device.
[0028] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features described herein can be combined with each other.
[0029] Please see Figure 1 , Figure 1 This is a flowchart illustrating the braking unit fault detection method provided in an embodiment of this application, as shown below. Figure 1 As shown, the braking unit fault detection method provided in this application includes the following steps: S10, preset power-on time t1, obtain the rated DC bus voltage V0 of the inverter, preset the first reference voltage V1 and the second reference voltage V2, and continuously sample the DC bus voltage Vdc.
[0030] The preset power-on time t1 refers to the maximum reasonable time required for a fully normal frequency converter to reach its rated value V0 for the first time after receiving the power-on start signal. The determination of the t1 value is usually related to the charging resistor and bus capacitor in the frequency converter's soft-start circuit.
[0031] Specifically, the time it takes for the capacitor voltage to charge from 0V to V0 can be estimated using the capacitor charging formula: V0 = Vin × (1 - e^(-t1 / τ)) Formula 1; Where Vin is the peak voltage of the input voltage; τ is the time constant, τ = the product of the charging resistance and the bus capacitance; When V0 = Vin, theoretically it would take an infinite amount of time to fully charge. However, in engineering practice, a peak voltage of 95% to 98% is usually taken as the mark of "fully charged"; in this scheme, 90% or 95% of Vin is taken as the value of V0. According to Formula 1, the value of t1 is approximately (3~4)τ, and in engineering practice, it cannot be lower than 3τ.
[0032] Based on this, the specific value of t1 can be further verified through experiments. For example, 20 frequency converters are selected and powered on under standard test conditions, and the power-on time t0 of each frequency converter is recorded. Statistical analysis is performed on the collected N t0 data points to calculate the average value μ and standard deviation σ of t0; the general criterion for t1 is set as t1=μ+k×σ; where k is usually a constant of 2, 3, 4, or 5. The value of k can be selected according to the sensitivity requirements and false alarm rate requirements. When k is 2, the detection sensitivity is high, but the risk of false alarm increases slightly; when k is 4, the detection sensitivity is low, but the false alarm rate is also very low; usually, when k is 3, the false alarm rate is also low and can cover most normal products.
[0033] Furthermore, the rated DC bus voltage V0 of the inverter is defined as the peak voltage of the inverter's input power supply voltage, and in the fault detection and judgment logic, V0 is usually taken as 90%Vin or 95%Vin.
[0034] Furthermore, it should be noted that the specific methods for the first reference voltage V1, the second reference voltage V2, and the continuous sampling of the DC bus voltage Vdc are described in detail below, and will not be repeated here.
[0035] S20: During the power-on phase of the inverter, acquire the power-on start signal and start timing according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, stop timing and record the time t0.
[0036] S30, compare the time t0 with the set time t1; if t0 < t1, the braking unit is determined to be operating normally; if t0 > t1, the braking unit is determined to be short-circuited.
[0037] Understandably, if the collected t0 > t1, it indicates that the power-on speed to the rated DC bus voltage V0 is slow, thus suggesting that a braking resistor is connected to the DC bus circuit, and a short-circuit fault has occurred in the braking unit. However, the above judgment method still has a certain false alarm rate. In the specific implementation of this scheme, regardless of whether the judgment result is normal or faulty, the next detection step can be directly initiated.
[0038] S40, during the normal operation of the inverter, changes in the motor state controlled externally cause the DC bus voltage to rise. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If the braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the inverter, timing stops and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3.
[0039] It should be noted that under normal braking conditions, a single switching of the braking resistor usually cannot completely consume the excess energy, requiring multiple switching of the braking resistor. Therefore, time t2 can be acquired either during the first switching or at any time after the braking resistor is connected.
[0040] S50, determine whether |Kb-Kr|<ε is true, where ε is the allowable error; if true, determine that the braking unit is short-circuited; if false, determine that the braking unit is operating normally.
[0041] Understandably, if the values of Kb and Kr are close, it indicates that the resistance values in the drive circuit are similar, further indicating that the braking resistor is always connected in the drive circuit, thus indicating a short circuit fault in the braking unit. It should also be noted that ε, the allowable error value, can be set as needed according to the required detection sensitivity.
[0042] It should also be noted that under normal braking conditions, the braking slope Kb caused by the repeated switching of the braking resistor is much greater than the normal recovery slope Kr. Therefore, by checking whether |Kb-Kr|<ε holds true, if it does not, it indicates that the braking unit is operating normally.
[0043] In one implementation, the braking unit fault detection method, after the step of determining whether |Kb-Kr|<ε holds true, where ε is the tolerance error; and if true, determining a short-circuit fault in the braking unit, further includes: S60, a slope threshold K1 is preset, where K1 is 5-10 times the average recovery slope under normal conditions; It should be noted that K1 cannot be directly calculated. K1 needs to be calibrated by experimentally analyzing the recovery slope of the voltage under normal conditions after V1 and V2 are determined. Therefore, this will be explained in detail below.
[0044] S70, if Kb>K1 and Kr>K1, then the braking unit is determined to be short-circuited; otherwise, the braking unit is determined to be operating normally.
[0045] It should be noted that the calibration value of K1 is usually taken as 5-10 times the average value of the normal recovery slope. Therefore, if the braking slope Kb>K1 and Kr>K1, it means that the time for the DC bus voltage Vdc to recover to V0 is longer, the resistance value in the drive circuit does not change, and the braking unit fails due to short circuit.
[0046] Furthermore, in practical applications, due to the discharge characteristics of the capacitors in the drive circuit, during a braking short circuit, the closer the DC bus voltage Vdc is to the rated voltage V0, the lower the recovery slope Kr is typically compared to the braking slope Kb during a braking short circuit. Moreover, the recovery slope Kr during a braking short circuit will be significantly higher than the recovery slope under normal conditions due to the presence of the braking resistor.
[0047] Therefore, when |Kb-Kr|<ε holds, a slope threshold K1 is set, and if Kb>K1 and Kr>K1, a short-circuit fault in the braking unit is determined again. This dual judgment mechanism can clearly distinguish between the two distinct physical processes of "normal braking" and "resistance short circuit," overcoming the shortcomings of a single mechanism that is prone to misjudgment and improving the accuracy of short-circuit fault alarms.
[0048] Furthermore, in actual operating conditions, during the normal operation of the frequency converter, changes in the externally controlled motor state cause the DC bus voltage to rise. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If a braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops, and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. The step also includes: If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is not completely consumed by the braking resistor, the DC bus voltage Vdc, which has decreased to the second reference voltage V2, will continue to rise to the first reference voltage V1. At this time, after the braking resistor is connected to the DC bus circuit, the braking slope Kb can still be collected and calculated, and this process repeats. If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is completely consumed by the braking resistor, the DC bus voltage Vdc will not rise to the first reference voltage V1 again, and the system will enter the next detection step.
[0049] It should be noted that the next detection step of the system is as follows: when the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, the timing of the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the frequency converter, the timing stops and the time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3.
[0050] It is understood that the above embodiment further defines the processing logic under actual operating conditions where braking energy is not fully consumed and bus voltage is repeatedly triggered. This scheme considers continuous braking scenarios that may occur in actual operation, and clarifies that even if the energy is not fully released in the first braking cycle and the voltage rises back to the first reference voltage V1, the braking slope Kb can still be normally collected and calculated. Only after the energy is completely consumed will the next detection cycle begin. Furthermore, the specific value of the braking slope Kb can also be obtained by calculating the average value of the braking slopes obtained from multiple repeated braking cycles.
[0051] Please see Figure 2 and Figure 3 In a second aspect, the present invention also proposes a braking unit system employing the braking unit fault detection method described above, comprising: Voltage sampling circuit 21 is connected to the DC bus of the frequency converter and is used to acquire a sampling signal reflecting the DC bus voltage Vdc. The reference voltage generating circuit 23 is connected to the DC bus via the pre-stepping circuit 22, and is used to generate the first reference voltage V1 and the second reference voltage V2. The comparison control circuit 24 is connected to the voltage sampling circuit 21 and the reference voltage generating circuit 23 respectively, and is used to output a status signal to the controller according to the comparison result of the sampling signal with the first and second reference voltages, so that the controller executes the steps of the braking unit fault detection method.
[0052] Please continue reading. Figure 2 and Figure 3In a specific embodiment, the voltage sampling circuit 21 includes resistors R1 and R2 connected in series with the positive and negative terminals of the DC bus, and the two ends of the resistor R2 are used to output the sampling voltage. The reference voltage generating circuit 23 includes resistors R4, R5, and R6 connected in series at the output of the pre-step-down circuit, and an adjustable voltage regulator DZ2 connected in parallel across resistors R5 and R6. The adjustable voltage regulator DZ2 has a reference terminal connected between resistors R5 and R6 to obtain the second reference voltage V2. The comparison control circuit 24 includes a comparator, a pull-up resistor, and a resistor R7. The positive input terminal of the comparator is used to receive the sampled voltage. The negative input terminal of the comparator is used to receive the stable DC voltage generated by the reference voltage generation circuit 23. One end of the pull-up resistor is connected to the level signal output terminal of the comparator, and the other end is connected to the output terminal of the pre-buck circuit 22 for powering the reference voltage generation circuit 23 and the comparison control circuit 24. The two ends of the resistor R7 are respectively connected to the level signal output terminal and the positive input terminal of the comparator. The resistor R7 is used for positive feedback hysteresis of the comparator to generate the first reference voltage V1.
[0053] In a specific embodiment, the pre-step-down circuit 22 includes resistors R3 and Zener diode DZ1 connected in series with the positive and negative terminals of the DC bus, and the Zener diode DZ1 is connected in parallel with the reference voltage generating circuit 23; the other end of the pull-up resistor is connected to the cathode of the Zener diode DZ1.
[0054] It should be noted that in the voltage sampling circuit 21, resistors R1 and R2 are connected in series to divide the voltage, so the sampling voltage Vf = Vdc * R2 / (R1 + R2); thus, the real-time sampling value of the DC bus voltage Vdc is obtained.
[0055] It should be noted that in practical applications, the first reference voltage V1 and the second reference voltage V2 can be arbitrarily selected based on the overvoltage point voltage of the frequency converter and the rated voltage of the DC bus, with a certain safety margin reserved; after selecting the values of V1 and V2, the specifications of each component in the braking unit circuit are determined.
[0056] It should also be noted that if the parameters of each component of the braking unit are determined in this embodiment, the first reference voltage V1 and the second reference voltage V2 can also be calculated.
[0057] Specifically, the DZ2 is a three-terminal adjustable voltage regulator (such as the TL431) whose reference voltage is stabilized at Vr≈2.5V.
[0058] Specifically, let the voltage division ratio of the sampling voltage Vf be k = R2 / (R1+R2); The stable voltage output by the comparator reference voltage generation circuit 23 is V-=V(R5)+V(R6)= (2.5V / R6)×R5+2.5V=2.5V(1+R5 / R6).
[0059] Furthermore, since the power supply voltage VCC output by the pre-stepping circuit 22 is the regulated voltage value of the Zener diode DZ1; Furthermore, when Vdc is short-circuited, the equivalent resistance (i.e., the parallel value of R1 and R2) when viewed from the positive input terminal of the comparator is when R1 and R2 are connected in parallel is calculated. Therefore: First reference voltage V1 (rising threshold) = V- / k; Second reference voltage V2 (fall threshold) = [(V-)-VCC*(R1 / / R2) / (R7+R1 / / R2)] / k; Wherein, VCC is the power supply voltage output by the pre-step-down circuit 22, which is determined by the Zener diode DZ1, i.e., VCC=VDZ1.
[0060] And R1 / / R2=(R1*R2) / (R1+R2).
[0061] Furthermore, if R7 >> R1 / / R2, then (R1 / / R2) / (R7 + R1 / / R2) = (R1 / / R2) / R7; That is, the second reference voltage V2 can be approximated as V2≈V1-(VDZ1*(R1 / / R2)) / (k*R7); Where k = R2 / (R1+R2); then V2≈V1–VDZ1(R1 / R7).
[0062] It can be clearly concluded that the hysteresis width of the comparator is mainly determined by the resistance values of R1 and R7.
[0063] Furthermore, given the first reference voltage V1 and the second reference voltage V2, by mounting a typical load motor test platform, the value of the recovery slope Kr after normal braking of the drive unit is collected, where Kr=(V2-V0) / t3, the average value of N Kr values is recorded, and K1=(5~10)Kr (average value) is set to obtain the value of K1.
[0064] Please continue reading. Figure 2The pre-step-down circuit 22 further includes a capacitor C2, which is connected in parallel with the Zener diode DZ1; the voltage sampling circuit 21 further includes a capacitor C1, which is connected in parallel with the resistor R2. The capacitor C2 is mainly used to smooth the power supply voltage, improving the stability and comparison accuracy of the stable voltage output by the comparator reference voltage generation circuit 23. The capacitor C1 is mainly used to filter out high-frequency noise in the sampled voltage Vf, improving the accuracy and anti-interference capability of the voltage sampling Vf.
[0065] In a specific embodiment of the technical solution of the present invention, the braking unit further includes a braking module 25, which includes a push-pull amplifier circuit 251, an IGBT 252, and a freewheeling diode 253. The gate of the IGBT252 is connected to the output terminal of the push-pull amplifier circuit 251, the emitter of the IGBT252 is connected to the negative terminal of the DC bus voltage, the collector of the IGBT252 is connected to the anode of the freewheeling diode 253, the cathode of the freewheeling diode 253 is connected to the positive terminal of the DC bus voltage, and the braking resistor is connected in parallel between the positive terminal of the DC bus voltage and the collector of the IGBT252.
[0066] Understandably, the configuration of the IGBT252 allows for precise control of the connection and disconnection of the braking resistor, ensuring timely and stable braking protection when the DC bus voltage is overvoltaged. Furthermore, the parallel freewheeling diode 253 provides a freewheeling path for the reverse induced electromotive force generated by the braking resistor, preventing reverse voltage spikes from damaging the IGBT252. This achieves overvoltage protection for the power switching device, ensuring the braking circuit can safely and reliably perform its overvoltage discharge braking function.
[0067] Please see Figure 4 , Figure 4 This is a schematic block diagram of the structure of the braking unit fault detection device 100 provided in the embodiments of this application, such as... Figure 4 As shown, in a third aspect, this application also proposes a brake unit fault detection device 100 for implementing the method described above, including... The parameter setting and acquisition module 110 presets the power-on time t1, acquires the rated DC bus voltage V0 of the inverter, presets the first reference voltage V1 and the second reference voltage V2, and continuously samples the DC bus voltage Vdc. The first processing module 120 acquires the power-on start signal during the power-on phase of the inverter and starts timing according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, the timing stops and the time t0 is recorded. The first judgment module 130 compares the time t0 with the set time t1; if t0 < t1, it determines that the braking unit is operating normally; if t0 > t1, it determines that the braking unit has a short circuit fault. The second processing module 140, during the normal operation of the inverter, the change in the motor state controlled by the external system causes the DC bus voltage to rise. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If the braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the inverter, timing stops and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3. The second judgment module 150 judges whether |Kb-Kr|<ε is true, where ε is the allowable error; if true, the braking resistor is short-circuited, and the braking unit is determined to be short-circuited.
[0068] The brake unit fault detection device 100 in this embodiment is used to execute the brake unit fault detection method described above. Therefore, the brake unit fault detection device 100 has all the beneficial effects of the brake unit fault detection method. Furthermore, the specific working process of the device and each module described above can be referred to the corresponding process in the aforementioned brake unit fault detection method embodiment, and therefore will not be repeated here. Please see Figure 5 Fourthly, this application also proposes an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the braking unit fault detection method as described above.
[0069] It is understood that the braking unit fault detection device 100 provided in the above embodiments can be implemented as a computer program, which can, for example, Figure 5 It runs on the electronic device shown.
[0070] Please see Figure 5 , Figure 3 The present invention provides a schematic block diagram of the structure of an electronic device 200. The electronic device 200 includes a processor 201 and a memory 202, which are connected via a system bus 203. The memory 202 may include a non-volatile storage medium and internal memory.
[0071] The non-volatile storage medium can store a computer program. The computer program includes program instructions that, when executed by the processor 201, cause the processor 201 to perform any of the aforementioned braking unit fault detection methods.
[0072] The processor 201 provides computing and control capabilities to support the operation of the entire electronic device 200.
[0073] The internal memory provides an environment for the execution of computer programs in non-volatile storage media. When the computer program is executed by the processor 201, the processor 201 can execute any of the above-mentioned braking unit fault detection methods.
[0074] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device 200 involved in the present application. The specific electronic device 200 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0075] It should be understood that the processor 201 can be a central processing unit or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for detecting faults in a braking unit, characterized in that, Including the following steps: The power-on time is preset to t1, the rated DC bus voltage V0 of the inverter is obtained, the first reference voltage V1 and the second reference voltage V2 are preset, and the DC bus voltage Vdc is continuously sampled. During the power-on phase of the inverter, the power-on start signal is acquired, and timing begins according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, timing stops, and the time t0 is recorded. Compare the time t0 with the set time t1; if t0 < t1, the braking unit is determined to be operating normally; if t0 > t1, the braking unit is determined to be short-circuited. During normal operation of the frequency converter, changes in the motor state controlled externally cause the DC bus voltage to rise. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If a braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops, and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the frequency converter, timing stops, and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3. Determine whether |Kb-Kr|<ε holds true, where ε is the tolerance error; if true, the braking unit is determined to be short-circuited; if false, the braking unit is determined to be operating normally.
2. The braking unit fault detection method as described in claim 1, characterized in that, After determining whether |Kb-Kr|<ε holds true, where ε is the tolerance error; and if true, determining a short-circuit fault in the braking unit, the method further includes: A slope threshold K1 is preset, where K1 is 5-10 times the average recovery slope under normal conditions; If Kb>K1 and Kr>K1, then the braking unit is determined to be short-circuited; otherwise, the braking unit is determined to be operating normally.
3. The braking unit fault detection method as described in claim 1, characterized in that, During the normal operation of the frequency converter, changes in the externally controlled motor state cause the DC bus voltage to rise. Timing begins when the DC bus voltage Vdc first reaches the first reference voltage V1. If a braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. Timing stops when the DC bus voltage Vdc drops to the second reference voltage V2, and time t2 is recorded to obtain the braking slope Kb = (V1 - V2) / t2. The process also includes: If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is not completely consumed by the braking resistor, the DC bus voltage Vdc, which has decreased to the second reference voltage V2, will continue to rise to the first reference voltage V1. At this time, after the braking resistor is connected to the DC bus circuit, the braking slope Kb can still be collected and calculated, and this process repeats. If the energy from the change in the motor state caused by external control to rise in the DC bus voltage is completely consumed by the braking resistor, the DC bus voltage Vdc will not rise to the first reference voltage V1 again, and the system will enter the next detection step.
4. A braking unit system employing the braking unit fault detection method as described in claims 1 to 3, characterized in that, include The voltage sampling circuit is connected to the DC bus of the frequency converter and is used to acquire a sampling signal that reflects the DC bus voltage Vdc. A reference voltage generating circuit is connected to the DC bus via a pre-stepping circuit to generate a first reference voltage V1 and a second reference voltage V2. A comparison control circuit, connected to the voltage sampling circuit and the reference voltage generating circuit respectively, is used to output a status signal to the controller based on the comparison result of the sampled signal with the first and second reference voltages, so that the controller executes the method steps of any one of claims 1 to 3.
5. The braking unit system as described in claim 4, characterized in that, The voltage sampling circuit includes resistors R1 and R2 connected in series with the positive and negative terminals of the DC bus, and the two ends of resistor R2 are used to output the sampling voltage. The reference voltage generating circuit includes resistors R4, R5, and R6 connected in series at the output of the pre-step-down circuit, and an adjustable voltage regulator DZ2 connected in parallel across resistors R5 and R6. The adjustable voltage regulator DZ2 has a reference terminal connected between resistors R5 and R6 to obtain the second reference voltage V2. The comparison control circuit includes a comparator, a pull-up resistor, and a resistor R7. The positive input terminal of the comparator is used to receive the sampled voltage. The negative input terminal of the comparator is used to receive the stable DC voltage generated by the reference voltage generation circuit. One end of the pull-up resistor is connected to the level signal output terminal of the comparator, and the other end is connected to the output terminal of the pre-buck circuit for powering the reference voltage generation circuit and the comparison control circuit. The two ends of the resistor R7 are respectively connected to the level signal output terminal and the positive input terminal of the comparator. The resistor R7 is used for positive feedback hysteresis of the comparator to generate the first reference voltage V1.
6. The braking unit system as described in claim 5, characterized in that, The pre-step-down circuit includes resistors R3 and Zener diode DZ1 connected in series with the positive and negative terminals of the DC bus, and Zener diode DZ1 is connected in parallel with the reference voltage generating circuit; the other end of the pull-up resistor is connected to the cathode of Zener diode DZ1.
7. The braking unit system as claimed in claim 5, characterized in that, The pre-step-down circuit also includes a capacitor C2, which is connected in parallel with the Zener diode DZ1. The voltage sampling circuit also includes a capacitor C1, which is connected in parallel with the resistor R2.
8. The braking unit system as claimed in claim 4, characterized in that, The braking unit also includes a braking module, which includes a push-pull amplifier circuit, an IGBT, and a freewheeling diode. The gate of the IGBT is connected to the output terminal of the push-pull amplifier circuit, the emitter of the IGBT is connected to the negative terminal of the DC bus voltage, the collector of the IGBT is connected to the anode of the freewheeling diode, the cathode of the freewheeling diode is connected to the positive terminal of the DC bus voltage, and the braking resistor is connected in parallel between the positive terminal of the DC bus voltage and the collector of the IGBT.
9. A brake unit fault detection device, characterized in that, For implementing the method as described in any one of claims 1-3, comprising: The parameter setting and acquisition module presets the power-on time t1, acquires the rated DC bus voltage V0 of the inverter, presets the first reference voltage V1 and the second reference voltage V2, and continuously samples the DC bus voltage Vdc. The first processing module acquires the power-on start signal during the power-on phase of the inverter and starts timing according to the power-on start signal. When the DC bus voltage Vdc reaches the rated DC bus voltage V0 for the first time, the timing stops and the time t0 is recorded. The first judgment module compares the time t0 with the set time t1; if t0 < t1, it determines that the braking unit is operating normally; if t0 > t1, it determines that the braking unit has a short circuit fault. The second processing module, during the normal operation of the inverter, causes the DC bus voltage to rise due to changes in the externally controlled motor state. When the DC bus voltage Vdc first reaches the first reference voltage V1, timing begins. If the braking resistor is connected to the DC bus circuit at this time, the DC bus voltage Vdc will drop rapidly. When the DC bus voltage Vdc drops to the second reference voltage V2, timing stops and time t2 is recorded to obtain the braking slope Kb=(V1-V2) / t2. When the real-time collected DC bus voltage Vdc is less than the second reference voltage V2, timing for the next cycle begins. When the DC bus voltage Vdc drops to the rated DC bus voltage V0 of the inverter, timing stops and time t3 is recorded to obtain the recovery slope Kr=(V2-V0) / t3. The second judgment module determines whether |Kb-Kr|<ε is true, where ε is the allowable error; if true, the braking resistor is short-circuited, and the braking unit is determined to be short-circuited.
10. An electronic device, characterized in that, The electronic device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the braking unit fault detection method as described in any one of claims 1 to 3.