A high-dimensional computing compilation architecture, instruction set architecture, and computing system based on a topological intermediate representation

Abstract

The application provides a high-dimensional calculation compiling architecture, an instruction set architecture and a calculation system based on a topological intermediate representation, and by introducing a structured relation representation of G=(V, E, W, P), a relation-driven unified instruction format, a state register heap and a relation processing unit, a cross-architecture mapping mechanism and a relation runtime scheduling mechanism, a traditional arithmetic-centered compiling and execution flow is converted into a relation-centered compiling and execution flow, so that the compiling adaptation capability and the execution efficiency of high-dimensional calculation on a heterogeneous hardware platform are improved.

Description

Technical Field

[0001] This invention relates to the fields of computer architecture, compilation technology, heterogeneous computing, in-memory computing, and high-dimensional data processing, and particularly to a high-dimensional computing compilation architecture, relation-driven instruction set architecture, and unified execution system based on structured relation representation.

[0002] More specifically, the present invention relates to a method and system for converting source programs, intermediate representations, tensor graphs, graph structure programs or other high-dimensional computational tasks into topological intermediate representations containing state nodes, relation edges, relation weights and path strategy parameters, and further generating relation-driven execution instructions for execution on an execution texture composed of a central processing unit, a graphics processing unit, a tensor processing unit, a multi-valued logic computation unit, an in-memory computing array or a combination thereof. Background Technology

[0003] With the development of artificial intelligence, large-scale model training and inference, graph neural networks, scientific computing, and complex data analysis, modern computing tasks are increasingly manifesting as state evolution problems on high-dimensional structures. Traditional computer software stacks typically transform programs into an execution form centered on arithmetic logic, organizing the computation process around addition, multiplication, loading, storage, and conditional branching. This approach is well-suited for low-dimensional scalar programs, but in high-dimensional tensor, graph structures, and complex dependency scenarios, it often requires decomposing the original relational structure into numerous arithmetic operations and intermediate state transports, leading to high memory access overhead, numerous redundant branches, and a mismatch between the compilation model and the hardware execution model.

[0004] While existing technologies include program dependency graphs, data flow graphs, graph intermediate representations, computation graph compilers, and heterogeneous runtimes, these solutions generally organize the computation process around "computation nodes." Nodes represent arithmetic operations or operator calls, and edges represent data flows or scheduling dependencies. For state relationships, contribution distributions, evolutionary trends, and path pruning strategies in high-dimensional computation, existing solutions typically require dispersed expression across multiple compilation stages or runtime layers, lacking a unified relational abstraction layer that can directly drive underlying heterogeneous hardware.

[0005] Furthermore, with the development of tensor processors, in-memory computing arrays, and other non-traditional computing hardware, the underlying execution structure is no longer simply adapted to the instruction flow of traditional arithmetic centers. If an intermediate representation and instruction system centered on arithmetic operations is still used, it will be difficult to fully leverage capabilities such as near-memory computation, relational fusion, path suppression, and in-situ relational processing. Therefore, a new computing architecture is needed that enables information such as multidimensional data states, structural correlation strength, statistical sensitivity, gradient or state evolution trends, and path strategy parameters in a program to be uniformly expressed during compilation, loading, and runtime, and further generates relation-driven instruction sequences that can be mapped to different execution units. Differences from existing graph intermediate representations and compilation frameworks

[0006] Traditional data flow graphs (DFG), program dependency graphs (PDG), and intermediate representations such as LLVM / MLIR / XLA typically use arithmetic operations, control nodes, or tensor operators as graph nodes, with edges primarily representing data flow direction, dependencies, or scheduling order. Edge attributes in these representations generally do not directly participate in machine-level execution control, nor do they uniformly handle contribution evaluation during the compilation phase, path pruning during runtime, or hardware backend gating control.

[0007] In contrast, the Structured Relationship Intermediate Representation (SR-IR) employed in this invention uses data states as nodes and state relationships as edges, forming a closed-loop control through a set of relationship weights W and a set of path strategy parameters P. Here, W not only characterizes the strength of state relationships but also drives contribution evaluation, prefetching priority, execution ordering, or relationship suppression; P not only characterizes strategy configuration but also drives branch pruning thresholds, audit thresholds, backend mapping modes, and hardware gating control. Therefore, the SR-IR of this invention is not a simple attribute extension of existing graph representations but a unified control representation that directly connects compilation optimization, instruction field generation, runtime state machines, and heterogeneous execution textures. Summary of the Invention

[0008] The purpose of this invention is to provide a high-dimensional computing compilation architecture, instruction set architecture, and computing system based on topological intermediate representation, in order to solve the problems in the prior art where high-dimensional computing tasks rely on arithmetic centers for execution, relation representations are scattered, heterogeneous hardware is underutilized, and execution paths are difficult to tailor based on relation contribution.

[0009] To achieve the above objectives, this invention proposes a computing platform centered on structured relation representation. This platform extracts the multidimensional data states and their dynamic evolution relationships from the source program into a unified topological intermediate representation. Then, based on a set of relation weights and a set of path strategy parameters, it evaluates, filters, trims, and maps execution paths, generating relation-driven instruction sequences for execution by different computing units in a heterogeneous execution texture.

[0010] In one aspect of the present invention, a method for program conversion and execution for high-dimensional computation is provided, comprising: receiving a source program or intermediate representation; extracting statistical sensitivity, gradient information, state evolution trend, and structural correlation strength between tensor blocks, graph nodes, state units, or intermediate state objects in the source program to characterize the dynamic evolution relationship between states; generating a structured relation intermediate representation based on the multidimensional data states and their dynamic evolution relationship; evaluating the contribution of state relationships based on the relation weight set and path strategy parameter set of the intermediate representation, and performing relation filtering, branch pruning, state binding, or relation fusion at least in at least one of the compilation, loading, and runtime stages; generating a relation-driven execution instruction sequence based on the optimized structured relation intermediate representation; and scheduling the execution instruction sequence to at least one execution unit for execution.

[0011] In some embodiments of the present invention, the structured relation intermediate representation is a topology intermediate representation Topology-IR, defined as: G = (V, E, W, P) Where V is the set of data state nodes, E is the set of state relationship edges, W is the set of relationship weights, and P is the set of path strategy parameters. W not only characterizes at least one of the strength, contribution, sensitivity, priority, or suppression degree of the relationship between states, but also drives subsequent hardware execution, including launch gating, cache priority, array activation threshold, heterogeneous link routing weights, or audit conditions. P controls path filtering, branch pruning, backend mapping strategies, audit thresholds, or runtime relationship scheduling strategies.

[0012] In some embodiments of the present invention, the state evolution satisfies the following relationship: S t+1 = F(S t , R t , P) Among them, S t Let R be the set of states at time t. t Let E be the set of relation operators jointly determined by E and W, P be the set of path strategy parameters, and F be the state evolution function used to determine state transition, relation fusion, contribution filtering, and branch retention strategies during the compilation, loading, or runtime phases.

[0013] In another aspect of the invention, a relation-driven instruction set architecture is provided, in which the instructions do not rely solely on traditional arithmetic logic operations as the core, but instead use state mapping, relation extraction, relation composition, relation pruning, path selection, and audit control as basic execution primitives. This instruction set can operate the state register file, relation processing unit, and result aggregation module through a unified instruction format, and can be mapped to different execution units, including a central processing unit, a graphics processing unit, a tensor processing unit, a multi-valued logic computation unit, and an in-memory computing array.

[0014] Through the above technical solution, the present invention can transform the traditional compilation process centered on arithmetic operations into a compilation process centered on state relationships and path strategies, thereby reducing intermediate state expansion, reducing invalid branch launches, reducing intermediate memory accesses and transfers, and improving program conversion methods, instruction generation methods, and resource scheduling methods for underlying heterogeneous hardware. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall architecture of the platform of the present invention;

[0016] Figure 2 This is a schematic diagram of the compilation process of the present invention;

[0017] Figure 3 This is a schematic diagram representing the intermediate structure of the relationship;

[0018] Figure 4 A hierarchy diagram of the relation-driven instruction set architecture and a schematic diagram of the instruction word bit field;

[0019] Figure 5 To illustrate the texture;

[0020] Figure 6 This is a schematic diagram of an in-memory computing execution architecture;

[0021] Figure 7 This is a diagram illustrating the compilation and execution process in a Transformer scenario. Detailed Implementation Example 1: Generation of SR-IR / Topology-IR

[0022] After receiving the source program or intermediate representation, the compilation frontend first performs syntax analysis, type inference, and dependency resolution. Unlike traditional graph construction methods centered on arithmetic operations, this invention prioritizes identifying independently schedulable data state objects, including tensor blocks, graph node features, vector fragments, sparse blocks, intermediate buffer states, and other high-dimensional state units, and registers them as a set of state nodes V.

[0023] Subsequently, the front-end establishes a set of relational edges E for any two or more state nodes based on control flow, data flow, statistical sensitivity, gradient information, structural correlation strength, and state evolution trends. These relational edges can represent dependencies, competition, combination, hedging, constraints, priorities, or evolutionary relationships. For each relational edge, a set of relational weights W is further calculated, including but not limited to contribution, sensitivity, inhibition degree, importance, activation priority, or near-term execution benefit. The path strategy parameter set P is used to describe subsequent branch retention rules, mapping strategies, audit conditions, and execution texture scheduling preferences.

[0024] In one exemplary implementation, G=(V,E,W,P) can be generated using the following pseudocode: Input: source program or IR Output: G = (V, E, W, P) 1. parse(source) 2. states = identify_state_objects(source) 3. V = register(states) 4. For each pair / group in V: 5. rel = infer_relation(pair / group) 6. If rel exists: 7. E.add(rel) 8. W.add(evaluate_weight(rel, sensitivity, trend, locality,contribution)) 9. P.add(build_policy(rel, pruning_rule, audit_rule, backend_rule))10. return G Unlike traditional data flow graphs, the nodes in this invention are not simply additions, multiplications, or operator calls, but rather data states that can be bound, merged, projected, or audited; the edges not only represent the flow direction, but also carry the weights and strategy parameters required for subsequent compilation optimization and hardware gating. Example 2: Construction and Optimization of Topology-AST

[0025] After generating the SR-IR / Topology-IR, the compiler constructs the Topology-AST. Tree nodes correspond to composite state groups, relation clusters, or jointly schedulable state subgraphs, and parent-child relationships represent state combinations, path expansions, and relation evolution levels. When traversing the Topology-AST, the following optimizations can be performed: state binding, relation fusion, low-contribution edge pruning, path priority rearrangement, and audit node insertion. This optimization process is not a general source code optimization, but rather a hardware-aware optimization that performs textured topology constraints on the target. For example, when the target backend is an in-memory compute array, the optimizer prioritizes aggregating high-weight, near-memory executable state clusters into the same array reachable domain to reduce cross-array movement. Example 3: CISA Instruction Set Architecture

[0026] This invention defines a relation-driven instruction set architecture (CISA). This instruction set includes four types of instructions: a state layer, a relation layer, an evolution layer, and a control layer. The state layer includes STATE_LOAD, STATE_STORE, STATE_MAP, and STATE_BIND; the relation layer includes REL_EXTRACT, REL_WEIGHT, DEV_EXTRACT, and TREND_EXTRACT; the evolution layer includes STATE_COMBINE, STATE_PROJECT, POLAR_HEDGE, RESIDUAL_PRUNE, and STATE_MERGE; and the control layer includes AUDIT_CHECK, AUDIT_TRAP, and EXEC_ROUTE.

[0027] The instructions use the format [Opcode | SrcStateA | SrcStateB | DstState | Param]. The Opcode indicates the relationship operation type; SrcStateA, SrcStateB, and DstState reference state entries in the state register file; the Param field can be further divided into a Weight Field and a Policy Field. The Weight Field can carry relationship weight indexes, activation thresholds, contribution thresholds, or array weight configurations, while the Policy Field can carry path policies, audit policies, backend mapping flags, cache priorities, or heterogeneous routing parameters.

[0028] In a specific example, the REL_EXTRACT instruction reads two source states and their parameter fields, extracts the corresponding relation descriptions, and writes the results to the target state register or relation buffer; the STATE_BIND instruction binds multiple state entries into a composite state group for unified scheduling; the RESIDUAL_PRUNE instruction removes low-contribution paths based on the contribution threshold in the Param; and the AUDIT_TRAP instruction terminates, masks, or reroutes the current branch when an audit condition is triggered. Example 4: Status Register File and Relationship Processing Unit

[0029] The execution unit comprises a state register file, a relation processing unit, a topology controller, and a result aggregation module. The state register file stores not only ordinary arithmetic register values, but also state descriptors, state indices, relation parameter indices, intermediate state results, and optional cache priority tags. The relation processing unit performs operations such as relation extraction, relation fusion, relation pruning, state projection, and auditing. The topology controller parses the CISA instruction stream and controls the issue gating, execution order, and backend mapping strategy of the relation processing unit based on the WeightField and Policy Field. Example 5: Cross-Architecture Mapping

[0030] To achieve unified execution texture, this invention defines a mapping mechanism for relational parameters to different backends, as shown in the table below: Relationship parameters / strategy CPU mapping action GPU mapping actions CIM mapping actions High contribution relationship Increase cache priority or thread priority Prioritize mapping to shared memory or tensor kernel path Increase the array activation threshold weight or prioritize loading into the nearest memory region. Complementary / Hedge Relationship Achieved through masking suppression, gate skipping, or digital cancellation. Implemented through warp-level reduction, shared memory fusion, or microcode suppression. This is achieved through differential accumulation, analog current superposition cancellation, or gated suppression. Highly Sensitive Relationships in Auditing Insert security check micro-operation or anomaly shielding sequence Enable asynchronous state checking kernel or control kernel functions Enable hardware-level auditing paths, output masking, or link rerouting. The above mapping illustrates that W and P are not simply software parameters, but can directly influence caching behavior, launch strategies, array activation thresholds, and heterogeneous link routing behavior. Example 6: Execution of POLAR_HEDGE

[0031] POLAR_HEDGE is used to handle state components with complementary, opposite, or canceling contribution relationships. For digital back-ends, this can be achieved through masking, symbolic cancellation, or gated suppression; for GPUs, it can be achieved through reduction and local fusion in shared memory; for in-memory compute arrays, it can be achieved through analog superposition on differential bit lines, local cancellation, or output gated suppression. When the superposition result of the relationship weights of two complementary states at a physical node is lower than a preset threshold, subsequent sampling, activation, or output propagation can be suppressed, thereby reducing the continued execution of invalid branches. To avoid unnecessarily limiting itself to a single analog mechanism, the "hedge" in this invention includes analog cancellation, digital cancellation, gated suppression, and their equivalent implementations. Example 7: AUDIT_CHECK and AUDIT_TRAP

[0032] Audit control is used to verify the consistency between the state evolution path and the preset policy. The topology controller or independent audit unit can compare the expected evolution path, actual state changes, execution timing offsets, energy consumption estimates, or backend feedback according to the audit rules defined in the Policy Field. When an abnormal relationship that does not meet preset constraints is detected, AUDIT_TRAP is triggered, executing termination of the current branch, state reset to zero, output masking, link rerouting, or anomaly reporting. This mechanism can be used for both robust control and path protection under execution environmental constraints. Example 8: Transformer Scenario

[0033] For the following attention calculation: Q = X @ Wq K = X @ Wk V = X @ Wv Attention = softmax(Q @ KT) @ V Traditional compilers typically generate matrix multiplication, normalization, and memory access sequences directly. This invention, however, first identifies Q, K, V, and intermediate attention states as state nodes, models relevance, competition, inhibition relationships, and path importance as relational edges and weight parameters, and then selects whether to prune low-contribution attention paths during compilation or runtime based on the policy parameter P. The resulting CISA instructions include STATE_MAP, REL_EXTRACT, STATE_BIND, POLAR_HEDGE, STATE_COMBINE, and EXEC_ROUTE, enabling execution on GPUs or CIMs that more closely resembles relational structures. Example 9: The Chain of Complexity and Technical Effect

[0034] For dimension N kFor high-dimensional tensor or graph state sets, traditional arithmetic-centric solutions typically require first expanding the relation structure into numerous intermediate states, and then completing the computation through multiple rounds of Load / Store and MAC instructions. In contrast, this invention reduces execution complexity from a model dependent on the expansion of all states to a model dependent on retaining a subset of relations by forming state bindings, relation weight sets, and path strategy parameter sets during the compilation phase, and performing relation filtering, branch pruning, and relation fusion during the loading or runtime phases. In practical implementation, this means reducing the number of intermediate state transfers, reducing the number of low-contribution branch instruction issuances, reducing cache conflict probability, and improving the effective utilization of near-memory execution. Although the benefits vary across different hardware platforms, the effectiveness of this technology stems from a unified relation abstraction and a unified relation-driven execution chain, rather than a single software-level renaming or conventional optimization. Example 10: Binary Serialization Format of SR-IR

[0035] In some implementations, the structured relationship is represented using a storable, transmissible, and loadable binary serialization format. The serialization format may consist of a file header, node table, edge table, weight table, and policy table, with an example structure as follows: Section Example fields Function Header Version, NodeCount, EdgeCount, WeightOffset, PolicyOffset, Flag Identify the SR-IR version, number of entries, and offset address of each segment, and reserve the extension bits. Node Table NodeID, StateType, Dimension, DescriptorPtr Record the state node identifier, state type, dimension information, and state descriptor index. Edge Table EdgeID, SrcID, DstID, RelationType, WeightIndex, PolicyIndex Record state relationship edges and their weights, and policy parameter indexes. Weight Table WeightValue, UpdateMode, Reserved Record relation weights and their update patterns Policy Table PruneThreshold, AuditThreshold, BackendMode, MaskValue Record clipping, auditing, and backend mapping strategies In the above format, the node table and edge table together define the topology skeleton of the SR-IR, while the weight table and policy table are used to pass parameters directly related to relation control to the backend. By adopting this serialization structure, the SR-IR generated during the compilation phase can be directly written to the file system, cache system, or runtime load buffer, and shared by the topology runtime module and instruction generation module. Example 11: RISA / CISA Instruction Decoding Flow and Topology Controller Control Flow

[0036] In some implementations, the Topology Controller is used to parse relation-driven instructions and generate control words for different backends. Its decoding process may include: Read the current relation-driven instruction word from the instruction buffer; Parse the Opcode field to determine which category the instruction belongs to: state mapping, relation extraction, state combination, path selection, or audit control. Parse the SrcStateA, SrcStateB, and DstState fields to access the corresponding state entries in the State Register Bank; Parse the weight subfield, strategy subfield, and mapping subfield in the Param field to obtain the current relationship strength, audit threshold, and backend selection information; The control word is generated by combining the Opcode and Param, and the control word can be sent to the CPU micro-operation queue, GPU kernel configuration unit, or in-memory computing array control unit; After execution, the result status is written back to the target status register, and the policy cache is updated or the audit control logic is triggered based on the execution feedback.

[0037] In an exemplary implementation, the decoded pseudocode for the Topology Controller can be represented as follows:

[0038] Through the above process, relation-driven instructions are no longer software-level operator encapsulations, but machine-level control interfaces with decodable, routable, and feedback-updating features. Example 12: Param subfield partitioning and W / P to hardware action mapping

[0039] In some implementations, the Param field can be divided into multiple subfields to achieve a direct mapping from the relation weight set W and the path policy parameter set P to hardware control actions. For example: Param = [Weight Segment | Policy Segment | Mapping Segment] subfield Example content Corresponding hardware actions Weight Segment Relationship weight value or weight index Control prefetch priority, execution order, relational suppression strength, or array activation strength. Policy Segment Crop threshold, audit threshold, dynamic mask Control branch pruning, audit triggering, power gating, or anomaly blocking. Mapping Segment Backend mode, array mode, caching mode Control commands are routed to the CPU, GPU, TPU, NPU, or CIM backend. For CPU backends, Weight Segments can be mapped to vectorized priorities or prefetch levels; for GPU backends, Policy Segments can be mapped to warp-level masking, shared memory usage patterns, or kernel pruning thresholds; for in-memory compute backends, Weight Segments and Policy Segments can be mapped to word line / bit line activation strengths, gating suppression parameters, sampling suppression parameters, or output aggregation weights, respectively. Thus, W and P are not only used for logic evaluation but also directly influence hardware control flow. Example 13: Runtime Topology State Machine

[0040] In some implementations, the system includes a Topology Runtime StateMachine, located between the compilation module and the execution texture, to maintain a state loop between the loading and runtime phases. The state machine can maintain a set of currently active states, a set of currently active relation edges, a policy cache, audit flags, and backend mapping patterns. The state machine performs the following actions based on runtime feedback: Update the set of executable paths based on the latest state set and relation weights; Perform immediate pruning or deweighting on low-contribution branches based on strategy parameters; Adjust the backend routing mode and gating status based on the execution texture feedback; When a policy violation, abnormal relationship propagation, or path conflict is detected, AUDIT_CHECK or AUDIT_TRAP is triggered.

[0041] Therefore, this invention is not a simple static compilation scheme, but a closed-loop control system that includes three stages: compilation, loading, and runtime. Example 14: Complexity, Performance, and Extreme Scenarios

[0042] To illustrate the technical effects of this invention, a theoretical comparison is provided below. Let the size of the high-dimensional tensor or graph state set be N. Traditional arithmetic-centric compilation methods typically require performing approximately O(N²) level expansion, memory access, and arithmetic emission on all candidate relations in scenarios involving attention computation, graph neighborhood expansion, or sparse propagation. This invention, however, uses the relation weight set W and path strategy parameter set P in the SR-IR to prune relation edges during compilation, loading, or runtime, retaining only a subset of significant relations. When the number of retained relations is kN (k is much smaller than N), relation computation and subsequent execution can be reduced from a mode dependent on the full relation expansion to a mode dependent on the retained relation subset, thereby reducing the relation processing complexity from approximately O(N²) to O(kN).

[0043] In a Transformer attention scenario, traditional methods perform dense scoring and full intermediate state expansion for all Query-Key pairs. This invention establishes state nodes and relation edges in the SR-IR stage first, and then retains only high-contribution relations based on weights and policy parameters, thereby reducing the number of intermediate state entries, instruction issuance, and shared cache pressure. In ultra-sparse tensor scenarios, when the sparsity exceeds a preset threshold, the Topology Runtime State Machine can directly close low-contribution relation channels based on the pruning threshold in the Policy Table, generating relation-driven instructions only for retained relation edges. In dynamic graph scenarios, the BackendMode and MaskValue in the policy table can be updated with state changes, enabling the system to reroute execution paths during state evolution.

[0044] The above complexity and effect analysis demonstrates that W and P in SR-IR are not merely subordinate attributes of the graph representation, but essential parameters for relation pruning, hardware routing, and audit control. Removing W would prevent relation contribution ranking and priority control; removing P would prevent maintaining consistent path selection and audit loops across compile, load, and runtime; and if Param does not contain subfields corresponding to W and P, relation control cannot be directly mapped to backend execution actions.

Claims

1. A method for program conversion and execution for high-dimensional computation, characterized in that, The process includes the following steps: (1) receiving the source program or intermediate representation; (2) extracting the statistical sensitivity, gradient information, state evolution trend, and structural correlation strength between tensor blocks, graph nodes, state units, or intermediate state objects in the source program to characterize the dynamic evolution relationship between states; (3) generating a structured intermediate representation of the relationship based on the multidimensional data states and their dynamic evolution relationship, wherein the structured intermediate representation of the relationship includes at least a set of state nodes, a set of relationship edges, a set of relationship weights, and a set of path strategy parameters; (4) evaluating the contribution of the relationship between different state nodes based on the structured intermediate representation of the relationship, and (5) Perform relation filtering, branch pruning, state binding or relation fusion at least in at least one of the compilation stage, loading stage and runtime stage; (6) Generate a relation-driven execution instruction sequence based on the optimized structured relation intermediate representation, wherein the execution instruction sequence includes at least one of state mapping instruction, relation extraction instruction, state combination instruction, path selection instruction and audit control instruction; (7) Schedule the execution instruction sequence to at least one execution unit for execution, wherein the execution unit includes at least one of central processing unit, graphics processing unit, tensor processing unit, multi-valued logic computing unit or in-memory computing array.

2. The method according to claim 1, characterized in that, The structured relation intermediate representation is a topology intermediate representation, defined as G=(V,E,W,P), where V is the set of data state nodes, E is the set of state relation edges, W is the set of relation weights, and P is the set of path strategy parameters.

3. The method according to claim 2, characterized in that, The set of relation weights W is used to characterize at least one of the contribution, strength, sensitivity, priority or inhibition degree of the relationship between states, and is used to drive the launch gating, cache priority, array activation threshold or heterogeneous link routing weight of at least one execution unit.

4. The method according to claim 2 or 3, characterized in that, The path strategy parameter set P is used to control at least one of branch pruning, path filtering, audit threshold, backend mapping strategy, or runtime relationship scheduling.

5. The method according to claim 1, characterized in that, The relation-driven execution instruction sequence adopts the following instruction format: [Opcode | SrcStateA | SrcStateB | DstState | Param], where the Param field includes at least one of the weight field and the policy field.

6. The method according to claim 5, characterized in that, The execution unit includes a state register file and a relation processing unit. The state register file is used to store state node descriptors, relation parameter indexes and intermediate state results. The relation processing unit is used to perform at least one of relation extraction, relation combination, relation pruning or audit control.

7. The method according to claim 5 or 6, characterized in that, When the execution unit is an in-memory computing array, the Param field is mapped to array control parameters, including at least one of word line activation control, bit line activation control, gating suppression parameters, output aggregation parameters, or audit control parameters.

8. A computing system, characterized in that, It includes a compilation module, a structured relation representation generation module, a relation instruction generation module, a topology runtime module, and an execution texture; wherein the compilation module, the structured relation representation generation module, the relation instruction generation module, the topology runtime module, and the execution texture are configured to perform the method described in any one of claims 1 to 7.

9. A computing device, characterized in that, It includes a processor, a memory, a status register file, and a relation processing unit; wherein the processor is configured to execute a program stored in the memory to implement the method of any one of claims 1 to 7.

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