A program dynamic updating method and a digital signal processing system

Abstract

The application discloses a program dynamic updating method and a digital signal processing system. The program dynamic updating method comprises the following steps: executing a pause instruction belonging to an instruction set in a program running on a DSP core; in an execution stage of the instruction, the DSP core enters an idle state specified by an immediate number in the instruction, and stops accessing all memories, at this time, an external host controls to modify the code in an instruction memory; after the idle state ends, the DSP core resumes running according to a previously saved pipeline state. Through the integration of a special pause instruction and a matching hardware cooperative control mechanism, the application fundamentally solves the bus access conflict, the pipeline timing destruction and the multi-cycle instruction adaptation problem during the program dynamic updating, and realizes the safe, real-time and reliable online updating.

Description

Technical Field

[0001] This invention relates to a method for dynamic program updating, and also to a digital signal processing system for implementing the method, belonging to the field of digital signal processing technology. Background Technology

[0002] Digital signal processors (DSPs) play a central role in numerous fields such as communications, industrial control, and medical equipment due to their efficient instruction execution, dedicated computing modules, and flexible programming capabilities. In these applications, especially those requiring real-time adaptive adjustment of algorithms or complex control logic, it is often necessary to dynamically modify and update the DSP program during system operation to ensure that it continuously maintains optimal performance and adaptability.

[0003] However, existing technologies face a series of thorny challenges in implementing dynamic updates to DSP programs. The primary problem lies in hardware access conflicts: the DSP core continuously accesses external memory to obtain instructions and data during runtime. If an external controller (such as the CPU) simultaneously attempts to modify the program code in memory, access conflicts are highly likely, leading to program execution errors or data corruption. Traditional conflict avoidance solutions, such as inserting a large number of redundant instructions or using dual memory area switching, have significant drawbacks, including low efficiency, wasted storage resources, increased hardware costs, and excessively long interrupt times. A deeper challenge lies in the coordination with the DSP core architecture: modern DSPs generally employ pipelined designs to improve efficiency. Forcibly inserting update operations can easily disrupt the normal pipeline timing, leading to errors in subsequent instruction execution or even system resets. Especially for multi-cycle instructions with uncertain execution cycles, existing technologies struggle to accurately determine their state and safely trigger updates at the appropriate time. Furthermore, existing instruction sets lack native support, and conventional instructions cannot bring the DSP core into a stable and controllable idle state. Pausing via software interrupts is not only slow and increases program complexity but also cannot guarantee that the DSP completely stops accessing memory, making it difficult to provide a stable window for code modification.

[0004] While technical solutions such as CN117687664A exist to enable online DSP upgrades, they primarily address the convenience of the upgrade process and do not tackle the core hardware coordination challenges mentioned above, such as instruction-level access conflicts, pipeline timing coordination, and multi-cycle instruction adaptation. Therefore, providing a mechanism that can securely and efficiently coordinate with the DSP pipeline and multi-cycle instruction execution to fundamentally resolve access conflicts and timing disruptions during dynamic program updates, while ensuring the real-time performance and reliability of updates, has become a pressing technical problem. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a method for dynamic program updates.

[0006] Another technical problem to be solved by the present invention is to provide a digital signal processing system for implementing the above-described method.

[0007] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution: According to a first aspect of the present invention, a method for dynamic program updating is provided, applied to a digital signal processing system including a DSP module, an instruction memory, and a data memory. The DSP module includes a DSP core, and the execution structure of the DSP core is a three-stage pipeline, including an instruction fetch stage, a decoding stage, and an execution stage; the method includes the following steps: S1: In the program running on the DSP core, execute a pause instruction belonging to its instruction set; S2: During the execution phase of the pause instruction, the DSP core enters an idle state for the number of clock cycles specified by the immediate value in the pause instruction; during the idle state, the DSP core stops all access to the instruction memory and the data memory, and the external master controller modifies the instruction code in the instruction memory; S3: After the idle state ends, the DSP core resumes operation according to the pre-saved pipeline state.

[0008] Preferably, the format of the pause instruction is "instruction opcode + immediate value", wherein the instruction opcode is an 8-bit binary number used to uniquely identify the pause instruction, and the immediate value is an 8-bit unsigned integer used to specify the number of clock cycles in the idle state.

[0009] Preferably, executing the pause command includes: During the instruction fetch phase, the pause instruction is read from the instruction memory; During the decoding phase, the opcode and immediate value of the pause instruction are parsed; During the execution phase, the idle state is triggered based on the immediate value.

[0010] Preferably, before the pause instruction is executed, the program dynamic update method further includes: The DSP core monitors the operation status of the pipeline and multi-cycle instructions, and selects the timing to trigger the pause instruction based on the monitoring results.

[0011] Among the more favorable options, the timing of the triggering process includes: If it is detected that a multi-cycle instruction is being executed during the execution phase, the pause instruction will be triggered to enter the pipeline for execution only after the multi-cycle instruction has been completed.

[0012] Preferably, before entering the idle state, the program dynamic update method further includes: The DSP core records the current state of the pipeline and saves it to a non-volatile temporary register; the pipeline state includes the value of the PC address register, the instruction data that has been fetched but not decoded, the contents of the decode status register, and the state of each arithmetic unit in the execution module.

[0013] Preferably, restoring the operation of the DSP core includes: Based on the recorded pipeline status, the instruction fetch module, decode module, and execution module are controlled to resume operation synchronously.

[0014] According to a second aspect of the present invention, a digital signal processing system is provided, comprising: a DSP module, an instruction memory, a data memory, and an external main controller; The instruction memory and the data memory are used to store the instructions and data required by the DSP module, respectively. The DSP module includes a DSP core, a program counter control module, general-purpose registers, a PC register, and an algorithm module; the DSP core is connected to the program counter control module; the PC register is used to store the address of the next instruction to be read. The instruction set of the DSP core includes a pause instruction. The DSP core is configured to execute the pause instruction and enter an idle state specified by the immediate value in the instruction during the execution phase of the instruction, while ceasing all access to the instruction memory and the data memory. The external master controller is configured to modify the instruction code in the instruction memory while the DSP core is in the idle state.

[0015] Preferably, the DSP module further includes an idle state management unit; the idle state management unit includes a counter, the initial value of which is set by the immediate value in the pause instruction, and is used to control the duration of the idle state.

[0016] Preferably, the DSP module further includes a status register; the status register has an idle status flag bit to indicate whether the DSP core is in an idle state.

[0017] Compared with existing technologies, this invention achieves a fundamental breakthrough in dynamic program updates by integrating a dedicated pause instruction with an immediate value and constructing a complete hardware collaborative control mechanism. This instruction enables the DSP core to atomically enter an idle state of precise duration, completely releasing bus resources and fundamentally eliminating access conflicts with external controllers. Simultaneously, its deep collaboration with the pipeline ensures complete pipeline timing and lossless state before and after entering and exiting the idle state, avoiding timing chaos or system resets caused by update operations. This mechanism can also intelligently monitor and adapt to the execution status of multi-cycle instructions, ensuring that updates are triggered only at safe times, guaranteeing the continuity and correctness of computation. Ultimately, this invention provides a safe, real-time, reliable, and universally applicable dynamic program update solution for DSPs without system downtime, without increasing redundant code or hardware costs, significantly improving system adaptability, performance, and reliability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a digital signal processing system in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the DSP module structure in the first embodiment of the present invention; Figure 3 This is a flowchart of a program dynamic update method in the second embodiment of the present invention; Figure 4 This is a timing diagram of the execution process of different instructions in the second embodiment of the present invention; Figure 5 This is a timing diagram of the execution process of the pause instruction in the second embodiment of the present invention. Detailed Implementation

[0019] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0020] First Embodiment like Figure 1 As shown, the digital signal processing system provided in the first embodiment of the present invention includes: a DSP module, an instruction memory, a data memory, and an external main controller. The instruction memory and the data memory are used to store the instructions and data required by the DSP module, respectively; the DSP module receives a reset signal.

[0021] like Figure 2 As shown, in one embodiment of the present invention, the DSP module includes a DSP core, and a program counter (PC) control module, general-purpose registers, a PC register, and an algorithm module that work in conjunction with it. The DSP core is the functional unit within the DSP module responsible for instruction fetching, decoding, and execution.

[0022] The DSP core is connected to the algorithm module and the program counter control module. When the system reset signal is removed, the DSP core begins the instruction fetch, decode, and execute processes, controlling the corresponding algorithm module to operate according to different instructions. The program counter control module manages the value of the program counter (PC) to ensure that instructions are read and executed in the correct order. The PC register stores the address of the next instruction to be fetched, ensuring accurate instruction retrieval during the fetch phase. The algorithm module connects to general-purpose registers via a data exchange channel to read operands and write the calculation results.

[0023] In one embodiment of the present invention, the DSP module further includes a register group, which includes at least eight general-purpose registers. Among them, at least six general-purpose registers are 32-bit data registers, at least one general-purpose register is a stack pointer register (SP register, used to manage stack operations), and at least one general-purpose register is a link register (LR register, used to store the subroutine return address).

[0024] In one embodiment of the present invention, the algorithm module includes: an F_DIV unit, an F_MUL unit, an F_SQRT unit, an F_ADD unit, an F_SUB unit, an F_CORDIC unit, an F_MOD unit, and an F_MAC unit. It should be noted that in this invention, when 'F_DIV', 'F_MUL', etc., refer to a hardware processing unit, the suffix is ​​'unit' (e.g., F_DIV unit); when referring to an operation in the instruction set, the suffix is ​​'instruction' (e.g., F_DIV instruction). For example, when an 'F_DIV instruction' is decoded and executed, it will control and start the 'F_DIV unit' to work.

[0025] The functions of each hardware processing unit are as follows: The F_DIV unit implements floating-point division, internally employing the Newton-Raphson iterative algorithm to perform mantissa division. This algorithm calculates the division result through iterative approximation, reducing the computation cycle compared to traditional long division while maintaining the same precision. The specific execution process consists of three steps: First, exponent processing: calculating the difference between the exponents of the dividend and divisor to obtain the exponent of the result; second, mantissa processing: normalizing the mantissas of both the dividend and divisor, and then calculating the quotient of the mantissa through multiple Newton-Raphson iterations, with a hardware multiplier introduced to accelerate the calculation of the iteration factor; third, result normalization: combining the obtained exponent and mantissa into a standard floating-point format and checking for overflow or underflow. If overflow or underflow occurs, the corresponding status flag is set to notify the DSP core for exception handling. The F_MUL unit implements floating-point multiplication operations. Internally, it employs Booth encoding to reduce the number of partial products, thus improving multiplication speed. Booth encoding transforms traditional bit-by-bit multiplication into multiplication grouped by 2 bits, halving the number of partial products. The specific execution process includes: exponent addition, adding the exponents of the multiplicand and multiplier to obtain the exponent of the result; mantissa Booth encoding and partial product generation, Booth encoding the mantissa of the multiplier to generate the corresponding partial product; partial product accumulation, using a Wallace tree adder to accumulate 16 partial products in parallel, reducing the accumulation cycle from 16 to 4 compared to a traditional serial adder; and result normalization and rounding, normalizing the accumulated mantissa, adjusting the exponent if the mantissa overflows, and using rounding to process the least significant bit of the mantissa to ensure operational precision. The F_SQRT unit implements floating-point square root operations, internally employing the Goldschmidt iterative algorithm. This algorithm eliminates the need for division, approximating the square root result solely through multiplication and addition, making it suitable for hardware implementation. The specific execution process is as follows: First, the input floating-point number is processed by its exponent. If the exponent is odd, it is incremented by 1 and the mantissa is shifted right by 1 bit to make the exponent even, facilitating subsequent calculations. Then, the iteration factor is initialized to 1.0. Subsequently, three iterations are performed, updating the iteration factor and intermediate results through multiplication in each iteration. The iteration formula is: Where s is the input floating-point number; x_n is the intermediate result of the nth iteration.

[0026] Finally, the iteration results are normalized to obtain the final square root result, and the result is checked to see if it is within the valid range. If the input is negative, an exception flag is set. The F_ADD unit implements floating-point addition, and its core function is to solve the mantissa alignment problem. The specific execution process is as follows: First, compare the exponents of the two addends. Shift the mantissa of the addend with the smaller exponent to the right by a number of bits equal to the exponent difference, and simultaneously adjust its exponent to match the larger exponent. During the right shift, sign bit extension is used to ensure the sign of the mantissa remains unchanged. Then, perform addition on the aligned mantissas. If it is a subtraction operation, convert it to addition. Finally, normalize the mantissa of the result. If the mantissa overflows, shift it left by 1 bit and adjust the exponent by 1; if the mantissa is not normalized, shift it right and adjust the exponent by 1, while also performing rounding to ensure the precision of the result. The F_SUB unit implements floating-point subtraction. Its hardware structure is highly reused from the F_ADD unit. Only the sign conversion logic is added in the mantissa operation stage—the sign bit of the subtrahend is inverted. Then, the exponent comparison, mantissa alignment, mantissa addition and result normalization are performed according to the floating-point addition process, which greatly reduces the occupation of hardware resources, while ensuring that the subtraction operation and the addition operation have the same execution cycle (1 clock cycle). The F_CORDIC unit implements a floating-point CORDIC algorithm, which calculates complex operations such as trigonometric functions, hyperbolic functions, arctangents, and square roots through iterative rotation. This algorithm requires no dedicated multipliers or dividers, simplifying hardware implementation. The F_CORDIC unit supports two operating modes: rotation mode and vector mode. Rotation mode rotates a vector by a specified angle, while vector mode converts a vector to polar coordinates. The unit includes an internal angle memory that stores preset iteration angle values. The iteration count is set to 16, and the execution cycle is 16 clock cycles, meeting the needs of coordinate transformation in motion control and phase calculation in signal processing. The F_MOD unit implements the floating-point MOD algorithm (modulo operation), which calculates the remainder after dividing the dividend by the divisor. The specific execution process is as follows: First, it checks if the absolute value of the dividend is less than the absolute value of the divisor. If so, the dividend is directly output as the remainder; otherwise, the remainder is calculated through multiple subtractions—first, the F_DIV unit calculates the quotient of the dividend and divisor, taking the integer part of the quotient; then, the F_MUL unit calculates the product of the integer quotient and the divisor; finally, the F_SUB unit calculates the difference between the dividend and the product to obtain the remainder. The execution cycle of the F_MOD unit is determined by the cycle of the F_DIV unit, which is 16 clock cycles, making it suitable for periodic control scenarios. The F_MAC unit implements the floating-point MAC algorithm (multiply-accumulate operation), which performs the operation "result = result + multiplicand × multiplier". It is the core operation unit for algorithms such as filtering and convolution in digital signal processing. The F_MAC unit integrates an F_MUL unit and an adder, supporting pipelined operation—simultaneously completing multiplication and accumulation operations within one clock cycle, with an execution cycle of one clock cycle. Furthermore, the F_MAC unit has an accumulator clearing function, which can reset the accumulator value to zero via a control signal, facilitating the start of a new multiply-accumulate sequence. This is suitable for scenarios requiring continuous multiply-accumulate operations, such as FIR (Finite Impulse Response) filters and IIR (Infinite Impulse Response) filters.

[0027] Second Embodiment like Figure 3 As shown, based on the aforementioned digital signal processing system, the second embodiment of the present invention provides a dynamic program update method, applied to a digital signal processing system including a DSP module, an instruction memory, and a data memory. The DSP module includes a DSP core, and the execution structure of the DSP core is a three-stage pipeline, including an instruction fetch stage, a decoding stage, and an execution stage. This dynamic program update method includes at least the following steps: S1: In the program running in the DSP core, execute a pause instruction belonging to its instruction set.

[0028] S2: During the execution phase of the pause instruction, the DSP core enters an idle state for the number of clock cycles specified by the immediate value in the pause instruction; during the idle state, the DSP core stops all access to the instruction memory and data memory, and the external master controller modifies the instruction code in the instruction memory.

[0029] S3: After the idle state ends, the DSP core resumes operation based on the pre-saved pipeline state.

[0030] like Figure 4 As shown, in one embodiment of the present invention, the execution structure of the DSP core is a three-stage pipeline. The three stages of the pipeline are: instruction fetch stage, decode stage, and execution stage. Specifically: The instruction fetch stage refers to the DSP core initiating a read request to the instruction memory and data memory, retrieving the corresponding instruction based on the address stored in the PC register, and transmitting the retrieved instruction to the decoding stage. At the same time, the value of the PC register is updated to the address of the next instruction to be fetched.

[0031] The decoding stage refers to parsing the instructions transmitted in the fetch stage, determining the instruction type (such as arithmetic operation instructions, stack instructions, pause instructions belonging to its instruction set, etc.), and generating corresponding control signals according to the instruction type; if it is an arithmetic operation instruction, it is also necessary to determine the address of the register involved in the operation and the corresponding algorithm module; in this stage, a new round of instruction fetching operation is started at the same time to realize the parallelism of instruction fetching and decoding.

[0032] The execution phase refers to: based on the control signals generated in the decoding phase, reading operands from the specified general-purpose registers and starting the corresponding algorithm module to perform calculations; single-cycle instructions (such as F_ADD) complete the calculation within one clock cycle and write the result back to the register; multi-cycle instructions (such as F_DIV, F_MUL) require multiple clock cycles and must wait for their execution to be completed before starting the execution phase of the next instruction to avoid data conflicts.

[0033] like Figure 5As shown, in one embodiment of the present invention, the format of the pause instruction is "instruction opcode + immediate value", where the instruction opcode is an 8-bit binary number with a value of 0x1A (this value is different from the opcodes of other instructions to ensure that the decoder can uniquely identify it), used to mark the instruction as a pause instruction; the immediate value is an 8-bit unsigned integer with a value range of 1 to 255, used to specify the number of clock cycles for the DSP core to enter the idle state. For example, when the immediate value is 4, the binary format of the instruction is 0x1A04, and the DSP core will enter an idle state for 4 clock cycles; when the immediate value is 5, the instruction format is 0x1A05, and the DSP core will enter an idle state for 5 clock cycles. This format design allows the pause instruction to flexibly adjust the idle cycle length according to the actual program update requirements. For example, when modifying a small number of instructions, a smaller immediate value (such as 4 to 8 cycles) can be selected, and when modifying a large number of instructions, a larger immediate value (such as 32 to 64 cycles) can be selected, ensuring that the external controller has enough time to complete the modification of the instruction code.

[0034] The execution of a pause instruction includes: in the fetch phase, reading the pause instruction from the instruction memory; in the decode phase, parsing the opcode and immediate value of the pause instruction; and in the execution phase, triggering the idle state based on the immediate value. The execution cycle of the pause instruction is one clock cycle. Specifically, the DSP core reads the pause instruction in the fetch phase (consuming one clock cycle), parses the instruction opcode and immediate value in the decode phase (consuming one clock cycle), and triggers the idle state in the execution phase (this phase only consumes one clock cycle and is used to start the idle control logic). From the start of fetching to entering the idle state, a total of three clock cycles are consumed. However, the execution cycle of the pause instruction itself (i.e., the control process that triggers the idle state) is one clock cycle, consistent with the execution cycles of other single-cycle instructions (such as the F_ADD instruction), facilitating unified pipeline scheduling and avoiding pipeline stalls caused by differences in instruction execution cycles.

[0035] When the DSP core executes a pause instruction, the execution control module generates an idle control signal during the execution phase. This signal acts on the instruction fetch module, decode module, and execution module, causing the DSP core to stop all operations. Specifically, the instruction fetch module stops initiating new instruction fetch requests to the instruction memory and data memory, and the address bus and data bus no longer transmit instruction fetch-related signals; the decode module stops parsing already fetched instructions, stops generating control signals, and stops updating the PC address register value, ensuring that the PC address remains at the address of the instruction following the pause instruction; the execution module stops starting any arithmetic units (such as F_DIV, F_MUL, etc.), stops reading and writing to general-purpose registers, and the arithmetic units are in a reset state. During this idle state, since the DSP core no longer accesses the instruction memory and data memory, the bus resources of the instruction memory and data memory are completely released. The external master controller can modify the instruction code in the instruction memory through the bus, including replacing existing instructions, adding new instructions, or deleting useless instructions, without causing access conflicts with the DSP core.

[0036] In one embodiment of the present invention, a pause instruction belonging to its instruction set is executed. Specifically, the opcode (0x1A) of the pause instruction is written into the opcode lookup table of the DSP core's instruction decoder. When the decoder receives instruction data transmitted from the instruction fetch module, it compares the high 8 bits of the instruction with the value in the opcode lookup table. If a match of 0x1A is found, it is identified as a pause instruction, and the corresponding idle control logic is triggered. Simultaneously, an idle state management unit is added to the DSP core's execution control module. This unit includes a counter, initially set to the immediate value of the pause instruction. The counter decrements by 1 every clock cycle. When the counter reaches 0, a recovery signal is automatically generated, triggering the DSP core to exit the idle state. Furthermore, pause instruction adaptation logic is added to the program counter control module. When the decoder recognizes a pause instruction, the program counter control module receives a prohibition signal, stopping the increment or jump of the PC address register. This ensures that the value of the PC address register remains unchanged during the DSP core's idle state, preventing instruction fetch address errors during recovery. Meanwhile, an idle state flag (bit 7) is added to the status register of the DSP core. When the DSP core enters the idle state, the flag is set to 1; when it exits the idle state, the flag is set to 0. This allows the external controller to read the flag to determine the status of the DSP core, thereby achieving complete integration of the pause instruction with the DSP core.

[0037] In one embodiment of the present invention, before the pause instruction is executed, the program dynamic update method further includes: the DSP core monitors the running status of the pipeline and multi-cycle instructions, and selects the timing to trigger the pause instruction based on the monitoring results.

[0038] The detailed steps are as follows: The DSP core collects real-time operating status information for each stage. Specifically, it collects the address to be fetched (PC address) and the fetch request signal (whether an instruction fetch is being initiated) from the instruction fetch module; it collects the currently parsed instruction type (data processing instruction, control instruction, multi-cycle instruction, etc.), the instruction's opcode, and operand information from the decode module; it collects the currently executed instruction name, the number of cycles executed, and the busy / idle status of the arithmetic unit (e.g., whether F_DIV is running) from the execution module; and it collects the current value of the PC address register and the PC address update status (whether an update is allowed) from the program counter control module.

[0039] The timing of the pause instruction is determined based on the monitoring results, ensuring that the execution of the pause instruction does not affect the complete execution of multi-cycle instructions and the normal timing of the pipeline.

[0040] The timing of triggering the instruction includes: if a multi-cycle instruction is detected being executed during the execution phase, the pause instruction is triggered to enter the pipeline only after the multi-cycle instruction has completed its execution. For example, if the instruction being executed is F_DIV and the cycle counter value is 10, it means that the instruction has executed 10 cycles and requires 6 more cycles to complete. At this time, the conflict detection unit will generate a wait signal to control the pause instruction to not execute until the cycle counter value reaches 16 (F_DIV has completed execution). After the execution module sends the instruction completion signal, the conflict detection unit will generate a trigger signal to allow the pause instruction to enter the pipeline for execution, thus avoiding data errors caused by the interruption of multi-cycle instruction execution.

[0041] If the execution phase detects that a single-cycle instruction (such as F_ADD) is being executed, since a single-cycle instruction only requires one clock cycle to complete, the conflict detection unit will immediately generate a trigger signal after the single-cycle instruction completes (the execution module sends an instruction completion signal), allowing the pause instruction to enter the pipeline for execution; or, simultaneously with the execution of the single-cycle instruction, the pause instruction can enter the fetch phase (because the execution cycle of a single-cycle instruction is short, by the time the pause instruction enters the decoding phase, the single-cycle instruction has already completed execution, and no conflict will occur). For example, when the execution phase executes the F_ADD instruction (one cycle), the fetch phase can simultaneously read the pause instruction. When the F_ADD instruction completes execution, the pause instruction just enters the decoding phase, achieving seamless pipeline transitions and reducing waiting time.

[0042] In addition, if the DSP program needs to be updated frequently, multiple pause instruction insertion points can be preset in the program. The DSP core selects the optimal triggering time based on the pipeline status at each insertion point to ensure the real-time performance and stability of the update operation.

[0043] In one embodiment of the present invention, before entering the idle state, the program dynamic update method further includes: the DSP core records the current state of the pipeline and saves it to a non-volatile temporary register; the pipeline state includes the value of the PC address register, the instruction data that has been fetched but not decoded, the contents of the decoding status register, and the state of each arithmetic unit in the execution module.

[0044] The detailed steps are as follows: When the pause instruction is triggered, the DSP core sends a pipeline protection signal to the instruction fetch module, decode module, and execution module to ensure that the pipeline remains stable during idle periods and that no instruction loss or errors occur.

[0045] Upon receiving the protection signal, the instruction fetch module immediately stops sending new instruction fetch requests to the instruction memory and data memory. If an instruction fetch operation is currently in progress (e.g., an address signal has been sent but no data has been received), it sends a cancel instruction fetch signal to the instruction memory and data memory to terminate the fetch and prevent invalid instructions from entering the pipeline. At the same time, the instruction fetch module temporarily stores the instruction data that has been read but not yet transmitted to the decoding module in a temporary buffer to prevent data loss.

[0046] After receiving the protection signal, the decoding module stops parsing the fetched instructions (including instructions in the temporary buffer), stops generating control signals, and temporarily stores the current decoding progress (such as the number of parsed opcodes and the extracted operand information) in the decoding status register. This facilitates continued parsing when the pipeline is restored, avoiding the time wasted due to re-decoding.

[0047] After receiving the protection signal, the execution module stops starting new arithmetic units. If a single-cycle instruction (such as F_ADD) is currently being executed, it waits for the instruction to complete before stopping the operation. If a multi-cycle instruction is currently being executed (but according to the triggering timing mentioned above, the multi-cycle instruction has already been completed), the arithmetic unit stops working directly to ensure that the arithmetic unit is in a stable reset state.

[0048] Meanwhile, the DSP core records the complete state of the pipeline before the pause instruction is executed, including the current value of the PC address register, the instruction data in the temporary buffer, the contents of the decode status register, and the status of each arithmetic unit in the execution module (busy / idle, number of cycles executed, etc.). This status information is stored in a non-volatile temporary register to provide an accurate basis for subsequent pipeline recovery and to avoid pipeline chaos during recovery.

[0049] In one embodiment of the present invention, restoring the operation of the DSP core includes: controlling the instruction fetch module, decoding module and execution module to synchronously resume operation according to the recorded pipeline status.

[0050] The detailed steps are as follows: After the idle period of the pause instruction ends, the DSP core reads the previously recorded pipeline status information and controls each module to resume operation synchronously based on this information, ensuring the timing consistency of the pipeline.

[0051] First, the instruction fetch module re-initiates an instruction fetch request to the instruction memory and data memory based on the recorded value of the PC address register, and reads the first instruction after the pause instruction (the modified instruction). If there is an instruction that has been read but not decoded in the temporary buffer, the instruction fetch module will first transfer the instruction to the decoding module before reading the new instruction to avoid instruction order errors.

[0052] Secondly, the decoding module continues to parse the undecoded instructions in the temporary buffer according to the recorded contents of the decoding status register, and generates the corresponding control signals. After parsing, it parses the newly read instructions from the instruction fetch module and updates the value of the PC address register (pointing to the address of the next instruction). At the same time, it sends an instruction fetch signal to the instruction fetch module to start a new instruction fetch operation, thereby achieving synchronization between decoding and instruction fetching.

[0053] Then, based on the recorded state of the arithmetic unit, if there is an unfinished single-cycle instruction (which rarely occurs according to the protection operation described above), the execution module continues to execute the instruction until it is completed; if the arithmetic unit is in a reset state, the corresponding arithmetic unit is started according to the control signal generated by the decoding module to execute the current instruction, and at the same time, an execution status signal is sent to the decoding module to facilitate the decoding module to adjust the parsing rhythm of subsequent instructions and achieve synchronization between execution and decoding.

[0054] For multi-cycle instructions, if there are decoded but not executed multi-cycle instructions (such as F_MUL) before the instruction execution is paused, after the pipeline resumes, the execution module will continue or re-execute the instruction based on the recorded number of executed cycles (0 if not executed). For example, if the F_MUL instruction has executed 3 cycles, execution will resume from the 4th cycle after resumption, until 8 cycles are completed; if it has not been executed, execution will start from the 1st cycle, ensuring that multi-cycle instructions can be executed completely.

[0055] Through the above timing synchronization operations, the pipeline can quickly enter a stable parallel working state after recovery, avoiding timing errors caused by the execution of pause instructions and ensuring the normal operation of the DSP core after dynamic program updates.

[0056] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of each embodiment can be combined, and all are within the protection scope of this invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0058] The above provides a detailed description of the program dynamic update method and digital signal processing system provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A dynamic program update method, applied to a digital signal processing system including a DSP module, an instruction memory, and a data memory, wherein the DSP module includes a DSP core, and the execution structure of the DSP core is a three-stage pipeline, including an instruction fetch stage, a decoding stage, and an execution stage; characterized in that... Includes the following steps: S1: In the program running on the DSP core, execute a pause instruction belonging to its instruction set; S2: During the execution phase of the pause instruction, the DSP core enters an idle state for the number of clock cycles specified by the immediate value in the pause instruction; During the idle state, the DSP core ceases all access to the instruction memory and the data memory, and the external controller modifies the instruction code in the instruction memory; S3: After the idle state ends, the DSP core resumes operation according to the pre-saved pipeline state.

2. The program dynamic update method as described in claim 1, characterized in that: The format of the pause instruction is "instruction opcode + immediate value", where the instruction opcode is an 8-bit binary number used to uniquely identify the pause instruction, and the immediate value is an 8-bit unsigned integer used to specify the number of clock cycles in the idle state.

3. The program dynamic update method as described in claim 1, characterized in that... Executing the pause command includes: During the instruction fetch phase, the pause instruction is read from the instruction memory; During the decoding phase, the opcode and immediate value of the pause instruction are parsed; During the execution phase, the idle state is triggered based on the immediate value.

4. The program dynamic update method as described in claim 1, characterized in that... Before the pause instruction is executed, the program dynamic update method further includes: The DSP core monitors the operation status of the pipeline and multi-cycle instructions, and selects the timing to trigger the pause instruction based on the monitoring results.

5. The program dynamic update method as described in claim 4, characterized in that... Selecting the trigger timing includes: If it is detected that a multi-cycle instruction is being executed during the execution phase, the pause instruction will be triggered to enter the pipeline for execution only after the multi-cycle instruction has been completed.

6. The method for dynamically updating a program as described in claim 1, characterized in that... Before entering the idle state, the program dynamic update method further includes: The DSP core records the current state of the pipeline and saves it to a non-volatile temporary register; the pipeline state includes the value of the PC address register, the instruction data that has been fetched but not decoded, the contents of the decode status register, and the state of each arithmetic unit in the execution module.

7. The program dynamic update method as described in claim 6, characterized in that... Restoring the operation of the DSP core includes: Based on the recorded pipeline status, the instruction fetch module, decode module, and execution module are controlled to resume operation synchronously.

8. A digital signal processing system for implementing the program dynamic update method according to any one of claims 1 to 7, characterized in that... include: DSP module, instruction memory, data memory, and external main controller; The instruction memory and the data memory are used to store the instructions and data required by the DSP module, respectively. The DSP module includes a DSP core, a program counter control module, general-purpose registers, a PC register, and an algorithm module; the DSP core is connected to the program counter control module; the PC register is used to store the address of the next instruction to be read. The instruction set of the DSP core includes a pause instruction. The DSP core is configured to execute the pause instruction and enter an idle state specified by the immediate value in the instruction during the execution phase of the instruction, while ceasing all access to the instruction memory and the data memory. The external master controller is configured to modify the instruction code in the instruction memory while the DSP core is in the idle state.

9. The digital signal processing system as described in claim 8, characterized in that: The DSP module also includes an idle state management unit; the idle state management unit includes a counter, the initial value of which is set by the immediate value in the pause instruction, and is used to control the duration of the idle state.

10. The digital signal processing system as described in claim 8, characterized in that: The DSP module also includes a status register; the status register has an idle status flag bit, which is used to indicate whether the DSP core is in an idle state.

Images