Method, circuit and cache for improving l2 cache reliability through address remapping
By establishing remapping entries and dynamically remapping SRAM addresses, the performance degradation caused by soft errors in the L2 cache system is resolved, enabling dynamic repair of soft errors and improvement of system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAHANG RADIO MEASUREMENT & RES INST
- Filing Date
- 2024-12-12
- Publication Date
- 2026-05-29
AI Technical Summary
SRAM soft errors cause performance degradation in L2 cache systems, and existing technologies struggle to effectively address this issue.
By establishing remapping entries, SRAM addresses and check bits are dynamically remapped, and the correct TAG values and check bits are stored in the remapping entries, thus achieving dynamic repair of soft errors.
It effectively reduces the impact of SRAM soft errors on L2 cache performance, and addresses are remapped after system restart to adapt to soft errors in different locations, thereby improving system stability.
Smart Images
Figure CN122111744A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory technology, specifically relating to a method, circuit, and cache for improving L2 cache reliability through address remapping. Background Technology
[0002] Due to manufacturing process limitations, SRAM cells in chips may contain both hard errors (always occurring) and soft errors (occasionally occurring). In design, extra rows or columns are often reserved for later remapping of storage locations; this is called SRAM repair. Repair is very effective against hard errors, but it is often a one-time fix (i.e., it can only be repaired once) and is largely ineffective against soft errors.
[0003] In L2 cache design, to improve data reliability, verification functions are often added, such as ECC (Error-Correcting Code) checks on data and parity checks on row address tags. ECC checks have error correction capabilities, and a few errors do not affect the correctness of the data. Parity checks on tags do not have error correction capabilities, so once a check fails, the data is considered invalid and must be read from memory again, causing a sharp drop in cache performance. If soft errors persist for a long time, it is equivalent to a cache row being continuously invalidated, and the impact on system performance will be even greater. Summary of the Invention
[0004] Based on the above analysis, the present invention aims to disclose a method, circuit, and cache for improving L2 cache reliability through address remapping, thereby solving the problem of L2 cache system performance degradation caused by SRAM soft errors.
[0005] This invention discloses a method for improving L2 cache reliability through address remapping, comprising:
[0006] Step S1: Create multiple sets of remapping table entries for storing remapping content;
[0007] Step S2: Read the row address TAG from the SRAM address storing the row address TAG and the corresponding check bit, and calculate the check bit; if the calculated check bit is different from the corresponding check bit stored in the SRAM address, it is determined that the row address TAG read from the SRAM address is incorrect and is an SRAM address that needs to be remapped.
[0008] Step S3: Allocate a set of remapping entries for the SRAM address that needs to be remapped. One SRAM address that needs to be remapped corresponds to one set of remapping entries until all remapping entries are allocated.
[0009] Step S4: When writing the row address TAG and the corresponding parity bit to the SRAM, the row address TAG and the corresponding parity bit written to the SRAM address to be remapped are mapped to the remapping table entry allocated to it; when reading the row address TAG and the parity bit from the SRAM, when the SRAM address to be remapped is read, the row address TAG value and the parity bit are read from the remapping table entry allocated to it.
[0010] Furthermore, in step S1, the number of remapping entries is determined by the capacity of the L2 cache and the tolerance for soft errors. The larger the capacity of the L2 cache and the lower the tolerance for soft errors, the more remapping entries there are.
[0011] Furthermore, each remapping entry corresponds to a set of registers for storing the remapping content; when there is only one SRAM block for storing the row address TAG and the corresponding parity bit, the remapping content stored in the register set of a remapping entry includes: SRAM address, mapping flag, TAG value, and parity bit; wherein,
[0012] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0013] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0014] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped.
[0015] Furthermore, when there are multiple SRAMs used to store TAGs and check bits, each SRAM is assigned a path number;
[0016] Each remapping entry corresponds to a set of registers, and the remapping information stored in the registers includes: SRAM address, path number, mapping flag, TAG value, and check bit; wherein,
[0017] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0018] The path number is the path number of the SRAM where the allocated SRAM address to be remapped is located;
[0019] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0020] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped.
[0021] Furthermore, in step S3, during the process of allocating a set of remapping entries for the SRAM address that needs to be remapped, a pointer is set; the pointer is used to record the position of the next allocated entry.
[0022] When a set of remapped entries needs to be allocated, the remapped entry pointed to by the current pointer is allocated, and the pointer is moved forward one step; if all remapped entries have been allocated, no operation is performed.
[0023] When allocating a set of remapping entries for an SRAM address that needs to be remapped, the SRAM address, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid. In the case of multiple SRAMs, the SRAM address, the path number, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid.
[0024] Furthermore, in step S4, when writing the row address TAG and the corresponding parity bit to the SRAM, the address to be written to the SRAM is monitored. When it is detected that the address to be written to the SRAM is the same as the SRAM address in the allocated remapping table entry, the TAG value and the corresponding parity bit of the SRAM address are synchronously mapped to the register of the TAG value and the corresponding parity bit in the corresponding remapping table entry.
[0025] In the case of multiple SRAMs, the address and path number of the SRAM being written are monitored. When it is detected that the address and path number of the SRAM being written are the same as the SRAM address and path number in the allocated remapping table entry, the TAG value and corresponding parity bit of that SRAM address will be written and synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
[0026] Further, in step S4, while reading the TAG value in the SRAM and checking the check bit, the keywords including the SRAM address and TAG value in the allocated remapping table entry are matched; if the match is successful and the mapping flag is valid, the TAG value of the matched remapping table entry and the check result are output; if the match is unsuccessful or the mapping flag is invalid, the TAG value read from the SRAM and the check result are output.
[0027] In the case of multiple SRAMs, match the keywords in the allocated remapping table entries, including the SRAM address, path number, and TAG value; if the match is successful and the mapping flag is valid, output the TAG value of the matched remapping table entry and the verification result; if the match is unsuccessful or the mapping flag is invalid, output the TAG value read from the SRAM and the verification result.
[0028] The present invention also discloses an L2 cache address remapping circuit, comprising: SRAM, an entry allocation circuit, a mapping circuit, and a read circuit;
[0029] The SRAM is used to store row address TAGs and corresponding check bits. When a row address TAG is written to the SRAM, the automatically calculated check bit is also written to the SRAM. When a TAG is read from the SRAM address, the check bit is automatically calculated and compared with the check bit stored in the SRAM. If the check bits are different, it indicates that the TAG read from the SRAM address is incorrect and needs to be remapped.
[0030] The entry allocation circuit includes multiple sets of remapping entries; the remapping entries are used to store remapping content; the entry allocation circuit is used to allocate a set of remapping entries for each SRAM address that needs to be remapped; until all remapping entries have been allocated.
[0031] The mapping circuit is used to map the row address TAG and corresponding check bit written to the SRAM address to be remapped to the remapping table entry allocated to it when writing row address TAG and corresponding check bit to SRAM.
[0032] The reading circuit is used to read the TAG and check bits from the remapping table entry or SRAM according to the remapping situation and send them to the subsequent circuit.
[0033] Furthermore, the table entry allocation circuit also includes a pointer, which is used to record the position of the next table entry allocation; when a group of remapped table entries needs to be allocated, the remapped table entry pointed to by the current pointer is allocated, and the pointer is moved forward one time; if all remapped table entries have been allocated, then no operation is performed.
[0034] The present invention also discloses a cache, which is an L2 cache, including the L2 cache address remapping circuit described above, for improving the reliability of L2 cache through address remapping and eliminating the impact of soft errors in SRAM on system performance.
[0035] This invention can achieve one of the following beneficial effects:
[0036] The present invention discloses a method, circuit, and cache for improving L2 cache reliability through address remapping. By remapping addresses, the impact of SRAM soft errors on L2 cache performance can be effectively reduced. Moreover, after system restart, the address is remapped (not a fixed, one-time mapping), which is also effective for soft errors that occur at different locations after each system startup. Attached Figure Description
[0037] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0038] Figure 1 This is a flowchart of a method for improving L2 cache reliability through address remapping in an embodiment of the present invention;
[0039] Figure 2 This is a block diagram of the L2 cache address remapping circuit in an embodiment of the present invention. Detailed Implementation
[0040] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.
[0041] Example 1
[0042] One embodiment of the present invention discloses a method for improving L2 cache reliability through address remapping, such as... Figure 1 As shown, it includes the following steps:
[0043] Step S1: Create multiple sets of remapping table entries for storing remapping content;
[0044] Step S2: Read the row address TAG from the SRAM address storing the row address TAG and the corresponding check bit, and calculate the check bit; if the calculated check bit is different from the corresponding check bit stored in the SRAM address, it is determined that the row address TAG read from the SRAM address is incorrect and is an SRAM address that needs to be remapped.
[0045] Step S3: Allocate a set of remapping entries for the SRAM address that needs to be remapped. One SRAM address that needs to be remapped corresponds to one set of remapping entries until all remapping entries are allocated.
[0046] Step S4: When writing the row address TAG and the corresponding parity bit to the SRAM, the row address TAG and the corresponding parity bit written to the SRAM address to be remapped are mapped to the remapping table entry allocated to it; when reading the row address TAG and the parity bit from the SRAM, when the SRAM address to be remapped is read, the row address TAG value and the parity bit are read from the remapping table entry allocated to it.
[0047] Specifically, in step S1, the number of remapping entries is determined by the capacity of the L2 cache and the tolerance for soft errors. The larger the capacity of the L2 cache and the lower the tolerance for soft errors, the more remapping entries there are.
[0048] Specifically, each group of remapping entries corresponds to a set of registers used to store the remapping content; when there is only one SRAM block used to store the row address TAG and the corresponding parity bit, the remapping content stored in the register set of a group of remapping entries includes: SRAM address, mapping flag, TAG value, and parity bit; wherein,
[0049] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0050] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0051] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped; the mapping flag is set to "1" to indicate validity; the mapping flag is set to "0" to indicate invalidity.
[0052] Specifically, when the number of row address TAGs and corresponding parity bits to be stored is large, multiple SRAMs are required, that is, there are multiple SRAMs used to store row address TAGs and parity bits; in order to distinguish each SRAM, each SRAM is assigned a path number.
[0053] To remap soft errors across multiple SRAMs, a set of registers storing remapped information includes: SRAM address, path number, mapping flag, TAG value, and parity bit; among which,
[0054] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0055] The path number is the path number of the SRAM where the allocated SRAM address to be remapped is located;
[0056] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0057] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped; the mapping flag is set to "1" to indicate validity; the mapping flag is set to "0" to indicate invalidity.
[0058] Specifically, in step S3, during the process of allocating a set of remapping entries for the SRAM address that needs to be remapped, a pointer is set; the pointer is used to record the position of the next allocated entry.
[0059] When a set of remapped entries needs to be allocated, the remapped entry pointed to by the current pointer is allocated, and the pointer is moved forward one step; if all remapped entries have been allocated, no operation is performed.
[0060] When allocating a set of remapping entries for an SRAM address that needs to be remapped, the SRAM address, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid. In the case of multiple SRAMs, the SRAM address, the path number, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid.
[0061] Specifically, in step S4, when writing row address TAG and corresponding parity bit to SRAM, the address to be written to SRAM is monitored. When it is detected that the address to be written to SRAM is the same as the SRAM address in the allocated remapping table entry, the TAG value and corresponding parity bit of the SRAM address are synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
[0062] In the case of multiple SRAMs, the address and path number of the SRAM being written are monitored. When it is detected that the address and path number of the SRAM being written are the same as the SRAM address and path number in the allocated remapping table entry, the TAG value and corresponding parity bit of that SRAM address will be written and synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
[0063] Specifically, in step S4, while reading the TAG value in the SRAM and checking the check bit, the keywords including the SRAM address and TAG value in the allocated remapping table entry are matched; if the match is successful and the mapping flag is valid, the TAG value and check result of the matched remapping table entry are output; if the match is unsuccessful or the mapping flag is invalid, the TAG value and check result read from the SRAM are output.
[0064] In the case of multiple SRAMs, match the keywords in the allocated remapping table entries, including the SRAM address, path number, and TAG value; if the match is successful and the mapping flag is valid, output the TAG value of the matched remapping table entry and the verification result; if the match is unsuccessful or the mapping flag is invalid, output the TAG value read from the SRAM and the verification result.
[0065] Specifically, after the system restarts, the contents of the multiple sets of remapping table entries established in step S1 for storing remapping content are reset to zero, and the pointers are restored to their initial state, pointing to the initial remapping table entries; steps S2-S4 are repeated to perform L2 cache address remapping to eliminate the impact of new soft errors in SRAM after the restart.
[0066] In summary, the embodiments of the present invention can achieve the following effects:
[0067] Methods to improve L2 cache reliability through address remapping and L2 cache: By remapping addresses, the impact of soft errors on L2 cache performance can be effectively reduced. Moreover, after system restart, the addresses are remapped (not a fixed, one-time mapping), which is also effective for soft errors that occur in different locations after each system startup.
[0068] Example 2
[0069] This embodiment discloses an L2 cache address remapping circuit, such as Figure 2 As shown, it includes: SRAM, entry allocation circuit, mapping circuit and read circuit;
[0070] The SRAM is used to store row address TAGs and corresponding check bits. When a row address TAG is written to the SRAM, the automatically calculated check bit is also written to the SRAM. When a TAG is read from the SRAM address, the check bit is automatically calculated and compared with the check bit stored in the SRAM. If the check bits are different, it indicates that the TAG read from the SRAM address is incorrect and needs to be remapped.
[0071] The entry allocation circuit includes multiple sets of remapping entries; the remapping entries are used to store remapping content; the entry allocation circuit is used to allocate a set of remapping entries for each SRAM address that needs to be remapped; until all remapping entries have been allocated.
[0072] The mapping circuit is used to map the row address TAG and corresponding check bit written to the SRAM address to be remapped to the remapping table entry allocated to it when writing row address TAG and corresponding check bit to SRAM.
[0073] The reading circuit is used to read the TAG and check bits from the remapping table entry or SRAM according to the remapping situation and send them to the subsequent circuit.
[0074] Specifically, the number of remapping entries is determined by the capacity of the L2 cache and the tolerance for soft errors. The larger the capacity of the L2 cache and the lower the tolerance for soft errors, the more remapping entries there are.
[0075] Specifically, when there is only one SRAM storing the TAG and parity bit, a set of remapping entries corresponds to a set of registers. The remapping content stored in the registers includes: SRAM address, mapping flag, TAG value, and parity bit; wherein,
[0076] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0077] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0078] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped; the mapping flag is set to "1" to indicate validity; the mapping flag is set to "0" to indicate invalidity.
[0079] When there are multiple SRAMs used to store TAGs and parity bits, each SRAM is assigned a path number;
[0080] Each remapping entry corresponds to a set of registers, and the remapping content stored in the registers includes: SRAM address, path number, mapping flag, TAG value, and check bit; wherein,
[0081] The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry;
[0082] The path number is the path number of the SRAM where the allocated SRAM address to be remapped is located;
[0083] The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped;
[0084] The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped; the mapping flag is set to "1" to indicate validity; the mapping flag is set to "0" to indicate invalidity.
[0085] Preferably, the table entry allocation circuit further includes a pointer, which is used to record the position of the next table entry allocation; when a group of remapped table entries needs to be allocated, the remapped table entry pointed to by the current pointer is allocated, and the pointer is moved forward one time; if all remapped table entries have been allocated, no operation is performed.
[0086] When allocating a set of remapping entries for an SRAM address that needs to be remapped, the SRAM address, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid. In the case of multiple SRAMs, the SRAM address, the path number, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid.
[0087] Specifically, when writing row address TAG and corresponding parity bit to SRAM, the mapping circuit monitors the address written to SRAM. When it detects that the address written to SRAM is the same as the SRAM address in the allocated remapping table entry, it synchronously maps the TAG value and corresponding parity bit of the written SRAM address to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
[0088] In the case of multiple SRAMs, the mapping circuit monitors the address and path number of the SRAM being written. When it detects that the address and path number of the SRAM being written are the same as the address and path number of the SRAM in the allocated remapping table, the TAG value and corresponding parity bit of the SRAM being written are synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
[0089] Specifically, the reading circuit reads the TAG value in the SRAM and checks the check bit while matching the keywords, including the SRAM address and TAG value, in the allocated remapping table entry; if the match is successful and the mapping flag is valid, the TAG value of the matched remapping table entry and the check result are output; if the match is unsuccessful or the mapping flag is invalid, the TAG value read from the SRAM and the check result are output.
[0090] In the case of multiple SRAMs, match the keywords in the allocated remapping table entries, including the SRAM address, path number, and TAG value; if the match is successful and the mapping flag is valid, output the TAG value of the matched remapping table entry and the verification result; if the match is unsuccessful or the mapping flag is invalid, output the TAG value read from the SRAM and the verification result.
[0091] Specifically, after the system restarts, the circuit resets the contents of the multiple sets of remapping table entries used to store the remapping content to zero, restores the pointer to the initial state, and points to the initial remapping table entry; and remaps the L2 cache address to eliminate the impact of soft errors in SRAM.
[0092] Example 3
[0093] This embodiment discloses a cache; the cache is an L2 cache, which includes an L2 cache address remapping circuit as described in Embodiment 2; address remapping improves the reliability of the L2 cache and eliminates the impact of soft errors in SRAM on system performance.
[0094] The specific technical details and beneficial effects in this embodiment are the same as those in Embodiments 1 and 2. Please refer to them for details, and they will not be repeated here.
[0095] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for improving L2 cache reliability through address remapping, characterized in that, include: Step S1: Create multiple sets of remapping table entries for storing remapping content; Step S2: Read the row address TAG from the SRAM address storing the row address TAG and the corresponding check bit, and calculate the check bit; if the calculated check bit is different from the corresponding check bit stored in the SRAM address, it is determined that the row address TAG read from the SRAM address is incorrect and is an SRAM address that needs to be remapped. Step S3: Allocate a set of remapping entries for the SRAM address that needs to be remapped. One SRAM address that needs to be remapped corresponds to one set of remapping entries until all remapping entries are allocated. Step S4: When writing the row address TAG and the corresponding parity bit to the SRAM, the row address TAG and the corresponding parity bit written to the SRAM address to be remapped are mapped to the remapping table entry allocated to it; when reading the row address TAG and the parity bit from the SRAM, when the SRAM address to be remapped is read, the row address TAG value and the parity bit are read from the remapping table entry allocated to it.
2. The method for improving L2 cache reliability through address remapping according to claim 1, characterized in that, In step S1, the number of remapping entries is determined by the capacity of the L2 cache and the tolerance for soft errors. The larger the capacity of the L2 cache and the lower the tolerance for soft errors, the more remapping entries there are.
3. The method for improving L2 cache reliability through address remapping according to claim 2, characterized in that, Each remapping entry corresponds to a set of registers for storing the remapping content. When there is only one SRAM block for storing the row address TAG and the corresponding parity bit, the remapping content stored in the register set of a remapping entry includes: SRAM address, mapping flag, TAG value, and parity bit; wherein, The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry; The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped; The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped.
4. The method for improving L2 cache reliability through address remapping according to claim 2, characterized in that, When there are multiple SRAMs used to store TAGs and parity bits, each SRAM is assigned a path number; Each remapping entry corresponds to a set of registers, and the remapping information stored in the registers includes: SRAM address, path number, mapping flag, TAG value, and check bit; wherein, The SRAM address is the SRAM address that needs to be remapped and allocated to the remapping entry; The path number is the path number of the SRAM where the allocated SRAM address to be remapped is located; The TAG value and check bit are the correct TAG value and corresponding check bit corresponding to the SRAM address that needs to be remapped; The mapping flag is used to identify whether the remapped content in the remapped entry is mapped; if the mapping flag is valid, the remapped entry is mapped; if the mapping flag is invalid, the remapped entry is not mapped.
5. The method for improving L2 cache reliability through address remapping according to claim 3 or 4, characterized in that, In step S3, during the process of allocating a set of remapping entries for the SRAM address that needs to be remapped, a pointer is set; the pointer is used to record the position of the next allocated entry. When a set of remapped entries needs to be allocated, the remapped entry currently pointed to by the pointer is allocated, and the pointer is moved forward one step. If all remapping entries have been allocated, no operation is performed; When allocating a set of remapping entries for an SRAM address that needs to be remapped, the SRAM address, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid. In the case of multiple SRAMs, the SRAM address, the path number, the correct TAG value, and the parity bit are written to the allocated remapping entry, and the mapping flag is set to valid.
6. The method for improving L2 cache reliability through address remapping according to claim 5, characterized in that, In step S4, when writing row address TAG and corresponding parity bit to SRAM, the address to be written to SRAM is monitored. When it is detected that the address to be written to SRAM is the same as the SRAM address in the allocated remapping table entry, the TAG value and corresponding parity bit of the SRAM address are written and synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry. In the case of multiple SRAMs, the address and path number of the SRAM being written are monitored. When it is detected that the address and path number of the SRAM being written are the same as the SRAM address and path number in the allocated remapping table entry, the TAG value and corresponding parity bit of that SRAM address will be written and synchronously mapped to the register of the TAG value and corresponding parity bit in the corresponding remapping table entry.
7. The method for improving L2 cache reliability through address remapping according to claim 6, characterized in that, In step S4, while reading the TAG value in the SRAM and checking the check bit, the keywords including the SRAM address and TAG value in the allocated remapping table entry are matched. If the match is successful and the mapping flag is valid, output the TAG value and verification result of the matched remapped entry; if the match is unsuccessful or the mapping flag is invalid, output the TAG value and verification result read from SRAM. In the case of multiple SRAMs, match keywords in the allocated remapping table entries that include SRAM address, path number, and TAG value; If the match is successful and the mapping flag is valid, output the TAG value and verification result of the matched remapped entry; if the match is unsuccessful or the mapping flag is invalid, output the TAG value and verification result read from SRAM.
8. An L2 cache address remapping circuit, characterized in that, include: SRAM, entry allocation circuit, mapping circuit and read circuit; The SRAM is used to store the row address TAG and the corresponding check bit; When writing a row address TAG to SRAM, the automatically calculated parity bit is also written to SRAM at the same time. When a TAG is read from an SRAM address, a check bit is automatically calculated and compared with the check bit stored in the SRAM. If the check bits are different, it indicates that the TAG read from the SRAM address is incorrect and needs to be remapped. The entry allocation circuit includes multiple sets of remapping entries; the remapping entries are used to store remapping content; the entry allocation circuit is used to allocate a set of remapping entries for each SRAM address that needs to be remapped; until all remapping entries have been allocated. The mapping circuit is used to map the row address TAG and corresponding check bit written to the SRAM address to be remapped to the remapping table entry allocated to it when writing row address TAG and corresponding check bit to SRAM. The reading circuit is used to read the TAG and check bits from the remapping table entry or SRAM according to the remapping situation and send them to the subsequent circuit.
9. The L2 cache address remapping circuit according to claim 8, characterized in that, The table entry allocation circuit also includes a pointer, which is used to record the position of the next table entry allocation; when a set of remapped table entries needs to be allocated, the remapped table entry currently pointed to by the pointer is allocated, and the pointer is moved forward one time; If all remapping entries have been allocated, no operation is performed.
10. A cache, characterized in that, The cache is an L2 cache, including the L2 cache address remapping circuit as described in any one of claims 8-9, used to improve the reliability of the L2 cache through address remapping and eliminate the impact of soft errors in SRAM on system performance.