An SPI interface communication method and system, and an SPI host and SPI slave

Abstract

The application belongs to the technical field of communication, and discloses a SPI interface communication method, a SPI interface communication system, a SPI host and a SPI slave. The application comprises the following steps: the SPI host sends a read-write data frame to the first bidirectional data transmission interface of the SPI slave through a bidirectional MIO data transmission interface, the read-write data frame comprises a start identifier, intermediate read-write data and an end identifier, the SPI slave receives the data frame according to the start identifier in the received read-write data frame, and ends the data frame receiving according to the end identifier, and the direction of the bidirectional MIO data transmission interface of the SPI host and the first bidirectional data transmission interface of the SPI slave is switched to the opposite direction after the read-write data frame is received. The application can reduce the number of connections, reduce the expansion cost, and improve the reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to an SPI interface communication method, system, SPI master, and SPI slave. Background Technology

[0002] With technological advancements, the number of devices requiring interconnection is increasing. Consequently, the number of SPI slave devices connected to an SPI master via the SPI bus is also growing. This has led to the development of a master-slave architecture. Taking SPI master control of an ADC chip as an example, this master-slave architecture primarily includes the classic four-wire connection structure where the SPI master simultaneously connects to multiple SPI slave devices, and the daisy-chain connection structure where the master and slave devices are connected in series.

[0003] For classic connection structures, such as Figure 1 As shown, this connection structure uses the SPI master's clock interface (SCLK interface), MO interface, and MI interface to simultaneously connect to the corresponding interfaces of multiple SPI slaves (i.e., ADC chips ADC1, ADC2, and ADC3 in the diagram). The SPI master's SCLK and MO interfaces output to the SPI slaves, and the three SPI slaves output data to the SPI master's MI interface through the SO interface. The SPI master's CS1~CS3 interfaces are respectively connected to the CS interfaces of each SPI slave for chip selection of the corresponding device.

[0004] The advantage of this connection structure is that each SPI slave can be selected individually with a chip select signal, eliminating the possibility of data mistransmission and enabling stable point-to-point transmission. However, the disadvantages are that this connection structure has more wiring, the number of CS chip select signals is directly related to the number of SPI slaves, and when adding SPI slaves later, the SPI master needs to add an additional CS interface, which is not conducive to future expansion.

[0005] Daisy chain connection structure, such as Figure 2 As shown, the SCLK interface of this connection structure is the same as the classic connection structure. The difference is that there is only one CS interface, and like the SCLK interface, it connects multiple SPI slaves simultaneously (i.e., ADC chips ADC1, ADC2, and ADC3 in the figure). The SPI master's MO interface connects to the SI interface of ADC1, the SO interface of ADC1 connects to the SI interface of ADC2, and so on, with the SO interface of the last SPI slave, ADC3, connecting to the MI interface of the SPI master. Through this serial connection, the information to be transmitted from the SPI master to the multiple ADCs is passed in sequence to complete the configuration.

[0006] This connection structure reduces the number of connecting wires compared to the classic connection structure. The SPI master only needs to provide four interfaces, and no additional interfaces are required for future expansion. However, its disadvantages are: if a new SPI slave is needed, the connection between the last SPI slave and the SPI master must be disconnected before adding the new SPI slave, resulting in poor scalability and requiring modification of the hardware routing; furthermore, the CS chip select only serves as a flag signal for the start and end, and for receiving and transmitting of all SPI slaves, and has no other function; moreover, the number of CS interface connections needs to be increased with the number of SPI slaves, increasing costs; additionally, due to the ring structure, if any one SPI slave fails, the entire system will be unable to transmit data to the SPI master, reducing reliability.

[0007] Therefore, while the daisy-chain connection structure has improved upon some of the shortcomings of the classic SPI connection structure, such as reducing the number of data transmission lines by half, there are still areas for improvement, such as:

[0008] Currently, the daisy chain connection structure still has a relatively large number of connection lines, especially the CS interface connection, which is not fully utilized and will increase with the increase of SPI slave devices. This increases costs invisibly and also increases the cost of subsequent iterations.

[0009] Another issue is that in a daisy-chain configuration, where components are connected in a loop, if one SPI slave device disconnects, it will affect all SPI slave devices upstream and downstream of it. For example... Figure 2 In the daisy-chain connection structure, during the read operation, when the SPI slave ADC3 sends data back to the MI interface of the SPI master, if the SPI slave ADC2 fails, the failure of the SPI slave ADC2 will cause the upstream SPI slave ADC1 to be unable to transmit data to the SPI master, and the downstream SPI slave ADC3 will also be unable to receive data, thus causing all SPI slaves to fail to work. Summary of the Invention

[0010] The purpose of this invention is to address the shortcomings of existing technologies by providing an SPI interface communication method, system, SPI master, and SPI slave. The SPI master only requires two interfaces, which can reduce the number of connections, lower expansion costs, and improve system reliability.

[0011] Specifically, the present invention is implemented using the following technical solutions:

[0012] This invention provides an SPI interface communication method, comprising:

[0013] The SPI master sends read / write data frames to the first bidirectional data transmission interface of the SPI slave through the bidirectional MIO data transmission interface. The read / write data frame includes a start identifier, intermediate read / write data, and an end identifier. The SPI slave receives the data frame according to the start identifier in the received read / write data frame and ends the data frame reception according to the end identifier in the received read / write data frame. After receiving the read / write data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

[0014] Furthermore, the SPI slave sends a reply data frame to the SPI master through the first bidirectional data transmission interface. The reply data frame includes a start identifier, intermediate reply data, and an end identifier. The SPI master receives the data frame according to the start identifier in the received reply data frame and ends the data frame reception according to the end identifier in the received reply data frame. After receiving the reply data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

[0015] Furthermore, the intermediate read / write data includes a device id field, a cmd field, an addr field, and a data field; the intermediate response data includes a device id field, an addr field, and a data field.

[0016] In the read / write data frame, the device id field is the ID of the SPI slave; the cmd field is the write or read operation performed on the SPI slave; the addr field is the register address of the SPI slave; when the cmd field is a write operation, the data field is the data written to the register address of the corresponding SPI slave in the addr field; when the cmd field is a read operation, the data field is invalid data.

[0017] In the response data frame, the device id is the ID of the SPI slave; when responding to a write operation, the addr field and data field are invalid; when responding to a read operation, the addr field is the register address of the SPI slave, and the data field is the data in the register address of the corresponding SPI slave in the addr field.

[0018] Furthermore, when the SPI slave receives the read / write data frame, it outputs the received read / write data frame to the first bidirectional data transmission interface of the adjacent downstream SPI slave through the second bidirectional data transmission interface.

[0019] After all SPI slave devices have received the read / write data frames, the directions of the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI master and SPI slave devices are switched to opposite directions.

[0020] The downstream SPI slave sends a reply data frame to the SPI master via the second bidirectional data transmission interface through its upstream SPI slave.

[0021] Furthermore, the read / write data frame includes a start character, several sets of intermediate read / write data, and an end character. Each set of intermediate read / write data includes a device id field, a cmd field, an addr field, and a data field. Each set of intermediate read / write data corresponds to an SPI slave device.

[0022] Furthermore, the cmd fields in the aforementioned sets of intermediate read and write data represent read and write operations, respectively.

[0023] Furthermore, the SPI host has the following states:

[0024] IDLE indicates that the device is idle and enters this state immediately upon power-on or during data transmission intervals, waiting for subsequent operations.

[0025] SEND_START_CODE is the state where the start character is sent. When a read or write operation needs to be initiated, this state is entered to send the start character; after sending, it enters SEND_SLAVE_ID.

[0026] SEND_SLAVE_ID: This status indicates that the corresponding device id field of the SPI slave is being sent. After the sending is completed, it jumps to SEND_CMD_ADDR_DATA;

[0027] SEND_CMD_ADDR_DATA is used to send the cmd, addr, and data fields. If it is necessary to send read / write operations for other SPI slaves after sending the read / write operations for this SPI slave, it jumps back to SEND_SLAVE_ID; otherwise, it jumps to SEND_FINISH_CODE to send the end character.

[0028] SEND_FINISH_CODE indicates the end of transmission; after sending the intermediate read / write data of the read / write data frame, this state is entered to send the end character to complete the transmission of this read / write data frame; after sending the end character, it enters RECV_DATA.

[0029] RECV_DATA is a state used to receive reply data frames output by the SPI slave and identify the intermediate read / write data between the start and end characters in the reply data frame. If the start character is not received within the set first time period, it jumps to WAIT_FINISH_RECV.

[0030] In the WAIT_FINISH_RECV state, the system will continue to check whether the start character output by the SPI slave has not been received for an extended period. If the start character is received within the set second time period, the system will jump back to RECV_DATA; otherwise, it will return to the IDLE state after the set second time period. The bidirectional MIO data transmission interface will switch to the output state to complete the read operation.

[0031] Furthermore, the SPI slave device has the following states:

[0032] IDLE indicates idle state. It enters this state when the device is powered on or during a data transmission gap, waiting for subsequent operations. In this state, the SPI slave continuously receives read and write data frames through the first bidirectional data transmission interface and outputs read and write data frames to downstream SPI slaves through the second bidirectional data transmission interface.

[0033] RECV_START_CODE is a state used to receive the start character from the SPI master and to begin the transmission of read and write data frames. If the start character reception is complete, it will enter RECV_SLAVE_ID_CMD_ADDR_DATA; otherwise, it will remain in this state to receive the start character.

[0034] RECV_SLAVE_ID_CMD_ADDR_DATA is used to receive the device id field, cmd field, addr field, and data field. When a device id field matching its own ID is received, the cmd field, addr field, and data field are received, and the internal operation of the SPI slave is performed. At the same time, it jumps to RECV_FINISH_CODE. Otherwise, it continues to wait for the next set of intermediate read / write data in the read / write data frame until a match is found.

[0035] RECV_FINISH_CODE is the state used for the SPI slave to receive the end character. Once the reception is complete, it enters the SEND_START_CODE state.

[0036] SEND_START_CODE is the state used by the SPI slave to send the start character. After sending, it enters SEND_SLAVE_ID_ADDR_DATA.

[0037] SEND_SLAVE_ID_ADDR_DATA is the state used by the SPI slave to send its own device id, addr and data fields. After sending, it enters the SEND_FINISH_CODE state.

[0038] The SEND_FINISH_CODE state is used for the SPI slave to send the end character. After sending, it returns to the IDLE state. At this time, it still needs to continue to receive the reply data frames output by the downstream SPI slave and transmit them upstream until no start character is received within the set time. Only then will the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI slave be switched back to the default state.

[0039] On the other hand, the present invention also provides an SPI master, including an SCLK clock signal interface and a bidirectional MIO data transmission interface, wherein the bidirectional MIO data transmission interface is used to send read / write data frames to the first bidirectional data transmission interface of the SPI slave and to receive reply data frames from the first bidirectional data transmission interface of the SPI slave.

[0040] After all the SPI slave devices have received the read / write data frames, the direction of the bidirectional MIO data transmission interface of the SPI master device is switched to the opposite direction.

[0041] In another aspect, the present invention also provides an SPI slave device, including an SCLK clock signal interface, a first bidirectional data transmission interface, and a second bidirectional data transmission interface. The first bidirectional data transmission interface is used to receive read / write data frames from the bidirectional MIO data transmission interface of the SPI master and to send reply data frames to the bidirectional MIO data transmission interface of the SPI master. The second bidirectional data transmission interface is used to output the received read / write data frames to the first bidirectional data transmission interface of the adjacent downstream SPI slave device and to receive reply data frames from the first bidirectional data transmission interface of the adjacent downstream SPI slave device.

[0042] After all SPI slave devices have received the read / write data frames, the directions of the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI slave devices are switched to opposite directions.

[0043] In another aspect, the present invention also provides an SPI interface communication system, including an SPI master and an SPI slave as described above;

[0044] The SCLK clock signal interface of the SPI master is connected to the SCLK clock signal interface of the SPI slave to provide a clock signal for the SPI slave. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface of the SPI slave, and the second bidirectional data transmission interface of the SPI slave is left floating.

[0045] Furthermore, the SPI interface communication system includes one SPI master and several SPI slaves as described above;

[0046] The SCLK clock signal interface of the SPI master is connected to the SCLK clock signal interface of each SPI slave, providing a unified clock signal for each SPI slave. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface of the first SPI slave, the second bidirectional data transmission interface of the first SPI slave is bidirectionally connected to the first bidirectional data transmission interface of the second SPI slave, the second bidirectional data transmission interface of the second SPI slave is bidirectionally connected to the first bidirectional data transmission interface of the third SPI slave, and so on, with the second bidirectional data transmission interface of the last SPI slave left floating.

[0047] The beneficial effects of the SPI interface communication method, system, SPI master, and SPI slave of the present invention are as follows:

[0048] 1) The chip select CS signal is not required. Instead, special characters indicating the start and end are sent to replace the chip select CS signal. This retains the point-to-point selection of the device to be communicated while reducing the number of connections. The SPI master is reduced from the original four interfaces in the daisy chain to two interfaces. This allows the SPI master of the FPGA to free up the interfaces for other functions.

[0049] 2) By changing all data interfaces except the SCLK interface to bidirectional ports, and switching the direction of each transmission interface to the opposite direction at the end of sending a data frame, each data interface can be used for the SPI master to send data frames to the SPI slave, and also for the SPI slave to reply with data frames to the SPI master. This eliminates the need for the connection between the SO interface output of the downstream SPI slave and the MI interface of the SPI master in the daisy chain structure, reducing the difficulty of hardware development, improving the scalability of the SPI slave, and reducing expansion costs.

[0050] 3) By using a bidirectional interface between the master and slave devices, the ring structure can be eliminated. As long as the SPI slave that fails is not the most upstream SPI slave, all devices above the failure point can perform complete read and write communication, thus improving the reliability of the system. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of a classic connection structure in existing technology.

[0052] Figure 2 This is a schematic diagram of a daisy chain connection structure in existing technology.

[0053] Figure 3 This is a schematic diagram of a master-slave chain structure according to an embodiment of the present invention.

[0054] Figure 4 This is a schematic diagram of a master-slave chain structure according to an embodiment of the present invention.

[0055] Figure 5 This is a waveform diagram illustrating how an SPI master sends a read / write data frame to an SPI slave device according to an embodiment of the present invention.

[0056] Figure 6 This is a schematic diagram of the waveform of the SPI master sending read and write data frames to three SPI slaves according to an embodiment of the present invention.

[0057] Figure 7 It is the transmission from each slave device and Figure 5 The waveform diagram of the corresponding response data frame for the read / write data frame.

[0058] Figure 8 It is the transmission from each slave device and Figure 6 The waveform diagram of the corresponding response data frame for the read / write data frame.

[0059] Figure 9 This is a schematic diagram of the SPI host chip state transition according to an embodiment of the present invention.

[0060] Figure 10 This is a schematic diagram of the SPI slave chip state transition according to an embodiment of the present invention. Detailed Implementation

[0061] The present invention will now be described in further detail with reference to the embodiments and the accompanying drawings.

[0062] Example 1:

[0063] One embodiment of the present invention is an SPI interface communication system, such as... Figure 3 As shown, the system includes an SPI master and an SPI slave. The SCLK interface of the SPI master is connected to the SCLK interface of the SPI slave, providing a clock signal to the SPI slave. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface (hereinafter referred to as the SIO1 interface) of the SPI slave, while the second bidirectional data transmission interface (hereinafter referred to as the SIO2 interface) of the SPI slave is left floating. This structure is simply referred to as a master-slave chain structure.

[0064] The read / write data includes a start identifier, intermediate read / write data, and an end identifier. The SPI slave receives data frames based on the start identifier and ends receiving data frames based on the end identifier. After receiving the entire read / write data frame, the directions of the SPI master's bidirectional MIO data transmission interface and the SPI slave's first bidirectional data transmission interface are switched to opposite directions. For example, by default, the bidirectional MIO data transmission interface is in output mode and the SIO1 interface is in input mode; when the SPI master sends a complete read / write data frame, it switches the bidirectional MIO data transmission interface to input mode; when the SPI slave receives a complete read / write data frame from the SPI master, it switches the SIO1 interface to output mode.

[0065] Example 2:

[0066] Another embodiment of the present invention, such as Figure 4 As shown, the system includes an SPI master and several SPI slaves. The SCLK interface of the SPI master is connected to the SCLK interfaces of each SPI slave, providing a unified clock signal for all SPI slaves. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface (hereinafter referred to as SIO1 interface) of the first SPI slave, the second bidirectional data transmission interface (hereinafter referred to as SIO2 interface) of the first SPI slave is bidirectionally connected to the first bidirectional data transmission interface (SIO1 interface) of the second SPI slave, the second bidirectional data transmission interface (SIO2 interface) of the second SPI slave is bidirectionally connected to the first bidirectional data transmission interface (SIO1 interface) of the third SPI slave, and so on, with the second bidirectional data transmission interface (SIO2 interface) of the last SPI slave left floating. This structure is simply referred to as a master-slave chain structure.

[0067] The working principle of this invention is as follows.

[0068] The data transmission between the SPI master and SPI slave in a master-slave chain structure and a master-multiple-slave chain structure is the same. The following section uses the SPI master sending a single read / write data frame in a master-multiple-slave chain structure as an example to introduce the SPI interface communication method for reading and writing data between the SPI master and SPI slave during the read / write process.

[0069] The SPI master sends read / write data frames to the first bidirectional data transmission interface of the SPI slave through the bidirectional MIO data transmission interface. The read / write data frame includes a start identifier, intermediate read / write data, and an end identifier. The SPI slave receives the data frame according to the start identifier in the received read / write data frame and ends the data frame reception according to the end identifier in the received read / write data frame. After receiving the read / write data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

[0070] Preferably, in another embodiment, the SPI slave sends a reply data frame to the SPI master through a first bidirectional data transmission interface. The reply data frame includes a start identifier, intermediate reply data, and an end identifier. The SPI master receives the data frame according to the start identifier in the received reply data frame and ends the data frame reception according to the end identifier in the received reply data frame. After receiving the reply data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

[0071] Preferably, in another embodiment, the intermediate read / write data includes a device id field, a cmd field, an addr field, and a data field; the intermediate response data includes a device id field, an addr field, and a data field. In the read / write data frame, the device id is the ID of the SPI slave; the cmd field represents the write or read operation performed on the SPI slave; the addr field is the register address of the SPI slave; when the cmd field is a write operation, the data field contains the data written to the register address of the SPI slave corresponding to the addr field; when the cmd field is a read operation, the data field contains invalid data. In the response data frame, the device id is the ID of the SPI slave; when responding to a write operation, the addr and data fields are invalid; when responding to a read operation, the addr field contains the register address of the SPI slave, and the data field contains the data in the register address of the SPI slave corresponding to the addr field.

[0072] Preferably, in another embodiment, when the SPI slave receives the read / write data frame, it outputs the received read / write data frame to the first bidirectional data transmission interface of the adjacent downstream SPI slave through the second bidirectional data transmission interface; after all SPI slaves have received the read / write data frame, the directions of the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI master and the SPI slave are switched to opposite directions; the downstream SPI slave sends the reply data frame to the SPI master through the second bidirectional data transmission interface via its upstream SPI slave.

[0073] like Figure 5As shown, by default, the bidirectional MIO data transmission interface of the SPI master is in output mode, while the SIO1 interface of all SPI slaves is in input mode and the SIO2 interface is in output mode. At this time, the SPI master sends read / write data frames to the three SPI slaves (i.e., ADC chips ADC1~ADC3). If ADC1 receives the first bit (bit0) of the read / write data frame on the rising edge of the first SCLK clock signal, it simultaneously outputs the received read / write data frame from the SIO2 interface to the SIO1 interface of ADC2 on the same rising edge of the SCLK clock signal. ADC2 will acquire the first bit (bit0) of the data output by ADC1 on the rising edge of the second SCLK clock signal and simultaneously output it to the SIO1 interface of ADC3 on the same rising edge of the second SCLK clock signal, and so on, transmitting read / write data frames downstream to each ADC chip. Furthermore, as long as there is an SCLK clock signal after each ADC chip is powered on, the transmission of read / write data frames will continue; and this transmission of read / write data frames will occur simultaneously with the identification ID and instructions, and the processing of read / write operations within the ADC chip (see...). Figure 10 (RECV_SLAVE_ID_CMD_ADDR_DATA status).

[0074] A single read / write data frame sent by the SPI master includes a start character, intermediate read / write data, and an end character. The start character is a preset, specific binary code (e.g., 8-bit 1111_1011). A start character is sent at the beginning of each data transmission. When the SPI master or ADC chip receives this start character, it determines that data transmission is about to begin, functioning similarly to the CS chip select in classic and daisy-chain connection structures. The end character is also a preset, specific binary code (e.g., 8-bit 1101_1111). A stop character is sent upon completion of each data transmission. When the SPI master or ADC chip receives this stop character, it indicates that data transmission has ended. Referring to Table 1, the `device id` field is the ID number of the ADC chip. When `cmd` is a write operation, the `device id` field is the ID of the ADC chip to be written; when `cmd` is a read operation, the `device id` field is the ID of the ADC chip whose data is being read. The `cmd` field is used to distinguish different commands, including write and read operations. The `addr` field is the address of the ADC chip's internal register. The `data` field is the data in the ADC chip's internal register. When `cmd` is a write operation, the `data` field is the data written to the ADC chip's internal register; when `cmd` is a read operation, the `data` field is the data output from the ADC chip's internal register. During transmission, the ADC chip, acting as an SPI slave, first recognizes the start character, then checks if the `device id` field matches its own ID. If they match, it retrieves the `cmd` field and performs the corresponding operation.

[0075] The timing waveforms for the SPI master accessing the three ADC chips are as follows: Figure 6 As shown. The SPI master first sends a start character, then sends the device id, cmd, addr, and data fields corresponding to ADC1, then sends the device id, cmd, addr, and data fields corresponding to ADC2, and similarly, sends the id, cmd, addr, and data fields corresponding to ADC3; finally, it sends an end character to end all operations of the SPI master in sending and writing data frames.

[0076] Table 1. Format of read / write data frames sent by the SPI master

[0077] A single read / write data frame sent by the SPI master may include reading and writing to the registers of multiple SPI slaves. Preferably, in another embodiment, the read / write data frame includes a start character, several sets of intermediate read / write data, and an end character. Each set of intermediate read / write data includes a device id field, a cmd field, an addr field, and a data field, and each set of intermediate read / write data corresponds to one SPI slave.

[0078] In another embodiment, if the SPI master needs to read data from the registers of the three SPI slaves or the conversion result of the ADC chip, after the SPI master sends the read operation data frame according to the above steps, the bidirectional MIO data transmission interface of the SPI master switches to the input state. After all the SPI slaves receive the end character, their SIO1 interfaces switch to the output state in sequence, and their SIO2 interfaces switch to the input state in sequence. After the switching is completed, the SPI slaves return the read operation result to the SPI master through reply data frames. The SPI slaves (SIO2 interface) and the SPI master (bidirectional MIO data transmission interface) will continuously receive reply data frames from downstream devices on the rising edge of the SCLK clock signal, while each SPI slave (SIO1 interface) sends reply data frames to upstream devices until each interface switches back to the default state.

[0079] The waveform of a single data frame replied by the SPI slave is as follows: Figure 7As shown, when the three ADC chips output data, they shift the data through the output register via the SIO1 interface on the rising edge of the SCLK clock signal. Simultaneously, the SIO2 interface begins receiving data from its downstream ADC chips and shifts it into its own output register. If the three ADC chips and the SPI master do not receive a data frame transmission request from the downstream ADC chips for an extended period (e.g., within a preset time), i.e., do not receive the start character of a reply data frame from the downstream ADC chips for a long time, then the ADC chips and the SPI master will switch their respective data interfaces back to their default states. Specifically, the SPI master's bidirectional MIO data transmission interface will switch back to output mode, the SPI slave's SIO1 interface will switch back to input mode, and the SIO2 interface will switch back to output mode.

[0080] Referring to Table 1, during a write operation, the SPI master sends a read / write data frame similar to that of a read operation, except that the `cmd` field is changed from a read operation field to a write operation field, and a valid `data` field is included (the `data` field of a read operation contains data but is invalid). The SPI slave also needs to reply to the read / write data frame of this write operation, outputting a reply data frame. The reply data frame includes a start character, intermediate reply data, and an end character. The intermediate reply data includes a device id field, an addr field, and a data field. The addr and data fields are invalid data (e.g., all 1s in binary), indicating that the address and data are invalid. After receiving the reply data frame and recognizing the device id field, the SPI master can determine the corresponding SPI slave based on the device id field, and based on the fact that a write operation was sent to that SPI slave, it can determine that this is a reply data frame from a previous write operation, thus determining that the addr and data fields in the reply data frame are invalid data.

[0081] During a read operation, the SPI slave needs to wait for the end character to be received before switching the SIO data interface direction. Then, the SPI slave replies to the read / write data frame of the read operation, outputting a reply data frame. The reply data frame also consists of a start character, intermediate reply data, and an end character. The intermediate reply data includes device id, addr, and data fields. The device id field is the ID of the SPI slave, the addr field is the internal register address of the SPI slave (e.g., the ADC chip), and the data field is the data read (see Table 2). While the SPI slave outputs the reply data frame to its upstream SPI slave or SPI master, it continuously receives data returned from its downstream SPI slave. The waveform timing of the reply data frames from the three ADC chips responding to the SPI master read operation is as follows: Figure 8 As shown.

[0082] Table 2. Format of SPI slave device reply data frame for read operation

[0083] Preferably, in another embodiment, the SPI master can perform mixed read and write operations on the SPI slave, for example, simultaneously performing write operations on some ADC chips and read operations on other ADC chips through a single transmitted read / write data frame. The read / write data frame transmitted by the SPI master includes a start symbol, several sets of intermediate read / write data, and an end symbol. Each set of intermediate read / write data corresponds to one ADC chip. The cmd fields in each of the several sets of intermediate read / write data represent read and write operations, respectively. In the intermediate read / write data corresponding to the ADC chip requiring a write operation, the device id field is the ID of the ADC chip, the cmd field indicates a write operation, the addr field is the internal register address of the ADC chip, and the data field contains valid data (data to be written to the ADC chip); in the intermediate read / write data corresponding to the ADC chip requiring a read operation, the device id field is the ID of the ADC chip, the cmd field indicates a read operation, and the data field contains data but is invalid. Similar to SPI slaves performing read operations, SPI slaves performing write operations also need to respond to the read / write data frames sent by the SPI master. The response data frame includes a start character, intermediate response data, and an end character. The intermediate response data includes device id, addr, and data fields. The device id field is the ID of the ADC chip corresponding to the write operation, while the addr and data fields contain invalid data (e.g., all-1 binary codes), indicating that the address and data are invalid. After receiving the response data frame and recognizing the device id field, the SPI master identifies the corresponding ADC chip based on the device id field. It then uses the cmd field corresponding to the ADC chip in the write operation command (i.e., the read / write data frame) sent to that ADC chip to determine that the response data frame is a reply to the previous write operation read / write data frame, thus determining that the addr and data fields are invalid.

[0084] SPI host chip implementation:

[0085] After the SPI master is powered on, the SCLK interface is generally only active when read and write operations are required. However, after the SPI slave is powered on, as long as there is an SCLK clock signal, it will continuously execute the operation of outputting data from the input state SIO interface to the output state SIO interface, regardless of how the SPI slave's state machine transitions.

[0086] The specific state transitions of the SPI master are as follows: Figure 9 As shown. The SPI master has the following states:

[0087] IDLE: This state indicates that the device is idle. It enters this state immediately after power-on or during data transmission intervals, waiting for subsequent operations.

[0088] SEND_START_CODE: This state is for sending the start character; when a read or write operation needs to be initiated, this state will be entered to send the start character (e.g., 1111_1011); after sending, it will enter SEND_SLAVE_ID.

[0089] SEND_SLAVE_ID: This state indicates the ID number of the SPI slave device being sent (i.e., the corresponding device id field). After the transmission is complete, it jumps to SEND_CMD_ADDR_DATA.

[0090] SEND_CMD_ADDR_DATA: Used to send the cmd, addr, and data fields; if after sending the read / write operation for this SPI slave, it needs to send read / write operations for other SPI slaves, it jumps back to SEND_SLAVE_ID. Otherwise, it jumps to SEND_FINISH_CODE to send the end character.

[0091] SEND_FINISH_CODE: This state indicates the end of transmission. After sending all valid data frames for reading and writing, this state is entered to send an end character (e.g., 1101_1111) to complete the transmission of this data frame. After sending the end character, the system enters RECV_DATA.

[0092] RECV_DATA: This state is used to receive the reply data frame output by the SPI slave, identify the intermediate reply data between the start character and the end character in the reply data frame, and if no start character is received within the set first time period, it jumps to WAIT_FINISH_RECV.

[0093] WAIT_FINISH_RECV: In this state, it continues to check whether the start character output by the SPI slave has not been received for an extended period (e.g., all 1s received for an extended period without any 0s). If the start character is received within the set second time period, it jumps back to RECV_DATA; otherwise, it returns to IDLE after the set second time period. The bidirectional MIO data transmission interface will switch to output state to complete the read operation.

[0094] SPI slave chip implementation:

[0095] After power-on, the SPI slave uses the SIO1 interface to receive data from the SPI master or upstream SPI slave, and also to output read / write data frames to the downstream SPI slave. When a reply data frame needs to be output, the SIO interface states are switched: one (SIO2 interface) is used to receive data from the downstream SPI slave, and the other (SIO1 interface) is used to output a reply data frame to the SPI master or upstream SPI slave. The specific state transitions of the SPI slave are as follows: Figure 10 As shown. The SPI slave device has the following states:

[0096] IDLE: This state indicates idle. It enters this state upon power-on or during data transmission gaps, waiting for subsequent operations. In this state, the SPI slave will continuously receive read / write data frames through the first bidirectional data transmission interface and output read / write data frames to downstream SPI slaves through the second bidirectional data transmission interface.

[0097] RECV_START_CODE: This state is used to receive the start character sent by the SPI master and to start the transmission of read and write data frames. If the start character reception is completed, it will enter RECV_SLAVE_ID_CMD_ADDR_DATA; otherwise, it will continue to receive the start character in this state.

[0098] RECV_SLAVE_ID_CMD_ADDR_DATA: Used to receive the device id, cmd, addr, and data fields. When a device id field matching its own ID is received, the cmd, addr, and data fields are received, and the internal operation of the SPI slave is performed. At the same time, it jumps to RECV_FINISH_CODE. Otherwise, it continues to wait for the next set of intermediate read / write data (i.e., device id, cmd, addr, and data fields) in the read / write data frame until a match is found.

[0099] RECV_FINISH_CODE: This state is used for the SPI slave to receive the end character. After receiving the end character, it enters the SEND_START_CODE state.

[0100] SEND_START_CODE: This state is used for the SPI slave to send the start character. After sending, it enters SEND_SLAVE_ID_ADDR_DATA.

[0101] SEND_SLAVE_ID_ADDR_DATA: This state is used by the SPI slave to send its own device id, addr, and data fields. After sending, it enters the SEND_FINISH_CODE state.

[0102] SEND_FINISH_CODE: This state is used for the SPI slave to send the end character. After sending, it returns to the IDLE state. At this time, the state machine returns to the IDLE state, but it still needs to continue to receive the reply data frames output by the downstream SPI slave and pass them upstream until no start character is received within the set time (for example, the character received within the set time is all 1s and no 0 is received). Only then will the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI slave be switched back to the default state (i.e., SIO1 interface is in the input state and SIO2 interface is in the output state).

Claims

1. An SPI interface communication method, characterized in that, include: The SPI master sends read / write data frames to the first bidirectional data transmission interface of the SPI slave through the bidirectional MIO data transmission interface. The read / write data frame includes a start identifier, intermediate read / write data, and an end identifier. The SPI slave receives the data frame according to the start identifier in the received read / write data frame and ends the data frame reception according to the end identifier in the received read / write data frame. After receiving the read / write data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

2. The SPI interface communication method according to claim 1, characterized in that, The SPI slave sends a reply data frame to the SPI master through the first bidirectional data transmission interface. The reply data frame includes a start identifier, intermediate reply data, and an end identifier. The SPI master receives the data frame according to the start identifier in the received reply data frame and ends the data frame reception according to the end identifier in the received reply data frame. After receiving the reply data frame, the directions of the bidirectional MIO data transmission interface of the SPI master and the first bidirectional data transmission interface of the SPI slave are switched to opposite directions.

3. The SPI interface communication method according to claim 2, characterized in that, The intermediate read / write data includes the device id field, cmd field, addr field, and data field; the intermediate response data includes the device id field, addr field, and data field. In the read / write data frame, the device id field is the ID of the SPI slave; the cmd field is the write or read operation performed on the SPI slave; the addr field is the register address of the SPI slave; when the cmd field is a write operation, the data field is the data written to the register address of the corresponding SPI slave in the addr field; when the cmd field is a read operation, the data field is invalid data. In the response data frame, the device id is the ID of the SPI slave; when responding to a write operation, the addr field and data field are invalid; when responding to a read operation, the addr field is the register address of the SPI slave, and the data field is the data in the register address of the corresponding SPI slave in the addr field.

4. The SPI interface communication method according to any one of claims 2-3, characterized in that, Upon receiving a read / write data frame, the SPI slave outputs the received read / write data frame to the first bidirectional data transmission interface of the adjacent downstream SPI slave through the second bidirectional data transmission interface. After all SPI slave devices have received the read / write data frames, the directions of the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI master and SPI slave devices are switched to opposite directions. The downstream SPI slave sends a reply data frame to the SPI master via the second bidirectional data transmission interface through its upstream SPI slave.

5. The SPI interface communication method according to claim 4, characterized in that, The read / write data frame includes a start character, several sets of intermediate read / write data, and an end character. Each set of intermediate read / write data includes a device id field, a cmd field, an addr field, and a data field. Each set of intermediate read / write data corresponds to an SPI slave device.

6. The SPI interface communication method according to claim 5, characterized in that, The cmd fields in the several sets of intermediate read and write data represent read operations and write operations, respectively.

7. The SPI interface communication method according to claim 3, characterized in that, The SPI host has the following states: IDLE indicates that the device is idle and enters this state immediately upon power-on or during data transmission intervals, waiting for subsequent operations. SEND_START_CODE is the state where the start character is sent. When a read or write operation needs to be initiated, this state is entered to send the start character; after sending, it enters SEND_SLAVE_ID. SEND_SLAVE_ID: This status indicates that the corresponding device id field of the SPI slave is being sent. After the sending is completed, it jumps to SEND_CMD_ADDR_DATA; SEND_CMD_ADDR_DATA is used to send the cmd, addr, and data fields. If it is necessary to send read / write operations for other SPI slaves after sending the read / write operations for this SPI slave, it jumps back to SEND_SLAVE_ID; otherwise, it jumps to SEND_FINISH_CODE to send the end character. SEND_FINISH_CODE indicates the end of transmission; after sending the intermediate read / write data of the read / write data frame, this state is entered to send the end character to complete the transmission of this read / write data frame; after sending the end character, it enters RECV_DATA. RECV_DATA is a state used to receive reply data frames output by the SPI slave and identify the intermediate read / write data between the start and end characters in the reply data frame. If the start character is not received within the set first time period, it jumps to WAIT_FINISH_RECV. In the WAIT_FINISH_RECV state, the system will continue to check whether the start character output by the SPI slave has not been received for an extended period. If the start character is received within the set second time period, the system will jump back to RECV_DATA; otherwise, it will return to the IDLE state after the set second time period. The bidirectional MIO data transmission interface will switch to the output state to complete the read operation.

8. The SPI interface communication method according to claim 1, characterized in that, The SPI slave device has the following states: IDLE indicates idle state. It enters this state when the device is powered on or during a data transmission gap, waiting for subsequent operations. In this state, the SPI slave continuously receives read and write data frames through the first bidirectional data transmission interface and outputs read and write data frames to downstream SPI slaves through the second bidirectional data transmission interface. RECV_START_CODE is a state used to receive the start character from the SPI master and to begin the transmission of read and write data frames. If the start character reception is complete, it will enter RECV_SLAVE_ID_CMD_ADDR_DATA; otherwise, it will remain in this state to receive the start character. RECV_SLAVE_ID_CMD_ADDR_DATA is used to receive the device id field, cmd field, addr field, and data field. When a device id field matching its own ID is received, the cmd field, addr field, and data field are received, and the internal operation of the SPI slave is performed. At the same time, it jumps to RECV_FINISH_CODE. Otherwise, it continues to wait for the next set of intermediate read / write data in the read / write data frame until a match is found. RECV_FINISH_CODE is the state used for the SPI slave to receive the end character. Once the reception is complete, it enters the SEND_START_CODE state. SEND_START_CODE is the state used by the SPI slave to send the start character. After sending, it enters SEND_SLAVE_ID_ADDR_DATA. SEND_SLAVE_ID_ADDR_DATA is the state used by the SPI slave to send its own device id, addr and data fields. After sending, it enters the SEND_FINISH_CODE state. The SEND_FINISH_CODE state is used for the SPI slave to send the end character. After sending, it returns to the IDLE state. At this time, it still needs to continue to receive the reply data frames output by the downstream SPI slave and transmit them upstream until no start character is received within the set time. Only then will the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI slave be switched back to the default state.

9. An SPI master, characterized in that, It includes an SCLK clock signal interface and a bidirectional MIO data transmission interface. The bidirectional MIO data transmission interface is used to send read and write data frames to the first bidirectional data transmission interface of the SPI slave and to receive reply data frames from the first bidirectional data transmission interface of the SPI slave. After all the SPI slave devices have received the read / write data frames, the direction of the bidirectional MIO data transmission interface of the SPI master device is switched to the opposite direction.

10. An SPI slave device, characterized in that, It includes an SCLK clock signal interface, a first bidirectional data transmission interface, and a second bidirectional data transmission interface. The first bidirectional data transmission interface is used to receive read / write data frames from the bidirectional MIO data transmission interface of the SPI master and send reply data frames to the bidirectional MIO data transmission interface of the SPI master. The second bidirectional data transmission interface is used to output the received read / write data frames to the first bidirectional data transmission interface of the adjacent downstream SPI slave and to receive reply data frames from the first bidirectional data transmission interface of the adjacent downstream SPI slave. After all SPI slave devices have received the read / write data frames, the directions of the first bidirectional data transmission interface and the second bidirectional data transmission interface of the SPI slave devices are switched to opposite directions.

11. An SPI interface communication system, characterized in that, It includes an SPI master as described in claim 9 and an SPI slave as described in claim 10; The SCLK clock signal interface of the SPI master is connected to the SCLK clock signal interface of the SPI slave to provide a clock signal for the SPI slave. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface of the SPI slave, and the second bidirectional data transmission interface of the SPI slave is left floating.

12. An SPI interface communication system, characterized in that, It includes an SPI master as described in claim 9 and a plurality of SPI slaves as described in claim 10; The SCLK clock signal interface of the SPI master is connected to the SCLK clock signal interface of each SPI slave, providing a unified clock signal for each SPI slave. The bidirectional MIO data transmission interface of the SPI master is bidirectionally connected to the first bidirectional data transmission interface of the first SPI slave, the second bidirectional data transmission interface of the first SPI slave is bidirectionally connected to the first bidirectional data transmission interface of the second SPI slave, the second bidirectional data transmission interface of the second SPI slave is bidirectionally connected to the first bidirectional data transmission interface of the third SPI slave, and so on, with the second bidirectional data transmission interface of the last SPI slave left floating.

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