Artificial intelligence chip and operating method thereof

Abstract

The present application relates to an artificial intelligence chip and an operating method thereof. Based on the present application, a pre-driver circuit in each transmitter channel circuit of a multi-channel transmitter of the chip can include an equalization logic operation part that can continuously generate at least one set of control codes for adapting at least one state in which an equalization function is activated, and the pre-driver circuit in each transmitter channel circuit can suppress logic operation power consumption of the equalization logic operation part due to level flipping by maintaining input clamping to the equalization logic operation part during a period in which the equalization function is turned off. Thus, since the pre-driver circuit in each transmitter channel circuit can suppress such logic operation power consumption during a period in which the equalization function is turned off, it can be helpful to reduce circuit power consumption of the multi-channel transmitter.

Description

Technical Field

[0001] This application relates to the field of AI (Artificial Intelligence) chips, and in particular to an AI chip and a method of operating the AI ​​chip. Background Technology

[0002] AI chips can achieve data transmission based on a multi-channel bus, and the multiple physical channels (lanes) of the multi-channel bus can transmit channel data independently of each other. Accordingly, the AI ​​chip may include a multi-channel transmitter, and the multi-channel transmitter of the AI ​​chip may include multiple transmitter channel circuits corresponding to the multiple physical channels of the multi-channel bus. Therefore, the circuit power consumption of the multi-channel transmitter of the AI ​​chip is directly proportional to the number of physical channels of the multi-channel bus, resulting in a relatively high overall circuit power consumption for the AI ​​chip.

[0003] Therefore, how to reduce the circuit power consumption of multi-channel transmitters in AI chips has become a technical problem that needs to be solved in related technologies.

[0004] It is understood that the content of the "Background Art" section is intended to aid in understanding this disclosure. Some (or all) of the content disclosed in the "Background Art" section may not be known to those skilled in the art. The content disclosed in the "Background Art" section does not imply that such content was known to those skilled in the art prior to this disclosure. Summary of the Invention

[0005] Embodiments of this application provide an AI chip and an operating method for the AI ​​chip, which helps to reduce the circuit power consumption of a multi-channel transmitter.

[0006] In one embodiment of this application, an AI chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes multiple transmitter lane circuits corresponding to multiple physical channels of the multi-channel bus, and each lane transmitter includes:

[0007] A serializer is configured to serialize parallel input channel data intended for transmission through the corresponding physical channel into an output serializer.

[0008] The pre-driver circuit is configured to concurrently generate multiple sets of control codes based on the channel data serialized from the serializer, for adapting to various states where the equalization function is selectively activated or deactivated.

[0009] The final driver is configured to serially transmit the level signal corresponding to the channel data on the physical channel in the multi-channel bus based on the valid control code specified by the mode selection signal in the multiple sets of control codes.

[0010] The pre-drive circuit includes a first logic circuit, a second logic circuit, and a third logic circuit. The first logic circuit is configured to drive the second logic circuit to generate the multiple sets of control codes based on the channel data serialized from the serializer. The second logic circuit includes an equalization logic operation section, and the multiple sets of control codes include at least one set of control codes for adapting to at least one state in which the equalization function is activated. The at least one set of control codes is generated by the equalization logic operation section. The third logic circuit is configured to maintain an input clamp on the equalization logic operation section during the period when the equalization function is disabled, or to deactivate the input clamp on the equalization logic operation section during the period when the equalization function is activated, based on the mode selection signal.

[0011] In some instances, the third logic circuit may optionally be configured to: based on the mode selection signal, continuously clamp the signal level input from the first logic circuit to the equalization logic operation section at a preset logic level during the period when the equalization function is disabled, or stop clamping the signal level during the period when the equalization function is activated.

[0012] Optionally, in some instances, the pre-drive circuit further includes an AND gate located between the first logic circuit and the equalization logic operation section, the output of the AND gate being connected to the equalization logic operation section, the first input of the AND gate being connected to the first logic circuit, and the second input of the AND gate being controlled by the third logic circuit; wherein, the preset logic level is 0, and the third logic circuit is specifically configured to: control the second input of the AND gate based on the mode selection signal, continuously setting the second input of the AND gate to 0 during the period when the equalization function is disabled, or setting the second input of the AND gate to 1 during the period when the equalization function is activated.

[0013] In some instances, optionally, the first logic circuit is specifically configured to input the channel data and equalization data generated based on the channel data to the second logic circuit; wherein the signals input by the first logic circuit to the equalization logic operation section include the channel data and the equalization data.

[0014] In some instances, optionally, the serializer is specifically configured to serialize and output the odd and even bits of the parallel-input channel data, respectively; the channel data input from the first logic circuit to the second logic circuit includes the odd and even bits input to the second logic circuit, respectively; the equalization data input from the first logic circuit to the second logic circuit includes odd-bit equalization data and even-bit equalization data input to the second logic circuit, wherein the odd-bit equalization data is generated based on the odd bits, and the even-bit equalization data is generated based on the even bits.

[0015] In some instances, optionally, the multiple sets of control codes include: a first set of control codes adapted to a state where both the impedance calibration function and the equalization function are turned off; a second set of control codes adapted to a state where the impedance calibration function is turned off and the equalization function is activated; a third set of control codes adapted to a state where the impedance calibration function is activated and the equalization function is turned off; and a fourth set of control codes adapted to a state where both the impedance calibration function and the equalization function are activated; wherein, the equalization logic operation part includes the portion of the second logic circuit used to generate the second set of control codes and the fourth set of control codes.

[0016] In some instances, the second logic circuit may optionally include a first logic operation section for generating the first set of control codes, a second logic operation section for generating the second set of control codes, a third logic operation section for generating the third set of control codes, and a fourth logic operation section for generating the fourth set of control codes; wherein the equalization logic operation section includes the second logic operation section and the fourth logic operation section.

[0017] Optionally, in some instances, the final-stage driver circuit includes a first transistor group and a second transistor group, wherein the first transistor group is located between the power supply and the output terminal of the physical channel corresponding to the connection, and the second transistor group is located between ground and the output terminal of the physical channel corresponding to the connection; the pre-drive circuit further includes a first transistor group driver array configured to control the first transistor group based on the valid control code, and a second transistor group driver array configured to control the second transistor group based on the valid control code; the final-stage driver circuit is specifically configured to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus through the coordinated operation of the first transistor group and the second transistor group under the control of the first transistor group driver array and the second transistor group driver array, respectively; wherein each of the first logic operation section, the second logic operation section, the third logic operation section, and the fourth logic operation section includes a first transistor group logic operation section and a second transistor group logic operation section for generating the first transistor group control code.

[0018] In some instances, optionally, the first transistor group driver array and the second transistor group driver array are further configured to: determine the valid control code among the multiple sets of control codes generated by the second logic circuit based on the input mode selection signal; wherein, the third logic circuit is specifically configured to, based on the mode selection signal input to the first transistor group driver array and the second transistor group driver array, maintain an input clamp on the equalization logic operation section during the period when the equalization function is disabled, or deactivate the input clamp on the equalization logic operation section during the period when the equalization function is activated.

[0019] In some instances, optionally, the first transistor group includes a plurality of first switching transistors connected in parallel between the power supply and the output terminal of the physical channel corresponding to the connection; the second transistor group includes a plurality of second switching transistors connected in parallel between the ground and the output terminal of the physical channel corresponding to the connection.

[0020] In some instances, optionally, each of the multiple sets of control codes includes a first transistor group control code for controlling the first transistor group drive array and a second transistor group control code for controlling the second transistor group drive array; the first transistor group drive array is specifically configured to control the first transistor group based on the first transistor group control code in the valid control code; the second transistor group drive array is specifically configured to control the second transistor group based on the second transistor group control code in the valid control code.

[0021] In another embodiment of this application, an operation method for an AI chip is provided. The AI ​​chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus. Each channel transmitter includes a serializer, a pre-driver circuit, and a final-stage driver circuit. The serializer is configured to serialize and output channel data input in parallel for transmission via the corresponding physical channel. The pre-driver circuit is configured to concurrently generate multiple sets of control codes based on the channel data serialized and output from the serializer, for adapting to multiple states where equalization is selectively activated or deactivated. The final-stage driver circuit is configured to serially transmit a level signal corresponding to the channel data via the corresponding physical channel in the multi-channel bus based on a valid control code specified by a mode selection signal in the multiple sets of control codes. The operation method includes:

[0022] The first logic circuit of the pre-drive circuit drives the second logic circuit of the pre-drive circuit to generate the multiple sets of control codes based on the channel data serialized from the serializer; wherein, the multiple sets of control codes include at least one set of control codes for adapting to at least one state in which the equalization function is activated, and the at least one set of control codes is generated by the equalization logic operation part of the second logic circuit;

[0023] The third logic circuit of the pre-drive circuit maintains an input clamp on the equalization logic operation section during the period when the equalization function is turned off, or removes the input clamp on the equalization logic operation section during the period when the equalization function is activated, based on the mode selection signal.

[0024] In some instances, optionally, the third logic circuit of the pre-drive circuit, based on the mode selection signal, maintains input clamping on the equalization logic operation section during the period when the equalization function is disabled, or deactivates input clamping on the equalization logic operation section during the period when the equalization function is activated, including: the third logic circuit of the pre-drive circuit, based on the mode selection signal, continuously clamps the signal level input from the first logic circuit to the equalization logic operation section at a preset logic level during the period when the equalization function is disabled, or stops clamping the signal level during the period when the equalization function is activated.

[0025] Optionally, in some instances, the pre-driver circuit further includes an AND gate located between the first logic circuit and the equalization logic operation section, the output of the AND gate being connected to the equalization logic operation section, the first input of the AND gate being connected to the first logic circuit, the second input of the AND gate being controlled by the third logic circuit, and the preset logic level being 0; the third logic circuit of the pre-driver circuit, based on the mode selection signal, continuously clamps the signal level input from the first logic circuit to the equalization logic operation section at the preset logic level during the period when the equalization function is disabled, or stops clamping the signal level during the period when the equalization function is activated, including: controlling the second input of the AND gate based on the mode selection signal to continuously set the second input of the AND gate to 0 during the period when the equalization function is disabled, or to set the second input of the AND gate to 1 during the period when the equalization function is activated.

[0026] Based on embodiments of this application, the pre-driver circuit in each transmitter channel circuit of a multi-channel transmitter in an AI chip may include an equalization logic operation section. This equalization logic operation section can continuously generate at least one set of control codes to adapt to at least one state where the eq (equalization) function is activated. Furthermore, the pre-driver circuit in each transmitter channel circuit can suppress the logic operation power consumption caused by level switching in the equalization logic operation section by maintaining an input clamp on the equalization logic operation section during the period when the eq function is disabled. Therefore, since the pre-driver circuit in each transmitter channel circuit can suppress such logic operation power consumption during the period when the eq function is disabled, it can help reduce the circuit power consumption of the multi-channel transmitter. Attached Figure Description

[0027] The following figures are for illustrative purposes only and do not limit the scope of this application:

[0028] Figure 1 This is an exemplary structural diagram of the AI ​​chip in the embodiments of this application;

[0029] Figure 2 This is a schematic diagram of the optimized structure of the multi-channel transmitter of the AI ​​chip in the embodiments of this application;

[0030] Figure 3 This is a schematic diagram of an example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application;

[0031] Figure 4 This is an exemplary structural diagram of the pre-drive circuit and the final drive circuit of the multi-channel transmitter of the AI ​​chip in the embodiments of this application;

[0032] Figure 5 This is a schematic diagram of an example structure of the front-end drive circuit of the multi-channel transmitter of the AI ​​chip in this application embodiment;

[0033] Figure 6 This is a schematic diagram of an improved structure of the serializer for the multi-channel transmitter of the AI ​​chip in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of an improved example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application.

[0035] Figure 8 This is a schematic diagram of an improved example of the front-end drive circuit of the multi-channel transmitter of the AI ​​chip in this application embodiment;

[0036] Figure 9 This is an exemplary flowchart illustrating the operation method of the AI ​​chip in the embodiments of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0038] Figure 1 This is an exemplary structural diagram of a multi-channel transmitter for an AI chip according to an embodiment of this application. Please refer to... Figure 1 In the embodiments of this application, the multi-channel transmitter of the AI ​​chip can be used to transmit data through a multi-channel bus. The multi-channel transmitter used to transmit data through the multi-channel bus may include a transmitter common circuit 10 and multiple transmitter channel circuits 20 corresponding to multiple physical channels of the multi-channel bus.

[0039] Exemplary examples, in embodiments of this application, include, as Figure 1 The AI ​​chip in the multi-channel transmitter shown can be any integrated circuit chip suitable for artificial intelligence, such as GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Units).

[0040] Exemplary examples, in embodiments of this application, such as Figure 1The multi-channel transmitter shown can utilize buses such as PCIE (Peripheral Component Interconnect Express), UCIE (Universal Chiplet Interconnect Express), and HBM (High Bandwidth Memory), which include multiple physical channels. Furthermore, data transmission via this multi-channel bus can involve either off-chip or on-chip data transfer. For example, the PCIE bus in the multi-channel bus can be used to implement off-chip data transfer between the AI ​​chip and other integrated circuit chips. As another example, for an AI chip packaged with at least two dies using Chiplet technology, the UCIE bus in the multi-channel bus can be used to implement on-chip data transfer between different dies, i.e., on-chip D2D (Die to Die) data transfer. Yet another example is the HBM bus in the multi-channel bus, which can be used to implement on-chip data transfer (or intra-die data transfer) between the SoC (System on Chip) within the AI ​​chip (or die) and other on-chip structures.

[0041] As an example, in embodiments of this application, the transmitter common circuit 10 can be used to provide a clock signal. For instance, the transmitter common circuit 10 may include a clock source for generating the clock signal.

[0042] For example, in an embodiment of this application, each transmitter channel circuit 20 may include a serializer 210, a pre-drive circuit 220, and a final drive circuit 230.

[0043] For example, in an embodiment of this application, the serializer 210 of each transmitter channel circuit 20 is configured to serialize the channel data input in parallel for transmission through the physical channel corresponding to the transmitter channel circuit 20, and the clock signal transmitted to the serializer 210 is used to control the frequency of the serialized output channel data.

[0044] For example, in an embodiment of this application, the pre-drive circuit 220 of each transmitter channel circuit 20 can be configured to generate a control code based on the channel data serialized and output by the serializer 210 of the transmitter channel circuit 20, and control the final-stage drive circuit 230 of the transmitter channel circuit 20 to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus based on the generated control code. That is, the final-stage drive circuit 230 of each transmitter channel circuit 20 can be configured to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus based on the control code generated by the pre-drive circuit 220 of the transmitter channel circuit 20.

[0045] For example, in embodiments of this application, the control code generated by the pre-drive circuit 220 of each transmitter channel circuit 20 may optionally implement at least one of the rcal (impedance calibration) function and the eq function. The rcal function is used to maintain the output impedance of the final stage drive circuit 230 at a target impedance (e.g., 25Ω), and the eq function is used to ensure that the transition edge of the level signal generated by the final stage drive circuit 230 in the corresponding physical channel has a peak, the peak of which is used to pre-compensate for the high-frequency component loss of the level signal in the physical channel.

[0046] Figure 2 This is a schematic diagram of the optimized structure of the multi-channel transmitter of the AI ​​chip in this embodiment. Please refer to... Figure 2 In the embodiments of this application, the serializer 210 of each transmitter channel circuit 20 may include a shift register 215. The channel data of the physical channel corresponding to the transmitter channel circuit 20 may be loaded into the shift register 215 of the serializer 210 of the transmitter channel circuit 20. The loaded channel data may be serialized and output from the serializer 210 of the transmitter channel circuit 20 by shifting the shift register 215 of the serializer 210 of the transmitter channel circuit 20.

[0047] For example, in an embodiment of this application, the loading of channel data into shift register 215 and the shifting of channel data after it has been loaded into shift register 215 can be controlled by a loading signal.

[0048] Figure 3 This is a schematic diagram illustrating an example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application. Please refer to... Figure 3 In embodiments of this application, the shift register 215 of the serializer 210 of each transmitter channel circuit 20 may include multiple flip-flops (e.g., D flip-flops).

[0049] For example, in an embodiment of this application, multiple flip-flops of the shift register 215 can be cascaded. Specifically, the multiple flip-flops of the shift register 215 can be cascaded by connecting the Q pin of the preceding flip-flop to the D pin of the following flip-flop via a multiplexer switch. In this case, each bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop and each multiplexer switch, and the clock signal can be connected to the CLK (clock) pin of each flip-flop of the shift register 215. Thus, the load signal can control the cascaded state between the multiple flip-flops of the shift register 215 by controlling each multiplexer switch.

[0050] For example, in an embodiment of this application, when the cascading state between multiple flip-flops of the shift register 215 is set to open by a load signal, that is, when the D pins of the flip-flops other than the first flip-flop receive the corresponding bits of the channel data, the parallel input channel data can be loaded into multiple flip-flops in parallel (i.e., the parallel loading of channel data into the shift register 215 is realized).

[0051] For example, in an embodiment of this application, when the cascaded state between multiple flip-flops in the shift register 215 is set to connected by the load signal, that is, when the D pins of the flip-flops other than the first flip-flop are turned on with the Q pins of the preceding flip-flops, the channel data that has been loaded can be serialized and output from the serializer by shifting in the cascaded direction of the multiple flip-flops (that is, shifting the loaded channel data in the shift register 215). Furthermore, the loading of the channel data in the multiple flip-flops and the shifting in the cascaded direction of the multiple flip-flops are achieved by the flipping of the multiple flip-flops based on the clock signal.

[0052] See also Figure 2 In embodiments of this application, the transmitter common circuit 10 of the multi-channel transmitter may include, in addition to a clock source 100 configured to generate a clock signal, a load signal generator 300 configured to generate a load signal based on the clock signal. Furthermore, the serializer 210 of each transmitter channel circuit 20 may not include the load signal generator 300. In this case, embodiments of this application can reduce the circuit area and power consumption of the multi-channel transmitter by reducing the number of load signal generators 300. Since the load signal generator 300 is only provided in the transmitter common circuit 10, rather than in each serializer 210 of the transmitter common circuit 10, it helps to reduce the increased power consumption of the multi-channel transmitter due to the load signal generator.

[0053] For example, in an embodiment of this application, the clock signal provided by the transmitter common circuit 10, after being transmitted to any transmitter channel circuit 20, can pass through the channel clock path 200 of that transmitter channel circuit 20 (not in...). Figure 1 (As shown in the diagram) the serializer 210 reaches the transmitter channel circuit 20. The channel clock path 200 can be a local transmission network of the transmitter channel circuit 20. Clock signals in each transmitter channel circuit 20 may experience channel transmission delays due to transmission via the channel clock path 200. Furthermore, embodiments of this application do not impose unnecessary limitations on the channel clock path 200. Accordingly, in embodiments of this application, the transmitter common circuit 10 may also include a delay compensation path 350.

[0054] For example, in an embodiment of this application, the delay compensation path 350 of the transmitter common circuit 10 is not a network necessary for signal transmission in the transmitter common circuit 10. Therefore, the delay compensation path 350 can be regarded as a redundant or dummy clock path set up to create delay. Furthermore, the transmission delay of the clock signal in the transmitter common circuit 10 due to transmission through the delay compensation path 350 can trigger delay compensation of the load signal generated based on the clock signal. Since this delay compensation matches the channel transmission delay of the clock signal in each transmitter channel circuit 20 caused by the channel clock path 200, timing errors (such as timing errors affecting the flip-flop toggling of the shift register 215 of the serializer 210) can be avoided when the load signal is used in multiple transmitter channel circuits 20.

[0055] Exemplarily, in an embodiment of this application, the delay compensation path 350 of the transmitter common circuit 10 may be located between the clock source 100 and the load signal generator 300. Specifically, the delay compensation path 350 may be configured to provide delay compensation for the clock signal transmitted from the clock source 100 to the load signal generator 300 in the transmitter common circuit 10, so that the load signal generated by the load signal generator 300 based on the clock signal has the same delay compensation. In this case, the clock signal arriving at the serializer 210 via the channel clock path 200 in each transmitter channel circuit 20 is bypassed by the delay compensation path 350 in the transmitter common circuit 10.

[0056] For example, in an embodiment of this application, the delay compensation for the loading signal generated by the delay compensation path 350 can be configured to: match the timing relationship between the loading signal and the clock signal transmitted to each transmitter channel circuit with the flip-flop's toggle association parameter (the toggle association parameter is a hardware parameter of the flip-flop), and the toggle association parameter includes the flip-flop's setup time (T). suThreshold and Hold Time (T) hd Threshold. The configuration of delay compensation can be achieved by setting the topology of delay compensation path 350.

[0057] For example, in an embodiment of this application, the delay compensation generated by the loading signal using the delay compensation path 350 can be specifically configured such that: the actual setup time of the trigger for the channel data is greater than the setup time threshold of the trigger, and the actual hold time of the trigger for the channel data is greater than the hold time threshold of the trigger.

[0058] For example, in an embodiment of this application, the transmitter common circuit 10 may further include a drive buffer 400. The drive buffer 400 of the transmitter common circuit 10 may be configured to boost the signal load of the clock signal and the signal load of the load signal with delay compensation to a multi-channel load level matching the multiple transmitter channel circuits 20, and then split them into single-channel load levels for transmission to the multiple transmitter channel circuits 20. Thus, the load signal generated by the load signal generator 300 in the transmitter common circuit 10 can be driven and buffered to a multi-channel load level matching the multiple transmitter channel circuits 20, just like the clock signal, and then split into single-channel load levels for transmission to the multiple transmitter channel circuits 20, thereby preventing waveform abnormalities in the load signals used in the multiple transmitter channel circuits 20 due to excessively low signal load.

[0059] For example, in an embodiment of this application, the drive buffer 400 of the transmitter common circuit 10 may include a clock drive buffer 410 and a signal drive buffer 430. The clock drive buffer 410 may be configured to enable the signal load of the clock signal to reach a multiple load level matching the multiple transmitter channel circuits 20; the signal drive buffer 430 may be configured to enable the signal load of the loaded signal to reach a multiple load level matching the multiple transmitter channel circuits.

[0060] For example, in an embodiment of this application, the clock signal load signal generated by the clock source 100 has a single-channel load level signal load, and the clock drive buffer 410 can be configured to increase the signal load of the clock signal generated by the clock source 100 from a single-channel load level to a multi-channel load level matching multiple transmitter channel circuits 20.

[0061] For example, in an embodiment of this application, the load signal generator 300 generates a load signal based on a signal load with a single-channel load level and a clock signal with delay compensation, and also has a signal load with a single-channel load level and delay compensation for the clock signal. Furthermore, the signal drive buffer 430 can be specifically configured to increase the signal load of the load signal generated by the load signal generator 300 from a single-channel load level to a multi-channel load level that matches multiple transmitter channel circuits 20.

[0062] For example, in embodiments of this application, at least one of the clock drive buffer 410 and the signal drive buffer 430 may include a multi-stage inverter with progressively increasing dimensions. For instance, the dimensions of the multi-stage inverter increase by an equal multiple at each stage.

[0063] As can be seen above, the embodiments of this application can avoid the abnormality of the serialized output quality of multiple transmitter channel circuits 20 due to the reduction of the load signal generator 300 by using the delay compensation path 350 in the transmitter common circuit 10 to compensate for the delay of the load signal and / or using the drive buffer 400 (e.g., signal drive buffer 430) in the transmitter common circuit 10 to boost the load of the load signal.

[0064] For example, in an embodiment of this application, the serializer 210 of each transmitter channel circuit 20 may further include a clock shaping buffer 211 and a signal shaping buffer 213. The clock shaping buffer 211 may be configured to allow the clock signal transmitted to the serializer 210 to be subjected to single-path load level beamforming correction before reaching the shift register 215. The signal shaping buffer 213 may be configured to allow the load signal transmitted to the serializer 210 to be subjected to single-path load level beamforming correction before reaching the shift register 215.

[0065] Figure 4 This is an exemplary structural diagram of the pre-amplifier and final-stage amplifier of the multi-channel transmitter in the AI ​​chip of this application embodiment. Please refer to... Figure 4 In the embodiments of the application, the pre-drive circuit 220 of each transmitter channel circuit 20 may include a first logic circuit 221, a second logic circuit 222, a first transistor group drive array 223a and a second transistor group drive array 223b, and the final drive circuit 230 of each transmitter channel circuit 20 may include a first transistor group 230a controlled by the first transistor group drive array 223a and a second transistor group 230b controlled by the second transistor group drive array 223b.

[0066] Exemplarily, in an embodiment of this application, the first transistor group 230a of the final stage drive circuit 230 of each transmitter channel circuit 20 may be located between the power supply VSS and the output terminal of the corresponding physical channel. Specifically, the first transistor group 230a of the final stage drive circuit 230 of each transmitter channel circuit 20 may include multiple first switching transistors connected in parallel between the power supply VSS and the output terminal of the corresponding physical channel. That is, the first transistor group 230a may include multiple parallel branches (legs), and when at least one first switching transistor in the first transistor group 230a is turned on, the final stage drive circuit 230 can generate a high-level signal of "1" in the corresponding ventilation channel data in the corresponding physical channel. For example, the first switching transistor may be a PMOS (P-channel Metal-Oxide-Semiconductor).

[0067] For example, in an embodiment of this application, the second transistor group 230b of the final stage drive circuit 230 of each transmitter channel circuit 20 may be located between ground GND and the output terminal connected to the corresponding physical channel. Specifically, the second transistor group 230b of the final stage drive circuit 230 of each transmitter channel circuit 20 may include multiple second switching transistors connected in parallel between ground GND and the output terminal connected to the corresponding physical channel. That is, the second transistor group 230b may also include multiple parallel branches, and when at least one of the second switching transistors in the second transistor group 230b is turned on, the final stage drive circuit 230 may generate a low-level signal of "0" in the corresponding ventilation channel data in the corresponding physical channel. For example, the second switching transistor may be an NMOS (N-channel Metal-Oxide-Semiconductor).

[0068] For example, in an embodiment of this application, the rcal function implemented by the pre-drive circuit 220 of each transmitter channel circuit 20 can maintain the output impedance of the final stage drive circuit 230 at a target impedance (e.g., 25Ω) by adjusting the number of first switching transistors turned on in the first transistor group 230a or the number of second switching transistors turned on in the second transistor group 230b.

[0069] For example, in an embodiment of this application, the eq function implemented by the pre-drive circuit 220 can enable the first switch in the first transistor group 230a and the second switch in the second transistor group 230b to be turned on simultaneously, and adjust the ratio of the number of the first switch and the second switch to be turned on, so that the transition edge of the level signal generated by the final stage drive circuit 230 in the corresponding physical channel has a peak for pre-compensating the high-frequency component loss peak of the level signal in the physical channel.

[0070] For example, in an embodiment of this application, the first logic circuit 221 of the pre-drive circuit 220 of each transmitter channel circuit 20 may be configured to drive the second logic circuit 222 to generate (e.g., concurrently generate) multiple sets of control codes for adapting to multiple states where the eq function is selectively activated or deactivated, based on the channel data serialized out from the serializer 210.

[0071] For example, in the embodiments of this application, the multiple sets of control codes generated by the second logic circuit 222 of the pre-driver circuit 220 of each transmitter channel circuit 20 may include: a first set of control codes for adapting to a state where both RCAL and EQ functions are disabled; a second set of control codes for adapting to a state where RCAL is disabled and EQ is activated; a third set of control codes for adapting to a state where RCAL is activated and EQ is disabled; and a fourth set of control codes for adapting to a state where both RCAL and EQ functions are activated. The algorithm used by the second logic circuit 222 of the pre-driver circuit 220 to generate the four sets of control codes can refer to related technologies, and the embodiments of this application do not limit this.

[0072] For example, in the embodiments of this application, each of the multiple sets of control codes generated by the second logic circuit 222 of the pre-drive circuit 220 of each transmitter channel circuit 20 (e.g., each of the first set of control codes, the second set of control codes, the third set of control codes, and the fourth set of control codes) can include a first transistor group control code for controlling the first transistor group 230a using the first transistor group drive array 233a, and a second transistor group control code for controlling the second transistor group 230b using the second transistor group drive array 233b.

[0073] For example, in an embodiment of this application, the first transistor group drive array 223a and the second transistor group drive array 223b of the pre-drive circuit 220 of each transmitter channel circuit 20 can be configured to: determine the valid control code (e.g., any one of the first control code, the second control code, the third control code, and the fourth control code) among multiple control codes generated by the second logic circuit 222 based on the input mode selection signal.

[0074] For example, in the embodiments of this application, the first transistor group drive array 233a of the pre-drive circuit 220 of each transmitter channel circuit 20 can also be configured to control the first transistor group 230a based on the first transistor group control code in the valid control codes (e.g., any one of the first set of control codes, the second set of control codes, the third set of control codes, and the fourth set of control codes). Furthermore, the second transistor group drive array 233b of the pre-drive circuit 220 of each transmitter channel circuit 20 can also be configured to control the second transistor group 230b based on the second transistor group control code in the valid control codes (e.g., any one of the first set of control codes, the second set of control codes, the third set of control codes, and the fourth set of control codes).

[0075] For example, in the embodiments of this application, the final-stage driving circuit of each transmitter channel circuit 20 can be specifically configured to, through the coordinated operation of the first transistor group 230a and the second transistor group 230b under the control of the first transistor group driving array 233a and the second transistor group driving array 233b respectively, serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus. Thus, the final-stage driving circuit 230 of each transmitter channel circuit 20 can, based on the valid control code specified by the mode selection signal among the multiple sets of control codes concurrently generated by the pre-driving circuit 220 of the transmitter channel circuit 20 (e.g., any one of the first set of control codes, the second set of control codes, the third set of control codes, and the fourth set of control codes), serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus.

[0076] For example, in an embodiment of this application, the second logic circuit 222 of the pre-drive circuit 220 of each transmitter channel circuit 20 may include an equalization logic operation section (such as... Figure 4 As shown in the shaded portion of the second logic circuit 222 (as indicated by the second logic circuit 222 in the diagram), multiple sets of control codes include at least one set of control codes (e.g., at least one set of control codes that can be referred to as eq function activation control codes) for adapting to at least one state where the eq function is activated. The at least one set of control codes that can be referred to as eq function activation control codes may include the second and fourth sets of control codes mentioned above, and the at least one set of control codes that can be referred to as eq function activation control codes may be generated by the equalization logic operation section. That is, the equalization logic operation section of the second logic circuit 222 may include the portion of the second logic circuit 222 used to generate the second and fourth sets of control codes.

[0077] For example, in an embodiment of this application, the second logic circuit 222 of the pre-amplifier driving circuit 220 of each transmitter channel circuit 20 may include a first logic operation section for generating a first set of control codes, a second logic operation section for generating a second set of control codes, a third logic operation section for generating a third set of control codes, and a fourth logic operation section for generating a fourth set of control codes. In this case, the equalization logic operation section of the second logic circuit 222 may include the second logic operation section and the fourth logic operation section. The second logic operation section and the fourth logic operation section may be as follows: Figure 4 The second logic circuit 222 in the diagram is shown in two pairs of shaded portions corresponding to the first transistor drive array 223a and the second transistor drive array 223b, respectively. Figure 4 Each pair of shaded portions shown can represent two parts of the second or fourth logic operation section used to generate the first transistor group control code and the second transistor group control code, respectively. This is because each of the first, second, third, and fourth logic operation sections includes a first transistor group logic operation section and a second transistor group logic operation section used to generate the first transistor group control code.

[0078] For example, in embodiments of this application, the probability of the eq function being activated in certain application scenarios may be lower than the probability of the rcal function being activated. In this case, relative to other logic operation parts of the second logic circuit 222 (such as... Figure 4 The control codes (e.g., the first and third sets of control codes) generated by the second logic circuit 222 (shown in the unshaded portion) and the control codes (e.g., the second and fourth sets of control codes) generated by the equalization logic operation section of the second logic circuit 222 are used less frequently. Therefore, if the equalization logic operation section of the second logic circuit 222 still performs the level switching required for logic operations to generate control codes (e.g., the second and fourth sets of control codes) during a period when the eq function is permanently disabled, unnecessary power consumption will occur. To avoid such unnecessary power consumption, in embodiments of this application, the pre-drive circuit 220 of each transmitter channel circuit 20 may further include a third logic circuit 225.

[0079] For example, in an embodiment of this application, the third logic circuit 225 of the pre-drive circuit 220 of each transmitter channel circuit 20 can be configured to: maintain an input clamp on the equalization logic operation portion of the second logic circuit 222 during the period when the eq function is off, or deactivate the input clamp on the equalization logic operation portion of the second logic circuit 222 during the period when the eq function is activated, based on a mode selection signal (e.g., a mode selection signal input to the first transistor group drive array 233a and the second transistor group drive array 233b).

[0080] For example, in an embodiment of this application, the third logic circuit 225 of the pre-drive circuit 220 of each transmitter channel circuit 20 can be specifically configured to: based on the mode selection signal (e.g., the mode selection signal input to the first transistor group drive array 233a and the second transistor group drive array 233b), continuously clamp the signal level of the equalization logic operation section of the first logic circuit 221 to a preset logic level (e.g., low level "0") during the period when the eq function is off, or stop clamping the signal level of the equalization logic operation section of the first logic circuit 221 to the second logic circuit 222 during the period when the eq function is activated.

[0081] Figure 5 This is a schematic diagram illustrating an example structure of the front-end driver circuit of the multi-channel transmitter of the AI ​​chip in this embodiment. Please refer to... Figure 5 In the embodiments of this application, the pre-drive circuit 220 of each transmitter channel circuit 20 may further include an AND gate located between the equalization logic operation section of the first logic circuit 221 and the second logic circuit 222. The output terminal of each AND gate may be connected to the equalization logic operation section of the second logic circuit 222, the first input terminal of each AND gate may be connected to the first logic circuit 221, and the second input terminal of each AND gate is controlled by the third logic circuit 225.

[0082] For example, in an embodiment of this application, the third logic circuit 225 of the pre-drive circuit 220 of each transmitter channel circuit 20 can be specifically configured to control the second input of each AND gate based on the mode selection signal (e.g., the mode selection signal input to the first transistor drive array 233a and the second transistor drive array 233b). Specifically, the third logic circuit 225 can continuously set the second input of each AND gate to 0 (i.e., a low level "0" as a preset logic level) during the period when the eq function is disabled, so that the signal level of the equalization logic operation section of the first logic circuit 221 input to the second logic circuit 222 is continuously clamped at the preset logic level (e.g., low level "0") through a logical AND operation with 0 during the period when the eq function is disabled, thereby preventing the signal level of the equalization logic operation section of the second logic circuit 222 from level flipping during the period when the eq function is disabled; or, the third logic circuit 225 can set the second input of each AND gate to 1 during the period when the eq function is activated, so that the signal level of the equalization logic operation section of the first logic circuit 221 input to the second logic circuit 222 maintains its original level through a logical AND operation with 1 during the period when the eq function is activated.

[0083] Based on embodiments of this application, the pre-driver circuit 220 in each transmitter channel circuit 20 of the multi-channel transmitter of the AI ​​chip may include an equalization logic operation section. This equalization logic operation section can continuously generate at least one set of control codes to adapt to at least one state where the eq function is activated. Furthermore, the pre-driver circuit in each transmitter channel circuit 20 can suppress the logic operation power consumption caused by level switching in the equalization logic operation section by maintaining an input clamp on the equalization logic operation section during the period when the eq function is disabled. Therefore, since the pre-driver circuit 220 in each transmitter channel circuit 20 can suppress such logic operation power consumption during the period when the eq function is disabled, it can help reduce the circuit power consumption of the multi-channel transmitter.

[0084] Moreover, from Figure 5 It can also be seen that the first logic circuit 221 of the pre-drive circuit 220 of each transmitter channel circuit 20 can be specifically configured to input the channel data serialized by the serializer 210 and the equalization data generated based on the channel data into the second logic circuit 222. The signals input from the first logic circuit 221 to the equalization logic operation section of the second logic circuit 222 include the channel data and the equalization data. Furthermore, the signals input from the first logic circuit 221 to other logic operation sections of the second logic circuit 222 may not include the equalization data. The equalization data can be obtained by inverting the channel data after a one-clock-cycle delay. This application embodiment does not intend to impose unnecessary limitations on the method of generating the equalization data.

[0085] In this case, the logic operations of the equalization logic operation section of the second logic circuit 222 are more complex than those of the other logic operation sections of the second logic circuit 222. Consequently, the power consumption of the equalization logic operation section of the second logic circuit 222 due to level switching is higher than that of the other logic operation sections. Therefore, during the extended period when the eq function, which has a relatively low activation probability, is disabled, maintaining input clamping on the equalization logic operation section to suppress the power consumption of this section due to level switching significantly reduces the circuit power consumption of the multi-channel transmitter.

[0086] Figure 6 This is a schematic diagram of an improved structure of the serializer for the multi-channel transmitter of the AI ​​chip in an embodiment of this application. Please refer to [link / reference]. Figure 6 In the embodiments of this application, the serializer 210 of each transmitter channel circuit 20 can serialize the parallel input channel data and output it in two ways, that is, serialize the odd-numbered bits D_e and the even-numbered bits D_e of the channel data respectively.

[0087] Figure 7 This is a schematic diagram illustrating an improved example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application. Please refer to... Figure 7 If the serializer 210 of each transmitter channel circuit 20 is configured to serialize the odd-numbered bits D_e and even-numbered bits D_e of the output channel data respectively, then the shift register 215 of the serializer 210 may include two sets of flip-flops corresponding to the odd-numbered bits D_e and even-numbered bits D_e respectively, and the load signal can synchronously control the cascaded state of the two sets of flip-flops corresponding to the odd-numbered bits D_e and even-numbered bits D_e respectively.

[0088] Exemplarily, in embodiments of this application, multiple flip-flops in each group of the shift register 215 can be cascaded. Specifically, multiple flip-flops in each group of the shift register 215 can be cascaded by connecting the Q pins of the preceding flip-flops to the D pins of the following flip-flops in the same group via multiplexers. In this case, each odd-numbered bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop of one group and each multiplexer of that group; each even-numbered bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop of another group and each multiplexer of that group; and the clock signal can be connected to the CLK pin of each flip-flop in both groups of the shift register 215. Thus, the load signal can control the intra-group cascaded state of the two groups of flip-flops in the shift register 215 by controlling the multiplexers of both groups.

[0089] For example, in the embodiments of this application, when the cascaded state of the two sets of flip-flops in the shift register 215 is set to open by the load signal, that is, when the D pins of the other flip-flops in each set of flip-flops (excluding the first flip-flop) receive the corresponding odd or even bits of the channel data, the odd and even bits of the parallel input channel data can be loaded into the two sets of flip-flops in parallel (that is, the parallel loading of channel data into the shift register 215 is realized).

[0090] For example, in an embodiment of this application, when the cascaded state of the two sets of flip-flops in the shift register 215 is set to connected by a load signal, that is, when the D pins of the flip-flops other than the first flip-flop in each set are turned on with the Q pins of the preceding flip-flops in the same set, the odd and even bits of the channel data that have been loaded can be serialized and output from the serializer by shifting in the cascaded direction of the multiple flip-flops in the corresponding set (that is, shifting the loaded channel data in the shift register 215). Furthermore, the odd and even bits of the channel data are shifted in the loading of the two sets of flip-flops and in the cascaded direction of the two sets of flip-flops by the toggling of the two sets of flip-flops based on the clock signal.

[0091] Figure 8This is a schematic diagram of an improved example of the front-end driver circuit of the multi-channel transmitter of the AI ​​chip in this application. Please refer to... Figure 8 If the serializer 210 of each transmitter channel circuit 20 is configured to serialize the odd-numbered bits D_e and even-numbered bits D_e of the output channel data respectively, and the signal input from the first logic circuit 221 to the equalization logic operation section of the second logic circuit 222 includes channel data and equalization data, then the channel data input from the first logic circuit 221 to the second logic circuit 222 (i.e., the equalization logic operation section and other logic operation sections) can specifically include the odd-numbered bits D_e and even-numbered bits D_o input to the second logic circuit 222 (i.e., the equalization logic operation section and other logic operation sections) respectively, and Furthermore, the equalization data input from the first logic circuit 221 to the second logic circuit 222 (i.e., the equalization logic operation section) may include odd-bit equalization data D_e_eq and even-bit equalization data D_o_eq respectively input to the second logic circuit 222 (i.e., the equalization logic operation section). The odd-bit equalization data D_e_eq is generated based on the odd-bit D_e (for example, by delaying the odd-bit D_e by one clock cycle and then inverting it), and the even-bit equalization data D_o_eq is generated based on the even-bit D_o (for example, by delaying the even-bit D_o by one clock cycle and then inverting it).

[0092] In this configuration, the first logic circuit 221 of the pre-driver circuit 220 for each transmitter channel circuit 20 can be configured to alternately use the odd-numbered bits D_e and even-numbered bits D_e of the serialized output of the channel data to drive the second logic circuit 222 to generate multiple sets of control codes. Specifically, the serializer 210 serializes the odd-numbered bits D_e and even-numbered bits D_e of the output channel data, and the pre-driver circuit 220 alternately uses the odd-numbered bits D_e and even-numbered bits D_e to control the final-stage driver circuit 230 to serially transmit the corresponding level signal of the channel data in the corresponding physical channel, which helps improve the bit width consistency of the level signal in the physical channel.

[0093] In another embodiment of this application, an operation method for an AI chip is also provided, which is applicable to AI chips including the multi-channel transmitter described above.

[0094] Figure 9 This is an exemplary flowchart illustrating the operation method of the AI ​​chip in this application embodiment. Please refer to... Figure 9 In embodiments of this application, the operation method of the AI ​​chip may include:

[0095] S910: The first logic circuit of the pre-drive circuit drives the second logic circuit of the pre-drive circuit to generate multiple sets of control codes based on the channel data serialized from the serializer; wherein, the multiple sets of control codes include at least one set of control codes for adapting to at least one state in which the eq function is activated, and the at least one set of control codes is generated by the equalization logic operation part of the second logic circuit.

[0096] S930: The third logic circuit of the preamplifier circuit maintains an input clamp on the equalization logic operation portion of the second logic circuit of the preamplifier circuit of each transmitter channel circuit during the period when the eq function is off, based on the mode selection signal, or deactivates the input clamp on the equalization logic operation portion of the second logic circuit of the preamplifier circuit of each transmitter channel circuit during the period when the eq function is activated.

[0097] For example, in the embodiments of this application, the above step S930 of the operation method of the AI ​​chip may specifically include: the third logic circuit of the pre-drive circuit continuously clamps the signal level of the equalization logic operation section of the first logic circuit of the pre-drive circuit of each transmitter channel circuit to a preset logic level based on the mode selection signal during the period when the eq function is turned off, or stops clamping the above signal level during the period when the eq function is activated.

[0098] For example, in an embodiment of this application, if the pre-driver circuit further includes AND gates located between the equalization logic operation sections of the first logic circuit and the second logic circuit, the output of each AND gate is connected to the equalization logic operation section of the second logic circuit, the first input of each AND gate is connected to the first logic circuit, the second input of each AND gate is controlled by the third logic circuit, and the preset logic level used as the clamping level is 0, then the above-mentioned step S930 of the AI ​​chip operation method may specifically include: the third logic circuit of the pre-driver circuit controls the second input of each AND gate based on the mode selection signal to continuously set the second input of each AND gate to 0 during the period when the eq function is turned off, or to set the second input of each AND gate to 1 during the period when the eq function is activated.

[0099] It is understood that, in the embodiments of this application, the various parts described by example may be related by an "and / or" relationship. In this document, "and / or" means that the contexts connected by it may be a common "and" relationship or an alternative "or" relationship. Therefore, the various parts having an "and / or" relationship can be understood to include different combinations of situations where the "and / or" between each pair of parts represents a common "and" relationship or an alternative "or" relationship, and such combinations of different situations can be considered substantially equivalent to the scope of "at least one of the parts".

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An artificial intelligence chip, characterized in that, The system includes a multi-channel transmitter for transmitting data via a multi-channel bus, the multi-channel transmitter comprising multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus, and each of the channel transmitters comprising: A serializer is configured to serialize parallel-input channel data intended for transmission through the corresponding physical channel into an output serializer; The pre-drive circuit is configured to concurrently generate multiple sets of control codes based on the channel data serialized from the serializer, for adapting to various states where the equalization function is selectively activated or deactivated. The final stage drive circuit is configured to serially transmit the level signal corresponding to the channel data on the physical channel in the multi-channel bus based on the valid control code specified by the mode selection signal in the plurality of control codes; The pre-drive circuit includes a first logic circuit, a second logic circuit, and a third logic circuit. The first logic circuit is configured to drive the second logic circuit to generate the multiple sets of control codes based on the channel data serialized and output from the serializer. The second logic circuit includes an equalization logic operation section, and the multiple sets of control codes include at least one set of control codes adapted to at least one state in which the equalization function is activated. The at least one set of control codes is generated by the equalization logic operation section. The third logic circuit is configured to maintain an input clamp on the equalization logic operation section during the period when the equalization function is disabled, or to deactivate the input clamp on the equalization logic operation section during the period when the equalization function is activated, based on the mode selection signal.

2. The artificial intelligence chip according to claim 1, characterized in that, The third logic circuit is specifically configured to: based on the mode selection signal, continuously clamp the signal level input from the first logic circuit to the equalization logic operation section at a preset logic level during the period when the equalization function is turned off, or stop clamping the signal level during the period when the equalization function is activated.

3. The artificial intelligence chip according to claim 2, characterized in that, The pre-drive circuit further includes an AND gate located between the first logic circuit and the equalization logic operation section. The output of the AND gate is connected to the equalization logic operation section, the first input of the AND gate is connected to the first logic circuit, and the second input of the AND gate is controlled by the third logic circuit. Wherein, the preset logic level is 0, and the third logic circuit is specifically configured to: control the second input terminal of the AND gate based on the mode selection signal, continuously set the second input terminal of the AND gate to 0 during the period when the equalization function is turned off, or set the second input terminal of the AND gate to 1 during the period when the equalization function is activated.

4. The artificial intelligence chip according to any one of claims 1 to 3, characterized in that, The multiple sets of control codes include: a first set of control codes adapted to the state where both the impedance calibration function and the equalization function are turned off; a second set of control codes adapted to the state where the impedance calibration function is turned off and the equalization function is activated; a third set of control codes adapted to the state where the impedance calibration function is activated and the equalization function is turned off; and a fourth set of control codes adapted to the state where both the impedance calibration function and the equalization function are activated. The equalization logic operation section includes the part of the second logic circuit used to generate the second set of control codes and the fourth set of control codes.

5. The artificial intelligence chip according to claim 4, characterized in that, The second logic circuit includes a first logic operation section for generating the first set of control codes, a second logic operation section for generating the second set of control codes, a third logic operation section for generating the third set of control codes, and a fourth logic operation section for generating the fourth set of control codes. The equalization logic operation section includes the second logic operation section and the fourth logic operation section.

6. The artificial intelligence chip according to claim 5, characterized in that, The final stage drive circuit includes a first transistor group and a second transistor group. The first transistor group is located between the power supply and the output terminal of the corresponding physical channel, and the second transistor group is located between ground and the output terminal of the corresponding physical channel. The pre-drive circuit further includes a first transistor group drive array configured to control the first transistor group based on the valid control code, and a second transistor group drive array configured to control the second transistor group based on the valid control code. The final stage driving circuit is specifically configured to serially transmit the level signal corresponding to the channel data through the physical channel in the multi-channel bus by the coordinated operation of the first transistor group and the second transistor group under the control of the first transistor group driving array and the second transistor group driving array, respectively. Each of the first logic operation part, the second logic operation part, the third logic operation part, and the fourth logic operation part includes a first transistor group logic operation part and a second transistor group logic operation part for generating the first transistor group control code.

7. The artificial intelligence chip according to claim 6, characterized in that, The first transistor group driver array and the second transistor group driver array are further configured to: determine the valid control code among the multiple sets of control codes generated by the second logic circuit based on the input mode selection signal; Specifically, the third logic circuit is configured to maintain an input clamp on the equalization logic operation section during the period when the equalization function is turned off, or to remove the input clamp on the equalization logic operation section during the period when the equalization function is activated, based on the mode selection signal input to the first transistor group driver array and the second transistor group driver array.

8. A method for operating an artificial intelligence chip, characterized in that, The artificial intelligence chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus. Each channel transmitter includes a serializer, a pre-drive circuit, and a final-stage drive circuit. The serializer is configured to serialize parallel-input channel data intended for transmission through the corresponding physical channel into an output serializer. The pre-drive circuit is configured to concurrently generate multiple sets of control codes based on the channel data serialized from the serializer, for adapting to various states where the equalization function is selectively activated or deactivated. The final-stage drive circuit is configured to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus based on the valid control code specified by the mode selection signal in the plurality of control codes; Furthermore, the operation method includes: The first logic circuit of the pre-drive circuit drives the second logic circuit of the pre-drive circuit to generate the multiple sets of control codes based on the channel data serialized from the serializer; wherein, the multiple sets of control codes include at least one set of control codes for adapting to at least one state in which the equalization function is activated, and the at least one set of control codes is generated by the equalization logic operation part of the second logic circuit. The third logic circuit of the pre-drive circuit maintains an input clamp on the equalization logic operation section during the period when the equalization function is turned off, or removes the input clamp on the equalization logic operation section during the period when the equalization function is activated, based on the mode selection signal.

9. The operating method according to claim 8, characterized in that, The third logic circuit of the pre-drive circuit, based on the mode selection signal, maintains input clamping on the equalization logic operation section during the period when the equalization function is disabled, or de-clamps input to the equalization logic operation section during the period when the equalization function is activated, including: The third logic circuit of the pre-drive circuit clamps the signal level input from the first logic circuit to the equalization logic operation section at a preset logic level based on the mode selection signal during the period when the equalization function is turned off, or stops clamping the signal level during the period when the equalization function is activated.

10. The operating method according to claim 9, characterized in that, The pre-drive circuit further includes an AND gate located between the first logic circuit and the equalization logic operation section. The output of the AND gate is connected to the equalization logic operation section, the first input of the AND gate is connected to the first logic circuit, the second input of the AND gate is controlled by the third logic circuit, and the preset logic level is 0. The third logic circuit of the pre-drive circuit, based on the mode selection signal, continuously clamps the signal level input from the first logic circuit to the equalization logic operation section at a preset logic level during the period when the equalization function is disabled, or stops clamping the signal level during the period when the equalization function is activated, including: controlling the second input terminal of the AND gate based on the mode selection signal to continuously set the second input terminal of the AND gate to 0 during the period when the equalization function is disabled, or to set the second input terminal of the AND gate to 1 during the period when the equalization function is activated.

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