A high performance computing system

Abstract

The application provides a high-performance computing system, comprising several machine frames; each machine frame is provided with several computing blades and a relay board, the computing blade is integrated with at least one processor chip; the rear part of the relay board is provided with a high-speed electrical interface connected with the backboard of the machine frame, used for receiving Y / Z direction communication signals from the computing blade and performing Y / Z direction communication signal loop in the relay board; the front part of the relay board is provided with an optical interconnection interface, used for connecting adjacent relay boards to perform X direction optical signal interconnection. The original backboard loop function is moved forward, the backboard only needs to provide a point-to-point channel, without complex ring wiring; the front part of the relay board is provided with an optical interconnection interface, directly connected with the relay board in the adjacent machine frame, to realize X direction optical signal interconnection, a plurality of machine frames can be connected in series or networked in the X direction, to realize horizontal expansion; the backboard design is significantly simplified, and the system cost and failure rate are reduced.

Description

Technical Field

[0001] This application relates to the field of high-performance computing technology, and more specifically, to a high-performance computing system. Background Technology

[0002] In the field of high-performance computing, each chip in a high-performance computing cluster employing a 3D torus architecture is interconnected with adjacent chips in the ± directions (a total of 6 directions) of the X / Y / Z coordinate axes, forming a three-dimensional mesh topology (N). N N). Its interconnection method is fixed according to the design of chips, blades, backplanes, etc., where the Z direction is completely connected through the backplane; one Y direction is directly connected through the chip, and the other is directly connected through a cable; the X direction is completely directly connected through a cable.

[0003] Expanding the connectivity topology of a traditional 3D torus architecture computing cluster requires redefining the connectivity methods in all directions. This necessitates redesigning the connections between blades, chassis, and high-speed cables. Furthermore, the system's scalability is limited by the distance constraints of copper cabling. Summary of the Invention

[0004] This application provides a high-performance computing system to address the problems of existing 3D architecture computing clusters requiring recalculation of hardware structures such as blades and chassis when expanding their topology, as well as their fixed interconnect topology and high cost.

[0005] To achieve the above objectives, this application provides the following technical solution: A high-performance computing system includes several chassis; each chassis is provided with several computing blades and a relay board, and the computing blades integrate at least one processor chip; The relay board is provided with a high-speed electrical interface at the rear, which is connected to the back plate of the chassis, for receiving Y / Z direction communication signals from the computing blades and performing Y / Z direction communication signal loopback inside the relay board; The front of the relay board is provided with an optical interconnection interface for connecting adjacent relay boards to perform X-direction optical signal interconnection.

[0006] Optionally, the relay board is further provided with an X-direction internal ring network redundancy control module, which is used to build a primary path and a backup path in the X direction to achieve communication link redundancy; The X-direction internal ring network redundancy control module includes a heartbeat monitoring module, which is used to detect the link status in real time and generate a fault signal when the main path fails, triggering the X-direction internal ring network redundancy control module to automatically switch communication traffic to the backup path.

[0007] Optionally, the optical interconnect interface is an OCS optical interconnect interface; The repeater board is connected to the repeater board in the adjacent frame via a front cable to achieve optical signal interconnection in the X and / or Y directions.

[0008] Optionally, the high-speed electrical interface is an Exmax interface, used to transmit high-speed data signals between the computing blade and the relay board.

[0009] Optionally, the computing blade integrates two processor chips; Each of the computing blades has 10 Exmax interfaces at the rear, 5 of which are used to connect to the backplane of the chassis, and the other 5 are used to connect to the X-direction communication interface of the processor chip via cables.

[0010] Optionally, each of the frames includes 18 blade slots; The two blade slots located on both sides of the frame are used to install management blades, while the remaining 16 blade slots in the middle are used to install computing blades and relay boards.

[0011] Optionally, the system includes 24 of the aforementioned frames; Each of the aforementioned chassis includes 12 of the aforementioned computing blades and 4 of the aforementioned relay boards; the total number of processor chips on all the aforementioned computing blades is 576, forming an 8×8×9 three-dimensional topology.

[0012] Optionally, each of the processor chips has six axial communication interfaces: X+, X-, Y+, Y-, Z+, and Z-. Among them, three communication interfaces in the Y+, Y-, Z+, and Z- directions are connected to the rear of the relay board through the chassis back panel; In addition, three communication interfaces in the X+, X-, Y+, and Y- directions are connected to the optical interconnect interface on the front of the repeater board via external cables.

[0013] This application provides a high-performance computing system comprising several chassis; each chassis is provided with several computing blades and a relay board, and the computing blades integrate at least one processor chip; The relay board is provided with a high-speed electrical interface at the rear, which is connected to the back plate of the chassis, for receiving Y / Z direction communication signals from the computing blades and performing Y / Z direction communication signal loopback inside the relay board; The front of the relay board is provided with an optical interconnection interface for connecting adjacent relay boards to perform X-direction optical signal interconnection.

[0014] The high-performance computing system provided in this application embodiment has the following technical advantages compared to the prior art: In this application, the chassis includes computing blades and a relay board. The relay board has a high-speed electrical interface at the rear that connects to the backplane of the chassis, receiving Y / Z direction communication signals from the computing blades. Loopback of the Y / Z direction communication signals is performed within the relay board, moving the original backplane loopback function forward. The backplane only needs to provide point-to-point channels, eliminating the need for complex ring wiring and simplifying backplane design. It also supports seamlessly splitting large computing systems into multiple independent subsystems or dynamically merging multiple subsystems into a larger system, improving resource utilization. The front of the relay board has an optical interconnect interface that directly connects to relay boards in adjacent chassis, enabling optical signal interconnection in the X direction. This allows multiple chassis to be connected in series or networked in the X direction, achieving horizontal expansion. This significantly simplifies backplane design and reduces system cost and failure rate. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of the axial connections of the processor chip within the computing blade provided in an embodiment of this application; Figure 2 A top view of the relay board provided in the embodiments of this application; Figure 3 A front view of a relay board provided in an embodiment of this application; Figure 4 Rear view of the relay board provided in an embodiment of this application; Figure 5 Front view of the chassis provided in an embodiment of this application; Figure 6 Rear view of the chassis provided for an embodiment of this application.

[0016] The following labels are shown in the attached diagram: Calculation blade 1, relay board 2, management blade 3, frame 4; Exmax interface 11. Detailed Implementation

[0017] This invention discloses a high-performance computing system to solve the problems of existing 3D architecture computing clusters requiring recalculation of hardware structures such as blades and chassis when expanding the topology, having a fixed interconnect topology, and high costs.

[0018] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0019] Please see Figure 1-6 , Figure 1 A schematic diagram of the axial connections of the processor chip within the computing blade provided in an embodiment of this application; Figure 2 A top view of the relay board provided in the embodiments of this application; Figure 3 A front view of a relay board provided in an embodiment of this application; Figure 4 Rear view of the relay board provided in an embodiment of this application; Figure 5 Front view of the chassis provided in an embodiment of this application; Figure 6 Rear view of the chassis provided for an embodiment of this application.

[0020] In one specific embodiment, the high-performance computing system provided in this application includes a plurality of chassis 4; each chassis 4 is provided with a plurality of computing blades 1 and a relay board 2, and the computing blades 1 integrate at least one processor chip. The rear of the relay board 2 is provided with a high-speed electrical interface that connects to the back plate of the frame 4, which is used to receive Y / Z direction communication signals from the computing blade 1 and to perform Y / Z direction communication signal loopback inside the relay board 2. The front of the repeater board 2 is equipped with an optical interconnection interface, which is used to connect adjacent repeater boards 2 for X-direction optical signal interconnection.

[0021] The chassis 4 is equipped with several blade slots. Some blade slots are used to place computing blades 1, and some blade slots are used to place relay boards 2. Specifically, the relay boards 2 and computing blades 1 share the same physical slots and interface standards, which can be flexibly replaced to realize the dynamic allocation of computing resources and interconnection resources.

[0022] Each computing blade 1 integrates at least one processor chip, which serves as the basic computing unit of the system; in a preferred embodiment, each blade integrates two processor chips, forming a symmetrical multiprocessor structure. The rear of the computing blade 1 is provided with multiple high-speed electrical interfaces, which are connected to the backplane of the chassis 4 via gold fingers for transmitting data, control signals, and clock signals.

[0023] The relay board 2 can be directly inserted into the standard blade slot and has front and rear dual-sided interfaces, enabling front-to-back decoupling and forward functional shift. Specifically, a high-speed electrical interface is provided at the rear of the relay board 2 for establishing an electrical connection with the backplane of the chassis 4 and for receiving Y / Z direction communication signals from the computing blade 1. The Y direction is for communication between horizontally adjacent blades within the same chassis 4; the Z direction is for vertical or inter-layer communication, used to construct a ring or three-dimensional mesh topology. The relay board 2 internally realizes the loopback of Y / Z direction signals. Compared with the traditional architecture, where the closure of the Y / Z direction ring topology relies on backplane wiring, this application moves this function forward to the inside of the relay board 2, where the internal circuitry completes the signal foldback. For FPGAs, dedicated ASICs, or switching chips, the backplane only needs to provide point-to-point channels, eliminating the need for complex ring wiring and simplifying the backplane design.

[0024] The front of repeater board 2 is equipped with an optical interconnection interface, which connects directly to repeater board 2 in adjacent chassis 4 via fiber optic cables to achieve optical signal interconnection in the X direction. The X direction represents the lateral expansion direction across chassis 4 and cabinets. Fiber optic transmission offers high bandwidth, low latency, and strong anti-interference capabilities; it breaks through the traditional copper cable length limitations (generally ≤1.6m), supporting long-distance interconnection (up to tens or even hundreds of meters); the cabling is simple, requiring only a small number of fiber optic connections at the front, facilitating maintenance and expansion; thus forming a high-speed X-direction link across chassis 4, supporting lateral expansion of the system.

[0025] The aforementioned computing system enables flexible topology reconfiguration and dynamic partitioning. By controlling whether relay board 2 enables Y / Z direction loopback, the communication path can be dynamically determined. When loopback is enabled, a closed loop network is formed locally for small-scale independent computing tasks. When loopback is disabled, interfaces can be opened for expansion. It supports seamlessly splitting a large computing system into multiple independent subsystems (partition mode), suitable for multi-tenant, isolation testing, and other scenarios. Multiple subsystems can also be dynamically merged into a larger system to improve resource utilization. Utilizing the front OCS optical interconnect interface, multiple chassis 4 can be easily connected in series or networked in the X direction; no longer limited by the physical connection capabilities of the chassis 4 backplane, it achieves near-infinite horizontal expansion. It breaks through the traditional blade server "single-chassis computing power bottleneck" and supports the construction of ultra-large-scale computing clusters. Traditional backplanes require complex wiring for Y / Z direction ring networks, resulting in many layers, high costs, and a high risk of errors. This application moves the loopback function forward to the relay board 2, and the backplane only needs to provide point-to-point direct connection channels, greatly simplifying the wiring. The backplane can be designed as a "passive" structure, reducing active components, improving reliability, reducing the manufacturing cost of the chassis 4, improving yield, and facilitating maintenance and upgrades.

[0026] In one embodiment, the relay board 2 is further provided with an X-direction internal ring network redundancy control module for constructing a primary and backup communication path in the X direction. The X-direction internal ring network redundancy control module includes a heartbeat monitoring module, which is used to detect the link status in real time and generate a fault signal when the primary path fails, triggering the X-direction internal ring network redundancy control module to automatically switch communication traffic to the backup path.

[0027] In the X direction, multiple repeater boards 2 are connected via front optical interconnect interfaces to form a main communication path. Simultaneously, the system is configured with a backup path, which is normally in standby mode. The heartbeat detection module continuously sends probe packets to the main path to monitor for responses from the peer, abnormal increases in link latency, excessive bit error rate, and optical power below thresholds. This can be implemented using hardware timers and state machines, or by an embedded microcontroller running the monitoring algorithm. When in a normal state, heartbeat packets are sent periodically, and the peer responds normally, with communication traffic following the main path. When a fault occurs, if the heartbeat monitoring module fails to receive responses multiple times consecutively, or if the bit error rate spikes, it determines that the main path is faulty and generates a fault signal. This fault signal triggers the X-direction internal ring network redundancy control module, which seamlessly switches communication traffic to the backup path via an internal crossbar switch or routing table reconfiguration. The switching process is completed in milliseconds, with no awareness from upper-layer applications. After the main path is repaired, it can automatically or manually switch back to the backup path, achieving load balancing.

[0028] It achieves physical layer redundancy for cross-chassis 4-way communication, avoiding system interruption due to single point of failure; provides rapid fault detection capability (<10ms), which is much faster than software polling (second-level); realizes self-healing of communication links, ensuring the continuity of long-cycle tasks such as AI training and HPC; has low switching latency and high reliability, and does not depend on the operating system or upper-layer software; the optical fiber itself has strong anti-interference, and the superimposed path redundancy significantly improves the robustness of the system.

[0029] In another alternative embodiment, the optical interconnect interface is an OCS optical interconnect interface; Repeater board 2 is connected to repeater board 2 in the adjacent frame 4 via front cable to realize optical signal interconnection in the X and / or Y directions.

[0030] The OCS (Optical Circuit Switching) interface establishes a dedicated optical path before communication, transmitting data as a continuous optical signal to avoid queuing delays and congestion associated with electronic switching. The repeater board 2 has an OCS interface on its front, which can be directly connected to the repeater board 2 in the adjacent chassis 4 via pluggable fiber optic cables. X-direction connections are used for horizontal system expansion; Y-direction connections are used for inter-layer or vertical communication; when X+Y directions are connected simultaneously, a two-dimensional planar interconnect network can be constructed, supporting complex topologies such as Mesh and Toroidal.

[0031] It adopts OCS optical interconnect interface to achieve ultra-high speed, low latency, and deterministic cross-chassis 4 communication, meeting the stringent bandwidth and synchronization requirements of AI / HPC; front cable connection, so that the cabling is located on the front of chassis 4, with strong visibility, easy maintenance and replacement, and supports hot-swapping; it breaks through the traditional "one-way expansion" limitation, supports the construction of two-dimensional or three-dimensional topologies (such as 8×8×9), and improves the system expansion freedom; it does not rely on chassis 4 backplane cabling, supports cross-rack, long-distance interconnection (up to tens of meters), and facilitates flexible layout of data centers.

[0032] In one optional embodiment, the high-speed electrical interface is an Exmax interface 11, used to transmit high-speed data signals, control signals, and clock signals between the computing blade 1 and the relay board 2. The Exmax interface 11 is located in the rear gold finger area of ​​the computing blade 1 and the relay board 2, and completes point-to-point or point-to-multipoint transmission through backplane traces. The high-speed data signals are the payloads for inter-chip communication, such as matrix calculation results, gradient data, and memory data. The control signals include address information, read / write commands, flow control signals, and topology configuration instructions. The clock signal is the synchronous communication timing, supporting source synchronization or embedded clocks. The Exmax interface 11 typically employs differential signaling, multi-channel parallelism (such as x16 lanes), and high-speed SerDes technology, achieving speeds of up to 25Gbps / lane or higher, supporting high-throughput communication. Optionally, the Exmax interface 11 is pin-compatible on both the computing blade 1 and the relay board 2, supporting hot-swappable identification.

[0033] It handles data exchange between computing blades 1 in the Y and Z directions. It receives signals from a specific direction via the Exmax interface 11, processes them internally, and then sends the signals back through the same interface, achieving local loop closure. Compared to general-purpose interfaces (such as Ethernet), Exmax is optimized for short-distance intra-board communication, resulting in lower latency and higher efficiency. Optimized for the communication mode of this system, it boasts high bandwidth utilization and low latency, surpassing general-purpose interfaces and supporting high-speed serial transmission.

[0034] In one optional embodiment, the computing blade 1 integrates two processor chips. Each computing blade 1 has 10 Exmax interfaces 11 on its rear, five of which are used to connect to the backplane of the chassis 4, and the other five are used to connect to the X-direction communication interface of the processor chip via cables. It is understood that each computing blade 1 integrates two high-performance processor chips, such as a GPU, AI accelerator, or multi-core CPU; the two chips are directly connected via high-speed interconnects to form a high-density computing unit, thereby improving the computing power density of a single blade. The five Exmax interfaces 11 are used for Y / Z direction communication with other modules in the system through the backplane of the chassis 4, and the other five are used to directly connect to the X-direction communication interface of the processor chip via external cables to support X-direction expansion or debugging.

[0035] Each chip is allocated 5 Exmax interfaces: 2-3 for backplane Y / Z communication and 2-3 for X-direction outgoing. The specific number can be dynamically adjusted according to the chip's I / O capabilities. High-speed copper cables (such as AOC and DAC) can be used for the outgoing interfaces, with a length generally not exceeding 1.6m, suitable for rack-mounted connections. When the relay board 2 is deployed, the X-direction interface of the computing blade 1 can be turned off or used as a backup path.

[0036] With the main X-direction expansion achieved by the OCS optical interconnection at the front of the relay board 2, the X-direction interface of the computing blade 1 itself can still serve as a supplementary path and redundant backup, forming a dual channel with the OCS path; or it can serve as a debugging channel, independent of the main communication network, for fault diagnosis.

[0037] Two processor chips significantly improve the computing power density of a single blade, reduce the number of blades required by the system, and reduce power consumption and space occupation; the 10 Exmax interfaces 11 have clear division of labor, realize the decoupling of communication in the Y / Z and X directions, and support three-dimensional topology construction; the X direction can be connected by cable or by optical connection through repeater board 2, making the deployment more flexible, and the same Exmax interface 11 can be dynamically configured for different purposes, improving hardware utilization.

[0038] Furthermore, each frame 4 includes 18 blade slots; Among them, the two blade slots on both sides of the frame 4 are used to install management blades 3, and the remaining 16 blade slots in the middle are used to install computing blades 1 and relay boards 2.

[0039] The slots can adopt a unified physical structure standard to ensure compatibility. The blade slots located on both sides of the chassis 4 are used to install management blades 3, which are responsible for the system management, monitoring, scheduling, and configuration distribution of the entire chassis 4. They provide out-of-band management interfaces (such as IPMI and Redfish), can run management firmware or lightweight operating systems, are fixed in deployment, and do not participate in computing or interconnect expansion. The two management blades 3 are physically symmetrical, which facilitates power and management bus cabling. This prevents the management module from being accidentally removed or replaced, improving system stability. The side-by-side layout is conducive to heat dissipation airflow design (cold air is drawn in from the middle, and hot air is exhausted from the sides). The repeater board 2 occupies a standard blade slot, requiring no additional space or dedicated slot; achieving "functional modularization and standardized deployment".

[0040] Understandably, the 18 blade slot design provides high-density computing power deployment capabilities, with a single chassis supporting up to 16 computing blades1 (32 chips) to meet high-performance requirements; fixed management blades3 on both sides ensure stable and reliable system management functions, avoid configuration errors, and improve operational security; the management blades3 on both sides help optimize airflow and power distribution, improving system reliability; unified slot standards reduce hardware design complexity and support hot-swapping and quick replacement.

[0041] In one embodiment, the number of computing blades 1 and relay boards 2 can be set as needed, such as setting 12 computing blades 1 and 4 relay boards 2 to support moderate expansion and retain some interconnection capabilities; or setting 8 computing blades 1 and 8 relay boards 2 to provide sufficient relay capabilities for large-scale X-direction networking; or setting 10 computing blades 1 and 6 relay boards 2 to construct a dual-ring network and improve the reliability of X-direction communication.

[0042] Specifically, the slots can be numbered #0 to #17, where #0 and #17 are management slots and #1 to #16 are general-purpose slots; the management blade 3 has low power consumption, and deployment on both sides helps to balance power; the high-density computing area in the middle is centrally cooled and supports intelligent fan speed control; the management blade 3 is connected to the management bus; the middle slot is connected to the high-speed Exmax channel and supports point-to-point direct connection.

[0043] In another embodiment, the system includes 24 chassis 4; Each chassis 4 includes 12 compute blades 1 and 4 relay boards 2; the total number of processor chips on all compute blades 1 is 576, forming an 8×8×9 three-dimensional topology.

[0044] The system chassis 4 comprises a total of 24 units, with each chassis 4 configured with 12 compute blades 1, 4 relay boards 2, and 2 management blades 3. Each compute blade 1 includes 2 processor chips. The total number of processor chips is calculated as follows: 24-chassis, 4 x 12 compute blades, 1 / chassis x 2 chips / blade = 576 processor chips It enables ultra-large-scale computing power clusters, suitable for scenarios such as AI large model training, high-performance computing (HPC), and scientific simulation.

[0045] The X-direction (9) extension relies on the front OCS optical interconnect interface of the relay board 2. In the 24 chassis 4, there are 4 relay boards 2 in each chassis, for a total of 24×4=96 relay boards 2. Each relay board 2 can support multiple OCS links to build the X-direction primary and backup paths. In the actual topology, the X-direction is 9, which means that the system is organized into 9 "computing unit groups" in the X dimension, and each group contains 8×8=64 chips.

[0046] The Y / Z direction (8×8) closed loop relies on the internal Y / Z signal loopback function of relay board 2. Each chassis has 412 compute blades 1 + 4 relay boards 2, which can divide 16 slots into an 8×2 structure, supporting the construction of Y / Z direction ring networks. Relay board 2 acts as a "local switching node" to realize localized processing of Y / Z direction communication, reducing dependence on the backplane. It achieves a balanced configuration of "high computing power" and "high interconnection" capabilities, provides extremely high parallelism, and supports large-scale parallel algorithms. It matches mainstream AI / HPC communication modes (such as Tensor Parallel and Pipeline Parallel) to reduce communication overhead. The X-direction optical interconnection enables expansion beyond the single chassis limitation, supporting long-distance, high-bandwidth cross-rack interconnection. The Y / Z direction loopback closure simplifies the backplane design and improves the communication efficiency and reliability within the chassis. It can be further expanded to 8×8×10 or larger scale, supporting smooth system upgrades.

[0047] In another embodiment, each processor chip has six axial communication interfaces: X+, X-, Y+, Y-, Z+, and Z-. Among them, three communication interfaces in the Y+, Y-, Z+, and Z- directions are connected to the rear of the relay board 2 through the back panel of the chassis 4; In addition, three communication interfaces in the X+, X-, Y+, and Y- directions are connected to the optical interconnect interface on the front of repeater board 2 via external cables.

[0048] The connection path for the Y / Z direction interface is: processor chip (Y+ / Y- / Z+ / Z-) → Exmax interface 11 → chassis 4 backplane → repeater board 2 rear Exmax interface 11; after receiving the Y / Z signal, the repeater board 2 realizes signal loopback (such as Z+→Z- foldback) inside it to build a local ring network; the backplane does not need complex wiring, only point-to-point channels are needed, simplifying the design.

[0049] Repeater board 2 serves as a "communication hub": the rear section takes over communication in the Y / Z direction to realize local switching and loopback; the front section supports X-direction expansion to realize cross-frame interconnection; thus realizing a new interconnection architecture of "decoupling between front and rear and functional integration".

[0050] Supports multiple operating modes: Local mode: Y / Z loopback enabled, X direction disabled; Extended mode: X direction cable connection enabled to build a large system; Redundancy mode: X direction primary and backup paths run in parallel.

[0051] It enables local loopback of signals in the Y / Z directions, simplifies backplane design, and reduces latency; it supports flexible expansion in the X direction, breaking through the chassis 4 limitation; it forms a hybrid architecture of "intra-chassis electrical connection + inter-chassis optical connection", which improves system scalability, reduces dependence on external switching equipment, and reduces system complexity.

[0052] In one specific implementation, the chassis 4 consists of 18 blades. The leftmost and rightmost blades are management blades 3, responsible for managing and scheduling the computing blades 1. The middle section contains 16 computing blades 1, each consisting of 2 chips. Each computing blade 1 has 10 chip interconnect communication interfaces at its rear, 5 of which connect to the backplane of the chassis 4, and the other 5 are connected via cables. All interfaces are high-speed Exmax interfaces 11. The repeater board 2 has essentially the same specifications as the blades and is deployed within the chassis 4, replacing the original blades. The repeater board 2 connects to the chassis 4 at the rear, with Exmax interfaces 11 and power supply interfaces at the rear, and optical interconnect interfaces at the front.

[0053] Repeater board 2 takes over the Y / Z direction signals of the original backplane and realizes loopback through repeater board 2; repeater board 2 provides internal ring network redundancy in the X direction, which can form a more flexible topology; externally, it provides OCS optical interconnection interface, which realizes X / Y direction interconnection through connection with other adjacent repeater boards 2, and realizes X direction extension and redundancy.

[0054] Depending on the business scenario, the large system can be flexibly divided into multiple smaller systems. Since the OCS optical interconnect interface connection only connects in the X direction from the front cable, configuration is simple and convenient. Furthermore, it is not limited by the length of the copper cable (generally not exceeding 1.6m).

[0055] With 12 computing blades 1 and 4 relay boards 2 in each chassis 4, a single chassis 4 has formed 2 2 (2+4) cuboid system; 2 frames and 4 can form 3 (3+1) (3+1) cuboid system; 4 frames can form 4 4 (4+2) Cuboid System. The above systems can be designed as either cuboid systems or cube systems with added redundancy. Their topology is flexibly configurable, including a partitioning mode that blocks specified Y / Z signals and triggers local loopback. This splits a large system into multiple independent smaller systems; an expansion mode that disables loopback and enables OCS connection to new nodes, enabling expansion of the system size in the X direction; and a ring network redundancy mode that creates a backup path in the X direction and automatically switches in case of a single point of failure.

[0056] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0057] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A high-performance computing system, characterized in that, It includes several chassis; each chassis is provided with several computing blades and relay boards, and the computing blades are integrated with at least one processor chip; The relay board is provided with a high-speed electrical interface at the rear, which is connected to the back plate of the chassis, for receiving Y / Z direction communication signals from the computing blades and performing Y / Z direction communication signal loopback inside the relay board; The front of the relay board is provided with an optical interconnection interface for connecting adjacent relay boards to perform X-direction optical signal interconnection.

2. The high-performance computing system according to claim 1, characterized in that, The relay board is also equipped with an internal ring network redundancy control module in the X direction, which is used to build a primary path and a backup path in the X direction to achieve communication link redundancy. The X-direction internal ring network redundancy control module includes a heartbeat monitoring module, which is used to detect the link status in real time and generate a fault signal when the main path fails, triggering the X-direction internal ring network redundancy control module to automatically switch communication traffic to the backup path.

3. The high-performance computing system according to claim 1, characterized in that, The optical interconnect interface is an OCS optical interconnect interface; The repeater board is connected to the repeater board in the adjacent frame via a front cable to achieve optical signal interconnection in the X and / or Y directions.

4. The high-performance computing system according to claim 1, characterized in that, The high-speed electrical interface is an Exmax interface, used to transmit high-speed data signals between the computing blade and the relay board.

5. The high-performance computing system according to claim 1, characterized in that, The computing blade integrates two processor chips; Each of the computing blades has 10 Exmax interfaces at the rear, 5 of which are used to connect to the backplane of the chassis, and the other 5 are used to connect to the X-direction communication interface of the processor chip via cables.

6. The high-performance computing system according to claim 1, characterized in that, Each of the aforementioned frames includes 18 blade slots; The two blade slots located on both sides of the frame are used to install management blades, while the remaining 16 blade slots in the middle are used to install computing blades and relay boards.

7. The high-performance computing system according to claim 6, characterized in that, The system includes 24 of the aforementioned frames; Each of the aforementioned chassis includes 12 of the aforementioned computing blades and 4 of the aforementioned relay boards; the total number of processor chips on all the aforementioned computing blades is 576, forming an 8×8×9 three-dimensional topology.

8. The high-performance computing system according to claim 3, characterized in that, Each of the processor chips has six axial communication interfaces: X+, X-, Y+, Y-, Z+, and Z-. Among them, three communication interfaces in the Y+, Y-, Z+, and Z- directions are connected to the rear of the relay board through the chassis back panel; In addition, three communication interfaces in the X+, X-, Y+, and Y- directions are connected to the optical interconnect interface on the front of the repeater board via external cables.

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