An electronic computing method and system based on an underwater unmanned submarine vehicle

Abstract

The application provides an underwater unmanned submarine-based electronic computing method and system, which comprises a case and a plurality of board card modules arranged in the case; the plurality of board card modules are installed in a stacked manner through stacked electrical connectors and comprise at least one general computing module and at least one interface expansion module; wherein the plurality of board card modules realize internal data interaction between the board cards through a high-speed Ethernet; the high-speed Ethernet comprises a control plane network for transmitting control signaling and a data plane network for transmitting large-capacity service data; the transmission rate of the data plane network is higher than that of the control plane network; the general computing module is used for fusing and processing data collected by the interface expansion module to generate control instructions; the interface expansion module is used for connecting with external devices of the underwater unmanned submarine, receiving data of the external devices and outputting the control instructions to the external devices, so that the modularization level and development efficiency of the system are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an electronic computing method and system based on an underwater unmanned submersible. Background Technology

[0002] As ocean exploration and development move towards deeper and more intelligent environments, the tasks undertaken by unmanned underwater vehicles (UUVs) are becoming increasingly complex. For example, they need to simultaneously perform high-resolution seabed topographic mapping (detection), underwater acoustic communication with the mother ship or other UUVs (communication), high-precision inertial and acoustic combined navigation (navigation), and real-time control of payloads such as robotic arms and samplers (control).

[0003] In existing technologies, the navigation, control, communication, and detection subsystems of traditional underwater unmanned vehicle (UUV) electronic systems are independent of each other. Each subsystem often requires customized selection or development of dedicated controllers based on the power and interface of its connected sensors or actuators. This discrete design results in a wide variety of electronic systems within the UUV, lacking a unified standard and greatly hindering modular design and integration of the system.

[0004] Furthermore, because the design units of each subsystem only consider their own needs, the electrical standards and communication buses (such as CAN, RS422, 1553B, etc.) used are numerous and difficult to unify, leading to problems such as complex interfaces and difficulties in protocol conversion during system integration. More importantly, this architecture results in uneven distribution of computing power and difficulty in coordinating power consumption management in the overall system. Moreover, electromagnetic compatibility issues are prone to arise between various independent electronic units, posing uncontrollable risks to the overall stability and reliability of the system. Summary of the Invention

[0005] The present invention aims to solve the technical problems of discrete, non-standard, and limited performance of electronic systems in existing underwater unmanned submersibles.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An electronic computing method and system based on an underwater unmanned submersible includes: At least one chassis; and Multiple board modules are disposed within the chassis, the multiple board modules are mounted in a stacked manner via stacked electrical connectors, and include at least one general-purpose computing module and at least one interface expansion module; The multiple board modules achieve internal data interaction between the boards through high-speed Ethernet. The high-speed Ethernet includes a control plane network for transmitting control signaling and a data plane network for transmitting large-capacity service data, and the transmission rate of the data plane network is higher than that of the control plane network. The general computing module is used to fuse and process the data collected by the interface extension module to generate control commands. The interface extension module is used to connect with the external devices of the underwater unmanned submersible, receive data from the external devices, and output the control commands to the external devices.

[0007] Furthermore, the general-purpose computing module includes a central processing unit and a field-programmable gate array (FPGA), with the FPGA serving as a data processing unit for: The central processing unit converts data access requests for remote resources into Ethernet packets; Process the network protocol stack to offload the protocol processing burden of the central processing unit; The received Ethernet packets are efficiently delivered to the central processing unit via DMA.

[0008] Furthermore, the control plane network is a gigabit Ethernet network, and the data plane network is a 10-gigabit Ethernet network or a 40-gigabit Ethernet network.

[0009] Furthermore, the system also includes multiple chassis, which are interconnected via an external high-speed network consistent with the internal high-speed Ethernet protocol, to achieve horizontal expansion of the electronic computing system and to realize unified addressing and transparent scheduling of all hardware resources at the software level.

[0010] Furthermore, the interface expansion module includes a field-programmable gate array (FPGA), which is used for: Implement the interface protocol for external devices, wherein the interface protocol includes at least one of the following: Controller Area Network Bus Protocol, RS422 Serial Protocol, RS485 Serial Protocol, or RS232 Serial Protocol; The data from the external device is encapsulated into Ethernet packets and transmitted to the general computing module via the high-speed Ethernet.

[0011] Furthermore, the mechanical dimensions of the board module conform to the PCIe / 104 standard or the COME standard, and the system adopts a passive heat dissipation method, with its heat dissipation structure integrated with the hull of the underwater unmanned submersible through the board's cooling plate.

[0012] An electronic computing method based on an underwater unmanned submersible, applied to any of the above-mentioned electronic computing systems, the method comprising: The interface expansion module receives target data from external devices of the underwater unmanned submersible, implements the interface protocol of the external devices through FPGA, and encapsulates the target data into Ethernet data packets. The interface expansion module sends the Ethernet data packets to the general computing module through a high-speed Ethernet control plane network or data plane network. The general computing module parses the received Ethernet data packets through the FPGA and delivers them to the central processing unit via DMA. The central processing unit then performs fusion processing on the target data to generate control instructions. The general computing module sends the control commands to the interface expansion module via the high-speed Ethernet, and the interface expansion module parses and outputs them to the corresponding external devices to execute control operations.

[0013] Furthermore, the method also includes: The operating system provides a device driver that virtualizes access to remote external devices connected to the interface extension module into read and write operations on local device files, thereby making access to upper-layer applications transparent.

[0014] Furthermore, the FPGA of the general computing module is connected to the control plane network and the data plane network through multiple high-speed Ethernet channels, including at least two 10 Gigabit Ethernet channels and two Gigabit Ethernet channels.

[0015] Compared with the prior art, the beneficial effects of the present invention include: 1. This invention fundamentally solves the problems of complex and inconsistent interfaces caused by existing architectures by deploying stacked modules within the chassis and replacing traditional diverse buses and interfaces with a unified, Ethernet-based data interaction channel. Standardized mechanical dimensions and electrical interfaces enable rapid interchange, iteration, and integration of different functional board modules, greatly improving the modularity of the system.

[0016] 2. This invention utilizes high-speed Ethernet as the internal data exchange channel and can divide the control plane and data plane, ensuring high bandwidth and low latency in data communication between modules. The separate design of the general-purpose computing module and the interface expansion module, as well as the vertical expansion achieved through stacked connectors and the horizontal expansion achieved through network interconnection, give the system strong customizability. It can flexibly add or remove computing resources and interface types according to task requirements, making it highly adaptable.

[0017] 3. The general-purpose computing module of this invention integrates a data processing unit (DPU), which relieves the CPU of the burden of network protocol processing, allowing the CPU to focus more on upper-layer application computing and improving overall computing performance. Simultaneously, by virtualizing physical interfaces distributed on the network as local devices through device driver software, upper-layer application software developers do not need to concern themselves with the complex details of underlying network communication and protocol conversion. They can access remote interfaces as if operating local devices, significantly reducing development difficulty and complexity. Attached Figure Description

[0018] The disclosure of this invention is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this invention. In the drawings, the same reference numerals are used to refer to the same parts. Wherein: Figure 1 This is a diagram of the computing environment system architecture for an underwater unmanned submersible platform.

[0019] Figure 2 This is a diagram of the internal structure of a distributed electronic computing system.

[0020] Figure 3 This is a perspective view of the equipment's interior.

[0021] Figure 4 This is a top view of the chassis.

[0022] Figure 5 This is a structural diagram of the board module.

[0023] Figure 6 This is a diagram of the system boot software architecture based on UEFI.

[0024] Figure 7 This is a hierarchical diagram of the UEFI system architecture.

[0025] Figure 8 A diagram illustrating the process from powering on the system to powering it off.

[0026] Figure 9 This is a schematic diagram of an integrated electronic computing system architecture.

[0027] 10. Chassis; 20. Board modules. Detailed Implementation

[0028] It is readily understood that, based on the technical solution of this invention, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention.

[0029] This invention proposes an integrated electronic computing system for exploration, communication, guidance, and control based on an unmanned underwater vehicle (UUV). This system aims to address increasingly complex mission requirements by integrating the electronic systems for detection, communication, navigation, and control. It achieves an autonomous, controllable, and multi-functional heterogeneous electronic system that combines general-purpose computing, heterogeneous computing acceleration, network data exchange, data storage, analog signal processing, and rich external interfaces.

[0030] Reference Figure 1 and Figure 9 The integrated electronic computing system disclosed in this invention is divided into three levels from top to bottom in terms of hierarchical structure: system level (computing environment) - chassis level - board module level.

[0031] At the system level, the entire computing environment can consist of one or more data chassis 10. When the computing resources of a single chassis 10 cannot meet the task requirements, multiple chassis 10 can be horizontally scaled up via an external high-speed network (such as fiber optic Ethernet) to form a larger-scale distributed computing cluster. It is important to note that the communication mechanism for this horizontal scaling is consistent with the communication mechanism inside the chassis 10, both being based on the Ethernet protocol, thus achieving unified addressing and transparent scheduling of all hardware resources at the software level.

[0032] At the chassis level, refer to Figure 2 The chassis 10 provides a standardized physical foundation, power supply, heat dissipation, and interconnection for the board modules 20. An innovation of this embodiment is that the board modules 20 inside the chassis 10 are vertically expanded through stacking and interconnected point-to-point via stacked high-speed electrical connectors. While the above structure borrows mechanical dimensions from mature embedded standards such as PCIe / 104 and CMe (e.g., supporting various specifications such as Compact Module: 90.17mm × 95.89mm, Basic Module: 125mm × 95.89mm, Extended Module: 155mm × 110mm), the definitions of its high-speed signal pins are completely refactored to Ethernet signals. This means that the traditional parallel bus architecture is replaced by an internal switched Ethernet with a bandwidth of at least 5GB / s and a latency of less than 5µs. Under this architecture, each board module 20 becomes an independent network node, and its function and access are no longer limited by the physical slot location, greatly improving the modularity and flexibility of the system.

[0033] Reference Figure 3 , Figure 4 and Figure 5 The chassis 10 and board module 20 of this invention have been designed mechanically and structurally to meet the harsh working environment requirements of UUVs. The design follows the following general specifications.

[0034] For example, the total system weight is controlled within 4kg; it supports a wide voltage input range of 9~36VDC; it can operate stably in an environment of -25℃ to +60℃; and the mean time between failures (MTBF) is no less than 5000 hours. To adapt to the compact space and limited heat dissipation conditions inside the UUV, this solution strictly controls power consumption, requiring the power consumption of a single module to be controlled within 18W, reducing the system's requirements for heat dissipation. In terms of heat dissipation, a design integrated with the hull structure is adopted. The cold plate of the board and the chassis are integrated into one unit. Through close contact with the hull, complete passive heat dissipation is achieved using the hull, eliminating the need for active fans or water cooling, greatly improving system reliability. Specifically, the single-board main frequency is 2.3GHz~2.6GHz; the typical power consumption of a single board is 10W@2.3GHz; and the single-board computing power is 36.8GFlops@2.3GHz.

[0035] The board module 20 includes a board and a cold plate. The cold plate is integrated with the chassis 10 housing. While the board size is standardized, the cold plate size can be defined according to the chassis 10. The fastening and positioning holes on the cold plate are used for chassis 10 assembly and also partially reinforce the board. By replacing the cold plate, different task requirements can be met, enabling board reuse.

[0036] Among them, such as Figure 5 The chassis 10's structural design can be broadly divided into two parts: the chassis 10 outer shell and the chassis 10 inner shell. The dimensions of the chassis 10 outer shell meet the actual equipment requirements, while the dimensions of the chassis 10 inner shell are more compact, occupying only a small portion of the chassis 10. The structural dimensions of the chassis 10 inner shell are 125mm (W) × 120mm (H) × 95.89mm (L), and the weight of the inner shell is ≤2.0kg.

[0037] On top of this physical architecture, various board modules 20 are deployed, including a general computing module as the computing core and an interface expansion module as the medium for interaction between the system and the outside world.

[0038] The general-purpose computing module is the main node of the system. It is responsible for running the operating system, scheduling distributed computing tasks, and executing upper-layer applications such as information fusion and decision planning. Its internal computing boards can be compatible with different types of CPUs, such as Phytium, Huawei, Loongson, Rockchip, and RISC-V. The requirements are low power consumption, multi-core, and the ability to undertake scientific computing and other computing tasks. It also manages the heterogeneous computing devices in the system and is the main body for running user applications.

[0039] In a preferred embodiment, the module employs a CPU+FPGA heterogeneous architecture. The core processor (CPU) can be a domestically produced Phytium FT2000 / 4 quad-core processor, responsible for general computing tasks. A high-performance FPGA (such as the Fudan Micro JFM7K325T) connected to the CPU via a PCIe bus serves as the core of the data processing unit (DPU). The FPGA provides multiple high-speed Ethernet channels (e.g., two 10 Gigabit and two Gigabit) to the upper and lower stacking connectors, respectively constructing a data plane network for high-capacity service data and a control plane network for control signaling. Furthermore, the FPGA handles the network protocol stack, converting CPU data access requests (such as memory read / write) into Ethernet packets and sending them to the target module via the internal network; conversely, it parses received network packets and efficiently delivers them to the CPU via DMA or other methods.

[0040] With this design, the CPU frees up power consumption from network I / O transactions and uses it for upper-layer application logic, while enabling transparent access to any remote resource on the network (such as sensors on another computing board or interface board).

[0041] The FT2000 general-purpose computing module in the above embodiments mainly comprises a Phytium FT2000 processor, a Fudan Microelectronics FPGA chip JFM7K325T, DDR4 memory chips, and an M.2 interface NVMe solid-state drive. The FT2000 / 4 general-purpose computing module is a standard PCIe / 104 board with a 22mm height and a passively cooled, conductive cold plate structure. Furthermore, the board design meets the following technical requirements: ① Processor: Phytium FT-2000 / 4 processor, integrating four 64-bit high-performance cores with a main frequency of 2.2GHz; ②Memory: Uses eight 8-bit DDR4 chips to form a 64-bit memory, with a total memory capacity of up to 8GB; ③ Storage: Supports two M.2 interface SSD slots; ④ Bus: Connect one gigabit Ethernet link to each of the upper and lower connectors, and one 10-gigabit Ethernet link (or multiplexed 40GbE) to each of the upper and lower connectors to realize the interconnection of the internal bus of the device; ⑤ Debugging interface: One JTAG interface supporting FPGA logic download and debugging, one Gigabit Ethernet RJ45 interface supporting FPGA debugging, and CPU debug serial port to TeypeC port conversion; ⑥ Power supply: 12V DC power supply; ⑦ Power consumption: Typical power consumption 10W; ⑧ Dimensions: PCIe / 104 standard motherboard, 120mm×95.89mm, board thickness 2.1mm.

[0042] The main heat-generating component on the FT2000 general-purpose computing module is the Phytium D2000 / 4-core processor, with a typical power consumption of 10W but a maximum power consumption of up to 25W. The module's heat dissipation design is based on this maximum power consumption. The general-purpose module employs heat pipe cooling. Copper pipes are designed within the module's heat sink. After the inside of the copper pipes is evacuated, a working fluid is filled in, utilizing the evaporation and condensation of the working fluid to transfer heat. The working fluid absorbs heat as it flows through the various heat dissipation components within the copper pipes, repeatedly circulating through the copper pipes via an evaporation-condensation phase change process, continuously transferring heat from the hot end to the cooling end of the chassis wall. Heat pipe-based cooling offers advantages such as high efficiency, low power consumption, and low noise.

[0043] The core function of the interface expansion module is to connect and convert protocols between the unified Ethernet network within the system and various external devices (sensors and actuators) mounted on the UUV. These external devices typically use non-Ethernet interfaces such as CAN, RS422 / 485, and 1553B.

[0044] Depending on the application requirements, the interface extension module can be designed in different types: For example, the Type I integrated interface module uses an FPGA as its core, integrating multiple interfaces on a single board, such as 16 configurable serial interfaces (RS232 / 422 / 485). Serial baud rate, parity, and data bit information are configurable, and each serial port is individually optically isolated. Depending on the module's board size, J30J series connectors are used to connect to the aviation connectors on chassis 10. The Type I integrated interface module has a high degree of integration and is suitable for mature product forms with fixed interface requirements, serving finalized equipment designs.

[0045] For example, the Type II extended interface module adds a CAN bus interface and an additional gigabit Ethernet interface to the Type I module, which is suitable for scenarios that require CAN bus communication with power systems, navigation systems, etc.

[0046] Its working principle is that the FPGA or onboard controller is responsible for parsing the instruction data packets from the internal Ethernet and driving the corresponding physical interface chips (such as CAN transceivers and serial transceivers) to communicate with external devices; conversely, the data received from external devices is encapsulated into Ethernet data packets and sent to the designated general computing module for processing.

[0047] The system's hardware and software work together, through UEFI firmware and operating system drivers, to achieve network transparency for application software, greatly simplifying the development of upper-layer applications.

[0048] During the system boot phase, the modular design of UEFI (Unified Extensible Firmware Interface) enables it to dynamically discover and initialize various heterogeneous board modules 20 in the stacked system. UEFI is a standard that describes a type of interface for the operating system to automatically load from a pre-boot operating environment onto an operating system. It facilitates the firmware providing sufficient information to ensure the OS remains unaffected when hardware changes occur, including chipset and peripheral chip drivers, and providing boot-time and runtime services through the system table. Before the operating system loads, the UEFI driver can establish the low-level communication protocol between boards.

[0049] UEFI boot uses a modular design, its logic divided into hardware control and OS software management, from hardware to firmware to the UEFI extensible firmware interface and finally to the operating system (OS). UEFI can be further divided into two main parts: the image (UEFI entity) and the platform (platform initialization standard framework). The UEFI image mainly includes the following three parts. UEFI application: Core applications that run after hardware initialization and before the operating system starts, such as boot management, UEFI shell, diagnostics, scheduling, and debugging.

[0050] OS Loaders: Specialized UEFI applications, primarily responsible for starting the operating system and exiting and closing UEFI applications.

[0051] Uefi Drivers: Provides inter-device interface protocols. Each device runs independently, providing device version number, corresponding parameters, and inter-device associations, eliminating the need for OS support.

[0052] The platform initialization framework mainly consists of two parts: PEI: EFI pre-initialization, used to detect the boot mode, load the main memory initialization module, and detect and load the driver execution environment kernel. DXE: Driver Execution Environment (drivers that do not conform to the UEFI standard), which provides a device driver and protocol interface environment.

[0053] After the operating system starts, the high-level device driver works in conjunction with the DPU (FPGA) on the general computing module and the controller on the interface expansion module to virtualize access to remote interfaces on the network into read and write operations on local device files (such as / dev / can0, dev / ttyS1 under Linux).

[0054] Taking underwater topographic mapping and obstacle avoidance tasks as an example, a complete data processing flow is illustrated: S1: The interface expansion module receives RS422 serial data from the sonar and CAN messages from the inertial navigation unit (IMU). Its onboard FPGA encapsulates this data into timestamped Ethernet packets.

[0055] S2: Large data packets such as sonar data packets are sent to the general computing module via a 10 Gigabit data plane network, while control data packets such as IMU data packets are sent via a gigabit control plane network.

[0056] S3: The DPU (FPGA) of the general-purpose computing module receives data packets and efficiently loads them into the CPU memory. The application running on the CPU fuses sonar and IMU data, builds an environmental map, plans obstacle avoidance paths, and finally generates control commands for the servos and propellers.

[0057] S4: Control commands are encapsulated into Ethernet packets and sent via the control plane network to the interface expansion module connected to the actuator. This module parses the commands and sends them to external devices such as servos via the CAN bus or serial port to complete the attitude adjustment of the UUV.

[0058] In summary, this invention constructs a high-performance, highly flexible, and highly reliable integrated electronic computing system for exploration, communication, guidance, and control through standardized mechanical structures, innovative Ethernet stacking interconnection methods, and a transparent access mechanism that integrates software and hardware.

[0059] The technical scope of this invention is not limited to the content described above. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this invention, and all such modifications and variations should fall within the protection scope of this invention.

Claims

1. An electronic computing system based on an underwater unmanned submersible, characterized in that, include: At least one chassis; as well as Multiple board modules are disposed within the chassis, the multiple board modules are mounted in a stacked manner via stacked electrical connectors, and include at least one general-purpose computing module and at least one interface expansion module; The multiple board modules achieve internal data interaction between the boards through high-speed Ethernet. The high-speed Ethernet includes a control plane network for transmitting control signaling and a data plane network for transmitting large-capacity service data, and the transmission rate of the data plane network is higher than that of the control plane network. The general computing module is used to fuse and process the data collected by the interface extension module to generate control commands. The interface extension module is used to connect with the external devices of the underwater unmanned submersible, receive data from the external devices, and output the control commands to the external devices.

2. The electronic computing system according to claim 1, characterized in that, The general-purpose computing module includes a central processing unit and a field-programmable gate array (FPGA), wherein the FPGA serves as a data processing unit for: Convert the central processing unit's data access requests for remote resources into Ethernet packets; Process the network protocol stack to offload the protocol processing burden of the central processing unit; The received Ethernet packets are efficiently delivered to the central processing unit via DMA.

3. The electronic computing system according to claim 1, characterized in that, The control plane network is a gigabit Ethernet network, and the data plane network is a 10-gigabit Ethernet network or a 40-gigabit Ethernet network.

4. The electronic computing system according to claim 1, characterized in that, The system also includes multiple chassis, which are interconnected via an external high-speed network consistent with the internal high-speed Ethernet protocol to enable horizontal expansion of the electronic computing system and to achieve unified addressing and transparent scheduling of all hardware resources at the software level.

5. The electronic computing system according to claim 1, characterized in that, The interface expansion module includes a field-programmable gate array (FPGA), which is used for: Implement the interface protocol for external devices, wherein the interface protocol includes at least one of the following: Controller Area Network Bus Protocol, RS422 Serial Protocol, RS485 Serial Protocol, or RS232 Serial Protocol; The data from the external device is encapsulated into Ethernet packets and transmitted to the general computing module via the high-speed Ethernet.

6. The electronic computing system according to claim 1, characterized in that, The mechanical dimensions of the board module conform to the PCIe / 104 standard or the COME standard, and the system adopts a passive heat dissipation method, with its heat dissipation structure integrated with the hull of the underwater unmanned submersible through the board's cold plate.

7. An electronic computing method based on an underwater unmanned submersible, characterized in that, Applied to the electronic computing system according to any one of claims 1-6, the method comprises: The interface expansion module receives target data from external devices of the underwater unmanned submersible, implements the interface protocol of the external devices through FPGA, and encapsulates the target data into Ethernet data packets. The interface expansion module sends the Ethernet data packets to the general computing module through a high-speed Ethernet control plane network or data plane network. The general computing module parses the received Ethernet data packets through the FPGA and delivers them to the central processing unit via DMA. The central processing unit then performs fusion processing on the target data to generate control instructions. The general computing module sends the control commands to the interface expansion module via the high-speed Ethernet, and the interface expansion module parses and outputs them to the corresponding external devices to execute control operations.

8. The method according to claim 7, characterized in that, The method further includes: The operating system provides a device driver that virtualizes access to remote external devices connected to the interface extension module into read and write operations on local device files, thereby making access to upper-layer applications transparent.

9. The method according to claim 7, characterized in that, The FPGA of the general computing module is connected to the control plane network and the data plane network through multiple high-speed Ethernet channels, including at least two 10 Gigabit Ethernet channels and two Gigabit Ethernet channels.

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