A device for dynamic allocation of on-chip memory in an SOC system
By using a dynamic memory allocation device, and leveraging an interface matrix and multiplexer group, flexible memory allocation and ping-pong operations are achieved. This solves the problems of poor flexibility and reliability caused by fixed memory mapping in SOC systems, and improves the availability and reliability of the system.
CN122111941APending Publication Date: 2026-05-29BEIJING HUAHANG RADIO MEASUREMENT & RES INST
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAHANG RADIO MEASUREMENT & RES INST
- Filing Date
- 2024-12-26
- Publication Date
- 2026-05-29
AI Technical Summary
Technical Problem
The fixed memory mapping method in existing SOC systems results in poor memory usage flexibility, damaged areas affect system availability and reliability, and cannot be expanded.
Method used
A dynamic memory allocation device is adopted, which realizes dynamic memory allocation through interface matrix and multiplexer group, supports ping-pong operation and multiple read and write modes, and adjusts the memory access address of functional modules.
Benefits of technology
It improves the flexibility of memory usage and the availability, reliability and scalability of the system, and can adjust access addresses in a timely manner when memory is damaged to ensure normal system operation.
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Smart Images
Figure CN122111941A_ABST
Abstract
The application relates to a SOC system on-chip memory dynamic allocation device; the device comprises a first group of interfaces: interface 1_a to interface N_a; a second group of interfaces: interface 1_b to interface N_b, on-chip memory and an interface matrix; the on-chip memory is divided into N banks, and each bank is subdivided into M SRAM blocks; the size of the SRAM block is the minimum unit of a memory area; the first group of interfaces is connected with the second group of interfaces through the interface matrix, N interfaces of the second group of interfaces are connected with N banks of the on-chip memory; the corresponding connection of the interface matrix, the first group of interfaces and the second group of interfaces provides a routing mapping, so that the first group of interfaces is connected with corresponding banks of the on-chip memory respectively; and the first group of interfaces is dynamically allocated with the memory through a control mapping path. The application improves the flexibility of on-chip memory use; effectively improves the reliability, robustness and scalability of the whole system operation.
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