A spiking neural network brain-like computing chip supporting on-chip online learning and a control method thereof

Abstract

The application discloses a kind of support on-chip online learning's pulse neural network brain-like computing chip and its control method, the chip contains multiple pulse processing core and on-chip routing network, each pulse processing core integrates neuron circuit array, reconfigurable synapse array and on-chip learning engine, global asynchronous event dispatcher can also be configured to divide inference and learning time window;Chip executes forward inference calculation at the same time, by on-chip learning engine according to pulse time-dependent plasticity rules, combine pulse time information to generate weight update signal, realize in situ update of synapse weight.Corresponding control method is completed by the alternate execution of inference, learning and update steps, and the on-chip online learning closed loop is completed.The application solves the defects of traditional brain-like chip relying on off-chip training, improves the system adaptive capacity and energy efficiency ratio, reduces processing delay, and is suitable for various edge intelligent terminals.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and artificial intelligence technology, specifically to a neuromorphic computing chip for spiking neural networks that supports on-chip online learning and its control method. Background Technology

[0002] Neuromorphic computing, by simulating the impulse information processing mechanism of the biological brain and employing an event-driven asynchronous architecture, enables intelligent tasks such as perception and decision-making with low power consumption, making it an ideal solution for edge computing scenarios. Currently, the industry has developed several neuromorphic chips, such as IBM's TrueNorth and Intel's Loihi, which offer significant improvements in energy efficiency compared to traditional architectures.

[0003] However, existing neuromorphic chips have fundamental limitations: their neural network models (including neuron parameters and synaptic weights) must be pre-trained on off-chip computing platforms (such as GPU / CPU clusters), and then the static model is stored in the chip's memory. During runtime, the chip can only perform forward inference computation and cannot directly adjust model parameters on-chip based on real-time input data streams (i.e., "on-chip online learning"). This separation of "cloud training + edge inference" leads to three major drawbacks: Inadequate adaptability: Unable to cope with dynamically changing environments or non-stationary data streams, such as real-time changing road scenarios in autonomous driving; Energy efficiency bottleneck: Frequent off-chip training and model updates generate a large amount of data migration overhead, significantly increasing total energy consumption; Excessive latency: The closed-loop cycle from perception to learning can take several seconds, which cannot meet the needs of real-time interactive applications.

[0004] Therefore, there is an urgent need in this field for a neuromorphic computing chip architecture and control method that can achieve efficient, low-power on-chip online learning, enabling smart terminals to have real-time autonomous adaptability. Summary of the Invention

[0005] To address the shortcomings of the existing technology, the purpose of this invention is to provide a neuromorphic computing chip for spiking neural networks that supports on-chip online learning and its control method, thereby solving the problems mentioned in the background art.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides a neuromorphic computing chip for spiking neural networks supporting on-chip online learning and its control method, comprising: multiple spiking processing cores and an on-chip routing network connecting each of the spiking processing cores; each spiking processing core includes: a neuronal circuit array for receiving input pulses and performing membrane potential integration and firing judgment; a reconfigurable synaptic array connected to the neuronal circuit array for storing connection weights between neurons and supporting in-situ weight updates; and an on-chip learning engine connected to both the neuronal circuit array and the reconfigurable synaptic array for executing local learning rules to generate weight update signals based on the pulse events generated by the neuronal circuit array, and sending the signals to the reconfigurable synaptic array for online weight updates; wherein the chip is configured to simultaneously run the forward inference computation of the spiking neural network and activate the on-chip learning engine to perform online learning on the reconfigurable synaptic array.

[0007] According to an embodiment of this application, a neuromorphic computing chip for spiking neural networks that supports on-chip online learning and its control method are provided, which realizes real-time online learning of spiking neural networks on the chip and significantly improves the system's adaptive capability and energy efficiency ratio.

[0008] In addition, the neuromorphic computing chip and its control method for supporting on-chip online learning of spiking neural networks proposed in this application may also have the following additional technical features: In one embodiment of this application, the on-chip learning engine is configured to implement a pulse time-dependent plasticity rule, which calculates the weight update amount based on the precise time difference between the firing pulses of the presynaptic neuron and the postsynaptic neuron corresponding to the target synapse.

[0009] In one embodiment of this application, the reconfigurable synaptic array is composed of non-volatile memory cells; the weight update signal is a programming electrical pulse applied to the target non-volatile memory cell to change its conductance state.

[0010] In one embodiment of this application, the non-volatile memory cell is one of resistive random access memory, phase change memory, and ferroelectric memory.

[0011] In one embodiment of this application, a global asynchronous event scheduler is also included, which works in conjunction with each of the pulse processing cores and the on-chip routing network to divide the chip's working time into alternating inference time windows and learning time windows; schedules the transmission and inference calculation of pulse events within the inference time window, and triggers the on-chip learning engine to perform weight update calculations in parallel within the subsequent learning time window.

[0012] The on-chip online learning control method for neuromorphic computing chips includes the following steps: Reasoning steps: The input pulse events are distributed to the target pulse processing core through the on-chip routing network, activating its synaptic array and neuronal circuit array, generating output pulse events, and recording the pulse timing information related to the activated synapses; Learning steps: The on-chip learning engine within the target pulse processing core executes local learning rules to generate weight update amounts based on the recorded pulse time information; Update steps: Apply the weight update amount to the corresponding synapse in the reconfigurable synaptic array to complete the in-situ adjustment of the connection weight.

[0013] In one embodiment of this application, the learning step is performed alternately with the inference step in time; the inference step is executed within each inference time window, and the learning step and the update step are executed together within each subsequent learning time window.

[0014] In one embodiment of this application, the local learning rule is an impulse-time dependent plasticity rule; the learning steps include: Obtain the presynaptic pulse timestamp and postsynaptic pulse timestamp associated with the target synapse; Calculate the time difference between the postsynaptic pulse timestamp and the presynaptic pulse timestamp; Based on the preset STDP function curve, the time difference is mapped to a weight update value.

[0015] An electronic device includes a neuromorphic computing chip and a sensor communicatively connected to the neuromorphic computing chip for providing an input pulse stream.

[0016] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0017] The advantages of this invention compared to existing technologies are: (1) The learning computation is migrated from the remote server or host to the sensing computing terminal (the chip itself), eliminating the power consumption overhead of off-chip data transfer. Simulation verification shows that for typical dynamic visual recognition tasks, the energy consumption of the complete "perception-learning" closed loop can be reduced to less than 20% of the traditional "cloud training + edge inference" mode.

[0018] (2) The system can adjust its own parameters based on new data on a millisecond time scale, enabling robots and smart sensors equipped with the chip to adapt to environmental changes in real time, learn new categories or new patterns, and reduce latency by 1-2 orders of magnitude compared to existing solutions.

[0019] (3) By hardware-based local learning rules through a dedicated learning engine and fine-grained pipeline scheduling of learning events and inference events, the additional power consumption added by the learning process itself accounts for less than 15% of the total power consumption of the chip, thus achieving high-efficiency integration of learning capabilities.

[0020] (4) By configuring parameters such as learning rules and learning rate, the same hardware platform can be applied to a variety of different machine learning tasks, thus enhancing its versatility.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the steps of a neuromorphic computing chip supporting on-chip online learning and its control method in one embodiment of the present invention. Figure 2 This is a schematic diagram of the internal module electrical connection relationship of a spiking neural network neuromorphic computing chip supporting on-chip online learning and its control method according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the timing control of alternating inference and learning execution in a spiking neural network neuromorphic computing chip and its control method that supports on-chip online learning, according to an embodiment of the present invention. Figure 4 This is a flowchart of the internal processing of the on-chip learning engine of a neuromorphic computing chip supporting on-chip online learning and its control method, according to an embodiment of the present invention. Figure 5 This is a flowchart illustrating the in-situ update operation of the synaptic array in an embodiment of the present invention, which describes a neuromorphic computing chip supporting on-chip online learning and its control method. Figure 6 This is a flowchart illustrating the chip operating mode configuration of a neuromorphic computing chip supporting on-chip online learning and its control method, according to an embodiment of the present invention. Figure 7 This is a flowchart illustrating the pulse event routing and transmission process of a spiking neural network neuromorphic computing chip and its control method that support on-chip online learning, according to an embodiment of the present invention. Figure 8This is a flowchart illustrating the multi-core parallel learning process of a neuromorphic computing chip supporting on-chip online learning and its control method, as described in one embodiment of the present invention. Figure 9 This is a flowchart illustrating the collaborative operation of a dynamic visual sensor and chip in a neuromorphic computing chip supporting on-chip online learning and its control method, according to an embodiment of the present invention. Figure 10 This is a flowchart illustrating the weight update verification and error correction process of a neuromorphic computing chip supporting on-chip online learning and its control method, according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] like Figures 1 to 10 As shown in the figure, a neuromorphic computing chip for spiking neural networks that supports on-chip online learning according to an embodiment of the present invention adopts the design concept of "distributed processing + global scheduling" in its core architecture. The chip includes three core modules: multiple spiking processing cores, an on-chip routing network, and a global asynchronous event scheduler. The modules work together to achieve parallel execution of forward inference and on-chip online learning of the spiking neural network.

[0026] In one embodiment of this application, the number of pulse processing cores can be flexibly configured according to the chip's computing power requirements and application scenarios (such as edge terminals, intelligent robots, industrial sensors, etc.). Typical configurations include 16, 32, or 64 pulse processing cores, each arranged in a two-dimensional grid. Adjacent cores communicate with each other via an on-chip routing network with low latency, while non-adjacent cores transmit pulse events across cores through routing nodes. This layout design ensures both high efficiency in inter-core communication and facilitates modular expansion of the chip, allowing the number of pulse processing cores to be increased or decreased according to actual needs.

[0027] In one embodiment of this application, the on-chip routing network serves as a communication hub connecting various pulse processing cores. It employs an event-driven asynchronous routing architecture, primarily composed of routing nodes, data buffer units, and routing control logic. Each routing node corresponds to one pulse processing core or a set of multiple cores. The data buffer unit temporarily stores pulse events to be forwarded (including pulse emission neuron identifiers, pulse timestamps, target core addresses, etc.). The routing control logic determines the optimal forwarding path based on the target address in the pulse event using a shortest path algorithm, achieving accurate and rapid distribution of pulse events among the cores.

[0028] Compared with traditional bus-type or cross-switch-type routing architectures, the on-chip routing network in this embodiment has the following advantages: First, it supports parallel transmission of pulse events, allowing multiple cores to send or receive pulse events simultaneously, thus improving communication bandwidth; second, it adopts an asynchronous communication mode, only starting to work when there is a pulse event transmission, and remaining in a low-power state when there are no events, reducing the overall power consumption of the chip; third, the routing path can be dynamically adjusted, adapting to scenarios of core failure or unbalanced load, thus improving the reliability and flexibility of the chip.

[0029] In one embodiment of this application, the global asynchronous event scheduler works collaboratively with each pulse processing core and the on-chip routing network through a control signal interface. Its core function is to divide the chip's working time into alternating inference time windows and learning time windows, and to perform fine-grained scheduling of task execution within the two time windows.

[0030] The global asynchronous event scheduler has a built-in time window configuration register, which allows software programming to set the duration of the inference and learning time windows. The duration configuration range is from microseconds to milliseconds, adapting to different application scenarios (such as shorter time windows for fast-response real-time perception tasks and longer time windows for complex pattern recognition tasks). The scheduler achieves alternating execution of inference and learning tasks by sending time window switching signals to each pulse processing core and the on-chip routing network: within the inference time window, the scheduler controls the on-chip routing network to prioritize the transmission of input pulse events, and each pulse processing core focuses on performing forward inference calculations; within the learning time window, the scheduler pauses the transmission of non-critical pulse events and triggers the on-chip learning engine within each pulse processing core to perform weight update calculations in parallel, ensuring that the learning process does not affect the real-time performance of the inference task.

[0031] In addition, the global asynchronous event scheduler also has event conflict detection and arbitration functions. When multiple pulse processing cores send pulse events or weight update related signals to the on-chip routing network at the same time, the scheduler avoids signal conflicts and ensures the orderly transmission of data through a priority arbitration mechanism (such as setting priorities according to core number, event type, and task urgency).

[0032] In one embodiment of this application, each pulse processing core serves as the basic computing unit of the chip, integrating three major modules: a neuron circuit array, a reconfigurable synapse array, and an on-chip learning engine. Each module achieves data interaction and control signal transmission through an internal signal bus.

[0033] (I) Design and working principle of neuronal circuit array The neuron circuit array adopts a hybrid analog-digital circuit architecture, consisting of multiple neuron circuit units arranged in a two-dimensional array. Each neuron circuit unit corresponds to a spiking neuron, and the array size can be configured according to the core computing power requirements (e.g., 64×64 or 128×128 neuron circuit units). The core function of the neuron circuit unit is to receive input pulses from the reconfigurable synaptic array, perform membrane potential integration and firing judgment, and output pulse events (including neuron identifiers and pulse timestamps).

[0034] 1. Composition of neuronal circuit units Each neuron circuit unit includes a membrane potential integration module, a threshold comparison module, a pulse firing module, and a timestamp recording module. The specific implementation of each module is as follows: The membrane potential integration module employs a capacitor-resistor (RC) integrator circuit to convert the synaptic current corresponding to the input pulse into a membrane potential signal, which is then accumulated and integrated. The membrane potential integration formula is: V(t) = V_rest + ∫(I_syn(t) / C_m)dt - (V(t) - V_rest) / τ_m, where V_rest is the resting membrane potential, I_syn(t) is the synaptic input current, C_m is the membrane capacitance, and τ_m is the membrane time constant. This module uses an adjustable resistor network to dynamically configure the membrane time constant τ_m, adapting to different types of neuron models (such as the Leaky Integrate-and-Fire model and the Izhikevich model).

[0035] Threshold comparison module: Implemented using a high-speed comparator, it compares the membrane potential V(t) output from the membrane potential integration module with the preset firing threshold V_th in real time. The firing threshold V_th is configured via a digital register and supports dynamic software adjustment, with a range of 0.5V-2.0V (analog voltage value).

[0036] Pulse emission module: When the membrane potential V(t) is greater than or equal to the emission threshold V_th, the pulse emission module generates a standard digital pulse signal (high level 1.8V, low level 0V, pulse width 10ns) and outputs it to the on-chip learning engine and on-chip routing network; at the same time, it triggers the membrane potential reset, pulling the membrane potential back to the resting membrane potential V_rest, in preparation for the next integration.

[0037] Timestamp recording module: It has a built-in high-precision counter (counting clock frequency of 1GHz, time resolution of 1ns) to record the precise time of pulse emission, generate pulse timestamps, and bind the timestamp information with the neuron identifier and store it in the cache unit of the on-chip learning engine.

[0038] 2. Working process of neuronal circuit array The workflow of a neuron circuit array is as follows: It receives input pulse signals from a reconfigurable synapse array, with each input pulse corresponding to the activation of a synaptic connection; The membrane potential integration module performs current-to-voltage conversion and integration on the input pulses of each neuron, updating the membrane potential of the neuron; The threshold comparison module monitors the membrane potential in real time to determine whether the release threshold has been reached. If the membrane potential reaches the emission threshold, the pulse emission module generates a pulse event, and the timestamp recording module records the pulse timestamp. The spike event (neuron identifier + timestamp) is sent to the on-chip learning engine and forwarded to the target spike processing core via the on-chip routing network (if the spike needs to be passed to other cores). The membrane potential is reset, and the next round of membrane potential integration begins.

[0039] (II) Design and Implementation of Reconfigurable Synaptic Arrays Reconfigurable synaptic arrays serve as storage and computation carriers for connection weights between neurons. They employ non-volatile memory units to construct a cross-array structure, enabling both long-term storage of connection weights and in-situ updates of weights without the need for off-chip data transfer.

[0040] 1. Selection and characteristics of non-volatile memory cells In this embodiment, the non-volatile memory cell can be selected from one of resistive random access memory (RRAM), phase change memory (PCM), or ferroelectric RAM (FeRAM). The core characteristics of the three memory cells are as follows: Resistive Random Access Memory (RRAM): Based on the resistive switching effect of metal oxides, by applying programming pulses of different amplitudes and polarities, the conductance of the memory cell can switch between a high-resistance state and a low-resistance state. The change in conductance corresponds to the adjustment of synaptic weights. RRAM cells have advantages such as low programming voltage (1V-3V), fast programming speed (10ns-100ns), high erase / write cycles (10^6-10^8 times), and low power consumption, making them a preferred solution for synaptic arrays.

[0041] Phase-change memory (PCM): Based on the phase-change effect of chalcogenide compounds, it uses electrical pulse heating to switch the material between an amorphous (high resistance) and crystalline (low resistance) state, thereby achieving conductivity regulation. PCM cells feature high storage stability, good conductivity, and strong compatibility with CMOS processes, making them suitable for applications requiring high weighting accuracy.

[0042] Ferroelectric RAM (FeRAM): Based on the polarization reversal effect of ferroelectric materials, the polarization direction of the ferroelectric material is changed by applying an electric pulse, thereby adjusting the capacitance or conductivity characteristics of the memory cell. FeRAM cells have advantages such as fast read / write speed (nanosecond level), extremely low power consumption, and strong radiation resistance, making them suitable for low-power, high-reliability applications.

[0043] In this embodiment, resistive random access memory (RRAM) is preferred as the non-volatile memory cell. Its specific parameters can be configured according to actual needs, such as a programming voltage amplitude of 1.5V-2.5V, a programming pulse width of 50ns, a conductance adjustment range of 1kΩ-100kΩ, and support for 256 levels of conductance quantization (corresponding to 8-bit weighted precision).

[0044] 2. Structural design of reconfigurable synaptic arrays The reconfigurable synaptic array adopts a crossbar structure, and the specific design is as follows: The rows of the array correspond to presynaptic neurons, and the columns correspond to postsynaptic neurons. A resistive random access memory unit is set at the intersection of each row and column, and this unit is a synaptic connection. The conductance of each resistive random access memory (RRAM) cell corresponds to the weight value of the synaptic connection. The larger the conductance, the greater the synaptic weight and the greater the contribution to the membrane potential of the postsynaptic neuron. The array has row drive circuits on the row side to apply gating signals and programming pulses to the target row lines; and column readout circuits on the column side to detect synaptic currents (corresponding to the product of the input pulse and the weight) and transmit the current signals to the membrane potential integration module of the neuron circuit array. The array has a built-in weight configuration interface that connects to the on-chip learning engine to receive weight update signals (programming electrical pulses) and achieve in-situ adjustment of synaptic weights.

[0045] 3. Reconfigurable characteristics of reconfigurable synaptic arrays The "reconfigurability" of reconfigurable synaptic arrays is reflected in two aspects: Reconfigurable connection topology: By controlling the gating of row driving circuits and column readout circuits, specific synaptic connections can be dynamically activated or deactivated, enabling flexible adjustment of the connection topology between neurons. For example, by configuring the gating signals in software, the synaptic array can be configured as fully connected, partially connected, or sparsely connected, adapting to different structures of spiking neural networks (such as convolutional spiking neural networks and recurrent spiking neural networks).

[0046] Reconfigurable weight precision: By adjusting the parameters (amplitude, width, number) of the programmed electrical pulses, weight quantization with different precisions can be achieved, such as 8-bit, 16-bit, or 32-bit weight precision, to meet the computational precision requirements of different tasks. For example, simple perception tasks can use 8-bit weight precision to reduce power consumption; complex pattern recognition tasks can use 16-bit or 32-bit weight precision to improve model performance.

[0047] 4. Operating mode of reconfigurable synaptic array The reconfigurable synaptic array has two operating modes: inference mode and update mode, which correspond to the forward inference and weight update processes of a spiking neural network, respectively. Inference mode: The row drive circuit receives pulse signals from the presynaptic neuron and selects the corresponding row line; the conductance value (synaptic weight) of the resistive random access memory unit converts the pulse signal into synaptic current, the column readout circuit summarizes each synaptic current and transmits it to the membrane potential integration module of the postsynaptic neuron to realize the calculation of "pulse × weight" and complete the synaptic calculation process of forward inference.

[0048] Update mode: Receives weight update signals (programming electrical pulses) from the on-chip learning engine, which contain programming polarity, amplitude, and width information; applies programming electrical pulses to the target resistive random access memory cell according to the parameters of the update signal, adjusts its conductance value, and realizes in-situ update of synaptic weights; after the update is completed, the array automatically switches back to inference mode without affecting subsequent forward inference calculations.

[0049] (III) Design and Functional Implementation of the On-Chip Learning Engine The on-chip learning engine is the core module for realizing on-chip online learning. Through hardware-based local learning rules, it calculates the update amount of synaptic weights in real time based on the pulse events generated by the neuron circuit array, generates the corresponding weight update signal, and sends it to the reconfigurable synaptic array to complete the weight update.

[0050] 1. Hardware implementation of local learning rules In this embodiment, the on-chip learning engine is configured to implement the pulse time-dependent plasticity rule (STDP). This rule is the core mechanism of synaptic plasticity in biological neural networks. Its core idea is that the change in synaptic weight depends on the precise time difference between the firing pulses of the presynaptic neuron and the postsynaptic neuron. Specifically, if the presynaptic neuron fires its pulse first and the postsynaptic neuron fires its pulse later (the time difference is positive), then the synaptic weight is enhanced (long-term potentiation, LTP); if the postsynaptic neuron fires its pulse first and the presynaptic neuron fires its pulse later (the time difference is negative), then the synaptic weight is weakened (long-term inhibition, LTD).

[0051] The on-chip learning engine implements the STDP rules through the following hardware modules: Pulse timestamp cache module: Used to store pulse events (presynaptic / postsynaptic neuron identifier + timestamp) sent by the neuronal circuit array. It adopts a FIFO cache structure with a cache depth of 1024 items to ensure that no pulse time information is lost.

[0052] Time difference calculation module: Implemented using a digital subtractor, it reads the presynaptic pulse timestamp (t_pre) and postsynaptic pulse timestamp (t_post) corresponding to the target synapse from the cache module, and calculates the time difference Δt=t_post-t_pre. The calculation precision of the time difference is 1ns (consistent with the resolution of the timestamp).

[0053] The STDP function mapping module includes a built-in preset STDP function curve, which is either a piecewise linear or nonlinear function that maps the time difference Δt to the corresponding weight update value Δw. The parameters of the STDP function curve (such as the LTP / LTD time window, the maximum weight update magnitude, etc.) can be configured via software programming to adapt to different learning needs. For example, the LTP time window can be configured to 0-20ms, the LTD time window to -20ms-0, and the maximum weight update magnitude to ±10% of the full-scale weight range.

[0054] Weight update calibration module: calibrates the mapped weight update value Δw to ensure that the update value is within the preset weight range (e.g., the weight range corresponding to 0-100kΩ) to avoid weight overflow. If Δw exceeds the weight range, it is truncated to the maximum or minimum value.

[0055] Programming electrical pulse generation module: Based on the calibrated weight update value Δw, it generates the corresponding programming electrical pulse signal. The polarity, amplitude, and width of the programming electrical pulse are related to the weight update value Δw: if Δw is positive (weight enhancement), a positive programming electrical pulse is generated; if Δw is negative (weight weakening), a negative programming electrical pulse is generated; the larger the absolute value of Δw, the larger the amplitude or width of the programming electrical pulse (must be within the rated parameter range of the memory cell).

[0056] 2. Workflow of the on-chip learning engine The workflow of the on-chip learning engine is as follows: (1) Within the inference time window, receive pulse events (presynaptic / postsynaptic neuron identifier + timestamp) sent by the neuron circuit array and store them in the pulse timestamp cache module; (2) When the learning time window is entered, the learning calculation process is started: a. Read the presynaptic pulse timestamp t_pre and postsynaptic pulse timestamp t_post of the target synapse from the cache module; b. The time difference calculation module calculates the time difference Δt = t_post - t_pre; c. The STDP function mapping module obtains the weight update value Δw based on Δt and the preset STDP function curve; d. The weight update calibration module calibrates Δw to ensure it is within the valid range; e. The programming electrical pulse generation module generates the corresponding programming electrical pulse (weight update signal) based on the calibrated Δw. (3) Send the programming electrical pulse to the target synapse in the reconfigurable synapse array to trigger in-situ weight update; (4) Repeat steps 1-3 until the weights corresponding to all cached pulse events are updated, the learning time window ends, the engine enters a low-power waiting state, and waits for the start of the next learning time window.

[0057] In one embodiment of this application, the on-chip online learning control method of the present invention is implemented based on the hardware architecture of the above-mentioned neuromorphic computing chip. The core is to realize the parallel execution of inference and learning by alternating the scheduling of inference time windows and learning time windows, specifically including inference steps, learning steps and update steps.

[0058] (a) The execution process of reasoning steps The inference step is executed within the inference time window. The core task is to complete the forward inference computation of the spiking neural network, generate output pulse events, and record the pulse timing information. The specific process is as follows: 1. Input Pulse Event Distribution: Sensors (such as vision sensors, hearing sensors, and touch sensors) collect external environmental data, convert it into pulse streams (input pulse events), and send them to the neuromorphic computing chip. The on-chip routing network receives the input pulse events and, based on the target core address in the event, distributes the pulse events to the corresponding target pulse processing core through an asynchronous routing architecture.

[0059] 2. Synaptic Array Activation and Computation: The reconfigurable synaptic array of the target pulse processing core receives input pulse events. The row drive circuit selects the corresponding presynaptic neuron row, and the synaptic array enters inference mode. Each activated synaptic connection converts the input pulse into a synaptic current through the conductance value (synaptic weight) of a non-volatile memory unit. The column readout circuit summarizes the synaptic currents and transmits them to the neuronal circuit array.

[0060] 3. Neuronal Membrane Potential Integration and Pulse Fire: Each postsynaptic neuron in the neuronal circuit array integrates the membrane potential of the received synaptic current, and a threshold comparison module monitors the membrane potential in real time. When the membrane potential reaches the firing threshold, the pulse firing module generates an output pulse event, and the timestamp recording module records the pulse timestamp (including the postsynaptic neuron identifier and firing time).

[0061] 4. Pulse Event Forwarding and Recording: Output pulse events are divided into two categories for processing: If the spur event needs to be used as input to the next layer of neurons (neurons in the same core or other cores), it is forwarded to the spur processing core where the target neuron is located through the on-chip routing network; If the pulse event is the final output of the entire neural network (such as classification results, decision instructions, etc.), it is sent to an external execution unit (such as a motor, display, etc.) through the chip's output interface. At the same time, the time information (neuron identifier + timestamp) of all output impulse events is sent to the cache module of the on-chip learning engine to provide data support for subsequent learning steps.

[0062] 5. Inference Time Window End Judgment: The global asynchronous event scheduler monitors the duration of the inference time window in real time. When the preset inference time window duration is reached, an inference end signal is sent, the inference step is terminated, the chip switches to the learning time window, and the learning step is started.

[0063] (II) The Implementation Process of Learning Steps The learning steps are executed within the learning time window. The core process is to calculate the synaptic weight update based on the pulse time information recorded in the inference steps. The specific process is as follows: 1. Pulse timing information reading: The on-chip learning engine receives the learning start signal sent by the global asynchronous event scheduler and reads the pulse timing information recorded in the inference steps from the cache module, including the presynaptic pulse timestamp (t_pre) and postsynaptic pulse timestamp (t_post) corresponding to all activated synapses.

[0064] 2. Target Synapse Selection: The learning engine selects target synapses whose weights need to be updated based on the connection topology information of the spiking neural network (pre-configured in the chip's configuration register). The selection criteria for target synapses are: synapses that are activated during the inference step (i.e., have input or output pulses), and synapses that need to be prioritized for updating according to the learning strategy (such as synapses corresponding to neurons with large errors).

[0065] 3. Time difference calculation: For each target synapse, the time difference calculation module reads its corresponding t_pre and t_post, and calculates the time difference Δt = t_post - t_pre. If the target synapse only receives input pulses but does not generate output pulses (the postsynaptic neuron does not fire pulses), then Δt is processed according to preset rules (such as setting it to a fixed value within the LTD time window, or not updating the weights).

[0066] 4. Weight Update Value Mapping and Calibration: The STDP function mapping module maps Δt to the initial weight update value Δw based on Δt and the preset STDP function curve. The weight update calibration module calibrates Δw to ensure that Δw is within the preset weight update range (e.g., ±5% × full scale of weights) to avoid excessive weight updates that could lead to model instability.

[0067] 5. Weight update value storage: The calibrated weight update value Δw is bound to the address information (row number + column number) of the target synapse and stored in the update queue of the learning engine, waiting for the update step to be executed.

[0068] 6. Learning step end judgment: When the weight update values ​​of all target synapses are calculated, or when the learning time window reaches the preset duration, the learning step ends and the update step begins.

[0069] (III) Execution process of the update step The update and learning steps are executed concurrently within the same learning time window. The core is to apply the calculated weight update amount to the reconfigurable synaptic array to complete the in-situ adjustment of the weights. The specific process is as follows: 1. Update queue reading: The on-chip learning engine reads the address information of the target synapse and the corresponding weight update value Δw sequentially from the update queue.

[0070] 2. Programming Pulse Generation: The programming pulse generation module generates corresponding programming pulse parameters (polarity, amplitude, and width) based on the sign (weight enhancement or reduction) and magnitude (update amplitude) of Δw. For example, when Δw is positive and has a large value, a positive programming pulse with an amplitude of 2.5V and a width of 80ns is generated; when Δw is negative and has a small value, a negative programming pulse with an amplitude of -2.0V and a width of 50ns is generated.

[0071] 3. In-situ update of synaptic weights: The reconfigurable synaptic array receives programming electrical pulses and target synaptic address information. The row drive circuit and column readout circuit select the resistive random access memory (RRAM) cell corresponding to the target synapse and apply the programming electrical pulse to that cell. The conductance value of the RRAM cell changes accordingly based on the parameters of the programming electrical pulse, realizing the in-situ update of synaptic weights (i.e., the application of the weight update value Δw).

[0072] 4. Update Result Verification: After the update is completed, the column readout circuit detects the conductance value of the target synapse to verify whether the weight update meets expectations. If the conductance value does not reach the target value (error exceeds ±2%), the programmed electrical pulse is regenerated for a second update; if the update is successful, the update completion flag is recorded.

[0073] 5. Update step completion judgment: When all target synapses in the update queue have completed weight updates (or are marked as abnormal after a second update failure), the learning time window ends, the global asynchronous event scheduler sends a learning end signal, the chip switches to the next inference time window, and starts a new round of inference steps.

[0074] (iv) The alternating execution mechanism of reasoning and learning The control method of this invention achieves parallel execution of reasoning and learning through the alternating cycle of "inference time window - learning time window". The specific mechanism is as follows: 1. After the chip is powered on, the global asynchronous event scheduler initializes the duration of the inference time window and the learning time window (e.g., the inference time window is 1ms and the learning time window is 0.2ms), and starts the first inference time window; 2. Within the inference time window, each pulse processing core performs forward inference in parallel, the on-chip routing network transmits pulse events, and the on-chip learning engine caches pulse time information; 3. After the inference time window ends, the learning time window is automatically switched to. The on-chip learning engines of each pulse processing core execute the learning steps (calculating the weight update amount) and the update steps (updating the weight in place) in parallel. 4. After the learning time window ends, it automatically switches to the next inference time window, performs forward inference using the updated synaptic weights, and caches new pulse time information at the same time; 5. Repeat the above loop to achieve closed-loop execution of "perception-reasoning-learning-update", enabling the chip to continuously perform on-chip online learning based on real-time input data and dynamically adjust model parameters.

[0075] In one embodiment of this application, the electronic device includes the aforementioned neuromorphic computing chip and sensor. The sensor and the neuromorphic computing chip are connected via a communication interface (such as SPI, I2C, LVDS, etc.). The core function is to collect environmental data through the sensor and convert it into a pulse stream, which is then input to the neuromorphic computing chip for online learning and inference.

[0076] 1. Sensor Types and Configuration The type of sensor is selected based on the application scenario of the electronic device, for example: Intelligent vision devices: Employ dynamic vision sensors (DVS) that generate pulses only when pixel brightness changes. The output pulse stream contains pixel coordinates, the direction of brightness change, and a timestamp, adapting to the event-driven characteristics of spiking neural networks. Intelligent hearing devices: They use microphone arrays and pulse coding modules to convert sound signals into frequency-time domain pulse streams, which are then output to neuromorphic computing chips for tasks such as speech recognition and sound source localization. Intelligent tactile devices: These devices use piezoelectric or capacitive sensors to convert physical quantities such as pressure and vibration into pulse signals, which are used in scenarios such as robot tactile perception and industrial inspection.

[0077] The sensor's pulse output format is matched with the input interface of the neuromorphic computing chip, and the pulse frequency is configured according to application requirements (e.g., 1kHz-1MHz) to ensure that the chip can receive and process the input pulse stream in real time.

[0078] 2. Working process of electronic devices The workflow of electronic devices is as follows: The sensor is activated and collects external environmental data (such as visual images, sound, pressure, etc.). The sensor's built-in signal processing module converts environmental data into a pulse stream (input pulse event) that meets the chip's requirements. The pulse event includes data identifiers, location information, timestamps, etc. The pulse stream is sent to the neuromorphic computing chip via a communication interface; Neuromorphic computing chips perform forward reasoning and on-chip online learning according to the above-mentioned alternating mechanism of "reasoning-learning-updating", and dynamically adjust synaptic weights. Neuromorphic computing chips output reasoning results (such as classification labels, control commands, etc.) and send them to the execution unit of electronic devices (such as displays, motors, alarms, etc.). The execution unit performs corresponding operations based on the inference results, while the sensors continuously collect new environmental data, entering the next round of data processing loop.

[0079] In one embodiment of this application, a computer program is stored on a computer-readable storage medium (such as a USB flash drive, hard disk, ROM, RAM, CD-ROM, non-volatile memory, etc.), which, when executed by a processor, implements the steps of the above-described on-chip online learning control method.

[0080] The core code of a computer program includes the following modules: Time window configuration module: Used to configure the duration of the inference time window and the learning time window, as well as the trigger conditions for switching time windows; Pulse event processing module: used to control the on-chip routing network to distribute input pulse events and record pulse time information; Learning rule implementation module: used to implement STDP rules and calculate synaptic weight update amounts; Weight update control module: used to control the in-situ update of the weights of the reconfigurable synaptic array and verify the update results; System scheduling module: Used to coordinate the execution order of reasoning, learning, and updating steps to ensure that all modules work together.

[0081] When the computer program is executed by the processor, it interacts with the hardware interface of the neuromorphic computing chip to control the various modules of the chip to perform operations according to the above steps, thereby realizing the on-chip online learning function.

[0082] The technical solutions described in the embodiments of this application integrate a pulse processing core, an on-chip routing network, and a global asynchronous event scheduler into a spiking neural network neuromorphic computing chip, and employ an alternating "inference-learning-update" execution mechanism to achieve efficient on-chip online learning functionality. This solution not only addresses the shortcomings of traditional neuromorphic chips in the "cloud training + edge inference" model, such as insufficient adaptability, energy efficiency bottlenecks, and excessive latency, but also possesses advantages such as high energy efficiency, low latency, and high versatility. It can provide strong hardware support for real-time intelligent applications such as autonomous driving, intelligent robots, and edge sensors, and has broad prospects for industrial application.

[0083] Obviously, the above-described embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A neuromorphic computing chip supporting on-chip online learning of spiking neural networks, characterized in that, include: Multiple pulse processing cores, and an on-chip routing network connecting each of the pulse processing cores; Each of the pulse processing cores includes: Neuron circuit arrays are used to receive input pulses and perform membrane potential integration and firing judgment; A reconfigurable synaptic array, connected to the neuron circuit array, is used to store connection weights between neurons and support in-situ updates of the weights; An on-chip learning engine is connected to the neuron circuit array and the reconfigurable synapse array, respectively, and is used to execute local learning rules to generate a weight update signal based on the pulse events generated by the neuron circuit array, and send the signal to the reconfigurable synapse array for online weight update; The chip is configured to simultaneously perform forward inference computation of the spiking neural network and activate the on-chip learning engine to perform online learning on the reconfigurable synaptic array.

2. The neuromorphic computing chip for spiking neural networks supporting on-chip online learning according to claim 1, characterized in that, The on-chip learning engine is configured to implement the pulse time-dependent plasticity rule, which calculates the weight update amount based on the precise time difference between the firing pulses of the presynaptic neuron and the postsynaptic neuron corresponding to the target synapse.

3. The neuromorphic computing chip for supporting on-chip online learning of spiking neural networks according to claim 1, characterized in that, The reconfigurable synaptic array is composed of non-volatile memory cells; the weight update signal is a programming electrical pulse applied to the target non-volatile memory cell to change its conductance state.

4. A neuromorphic computing chip supporting on-chip online learning of a spiking neural network according to claim 3, characterized in that, The non-volatile memory unit is one of resistive random access memory, phase change memory, and ferroelectric memory unit.

5. A neuromorphic computing chip supporting on-chip online learning of spiking neural networks according to claim 1, characterized in that, It also includes a global asynchronous event scheduler, which works in conjunction with each of the pulse processing cores and the on-chip routing network to divide the chip's working time into alternating inference time windows and learning time windows; schedules the transmission and inference calculation of pulse events within the inference time window, and triggers the on-chip learning engine to perform weight update calculations in parallel within the following learning time window.

6. An on-chip online learning control method for a neuromorphic computing chip according to any one of claims 1-5, characterized in that, Includes the following steps: Reasoning steps: The input pulse events are distributed to the target pulse processing core through the on-chip routing network, activating its synaptic array and neuronal circuit array, generating output pulse events, and recording the pulse timing information related to the activated synapses; Learning steps: The on-chip learning engine within the target pulse processing core executes local learning rules to generate weight update amounts based on the recorded pulse time information; Update steps: Apply the weight update amount to the corresponding synapse in the reconfigurable synaptic array to complete the in-situ adjustment of the connection weight.

7. The method according to claim 6, characterized in that, The learning steps alternate with the inference steps in time; the inference steps are executed within each inference time window, and the learning steps and update steps are executed together within each subsequent learning time window.

8. The method according to claim 6, characterized in that, The local learning rule is an impulse-time dependent plasticity rule; the learning steps include: Obtain the presynaptic pulse timestamp and postsynaptic pulse timestamp associated with the target synapse; Calculate the time difference between the postsynaptic pulse timestamp and the presynaptic pulse timestamp; Based on the preset STDP function curve, the time difference is mapped to a weight update value.

9. An electronic device, characterized in that, It includes a neuromorphic computing chip as described in any one of claims 1-5, and a sensor communicatively connected to the neuromorphic computing chip for providing an input pulse stream.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps of the method as described in any one of claims 6 to 8.

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