A synchronization module, a synchronization control method and a data processing system

Abstract

The application relates to the technical field of computer application, and particularly discloses a synchronization module, a synchronization control method and a data processing system, wherein the synchronization module at least comprises an instruction queue and a state score board; the instruction queue is used for saving processing instructions of a first processor, forwarding the processing instructions to a second processor, and feeding back processing results generated by the second processor to the first processor; and the state score board is used for recording a working state of the second processor and feeding back the working state to the first processor. The embodiment of the application can solve the data synchronization control problem between different processors, reduce the software complexity of the data synchronization process, and thus reduce the overall power consumption of the system.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and in particular to a synchronization module, a synchronization control method, and a data processing system. Background Technology

[0002] Reduced Instruction Set Computing – V (RISC-V) architecture, due to its flexibility, openness, and scalability, is gradually becoming the mainstream architecture for artificial intelligence (AI) accelerator chips, allowing for customization to meet the needs of chip designers. Currently, AI chips typically consist of a RISC-V processor core and an AI coprocessor. The RISC-V processor core requires less computational power to perform control functions, while the AI ​​coprocessor provides the main computational power. The configuration, startup, and status feedback of the AI ​​coprocessor are often controlled by the RISC-V processor core. In many cases, the RISC-V processor core and the AI ​​coprocessor also need to interact with each other; for example, the AI ​​coprocessor may need data computed by the RISC-V processor core, or vice versa. Therefore, a synchronization mechanism is needed between the RISC-V processor core and the AI ​​coprocessor to enable the RISC-V processor core to control and manage the AI ​​coprocessor, the AI ​​coprocessor to provide status feedback to the RISC-V processor core, and the RISC-V processor core and AI coprocessor to synchronize data. Summary of the Invention

[0003] This invention provides a synchronization module, a synchronization control method, and a data processing system, aiming to solve the data synchronization control problem between different processors, thereby reducing the software complexity of the data synchronization process and reducing the overall power consumption of the system.

[0004] According to one aspect of the present invention, a synchronization module is provided, wherein the synchronization module includes at least an instruction queue and a status scoring board; The instruction queue is used to store the processing instructions of the first processor, forward the processing instructions to the second processor, and feed back the processing results generated by the second processor to the first processor. The status scoring board is used to record the working status of the second processor and feed the working status back to the first processor.

[0005] According to another aspect of the present invention, a synchronization control method is also provided, wherein the method includes: Receive processing instructions sent by the first processor and save the processing instructions to the instruction queue; If the second processor is determined to be in an idle state based on the status scoreboard, the processing instructions stored in the instruction queue are transmitted to the second processor. The second processor receives the processing result from the instruction queue and then feeds the processing result back to the first processor.

[0006] According to another aspect of the present invention, a data processing system is provided that includes at least: First processor, second processor, and synchronization module; The synchronization module is used to execute any of the synchronization control methods described in the embodiments of the present invention.

[0007] The technical solution of this invention provides a synchronization module, which consists of an instruction queue and a status scoring board. The instruction queue is used to store the processing instructions of the first processor, forward the processing instructions to the second processor, and feed back the processing results generated by the second processor to the first processor. The status scoring board is used to record the working status of the second processor and feed back the working status to the first processor. Thus, data synchronization between the first processor and the second processor is realized based on the synchronization module, which can improve the parallel processing efficiency of instructions, reduce the software complexity of data synchronization, and reduce the power consumption of the data synchronization process.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of an existing architecture for inter-processor data synchronization; Figure 2 This is a schematic diagram of another inter-processor data synchronization architecture in the existing technology; Figure 3 This is a schematic diagram of the structure of a synchronization module according to an embodiment of the present invention; Figure 4 This is a schematic diagram of another synchronization module provided according to an embodiment of the present invention; Figure 5 This is a structural example diagram of another synchronization module provided according to an embodiment of the present invention; Figure 6 This is an example diagram of the encoding of a WEF instruction provided according to an embodiment of the present invention; Figure 7 This is a flowchart of a synchronization control method provided according to an embodiment of the present invention; Figure 8 This is a flowchart of another synchronization control method provided according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a data processing system provided according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of an electronic device that implements the synchronization control method of the present invention. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Currently, the synchronization mechanisms between RISC-V processor cores and AI coprocessors are mainly divided into two types: asynchronous synchronization and synchronous synchronization. In the asynchronous synchronization mechanism, the RISC-V processor core and the AI ​​coprocessor are asynchronous; the RISC-V processor core can perform its own tasks without waiting for the AI ​​coprocessor to complete its processing. In the synchronous synchronization mechanism, the instructions processed by the AI ​​coprocessor are part of the RISC-V processor core's operation. The RISC-V processor core needs to wait, check the status of the AI ​​coprocessor, and wait until the AI ​​coprocessor completes its operation. See also... Figure 1Some designs employ a synchronous mechanism, which is simple to design and easy to implement. However, because the execution of the AI ​​coprocessor blocks the execution of the RISC-V processor core, its overall efficiency is relatively low. While the AI ​​coprocessor is executing AI instructions, the RISC-V processor core cannot execute non-AI instructions. See also... Figure 2 Some designs employ asynchronous synchronous mechanisms, allowing the RISC-V processor core to execute additional instructions while the AI ​​coprocessor executes its own instructions. However, this uses a polling approach, requiring the RISC-V processor core to periodically poll the AI ​​coprocessor's execution status to ensure it can continue executing new AI coprocessor instructions after the latter has finished. While the RISC-V processor core can execute non-AI instructions while the AI ​​coprocessor executes AI instructions, it still needs to poll the AI ​​coprocessor's status after completing these non-AI instructions, continuing this polling until the AI ​​coprocessor finishes execution. This increases software complexity, and the polling operation of the RISC-V processor core also adds to power consumption.

[0014] Figure 3 This is a schematic diagram of a synchronization module according to an embodiment of the present invention. This embodiment is applicable to data synchronization between different processors. See also... Figure 3 The synchronization module provided in this embodiment of the invention includes at least an instruction queue 101 and a status scoring board 102. The instruction queue 101 is used to store the processing instructions of the first processor, forward the processing instructions to the second processor, and feed back the processing results generated by the second processor to the first processor. The status scoring board 102 is used to record the working status of the second processor and feed back the working status to the first processor.

[0015] In this embodiment of the invention, the first processor and the second processor can be processor chips that require data synchronization. The first processor and the second processor can have different functions; for example, the first processor can be a RISC-V processor, while the second processor is an AI coprocessor. The synchronization module can provide data synchronization functionality between the first processor and the second processor. The instruction queue 101 can be implemented through a FIFO cache array. The instruction queue 101 can store the processing instructions sent by the first processor and send the stored processing instructions to the second processor for processing. The instruction queue 101 can send the previously stored processing instructions to the second processor first. The status scoring board 102 can be implemented through registers. The status scoring board 102 can store the current working state of the second processor, thereby temporarily storing the processing instructions and avoiding active detection of the working state of the second processor, which can reduce the waiting time for the transmission of the working state. The working state stored in the status scoring board 102 can also be obtained by the first processor so that the first processor can know the working state of the second processor, thereby facilitating the scheduling of processing instructions by the first processor.

[0016] Based on the above embodiments of the invention, see [link to invention]. Figure 4 The synchronization module provided in this embodiment of the invention also includes an exception management unit 103, which is used to obtain the exception status information of the second processor and send the exception status information to the first processor.

[0017] Specifically, the synchronization module may further include an exception management unit 103, which can be implemented via registers. This exception management unit 103 can receive exception status information sent by the second processor. This exception status information indicates that the second processor cannot execute processing instructions. The exception status information can be triggered by the second processor's own exception status or by an exception status based on a processing instruction. When the second processor determines that it is in an exception status or that a processing instruction is in an exception status, it can send exception status information to the exception management unit 103 of the synchronization module. The exception management unit 103 can save this exception status information. Furthermore, the exception management unit 103 can also send this exception status information to the first processor, thereby enabling the first processor to obtain the exception status of the second processor.

[0018] Based on the above embodiments of the invention, the synchronization module further includes at least a source operation register and a timeout register. The source operation register is used to store a synchronization mask, which is used to verify the working state. The timeout register is used to store the timeout time, which is used to determine the timeout status of the processing instruction.

[0019] Specifically, the synchronization module may further include a source operation register and a timeout register. The source operation register can be used to store a synchronization mask, which can be pre-configured mask information. This synchronization mask can be verified by checking the working state stored on the status scoring board 102. The verification process of the working state using the synchronization mask can be obtained through logical operations. For example, the synchronization mask and the working state can be bitwise ANDed, and the specific situation of the working state can be determined by whether the operation result is a specific value. Of course, the above logical operation methods are only examples and are not limited. Other logical operation methods such as OR, XOR, etc. are also within the scope of protection of this invention. The timeout register is used to store the timeout time of the processing instruction. If the time taken for the synchronization module and / or the second processor to process the instruction exceeds the timeout time stored in the timeout register, the processing instruction can be determined to be in an abnormal state.

[0020] Based on the above embodiments of the invention, the synchronization module further includes a mode selection register, which is used to store the processing mode of the processing instructions processed by the synchronization module. The processing mode includes at least a first mode in which the synchronization module cooperates with the second processor to process the processing instructions or a second mode in which the synchronization module does not cooperate with the second processor to process the processing instructions.

[0021] In this embodiment of the invention, the synchronization module may further include a mode selection register, which can store processing modes. Different processing modes can correspond to the processing methods of the synchronization module for processing instructions. For example, if the processing mode stored in the mode selection register of the processing instruction is the first mode, then the synchronization module does not perform cooperative synchronization operation on the processing instruction. Alternatively, if the processing mode stored in the mode selection register of the processing instruction is the second mode, then the synchronization module performs cooperative synchronization on the processing instruction.

[0022] In one exemplary implementation, see Figure 5 This invention provides a synchronization module that can be used as a mechanism for synchronization between a RISC-V processor core and an AI coprocessor. Based on the flexibility of the RISC-V architecture and the specific characteristics of the AI ​​coprocessor, an asynchronous synchronization method is adopted, improving the parallel efficiency of instructions. By extending the WFE (Wait For Event) instructions in the RISC-V instruction set, low power consumption during synchronization is achieved, and software complexity is reduced. It is understood that the hardware synchronization module is decoupled from the RISC-V processor core and the AI ​​coprocessor. The synchronization module can be implemented in two parts: part A is the structural design of the synchronization module, and part B is the extended WFE instructions in the RISC-V processor core.

[0023] The synchronization module in Part A mainly includes an instruction queue (1), a status scoring board (2), and an exception management unit (3).

[0024] The instruction queue (1) is mainly responsible for receiving instructions sent by the RISC-V processor core, feeding back the processing results corresponding to the instructions to the RISC-V processor core, caching and forwarding AI instructions to the AI ​​coprocessor, and handling the dependencies between AI instructions.

[0025] The status scoreboard (2) is used to record the working status of the modules in the AI ​​coprocessor. When a module in the AI ​​coprocessor is working, the scoreboard will be set to busy; when a module in the AI ​​coprocessor is idle, the scoreboard will be set to idle. The status of the scoreboard will be fed back to the RISC-V processor core so that the RISC-V processor core can perform corresponding operations.

[0026] The exception management unit (3) is used to manage exceptions of the AI ​​coprocessor. If an exception or error occurs in the AI ​​coprocessor, this information will be sent to the exception management unit, which is responsible for notifying the RISC-V processor core of the status.

[0027] Based on the above embodiments, the AI ​​instruction in Part B is implemented using an extended WFE instruction. This AI instruction can be configured with a timeout function. If the AI ​​instruction is not activated within a specified time, a timeout exception is entered. Software developers can find the specific cause of the exception within the timeout exception so as to perform corresponding processing.

[0028] See Figure 6 The AI ​​instruction can be encoded using WFE instructions, which are extensions based on the RISC-V standard instruction set. Figure 6 The rs1 parameter indicates the source operation register, which stores the synchronization mask. This mask can be logically manipulated with the value in the synchronization module's status scoring board to determine whether synchronization waiting is necessary. In addition, the synchronization module includes a timeout register, which stores the timeout period. When the mode field in the sent WFE instruction carries a start timeout flag, the value in the timeout register will be used to determine if synchronization has timed out. The mode selection field in the WFE instruction encoding provides backward compatibility.

[0029] In this embodiment of the invention, when the RISC-V processor core decodes an AI instruction, it sends the AI ​​instruction to synchronization module A, which then provides feedback on the result of the instruction. Upon receiving the result, the RISC-V processor core can continue executing other instructions. Simultaneously, synchronization module A forwards the AI ​​instruction to the AI ​​coprocessor based on the status recorded in the status scoreboard, and updates the status scoreboard based on the transmission result fed back by the AI ​​coprocessor. When synchronization is required, the RISC-V processor core executes the WFE instruction, enters a sleep state, and waits to be woken up. When the AI ​​coprocessor finishes executing the AI ​​instruction, it notifies the synchronization module, which updates the status scoreboard and wakes up the RISC-V processor core, thus completing the synchronization. The RISC-V processor core can then continue executing subsequent instructions.

[0030] Figure 7 This is a flowchart of a synchronization control method according to an embodiment of the present invention. This embodiment is applicable to data synchronization between different processors. The method can be executed by a synchronization module, which can be implemented in hardware and / or software. Figure 7 As shown, the method includes: Step 210: Receive the processing instructions sent by the first processor and save the processing instructions to the instruction queue.

[0031] In this embodiment of the invention, after receiving the processing instruction sent by the first processor, the synchronization module can temporarily store the processing instruction in the instruction queue so that the first processor can process the processing instruction in parallel. The depth of the instruction queue can match the maximum number of parallel processing instructions in the first processor. For example, the depth of the instruction queue can be equal to or greater than the maximum number of parallel processing instructions.

[0032] Step 220: Determine that the second processor is in an idle state based on the status scoreboard, and transfer the processing instructions stored in the instruction queue to the second processor.

[0033] Specifically, the working status saved on the status scoreboard can be judged. If the working status indicates an idle state, it is determined that the second processor is currently in an idle state. The processing instruction saved at the head of the instruction queue can be popped and transmitted to the second processor so that the second processor can execute the processing instruction.

[0034] Step 230: Receive the processing result from the second processor according to the instruction queue, and then send the processing result back to the first processor.

[0035] In this embodiment of the invention, after executing the processing instruction, the second processor can generate a corresponding processing result. The second processor can send the processing result to the instruction queue of the synchronization module, and the instruction queue can send the processing result to the first processor.

[0036] In this embodiment of the invention, the processing instructions sent by the first processor are received and stored through an instruction queue. The second processor is determined to be in an idle state based on a status scoring board. The processing instructions stored in the instruction queue are then sent to the second processor. The processing results fed back by the second processor are obtained according to the instruction queue and sent back to the first processor, thereby completing the data synchronization between the first and second processors. This embodiment of the invention achieves data synchronization between the first and second processors based on a synchronization module, which can improve the parallel processing efficiency of instructions, reduce the software complexity of data synchronization, and reduce the power consumption of the data synchronization process.

[0037] Furthermore, based on the above embodiments of the invention, it also includes: determining that the exception management unit receives the exception status information sent by the second processor, and transmitting the exception status information to the first processor.

[0038] In this embodiment of the invention, when the abnormality management unit receives the abnormality status information sent by the second processor, it can send the abnormality status information to the first processor, so that the first processor can perform corresponding operations according to the abnormality status information. It can be understood that the abnormality status information may include a processing instruction abnormality or a second processor abnormality. For example, if the abnormality status information is that the processing instruction is a timeout abnormality, the first processor can resend the processing instruction. If the abnormality status information is that the second processor is abnormal, the execution of the processing instruction can be stopped and alarm information can be generated.

[0039] In some embodiments of the invention, the abnormal status information is generated by the second processor based on the timeout period stored in the timeout register within the synchronization module.

[0040] Specifically, the abnormal status information can be generated by the second processor. When processing the processing instruction, the second processor can read the timeout time stored in the timeout register in the synchronization module. If the current time of the second processor executing the processing instruction is greater than the timeout time, the second processor can generate abnormal status information for the processing instruction and feed the abnormal status information back to the abnormal management unit of the synchronization module. The abnormal management unit of the synchronization module can receive the abnormal status information and feed it back to the first processor, so that the first processor can perform the corresponding operation according to the abnormal status information.

[0041] Based on the above embodiments of the invention, the method further includes: determining the working state of the second processor, and adjusting the status scoreboard to a busy state or an idle state according to the working state.

[0042] In this embodiment of the invention, the synchronization module can determine the working state of the second processor and set the status scoreboard to a busy state or an idle state according to the different working states of the second processor. It is understood that the busy state or the idle state can be represented by different values. For example, the busy state can be represented by setting the status scoreboard to 1, while the idle state can be represented by setting the status scoreboard to 0, etc.

[0043] Figure 8 This is a flowchart of another synchronization control method provided by an embodiment of the present invention. This embodiment of the present invention describes the adjustment process of the state scoreboard in the above embodiment. See [link to flowchart]. Figure 8 The method provided in this embodiment of the invention specifically includes the following steps: Step 310: Receive the processing instructions sent by the first processor and save the processing instructions to the instruction queue.

[0044] Step 320: Determine that the second processor is in an idle state based on the status scoreboard, and transfer the processing instructions stored in the instruction queue to the second processor.

[0045] Step 330: If a busy status indication is received from the second processor, the status scoreboard is set to busy status.

[0046] The busy status indicator can be an indication message sent by the second processor, indicating that the second processor is in a busy state and is currently executing processing instructions.

[0047] Specifically, when the synchronization module receives a busy status indication sent by the second processor, it can set the status scoreboard to a busy state.

[0048] Step 340: Receive the processing result fed back by the second processor according to the instruction queue, and feed the processing result back to the first processor.

[0049] Step 350: Upon receiving the processing result from the second processor, the status scoring board is set to idle state.

[0050] In this embodiment of the invention, when the synchronization module receives the processing result fed back by the second processor through the instruction queue, it can synchronously set the status scoring board to an idle state. At this time, the second processor can obtain new processing instructions for processing. If there are saved processing instructions in the instruction queue, the processing instructions at the head of the queue can be popped and sent to the second processor for execution.

[0051] In this embodiment of the invention, processing instructions from the first processor are received and stored through an instruction queue. If the second processor is determined to be in an idle state according to the status scoreboard, the processing instructions in the instruction queue are sent to the second processor. When a busy status indication is received from the second processor, the status scoreboard is set to a busy state. The processing result from the second processor is obtained through the instruction queue and sent to the first processor. When the processing result is received, the status scoreboard is set to an idle state. This embodiment of the invention achieves data synchronization between the first and second processors based on a synchronization module, which can improve the parallel processing efficiency of instructions, reduce the software complexity of data synchronization, and reduce the power consumption of the data synchronization process.

[0052] Figure 9 This is a schematic diagram of the structure of a data processing system according to an embodiment of the present invention. See also: Figure 9 The data processing system provided in this embodiment of the invention includes at least a first processor, a second processor, and a synchronization module. The synchronization module is used to execute a synchronization control method, which includes: Receive processing instructions sent by the first processor and save the processing instructions to the instruction queue; Based on the status scoreboard, the second processor is determined to be in an idle state, and the processing instructions stored in the transmission instruction queue are transferred to the second processor; The system receives the processing results from the second processor according to the instruction queue and then feeds the processing results back to the first processor.

[0053] Based on the above embodiments of the invention, it further includes: determining that the exception management unit receives the exception status information sent by the second processor, and transmitting the exception status information to the first processor.

[0054] Based on the above embodiments of the invention, the abnormal status information is generated by the second processor based on the timeout time stored in the timeout register in the synchronization module.

[0055] In some embodiments of the invention, the method further includes: determining the working state of the second processor and adjusting the state scoreboard to a busy state or an idle state according to the working state.

[0056] Based on the above embodiments of the invention, the working state of the second processor is determined, and the status scoreboard is adjusted to a busy state or an idle state according to the working state, including at least one of the following: If a busy status indication is received from the second processor, the status scoreboard is set to busy status. Once the processing result is received from the second processor, the status scoreboard is set to idle state.

[0057] Figure 10This is a schematic diagram of the structure of an electronic device implementing the synchronization control method of embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0058] like Figure 10 As shown, the electronic device 10 includes at least one data processing system 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one data processing system 11. The memory stores computer programs executable by the at least one data processing system 11. The data processing system 11 can perform various appropriate actions and processes based on the computer programs stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The data processing system 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0059] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0060] The data processing system 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the data processing system 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various data processing systems running machine learning model algorithms, digital signal data processing systems (DSPs), and any suitable data processing system, controller, microcontroller, etc. The data processing system 11 performs the various methods and processes described above, such as synchronous control methods.

[0061] In some embodiments, the synchronization control method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by data processing system 11, one or more steps of the synchronization control method described above may be performed. Alternatively, in other embodiments, data processing system 11 may be configured to perform the synchronization control method by any other suitable means (e.g., by means of firmware).

[0062] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable data processing system, which may be a dedicated or general-purpose programmable data processing system, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0063] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a data processing system of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the data processing system, the functions / operations specified in the flowcharts and / or block diagrams are performed. The computer programs can be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0064] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0065] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0066] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0067] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0068] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A synchronization module, characterized in that, The synchronization module includes at least an instruction queue and a status scoring board; The instruction queue is used to store the processing instructions of the first processor, forward the processing instructions to the second processor, and feed back the processing results generated by the second processor to the first processor. The status scoring board is used to record the working status of the second processor and feed the working status back to the first processor.

2. The synchronization module according to claim 1, characterized in that, The synchronization module further includes an exception management unit, which is used to obtain the exception status information of the second processor and send the exception status information to the first processor.

3. The synchronization module according to claim 1, characterized in that, The synchronization module further includes a source operation register and a timeout register. The source operation register is used to store a synchronization mask, which is used to verify the working state. The timeout register is used to store a timeout period, which is used to determine the timeout status of the processing instruction.

4. The synchronization module according to claim 3, characterized in that, The synchronization module further includes a mode selection register, which stores the processing mode of the synchronization module in processing the processing instruction. The processing mode includes at least a first mode in which the synchronization module cooperates with the second processor to process the processing instruction or a second mode in which the synchronization module does not cooperate with the second processor to process the processing instruction.

5. A synchronization control method, characterized in that, Applied to a synchronization module, the method includes: Receive processing instructions sent by the first processor and save the processing instructions to the instruction queue; If the second processor is determined to be in an idle state based on the status scoreboard, the processing instructions stored in the instruction queue are transmitted to the second processor. The second processor receives the processing result from the instruction queue and then feeds the processing result back to the first processor.

6. The method according to claim 5, characterized in that, Also includes: The abnormality management unit receives the abnormality status information sent by the second processor and transmits the abnormality status information to the first processor.

7. The method according to claim 6, characterized in that, The abnormal status information is generated by the second processor based on the timeout period stored in the timeout register within the synchronization module.

8. The method according to claim 5, characterized in that, Also includes: Determine the operating state of the second processor, and adjust the status scoreboard to either a busy or idle state according to the operating state.

9. The method according to claim 8, characterized in that, Determining the operating state of the second processor and adjusting the status scoreboard to a busy or idle state according to the operating state includes at least one of the following: If a busy status indication is received from the second processor, the status scoreboard is set to a busy status. Upon receiving the processing result from the second processor, the status scoring board is set to an idle state.

10. A data processing system, characterized in that, The data processing system includes at least: First processor, second processor, and synchronization module; The synchronization module is used to execute the synchronization control method according to any one of claims 5-9.

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