Architecture vulnerability factor calculation method and device based on function simulation

Abstract

The embodiment of the application discloses a kind of based on function simulation architecture vulnerability factor calculation method and device, the method comprises: according to circuit design source file, circuit compilation is generated simulation data and circuit topology chart;According to test excitation and simulation data, function simulation is formed at each simulation time simulation result data;Simulation result data is backfilled into circuit topology chart, determines the visible input end information of each signal node in circuit under each simulation time;The visible input end information of each signal node under each simulation time is summarized and analyzed, determines the target time window that each signal node corresponding soft error can be observed;For each signal node, the proportion of its corresponding target time window in entire simulation period is calculated as the architecture vulnerability factor data of this signal node.The application greatly reduces the time overhead required for AVF data calculation, effectively improves the calculation efficiency of AVF data.

Description

Technical Field

[0001] This application relates to the field of Internet technology, specifically to a method and apparatus for calculating architectural vulnerability factors based on functional simulation. Background Technology

[0002] The Architectural Vulnerability Factor (AVF) refers to the probability that a soft error occurring in the circuit will propagate through the circuit design structure, eventually reaching the functional output and causing visible errors. Typically, each signal line and register in a circuit system has an AVF value, which measures the impact of a soft error on the overall circuit functionality. A lower AVF value indicates a lower probability of a soft error at that point causing visible errors in the system. Therefore, AVF is a crucial metric in high-reliability chip design. To improve chip design reliability while reducing hardware hardening costs, designers need to identify circuit sections with high AVF values ​​and perform targeted physical or logical hardening to meet the functional safety requirements of the entire circuit.

[0003] Soft errors in circuits refer to temporary errors in circuit state caused by external interference (such as bombardment by high-energy particles) or internal noise, without permanent damage to the circuit hardware itself. These errors typically manifest as data flips in memory cells, logic state transitions, or signal transmission errors. The system can continue to operate after the error occurs, but may produce incorrect results. Single Event Upset (SEU) and Single Event Transient (SET) are two important types of soft errors in semiconductor devices, affecting the stability of digital integrated circuits. SEU occurs in memory cells (such as SRAM, DRAM, or registers), where bombardment by high-energy particles causes logic state flips (e.g., 0 becomes 1 or vice versa), leading to data corruption or calculation errors. SET primarily affects combinational logic circuits; high-energy particles generate brief voltage pulses, causing transient errors in the output. SET is usually extremely short-lived and may be corrected by circuit recovery or error correction mechanisms. However, if it occurs in critical paths such as clock or control signals, it can disrupt signal integrity and indirectly lead to system function interruption. Both originate from single-event effects, but SEU targets storage nodes, while SET targets logic nodes.

[0004] Throughout the entire circuit system's operating cycle, errors may occur randomly at any time and location, but not every error will propagate to the functional output and produce an observable error result. During the propagation of soft errors, they may be masked by various reasons, such as logical de-rating (LDR), temporal de-rating (TDR), functional de-rating (FDR), and electrical de-rating (EDR), so that no observable error appears at the functional output, thus preventing the triggering of a serious functional error.

[0005] AVF (Active Functional Frame) data is a crucial parameter for high-reliability circuit design. To ensure circuits meet functional safety requirements, designers must invest significant time and effort in analyzing and acquiring AVF parameters. Currently, there is no standard method for accurately calculating AVF. In practice, designers often estimate AVF parameters through experience or use EDA tools for circuit simulation. To obtain accurate AVF data, current techniques require designers to perform extensive simulation tests using EDA tools, simulating the impact of soft errors occurring at a specific point in time on the observed results. As circuit designs grow in scale, this comprehensive approach incurs substantial time overhead, resulting in high computational costs and low AVF calculation efficiency, increasingly failing to meet designers' needs. Summary of the Invention

[0006] In view of the above problems, this application proposes a method and apparatus for calculating architectural vulnerability factors based on functional simulation, which is used to solve the following problems: existing methods for calculating architectural vulnerability factors have high time overhead and low computational efficiency.

[0007] According to one aspect of the embodiments of this application, a method for calculating architectural vulnerability factors based on functional simulation is provided, comprising: Obtain the circuit design source file, compile the circuit based on the circuit design source file, and generate simulation data and circuit topology diagram; Functional simulation is performed based on test stimuli and simulation data to generate simulation result data at each simulation moment; The simulation results data at each simulation time are backfilled into the circuit topology diagram to determine the visible input terminal information of each signal node in the circuit at each simulation time. The visible input information of each signal node at each simulation time is summarized and analyzed to determine the target time window in which the soft error of each signal node can be observed. For each signal node, calculate the proportion of the target time window corresponding to that signal node to the entire simulation cycle, and use the proportion as the architecture vulnerability factor data for that signal node.

[0008] Optionally, functional simulation is performed based on test stimuli and simulation data to generate simulation result data for each simulation moment, which further includes: The simulation data is input into the simulator, which then initiates the functional simulation based on the test stimulus and the simulation data. During the simulation process of each test stimulus, the signal lines in the circuit that have changed data, the information and values ​​of the triggered registers are recorded at each simulation moment to form the simulation result data for that simulation moment.

[0009] Optionally, summarizing and analyzing the visible input information of each signal node at each simulation time, and determining the target time window for the observable soft error corresponding to each signal node, further includes: The visible input terminal information of each signal node at each simulation time is summarized, and the summarized visible input terminal information is analyzed to obtain the trigger path information of each signal node. Based on the trigger path information of each signal node, starting from the functional output port and traversing each triggered signal node step by step towards the input port, the target path that can propagate to the functional output port in the circuit when a soft error occurs at each signal node is obtained. For each signal node, the target time window in which the soft error of the corresponding signal node can be observed is determined based on the time window in which the simulation time of the target path is located.

[0010] Optionally, summarizing the visible input information of each signal node at each simulation time further includes: Based on the simulation time dimension and the signal node dimension, the visible input terminal information of each signal node at each simulation time is summarized.

[0011] Optionally, the analysis and summarization of the visible input information to obtain the trigger path information for each signal node further includes: Based on the aggregated visible input information, the triggering status of each signal node at each simulation moment is identified. At the simulation moment when the signal node is triggered, the path information of the previous level signal node reached by the signal node in the input direction is recorded as the triggering path information of the signal node.

[0012] Optionally, after calculating the proportion of the target time window corresponding to each signal node to the entire simulation cycle for each signal node, and using this proportion as the architectural vulnerability factor data for that signal node, the method further includes: Based on the architectural vulnerability factor data of each signal node, the specified signal node is selected from the signal nodes. For each specified signal node, functional simulation is performed based on test stimuli and simulation data. Faults are injected into each target time window of the specified signal node, and the data of the specified signal node in the visible input information of the functional output port is detected to see if it has changed. If a change occurs, the target time window is determined as the time window in which soft errors based on functional masking factors can be observed for the specified signal node; Calculate the proportion of the time window during which soft errors based on functional masking factors can be observed for the specified signal node within the entire simulation cycle, and update the architectural vulnerability factor data for the specified signal node according to the proportion.

[0013] According to another aspect of the embodiments of this application, an architecture vulnerability factor calculation device based on functional simulation is provided, comprising: The circuit compilation module is suitable for obtaining circuit design source files, compiling circuits based on circuit design source files, and generating simulation data and circuit topology diagrams. The simulation module is suitable for performing functional simulations based on test stimuli and simulation data, generating simulation result data at each simulation moment; The fault analysis module is suitable for backfilling the simulation result data at each simulation moment into the circuit topology diagram, determining the visible input terminal information of each signal node in the circuit at each simulation moment; summarizing and analyzing the visible input terminal information of each signal node at each simulation moment, determining the target time window for the observable soft error corresponding to each signal node; for each signal node, calculating the proportion of the target time window corresponding to the signal node to the entire simulation cycle, and using the proportion as the architectural vulnerability factor data of the signal node.

[0014] According to another aspect of the embodiments of this application, a computing device is provided, including: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the above-mentioned functional simulation-based architecture vulnerability factor calculation method.

[0015] According to another aspect of the embodiments of this application, a computer storage medium is provided, wherein at least one executable instruction is stored in the storage medium, the executable instruction causing a processor to perform the operation corresponding to the above-described method for calculating the architecture vulnerability factor based on functional simulation.

[0016] According to another aspect of the embodiments of this application, a computer program product is provided, including at least one executable instruction that causes a processor to perform operations corresponding to the above-described method for calculating the architecture vulnerability factor based on functional simulation.

[0017] According to the technical solution provided in this application, by analyzing the circuit topology in real time during functional simulation, the visible input terminal information of each signal node in the circuit at each simulation moment is determined. Based on the visible input terminal information, the influence of logic masking and time masking on soft error propagation is dynamically analyzed, and the time window where soft errors cannot be observed is excluded, thus obtaining the target time window where soft errors can be observed for each signal node. Based on the proportion of the target time window to the entire simulation cycle, the AVF data of each signal node in the circuit based on logic masking factors and time masking factors can be quickly calculated, which to a certain extent meets the reliability design requirements, allowing further functional safety testing to focus earlier on the circuit parts with higher AVF data and greater impact on system stability. This solution rapidly reduces the scale of merged tests, greatly reduces the time overhead required for AVF data calculation, improves the efficiency of fault injection testing based on functional masking factors, and effectively improves the calculation efficiency of AVF data.

[0018] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of the embodiments of this application are described below. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating an architecture vulnerability factor calculation method based on functional simulation according to an embodiment of this application is shown. Figure 2 This illustration shows a schematic diagram of the principle of an architecture vulnerability factor calculation method based on functional simulation according to an embodiment of this application. Figure 1 ; Figure 3 A schematic diagram of the circuit structure is shown. Figure 1 ; Figure 4 This illustration shows a schematic diagram of the principle of an architecture vulnerability factor calculation method based on functional simulation according to an embodiment of this application. Figure 2 ; Figure 5 A schematic diagram of the circuit structure is shown. Figure 2 ; Figure 6 It shows Figure 5 A schematic diagram of the visible input terminal information and trigger path information of each signal node in the circuit shown; Figure 7 It shows that according to Figure 6 A schematic diagram of the target path that can propagate to the functional output port in the circuit when a soft error occurs at each identified signal node; Figure 8 A structural block diagram of an architecture vulnerability factor computing device based on functional simulation according to an embodiment of this application is shown; Figure 9 A schematic diagram of the structure of a computing device according to an embodiment of this application is shown. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0022] Logic masking refers to the probability that a single-event flip (SEU) or transient (SET) caused by some particles due to the logic circuit structure itself cannot propagate to the next stage flip-flop or system output.

[0023] Temporal masking refers to the phenomenon that, in the error process caused by a single-event upset (SEU) or transient event (SET), considering the temporal characteristics of the circuit signal, not all particle hits can be captured by the timing sampling circuit (such as a trigger), thereby reducing the actual visible error rate.

[0024] Functional masking refers to the proportion of functional masking caused by particle soft errors by system-level logic and application behavior.

[0025] Electrical masking refers to the process where a single-event transient (SET) on a device is shielded from causing an error because the voltage does not exceed a threshold. Logic gates, due to their limited slew rate and inherent capacitance, act as low-pass filters, blocking very weak pulses.

[0026] To facilitate a clear and intuitive understanding of the differences between this application and existing technologies, the following section will first provide a detailed explanation of the calculation method for the architectural vulnerability factor in existing technologies: In practical circuits, calculating the AVF (Advanced Visual Failure Rate) for each signal line or register requires considering the combined influence of various complex factors to obtain AVF data that more closely approximates reality. To obtain more accurate and reliable AVF data, AVF calculation typically employs a time-sampling method. For a given signal line or register, an error is injected sequentially at each sampling time point, and then the changes in the data at the functional output are observed. The proportion of sampling time points that lead to changes in the observable result out of all sampling time points is used as a reference value for AVF, expressed by the formula:

[0027] in, This represents the AVF data of the i-th signal node (e.g., a signal line or register).

[0028] To obtain accurate AVF data, designers need to use EDA tools to perform extensive simulation tests, simulating the impact of a soft error occurring at a specific point in time on the observed results. As circuit designs grow in scale, this comprehensive approach requires significant time investment and is increasingly unable to meet designers' needs.

[0029] For example, if the number of signal nodes (such as signal lines or registers) in a circuit design is N, and the number of sampling time points that need to be injected with soft errors throughout the simulation cycle is M, then for a single test stimulus (or test case), the total number of simulations required is... for:

[0030] A circuit design typically requires multiple test stimuli for coverage, with each test stimulus having a different simulation duration. If the number of sampling time points for injecting soft errors is Mi, then the total number of tests T is:

[0031] Where p represents the total number of test stimuli.

[0032] It is evident that for a circuit with a scale of over one million, the amount of simulation required for this full-coverage approach is enormous and difficult to achieve.

[0033] To address the issues of high time overhead and low computational efficiency in existing methods for calculating architectural vulnerability factors (AVFs), this application proposes a novel functional simulation-based method. At each simulation moment, through real-time analysis of the circuit topology, the method dynamically considers the impact of logic masking (LDR) and time masking (TDR) on soft error propagation, excluding time windows where soft errors are unobservable, thus obtaining the target time window where soft errors can be observed for each signal node. For each signal node, the AVF data is calculated based on the proportion of the target time window corresponding to that signal node to the entire simulation cycle. The formula for calculating the AVF data of the i-th signal node is as follows:

[0034] in, This represents the AVF data of the i-th signal node.

[0035] This application obtains AVF data for each signal node through the above processing, enabling targeted physical or logical hardening of certain signal nodes based on the AVF data, thereby meeting the functional safety requirements of the entire circuit. Compared with the existing full-coverage approach, this application calculates AVF data based on the target time window where soft errors corresponding to signal nodes can be observed, greatly reducing the computation time overhead and effectively improving the computation efficiency of AVF data.

[0036] Figure 1 A flowchart illustrating a method for calculating architectural vulnerability factors based on functional simulation according to an embodiment of this application is shown, as follows. Figure 1 As shown, the method includes the following steps: Step S101: Obtain the circuit design source file, compile the circuit based on the circuit design source file, and generate simulation data and circuit topology diagram.

[0037] Among them, circuit design source files refer to editable project files generated by circuit design software, which contain all design information such as circuit schematics, PCB layouts, component libraries, netlists, and design rules. The format and structure of source files vary between different software. Figure 2 This illustration shows a schematic diagram of the principle of an architecture vulnerability factor calculation method based on functional simulation according to an embodiment of this application. Figure 1 ,like Figure 2 As shown, the circuit design source file is obtained, read by the compiler, and the circuit is compiled to generate the simulation data required for simulation, as well as the circuit topology diagram. The simulation data refers to the data file required by the simulator during simulation, and is usually event-driven. The circuit topology diagram records the circuit connections, specifically the point-to-point topological connections.

[0038] Step S102: Perform functional simulation based on test stimuli and simulation data to generate simulation result data for each simulation moment.

[0039] Simulation data is input into the simulator, which then initiates functional simulation based on the test stimuli and simulation data. During the simulation of each test stimulus, the signal lines in the circuit that undergo data changes, the triggered register information, and values ​​are recorded at each simulation moment, forming the simulation result data for that simulation moment. For example... Figure 2 As shown, the simulator reads the simulation data, starts the functional simulation according to the test stimulus and simulation data, records the data changes in the circuit at each simulation moment, and uses the signal lines with data changes, the triggered register information and values ​​as the simulation result data of the corresponding simulation moment, and sends them to the fault analysis tool, and then enters the next simulation moment.

[0040] Step S103: Fill the simulation result data at each simulation time into the circuit topology diagram to determine the visible input terminal information of each signal node in the circuit at each simulation time.

[0041] In this application, the simulation result data at each simulation moment is backfilled into the circuit topology diagram. By analyzing the circuit topology diagram in real time, the influence of logic masking and time masking on soft error propagation is dynamically considered, thereby realizing the analysis of soft error shielding.

[0042] like Figure 2 As shown, the fault analysis tool reads the circuit topology diagram. After obtaining the signal lines and values ​​of data changes occurring at the current simulation moment (i.e., the simulation result data at the current simulation moment) sent by the simulator, it back-annotates the values ​​onto the circuit topology diagram. Taking registers as an example, for any register, when the register is triggered, only errors in the register or combinational logic that are visible at the input terminals can be captured by the current register and propagated backward. The fault analysis tool dynamically analyzes the circuit topology diagram in real time and records the visible input terminal information of the current register. Visible input terminal information refers to information such as the input terminals that signal nodes like registers can obtain, and the specific values ​​of those input terminals.

[0043] Step S104: Summarize and analyze the visible input terminal information of each signal node at each simulation time, and determine the target time window in which the soft error of each signal node can be observed.

[0044] like Figure 2As shown, after the simulation ends, the fault analysis tool summarizes and generates the time window in which each signal node can affect the functional output port (or observation point, functional observation point) based on the information collected during the simulation. That is, the target time window in which soft errors can be observed, thereby calculating AVF data.

[0045] To facilitate the determination of the target time window in which soft errors can be observed for signal nodes, the propagation process of soft errors will be introduced below.

[0046] For SEU-type soft errors, based on the register's transfer characteristics, when the control signal C is triggered, the data at the register's input D is latched at the output Q and held until the control signal C is triggered again, at which point the data at output Q is overwritten by the new input data. For any register or signal line in the circuit, soft error propagation requires both logical and temporal conditions to be met simultaneously: 1) Logical condition: Soft errors can be seen by the next level register. Errors suppressed by combinational logic on the path (including SEU and SET) will not cause errors in the next level register.

[0047] 2) Timing conditions: Soft errors will persist until the triggering time of the next level register, or cause the next level register to trigger. Errors that have been recovered before the next level register triggers (including SEU and SET) will not cause errors in the next level register.

[0048] Figure 3 A schematic diagram of the circuit structure is shown. Figure 1 ,by Figure 3 Taking register R3 as an example, an error that can propagate backward through R3 must occur within the visible cone of input D of R3 (W3, C3, C0, W1 and R1, or W2 and R2). Simultaneously, a soft error occurs before the control signal C3 is triggered and is not recovered. Single-event upset (SEU) errors are reset, or transient (SET) errors are automatically recovered.

[0049] like Figure 3 As shown, when the control signal C0 of the selector MUX is 1, W1 and W3 are connected, and W2 is blocked. At this time, the register within the visible cone range of the input terminal D of R3 is R1, and the visible signal lines are W3, C3, C0, and W1. Therefore, SEU type errors generated after the previous trigger moment of register R1, and SET type errors generated on signal lines W1, W3, C0, and C3 and held until the trigger moment of R3, will be captured by register R3 and propagated to the output. Any errors generated in register R2 and on signal line W2 will not propagate backward through R1.

[0050] Furthermore, for soft errors of the SET type, since the error occurs in combinational logic circuits and lasts for a short period, there are two scenarios in which the error can be retained and propagated backward: 1) The error is caught and propagated by the next-level register during its duration. This situation is handled in the same way as an observable error on a register.

[0051] 2) Soft errors occur when data is latched by combinational logic, causing the erroneous data and logic to be held for an extended period and captured and propagated by the next-level register. In this case, the combinational logic can be considered a special type of SEU fault. The handling is the same as for observable errors in registers.

[0052] Figure 4 This illustration shows a schematic diagram of the principle of an architecture vulnerability factor calculation method based on functional simulation according to an embodiment of this application. Figure 2 ,like Figure 4 As shown, the circuit is compiled based on the circuit design source file, generating simulation data and topology data. A circuit topology diagram is then built based on this topology data. During each event-driven time segment in the functional simulation process, the simulator records the signal lines where data changes occur and the information of the triggered registers. At the end of the simulation time segment, the simulator sends the collected device information, values, and the current simulation time as the simulation result data for the current simulation moment to the fault analysis tool. The simulator then continues to the next time segment for simulation calculation. The fault analysis tool marks the changed values ​​in the circuit topology diagram, thus obtaining the logic masking information of the circuit at the current simulation moment.

[0053] The fault analysis tool iterates backward from the function output port, traversing each triggered register. Starting from each register, it searches towards the input port for the nearest accessible register. The corresponding code could be:

[0054] In addition, for SEU type soft errors, it is also necessary to record the combinational logic signal information on the path.

[0055] In step S104, the visible input terminal information of each signal node at each simulation time is summarized, and the summarized visible input terminal information is analyzed to obtain the trigger path information of each signal node. Based on the trigger path information of each signal node, each triggered signal node is traversed step by step from the functional output port towards the input terminal to obtain the target path that can propagate to the functional output port in the circuit when a soft error occurs at each signal node. For each signal node, the target time window where the soft error can be observed is determined according to the time window of the simulation time corresponding to the target path. The target time window obtained here refers to the time window where the soft error can be observed considering the influence of LDR and TDR.

[0056] Specifically, the visible input information of each signal node at each simulation time can be summarized according to the simulation time dimension and the signal node dimension. Based on the summarized visible input information, the triggering status of each signal node at each simulation time is identified, and at the simulation time when the signal node is triggered, the path information of the previous level signal node reached by the signal node in the input direction is recorded as the triggering path information of the signal node.

[0057] Figure 5 A schematic diagram of the circuit structure is shown. Figure 2 ,by Figure 5 Taking the circuit structure shown as an example, registers R1 to R4 are used as signal nodes. Through functional simulation and fault analysis, the visible input terminal information of each signal node in the circuit at each simulation time (t0 to t12) is obtained. This information is then summarized according to the simulation time dimension and the signal node dimension. The summarized visible input terminal information is as follows: Figure 6 As shown, Figure 6 The table summarizes the visible input information of each signal node in the circuit from time t2 to t11. Among them, the functional output port Rout is the register R4. Taking the simulation time t3 as an example, the visible input information of register R2 is "W2, W1, R1", which means that at time t3, register R2 can obtain the data of signal line W2, signal line W1 and register R1.

[0058] Figure 6 The green color in the code indicates that the register is triggered at a specified time, and records the path information from this register to the input terminal, which can reach the previous level register. This path information is used as the trigger path information for this register. Figure 6 The white value in the code indicates that the register was not triggered at the specified time and there was no event.

[0059] Based on the trigger path information of each register, the fault analysis tool further sequentially traverses each simulation time point (i.e., time points t0 to t12), starting from each functional output port (i.e., Rout). When a trigger occurs, such as at time t3, it searches for the visible input information of Rout at time t3 and finds that it can obtain the data of register R3, indicating that the visible input of Rout at time t3 includes register R3. The period from the previous trigger time of the visible input (i.e., time point t2) to the current time (i.e., time point t3) is taken as the target time window in which the soft error corresponding to the visible input register R3 can be observed.

[0060] For time t4, when Rout is triggered, we look up the visible input information of Rout at time t4 and find that it can obtain the data of register R2. This indicates that the visible input of Rout at time t4 includes register R2. We take the period from the previous trigger time of the visible input (i.e., time t3) to the current time (i.e., time t4) as the target time window for the soft error corresponding to the visible input register R2 to be observed. Since the visible input information of register R2 at time t3 is "W2, W1, R1", it indicates that the visible input of R2 at time t3 includes register R1. Therefore, we take the period from the previous trigger time of the visible input (i.e., time t2) to the current time (i.e., time t3) as the target time window for the soft error corresponding to the visible input register R1 to be observed.

[0061] The code for determining the target time window can be:

[0062] By combining the trigger path information of each register, fault analysis can obtain the target path of soft errors that ultimately propagate to the functional output port (i.e., the functional observation point) in the entire circuit design.

[0063] Figure 7 It shows that according to Figure 6 A schematic diagram showing the target path that can propagate to the functional output port in the circuit when a soft error occurs at each identified signal node. Figure 7 The red text indicates that the register is triggered at a specified time, and that a soft error in the register can propagate to the function output port in the circuit. Figure 7 The green color indicates that the register was triggered at the specified time and can be retrieved by the next level register, but cannot be retrieved by the registers after that.

[0064] Taking a SEU-type soft error in register R1 as an example: a SEU-type soft error within the time window formed by simulation times t2 and t3 can be read and propagated by register R2 at time t3, and at time t4, this error will be read by Rout, meaning it can propagate to the functional observation point. A SEU-type soft error within the time window formed by simulation times t4 and t5 can be read by register R3 at time t5, but this error does not continue to propagate to the functional observation point; instead, it is recovered at a later time due to the re-triggering of R3. Similarly, the analysis determines whether SEU-type soft errors within the time windows formed by simulation times t6 and t7, t8 and t9, and t10 and t11 can propagate to the functional observation point. The analysis shows that the target time windows for the soft errors corresponding to register R1 to be observable include the time windows formed by simulation times t2 and t3, and the time windows formed by simulation times t8 and t9. Therefore, the AVF data of register R1 considering the influence of LDR and TDR is:

[0065] in, This indicates the AVF data in register R1.

[0066] Step S105: For each signal node, calculate the proportion of the target time window corresponding to the signal node to the entire simulation cycle, and use the proportion as the architecture vulnerability factor data of the signal node.

[0067] Since the target time window obtained above refers to the time window during which soft errors can be observed considering the effects of LDR and TDR, i.e., the time window during which soft errors can be observed based on logic masking and time masking factors, the AVF data of each signal node in the calculated circuit is essentially AVF data considering logic masking and time masking factors. It can be assumed that soft errors occurring at these signal nodes with higher AVF data have a greater probability of affecting the functional output. Therefore, based on the above AVF data, further SET and SEU fault injection tests can be performed on the circuits with higher AVF data, i.e., the circuits where soft errors have a greater impact on functional observation points, considering the impact of functional masking (FDR) on error propagation, thereby improving the computational efficiency of AVF data and obtaining more accurate AVF data.

[0068] The method may further include: selecting designated signal nodes from among the signal nodes based on the architectural vulnerability factor data of each signal node; performing functional simulation for each designated signal node based on test stimuli and simulation data, injecting faults within each target time window of the designated signal node, and detecting whether the data of the designated signal node in the visible input information of the functional output port has changed; if a change has occurred, determining the target time window as the time window in which soft errors based on functional masking factors can be observed for the designated signal node; calculating the proportion of the time window in which soft errors based on functional masking factors can be observed for the designated signal node to the entire simulation cycle, and updating the architectural vulnerability factor data of the designated signal node according to the proportion. In other words, the calculated proportion is used as the updated architectural vulnerability factor data for the designated signal node.

[0069] For example, an AVF threshold is set, and signal nodes whose AVF data exceeds the threshold are selected as designated signal nodes. For each designated signal node, functional simulation is performed based on test stimuli and simulation data. Fault injection tests are performed one by one within each target time window of the designated signal node to detect whether the data of the designated signal node in the visible input information of the functional output port has changed. If it has changed, it means that the soft error can be observed by the functional observation point under the influence of FDR, and the target time window is determined as the time window in which the soft error based on the FDR factor can be observed for the designated signal node. If it has not changed, it means that the soft error cannot be observed by the functional observation point under the influence of FDR.

[0070] by Figure 7 Taking register R1 as an example, fault injection tests are performed one by one for the target time windows formed by simulation times t2 and t3, and the target time windows formed by simulation times t8 and t9. If the tests show that the soft errors in the target time windows formed by simulation times t2 and t3 can propagate to the functional observation point (i.e., can be observed), while the soft errors in the target time windows formed by simulation times t8 and t9 cannot propagate to the functional observation point (i.e., cannot be observed), then the time window for the soft errors in register R1 based on the FDR factor that can be observed includes the time window formed by simulation times t2 and t3. Therefore, the AVF data update of register R1, which considers the effects of LDR and TDR as well as the effects of FDR, is as follows:

[0071] Wherein, AVF(R1) represents the AVF data in register R1.

[0072] By considering the effects of LDR and TDR, as well as the impact of FDR on soft error propagation, more accurate AVF data can be calculated, serving as a reference for circuit safety hardening.

[0073] According to the functional simulation-based architecture vulnerability factor calculation method provided in this application, by analyzing the circuit topology in real time during functional simulation, the visible input terminal information of each signal node in the circuit at each simulation moment is determined. Based on the visible input terminal information, the influence of logic masking and time masking on soft error propagation is dynamically analyzed, and the time window where soft errors cannot be observed is excluded to obtain the target time window where soft errors can be observed for each signal node. Based on the proportion of the target time window to the entire simulation cycle, the AVF data of each signal node in the circuit based on logic masking and time masking factors can be calculated quickly. This satisfies the reliability design requirements to a certain extent, allowing further functional safety testing to focus earlier on the circuit parts with higher AVF data and greater impact on system stability. This scheme rapidly reduces the scale of merged tests, greatly reduces the time overhead required for AVF data calculation, improves the efficiency of fault injection testing based on functional masking factors, and effectively improves the calculation efficiency of AVF data.

[0074] Figure 8 A structural block diagram of an architecture vulnerability factor calculation device based on functional simulation according to an embodiment of this application is shown, as follows: Figure 8 As shown, the device includes: a circuit compilation module 810, a simulation module 820, and a fault analysis module 830.

[0075] The circuit compilation module 810 is suitable for: acquiring circuit design source files, compiling circuits based on circuit design source files, and generating simulation data and circuit topology diagrams.

[0076] The simulation module 820 is suitable for performing functional simulations based on test stimuli and simulation data, and generating simulation result data for each simulation moment.

[0077] The fault analysis module 830 is suitable for: backfilling the simulation result data at each simulation moment into the circuit topology diagram, determining the visible input terminal information of each signal node in the circuit at each simulation moment; summarizing and analyzing the visible input terminal information of each signal node at each simulation moment, determining the target time window in which the soft error corresponding to each signal node can be observed; and for each signal node, calculating the proportion of the target time window corresponding to the signal node to the entire simulation cycle, and using the proportion as the architectural vulnerability factor data of the signal node.

[0078] Optionally, the simulation module 820 is further adapted to: input simulation data into the simulator, and have the simulator start functional simulation based on the test stimulus and simulation data; during the simulation process of each test stimulus, record the signal lines in the circuit that have changed data, the information and values ​​of the triggered registers at each simulation moment, to form the simulation result data at that simulation moment.

[0079] Optionally, the fault analysis module 830 is further adapted to: summarize the visible input terminal information of each signal node at each simulation time, analyze the summarized visible input terminal information, and obtain the trigger path information of each signal node; based on the trigger path information of each signal node, traverse each triggered signal node step by step from the functional output port towards the input terminal to obtain the target path that can propagate to the functional output port in the circuit when a soft error occurs at each signal node; for each signal node, determine the target time window in which the soft error corresponding to the signal node can be observed based on the time window of the simulation time corresponding to the target path.

[0080] Optionally, the fault analysis module 830 is further adapted to: summarize the visible input terminal information of each signal node at each simulation time according to the simulation time dimension and the signal node dimension.

[0081] Optionally, the fault analysis module 830 is further adapted to: identify the triggering status of each signal node at each simulation moment based on the summarized visible input terminal information, and at the simulation moment when the signal node is triggered, record the path information of the previous level signal node reached by the signal node in the input direction as the triggering path information of the signal node.

[0082] Optionally, the fault analysis module 830 is further adapted to: select a specified signal node from the various signal nodes based on the architectural vulnerability factor data of each signal node. The simulation module 820 is further adapted to: perform functional simulation for each specified signal node based on test stimuli and simulation data, and inject faults within each target time window of the specified signal node. The fault analysis module 830 is further adapted to: detect whether the data of the specified signal node in the visible input information of the functional output port has changed; if it has changed, determine the target time window as the time window in which the soft error based on the functional masking factor can be observed for the specified signal node; calculate the proportion of the time window in which the soft error based on the functional masking factor can be observed for the specified signal node to the entire simulation cycle, and update the architectural vulnerability factor data of the specified signal node according to the proportion.

[0083] The descriptions of the above modules refer to the corresponding descriptions in the method embodiments, and will not be repeated here.

[0084] According to the functional simulation-based architecture vulnerability factor calculation device provided in this application, by analyzing the circuit topology in real time during functional simulation, the visible input terminal information of each signal node in the circuit at each simulation moment is determined. Based on the visible input terminal information, the influence of logic masking and time masking on soft error propagation is dynamically analyzed, and the time window where soft errors cannot be observed is excluded to obtain the target time window where soft errors can be observed for each signal node. Based on the proportion of the target time window to the entire simulation cycle, the AVF data of each signal node in the circuit based on logic masking factors and time masking factors can be quickly calculated. To a certain extent, this meets the reliability design requirements, allowing further functional safety testing to focus earlier on the circuit parts with higher AVF data and greater impact on system stability. This solution rapidly reduces the scale of merged tests, greatly reduces the time overhead required for AVF data calculation, improves the efficiency of fault injection testing based on functional masking factors, and effectively improves the calculation efficiency of AVF data.

[0085] This application provides a non-volatile computer storage medium storing at least one executable instruction or computer program that enables a processor to perform the operation corresponding to the functional simulation-based architecture vulnerability factor calculation method in any of the above method embodiments.

[0086] This application provides a computer program product comprising at least one executable instruction or computer program that enables a processor to perform the operation corresponding to the functional simulation-based architecture vulnerability factor calculation method in any of the above method embodiments.

[0087] Figure 9 The diagram shows a structural schematic of a computing device according to one embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the computing device.

[0088] like Figure 9 As shown, the computing device may include: a processor 902, a communications interface 904, a memory 906, and a communications bus 908.

[0089] In this system, the processor 902, communication interface 904, and memory 906 communicate with each other via communication bus 908. Communication interface 904 is used to communicate with other network elements, such as clients or other servers. The processor 902 executes program 910, specifically performing the relevant steps in the above-described embodiment of the architecture vulnerability factor calculation method for computing devices based on functional simulation.

[0090] Specifically, program 910 may include program code that includes computer operation instructions.

[0091] The processor 902 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The computing device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0092] Memory 906 is used to store program 910. Memory 906 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0093] Specifically, program 910 can be used to cause processor 902 to execute the architecture vulnerability factor calculation method based on functional simulation in any of the above method embodiments. The specific implementation of each step in program 910 can be found in the corresponding descriptions in the corresponding steps and units of the above-described architecture vulnerability factor calculation embodiments based on functional simulation, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0094] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, the embodiments of this application are not directed to any particular programming language. It should be understood that the contents of the embodiments of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best implementation of the embodiments of this application.

[0095] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0096] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various inventive aspects, in the foregoing description of exemplary embodiments of the present application, various features of the present application embodiments are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed embodiments of the present application require more features than expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the present application.

[0097] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0098] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are meant to be within the scope of the embodiments of this application and form different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

[0099] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of this application. The embodiments of this application can also be implemented as device or apparatus programs (e.g., computer programs and computer program products) for performing part or all of the methods described herein. Such programs implementing the embodiments of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0100] It should be noted that the above embodiments are illustrative of the embodiments of this application and not limiting of the embodiments of this application, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Embodiments of this application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A method for calculating architectural vulnerability factors based on functional simulation, characterized in that, include: Obtain the circuit design source file, compile the circuit based on the circuit design source file, and generate simulation data and circuit topology diagram; Functional simulation is performed based on the test stimulus and the simulation data to generate simulation result data at each simulation moment; The simulation results data at each simulation time are backfilled into the circuit topology diagram to determine the visible input terminal information of each signal node in the circuit at each simulation time. The visible input information of each signal node at each simulation time is summarized and analyzed to determine the target time window in which the soft error of each signal node can be observed. For each signal node, calculate the proportion of the target time window corresponding to that signal node to the entire simulation cycle, and use the proportion as the architecture vulnerability factor data for that signal node.

2. The method according to claim 1, characterized in that, The step of performing functional simulation based on the test stimulus and the simulation data to form simulation result data at each simulation moment further includes: The simulation data is input into the simulator, which then initiates functional simulation based on the test stimulus and the simulation data. During the simulation process of each test stimulus, the signal lines in the circuit that have changed data, the information and values ​​of the triggered registers are recorded at each simulation moment to form the simulation result data for that simulation moment.

3. The method according to claim 1, characterized in that, The step of summarizing and analyzing the visible input information of each signal node at each simulation time, and determining the target time window in which the soft error corresponding to each signal node can be observed, further includes: The visible input terminal information of each signal node at each simulation time is summarized, and the summarized visible input terminal information is analyzed to obtain the trigger path information of each signal node. Based on the trigger path information of each signal node, starting from the functional output port and traversing each triggered signal node step by step towards the input port, the target path that can propagate to the functional output port in the circuit when a soft error occurs at each signal node is obtained. For each signal node, the target time window in which the soft error of the target path can be observed is determined based on the time window in which the simulation time of the target path is located.

4. The method according to claim 3, characterized in that, The process of summarizing the visible input information of each signal node at each simulation time further includes: Based on the simulation time dimension and the signal node dimension, the visible input terminal information of each signal node at each simulation time is summarized.

5. The method according to claim 3, characterized in that, The analyzed and summarized visible input information, yielding trigger path information for each signal node, further includes: Based on the aggregated visible input information, the triggering status of each signal node at each simulation moment is identified. At the simulation moment when the signal node is triggered, the path information of the previous level signal node reached by the signal node in the input direction is recorded as the triggering path information of the signal node.

6. The method according to any one of claims 1-5, characterized in that, After calculating the proportion of the target time window corresponding to each signal node to the entire simulation cycle for each signal node, and using the proportion as the architectural vulnerability factor data for that signal node, the method further includes: Based on the architectural vulnerability factor data of each signal node, the specified signal node is selected from the signal nodes. For each specified signal node, functional simulation is performed based on the test stimulus and the simulation data. Faults are injected into each target time window of the specified signal node, and the data of the specified signal node in the visible input information of the functional output port is detected to see if the data has changed. If a change occurs, the target time window is determined as the time window in which soft errors based on functional masking factors can be observed for the specified signal node; Calculate the proportion of the time window during which soft errors based on functional masking factors can be observed for the specified signal node within the entire simulation cycle, and update the architectural vulnerability factor data of the specified signal node according to the proportion.

7. A device for calculating architectural vulnerability factors based on functional simulation, characterized in that, include: The circuit compilation module is suitable for acquiring circuit design source files, compiling circuits based on the circuit design source files, and generating simulation data and circuit topology diagrams. The simulation module is adapted to perform functional simulation based on test stimuli and the simulation data, and generate simulation result data at each simulation moment; The fault analysis module is suitable for backfilling the simulation result data at each simulation moment into the circuit topology diagram, and determining the visible input terminal information of each signal node in the circuit at each simulation moment; The visible input information of each signal node at each simulation time is summarized and analyzed to determine the target time window in which the soft error of each signal node can be observed. For each signal node, the proportion of the target time window corresponding to the signal node to the entire simulation cycle is calculated, and the proportion is used as the architecture vulnerability factor data of the signal node.

8. A computing device, comprising: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the architecture vulnerability factor calculation method based on functional simulation as described in any one of claims 1-6.

9. A computer storage medium storing at least one executable instruction that causes a processor to perform an operation corresponding to the architectural vulnerability factor calculation method based on functional simulation as described in any one of claims 1-6.

10. A computer program product comprising at least one executable instruction that causes a processor to perform an operation corresponding to the architectural vulnerability factor calculation method based on functional simulation as described in any one of claims 1-6.

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