A layout optimization method, device and equipment based on probability driving and a medium

Abstract

The application provides a probability-driven-based layout optimization method, device, equipment and medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target polygon to be optimized and a plurality of adjacent polygons thereof from an integrated circuit layout file; calculating the vertex interior angle of the target polygon, identifying convex points and convex degrees; performing a setback operation on each target convex point according to a set number of setback points and a setback step length; searching for a shortest distance critical interval of the target polygon and its adjacent polygons under the condition of meeting the process minimum distance, and calculating the confidence probability; iteratively calculating the confidence probability and the area ratio of the target polygon until the target confidence probability or the minimum area ratio is met, and stopping the iteration; and outputting the optimized layout data and generating an iteration log. The application makes the optimized layout meet the manufacturing tolerance requirements of advanced processes in a statistical sense, significantly reduces the risk of short circuit or performance deviation caused by random process fluctuations, and improves the manufacturing yield.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, specifically to a probability-driven layout optimization method, apparatus, device, and medium. Background Technology

[0002] In today's rapidly evolving semiconductor technology landscape, integrated circuit feature sizes continue to break through to the nanometer and sub-nanometer levels, with 5nm and below advanced processes becoming the core direction for high-end chip R&D and mass production. However, as dimensions continue to shrink, various errors in the process technology have an increasingly significant impact on device performance and production yield. Factors such as random process fluctuations, limitations in photolithography imaging, and shape transfer errors can easily cause the critical wiring spacing between adjacent patterns in the layout to deviate from design standards, leading to serious problems such as electrical failures, exacerbated parasitic effects, or short circuits, directly restricting the stability and reliability of chip manufacturing.

[0003] As the core carrier of integrated circuit physical realization, the layout's geometric rationality and process adaptability directly determine the chip's manufacturability. To resolve the contradiction between layout design and manufacturing, the industry has developed various layout optimization and modification schemes, but existing technologies still have significant limitations and are unable to meet the precision requirements of advanced processes.

[0004] The following are the technical shortcomings of traditional map optimization methods: 1. Fixed Offset Geometric Correction: This method adjusts the entire graphic boundary through a uniform expansion or contraction operation, relying solely on a preset fixed offset to achieve global adjustment. Its core drawback lies in the lack of local adaptability. It cannot dynamically optimize based on the neighboring environment of different regions, often leading to over-correction in some areas (such as excessive contraction of non-critical areas causing functional abnormalities) or under-correction (such as high-risk areas like protrusions still having the risk of spacing violations), making it difficult to balance the optimization needs of the global and local areas.

[0005] 2. Rule-driven global Boolean operations: Based on the process rules provided by the wafer fab, safe geometry is constructed through inter-layer Boolean combinations. However, this method requires large-scale expansion and contraction operations on the entire layout, resulting in extremely high computational complexity. It is not only inefficient but also prone to disrupting local topology, leading to abnormal circuit connections. Furthermore, its optimization logic relies solely on deterministic rules and lacks a dynamic feedback mechanism based on actual spacing distribution, making it unable to handle geometric deviations in complex scenarios.

[0006] 3. Manual Intervention-Based Local Adjustments: This method relies on engineers manually identifying high-risk areas such as convex corners in the layout and optimizing by modifying the coordinates of key points. This approach is not only labor-intensive and inefficient, but also highly dependent on the engineer's experience, resulting in poor repeatability and stability. More importantly, manual adjustments cannot quantify the impact of the modifications on the statistical spacing distribution, making it difficult to fundamentally guarantee the manufacturing reliability required for advanced processes.

[0007] As process nodes advance to 5nm and below, random process deviations have become a key bottleneck restricting layout optimization. Effects such as random offsets, etching inhomogeneities, and metal depressions during wafer manufacturing introduce spatially correlated random errors, leading to significant statistical fluctuations in the spacing between adjacent patterns. Existing Design for Manufacturability (DFM) optimization processes still rely on deterministic geometric rules, lacking statistical modeling and probabilistic constraints for random deviations. Traditional geometric correction methods can only determine spacing compliance based on fixed thresholds, failing to assess the probabilistic manufacturing tolerance of the layout shape under random process fluctuations. This results in optimized layouts that, while theoretically meeting design rules, still face a high risk of failure in actual mass production due to random errors.

[0008] Therefore, in the design and manufacturing processes of advanced processes, traditional layout optimization methods suffer from problems such as a lack of specificity in global adjustments, the inability of deterministic rules to cope with random deviations, and low efficiency and poor reliability of manual intervention. Summary of the Invention

[0009] The purpose of this application is to provide a probability-driven layout optimization method, apparatus, electronic device, and storage medium to achieve refined layout optimization without human intervention.

[0010] In a first aspect, embodiments of this application provide a probability-driven layout optimization method, comprising: The target polygon to be optimized and its multiple neighboring polygons are determined from the integrated circuit layout file, and the vertex information of the target polygon and its multiple neighboring polygons is obtained. Calculate the interior angles of the vertices of the target polygon and identify convex points with interior angles smaller than a preset angle; quantify the degree of protrusion of each convex point based on the size of its exterior angle, and sort the convex points from largest to smallest degree of protrusion. According to the set number of indentation points, determine the target convex points with the aforementioned number of indentation points from the convex point sort; according to the set indentation step size, perform a small step geometric indentation operation on each target convex point in the inward normal direction; For the latest target polygon after the indentation operation, the shortest distance critical interval between the latest target polygon and its neighboring polygons is searched using a bisection method under the condition of meeting the minimum process spacing. The confidence probability of the shortest distance critical interval is calculated based on the cumulative probability function of Gaussian distribution. Calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​its circumscribed rectangle; Using the target confidence probability and the minimum area ratio as constraints, the confidence probability and area ratio of the latest target polygon are iterated. After each iteration, the confidence probability and area ratio are updated until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, at which point the iteration stops. Output the optimized layout data and generate an iteration log that includes polygon identifiers, iteration count, area ratio, confidence probability, step size, and convergence status.

[0011] In one possible implementation, calculating the interior angles of the vertices of the target polygon includes: The interior angles of the vertices of the target polygon are calculated using the cross product method.

[0012] In one possible implementation, the calculation of the confidence probability of the shortest distance critical interval using the Gaussian distribution-based cumulative probability function includes: Determine the critical interval [a, b] for the shortest distance; The cumulative probability function F(x) is used to calculate the probabilities of [-∞, a] and [-∞, b], and the two probabilities of F(x) are subtracted to obtain the cumulative probability of satisfying the minimum process spacing: P(a ≤X≤ b)=F(b)-F(a); Wherein, the cumulative probability P represents the confidence level that the current shape of the target polygon still satisfies the minimum process spacing under manufacturing deviation, i.e., the confidence probability.

[0013] In one possible implementation, the preset angle is set to 180°.

[0014] Secondly, embodiments of this application provide a probability-driven layout optimization apparatus, comprising: The layout parsing module is used to determine the target polygon to be optimized and its multiple neighboring polygons from the integrated circuit layout file, and to obtain the vertex information of the target polygon and its multiple neighboring polygons. The convex point recognition module is used to calculate the interior angles of the vertices of the target polygon, identify convex points whose interior angles are smaller than a preset angle, quantify the degree of convexity of each convex point based on the size of its exterior angle, and sort the convex points from largest to smallest degree of convexity. The convex point indentation module is used to determine the target convex point with the set number of indentation points from the convex point sort; and to perform a small step geometric indentation operation on each target convex point in the inward normal direction according to the set indentation step size. The parameter calculation module is used to search for the shortest distance critical interval between the latest target polygon and its neighboring polygons using a bisection method, based on the condition of meeting the minimum process spacing, and to calculate the confidence probability of the shortest distance critical interval based on the cumulative probability function of Gaussian distribution; and to calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​the circumscribed rectangle. The iterative indentation module is used to iterate the confidence probability and area ratio of the latest target polygon with the target confidence probability and minimum area ratio as constraints. After each iteration, the confidence probability and area ratio are updated until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, at which point the iteration stops. The data output module is used to output the optimized layout data and generate an iteration log that includes polygon identifiers, iteration counts, area ratios, confidence probabilities, step size, and convergence status.

[0015] In one possible implementation, the convexity recognition module is specifically used for: The interior angles of the vertices of the target polygon are calculated using the cross product method.

[0016] Thirdly, embodiments of this application provide an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the probability-driven layout optimization method described in the first aspect of this application.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions thereon, which can be executed by a processor to implement the probability-driven layout optimization method described in the first aspect of this application.

[0018] This application provides a probability-driven layout optimization method, apparatus, electronic device, and storage medium. The method involves: determining the target polygon to be optimized and its multiple neighboring polygons from an integrated circuit layout file; calculating the interior angles of the vertex of the target polygon to identify convex points and their degree of convexity; performing small-step geometric indentation operations in the inward normal direction for each target convex point according to a set number of indentation points and indentation step size; searching for the shortest distance critical interval between the target polygon and its neighboring polygons, and calculating the confidence probability, based on the condition of meeting the minimum process spacing; calculating the area ratio of the target polygon; iterating the confidence probability and area ratio of the target polygon until the target confidence probability or minimum area ratio is met, at which point the iteration stops; outputting the optimized layout data and generating an iteration log. Compared to existing technologies, this application, by constructing a cumulative probability function and setting a target probability threshold, enables the optimized layout to statistically meet the manufacturing tolerance requirements of advanced processes, significantly reducing the risk of short circuits or performance deviations caused by random process fluctuations and improving manufacturing yield. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart of a probability-driven layout optimization method provided in this application is shown; Figure 2 A schematic diagram of the target polygon and its neighboring polygons is shown; Figure 3 This application provides a schematic diagram of the interior angles. Figure 4 This application provides a diagram illustrating the convexity of polygon vertices. Figure 5 A schematic diagram of the critical interval for the shortest search distance provided in this application is shown; Figure 6 The flowchart illustrating the probability assessment and spacing calculation of the shortest distance critical interval provided in this application is shown. Figure 7 A schematic diagram showing the comparison of iterative effects of the target polygon provided in this application is shown; Figure 8 A schematic diagram of a probability-driven layout optimization device provided in this application is shown. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0022] Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to those processes, methods, products, or apparatuses.

[0023] Definitions of abbreviations and key terms in this application:

[0024] After loading a layout database (such as GDSII / OASIS format), this application automatically identifies convex feature points of polygons in the editable layer using a geometric analysis algorithm. It then employs a strategy combining the vector cross product method and the convex hull algorithm to quantitatively analyze and prioritize the morphological features of each vertex. Subsequently, based on the spatial distribution information of the spacing between adjacent graphics, a statistical model centered on the minimum distance probability distribution function (PDF / CDF) is constructed. Through a convex point iterative indentation algorithm based on probability objective constraints, the boundary of the target polygon is gradually adjusted to meet the combined constraints of Design Rules (DRC) and Manufacturing Tolerances (DFM) in the geometric dimension. After each round of geometric updates, this method automatically calculates the minimum distance distribution and its statistical probability between the shape and adjacent structures. When a set probability threshold is met, the iteration stops and optimized layout data is output.

[0025] This application enables intelligent fine-tuning of local geometry in complex layouts without human intervention. While ensuring the consistency of layout topology and logical functions, it significantly improves the manufacturability and robustness of the design, making it suitable for advanced process nodes, such as EDA automated optimization processes below 5nm.

[0026] This application provides a probability-driven layout optimization method and apparatus, an electronic device, and a computer-readable storage medium, which will be described below with reference to the accompanying drawings.

[0027] This application relates to post-layout physical verification and geometric correction, and is particularly applicable to an algorithm system for adaptive optimization of polygon boundaries based on layout manufacturing deviation tolerance modeling. This application can be embedded into existing physical design and post-layout simulation workflows for applications such as manufacturability design optimization, local geometric consistency enhancement, and automated layout correction.

[0028] Please refer to Figure 1 The diagram illustrates a flowchart of a probability-driven layout optimization method provided in this application. Figure 1 As shown, the method includes the following steps: S101. Determine the target polygon to be optimized and its multiple neighboring polygons from the integrated circuit layout file, and obtain the vertex information of the target polygon and its multiple neighboring polygons; The core idea of ​​this application is to use automated algorithms to adaptively adjust the geometry of specific layers (such as metal layers, contact layers, or polysilicon layers) in the later verification stage of integrated circuit layout design, so that the minimum spacing between the layer and the adjacent layers meets the statistical manufacturing reliability target, while maintaining the integrity of the geometric topology and the electrical function.

[0029] This method takes a map database (such as OASIS or GDSII format) as input, such as... Figure 2 As shown, the graph consists of five polygons. The red polygon represents the target polygon that needs optimization, while the four purple polygons are the interference polygons, or neighboring polygons. Considering that the graphic will not exhibit significant shifts in practical engineering applications, the four neighboring polygons are set in a relatively regular manner, with different but not significantly different shortest distances from the target polygon.

[0030] In this step, the original OASIS layout file is read, the target polygon and its neighboring polygons are located, and the vertex information of all polygons is obtained. The layer to which the target polygon belongs is usually a polysilicon layer, a metal layer, or a combination of layers, while the layers to which the neighboring polygons belong are such as metal or contact layers.

[0031] The bounding box method is used to calculate the initial area ratio of the target polygon (the ratio of the actual area of ​​the polygon to the area of ​​the circumscribed rectangle). Two dedicated layers can be created: a marker layer for visualizing and annotating key points; and an indentation layer for storing the polygon version during the optimization process, laying the foundation for subsequent geometric analysis, iterative optimization, and result output.

[0032] S102. Calculate the interior angles of the vertices of the target polygon and identify convex points with interior angles smaller than a preset angle; quantify the degree of protrusion of each convex point based on the size of its exterior angle and sort them from largest to smallest degree of protrusion. Specifically, the first step is to identify convex points in the target polygon. This can be done by calculating the interior angles of the polygon's vertices using the cross product method. Vertices with interior angles smaller than a preset angle are considered convex points. The preset angle can be set to 180°, but it can also be set to other angles as needed; this application does not impose any limitations on this.

[0033] The specific process of convex dot recognition: First, calculate the directed area of ​​the polygon. Then, calculate the cross product of vectors between adjacent vertices. Each step accumulates the projection of the cross product of vectors formed by two adjacent vertices (represented as a scalar in two dimensions). Half of the accumulated value is the area of ​​the polygon. Positive values ​​indicate counterclockwise direction, and negative values ​​indicate clockwise direction.

[0034] Then, the vertex coordinates and edge vectors of each polygon are extracted through geometric calculations. The current vertex and its adjacent vertices are obtained, and the two vectors are calculated. The angle between adjacent sides, i.e., the interior angle, is calculated using the cross product method. ; like Figure 3 The diagram shows the interior angle. Where P... i Let represent the i-th vertex of the polygon. Let θ represent the i-th side of the polygon. i Represents vertex P i The corresponding interior angle.

[0035] When θ i When the angle is less than 180°, define the vertex P. i It is a convex point. And the interior angle value is used to calculate the exterior angle size (180° - θ). i Sort all vertices by their degree of convexity; the larger the exterior angle, the greater the convexity. Then, mark the results on the original map and save it, such as... Figure 4 As shown.

[0036] S103. Determine the target convex point with the set number of indentation points from the convex point sort; perform a small step geometric indentation operation on each target convex point in the inward normal direction according to the set indentation step size. Based on the convexity sorting, optimization starts from the vertices with the greater convexity. The number of indentation points can be set to 1~5, and the indentation step size can be set to 0.1nm-0.3nm. The specific indentation step size and number of indentation points can be set according to the actual situation, such as indenting 3 convex points each time, with an indentation of 0.25nm.

[0037] S104. For the latest target polygon after the indentation operation, under the condition of satisfying the minimum process spacing, the shortest distance critical interval between the latest target polygon and its neighboring polygons is searched using the bisection method, and the confidence probability of the shortest distance critical interval is calculated based on the cumulative probability function of Gaussian distribution. like Figure 5 As shown, the bisection method is used to find the critical point of the shortest distance. This involves continuously moving the target polygon along the y-axis, setting a suitable initial search interval that includes all critical points without wasting computational resources, and then continuously narrowing the search interval using the bisection method. Simultaneously, the shortest distance to surrounding polygons after each movement is calculated. When all distances are greater than a threshold (minimum process spacing), this is the critical point. By finding two critical points along the y-axis, the critical interval of the shortest distance can be obtained.

[0038] When calculating the shortest distance, for each convex polygon region, a local window analysis region is defined to obtain the vertices of all polygons. The minimum distance between the target polygon and all vertices of the neighboring polygons is calculated. The minimum value is found, which is the minimum distance between the two polygons. Then, the shortest distance after each movement of the polygon is compared with the threshold, and the critical interval is found by searching using the bisection method.

[0039] When calculating the probability interval, the shortest distance between each shape and its four surrounding shapes is calculated. For example, at the upper boundary, when all the shortest distances between the target polygon and the used polygons are greater than a threshold, the dy value at this point is recorded as the upper boundary critical point. A binary search is used to quickly find the critical point, thus obtaining the offset dy interval that satisfies the threshold condition.

[0040] To simulate the impact of real random effects on the graph, this application conducted a Monte Carlo sampling experiment and found that the Gaussian distribution best matches the distribution of random effects. Finally, the cumulative probability function of the Gaussian distribution was used to calculate the probability, where the mean of the Gaussian distribution is 2nm and the standard deviation is 0nm.

[0041] Then, for the shortest distance critical interval [a,b], the cumulative probability function F(x) is used to calculate the probabilities of [-∞,a] and [-∞,b], and the two F(x) are subtracted to obtain the cumulative probability of satisfying the minimum process spacing: P(a ≤X≤ b)=F(b)-F(a); Wherein, the cumulative probability P represents the confidence level that the current shape of the target polygon still satisfies the minimum process spacing under manufacturing deviation, i.e., the confidence probability.

[0042] For ease of understanding, this application provides the following: Figure 6 The flowchart shown illustrates the probability assessment and spacing calculation process for the shortest distance critical interval.

[0043] S105. Calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​the circumscribed rectangle. S106. Using the target confidence probability and the minimum area ratio as constraints, iterate the confidence probability and area ratio of the latest target polygon. Update the confidence probability and area ratio after each iteration until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, and then stop iterating. This application uses a dual-constraint control iteration with a target confidence probability and a minimum area ratio. During iteration, the target confidence probability P is set. target (e.g., 0.9) and the minimum area ratio R min (e.g., 0.65~0.75) is the control target, and a small step geometric indentation operation is performed on each convex point in the direction of the inward normal.

[0044] Sort the points by their convexity, and indent the three most convex points in each iteration, moving inwards towards the inward normal direction. After each iteration and shape update, recalculate the confidence probability P. k Ratio of area k The iteration continues until the set conditions are met.

[0045] The iteration stopping condition is: P k ≥P target Or R k <R min .

[0046] Experiments showed that by indenting 3 bumps each time, with an indentation of 0.25nm, it only takes 7 iterations and a total time of 5.2 seconds to complete the optimization of a polygon with 41 vertices.

[0047] Figure 7 The image shows a comparison of the iterative effects on the target polygon. For example... Figure 7 As shown, the optimized polygon is green, which is smoother than the initial red polygon, and the shape is not obviously distorted, showing a significant optimization effect.

[0048] As can be seen, the dual-constraint control mechanism of this application can ensure that: if the shape has met the probability target, it will automatically converge; if it continues to shrink but the area is lower than the safe ratio, it will be forcibly terminated to prevent shape distortion or loss of function.

[0049] S107. Output the optimized layout data and generate an iteration log containing polygon identifiers, iteration counts, area ratios, confidence probabilities, step size, and convergence status.

[0050] Once all convex regions have been optimized, the results are written back to a newly created OASIS file, and an iteration log is generated, which includes the number of polygons, the number of vertices, the initial probability and area ratio, the initial threshold, the target probability, the area ratio, the number of indentation points and distance each time, the final number of iterations, and the final probability and area ratio. This data can be used for subsequent manufacturability design analysis and statistical tracking.

[0051] The beneficial effects of the probability-driven layout optimization method provided in this application are as follows: 1. Improve statistical reliability: By constructing PDF / CDF probability models and setting target probability thresholds, the optimized layout can meet the manufacturing tolerance requirements of advanced processes in a statistical sense, significantly reducing the risk of short circuits or performance deviations caused by random process fluctuations and improving manufacturing yield.

[0052] 2. Fully automated cost reduction and efficiency improvement: Through automatic convex point identification and priority sorting, automatic probability calculation and dual-constraint iterative control, it completely replaces traditional manual intervention, greatly improves optimization efficiency, and the results are repeatable and stable.

[0053] 3. Ensure geometric and functional integrity: Adopt a dual constraint mechanism of probabilistic objective and minimum area ratio, monitor the area change in real time during the optimization process, effectively prevent polygon topology degradation or electrical function failure caused by excessive indentation, and balance optimization effect and geometric stability.

[0054] 4. Strong adaptability to advanced processes: Through Monte Carlo sampling experiments and Gaussian distribution modeling, it accurately simulates the random deviation effect of 5nm and below processes, solves the statistical fluctuation problem that traditional deterministic optimization methods cannot handle, and has the ability to finely adjust.

[0055] In the above embodiments, a probability-driven layout optimization method is provided. Correspondingly, this application also provides a probability-driven layout optimization apparatus, which can be implemented by software, hardware, or a combination of both. For example, the probability-driven layout optimization apparatus may include integrated or separate functional modules or units to perform the corresponding steps in the above methods. Please refer to... Figure 8 This illustration shows a schematic diagram of a probability-driven layout optimization apparatus provided by some embodiments of this application. Since the apparatus embodiments are basically similar to the method embodiments, the description is relatively simple; relevant details can be found in the description of the method embodiments. The apparatus embodiments described below are merely illustrative.

[0056] like Figure 8 As shown, the probability-driven layout optimization device 10 may include: The layout parsing module 101 is used to determine the target polygon to be optimized and its multiple neighboring polygons from the integrated circuit layout file, and to obtain the vertex information of the target polygon and its multiple neighboring polygons. The convex point recognition module 102 is used to calculate the interior angles of the vertices of the target polygon, identify convex points whose interior angles are smaller than a preset angle, quantify the degree of convexity of each convex point based on the size of its exterior angle, and sort the convex points from largest to smallest degree of convexity. The convex point indentation module 103 is used to determine the target convex point with the aforementioned number of indentation points from the convex point sorting according to the set number of indentation points; and to perform a small step geometric indentation operation on each target convex point in the inward normal direction according to the set indentation step size. The parameter calculation module 104 is used to search for the shortest distance critical interval between the latest target polygon and its neighboring polygons using a bisection method, based on the condition of meeting the minimum process spacing, and to calculate the confidence probability of the shortest distance critical interval based on the cumulative probability function of Gaussian distribution; and to calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​the circumscribed rectangle. The iterative indentation module 105 is used to iterate the confidence probability and area ratio of the latest target polygon with the target confidence probability and the minimum area ratio as constraints. After each iteration, the confidence probability and area ratio are updated until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, at which point the iteration stops. The data output module 106 is used to output the optimized layout data and generate an iteration log that includes polygon identifiers, iteration counts, area ratios, confidence probabilities, step size, and convergence status.

[0057] In one possible implementation, the convexity recognition module is specifically used for: The interior angles of the vertices of the target polygon are calculated using the cross product method.

[0058] The probability-driven layout optimization device provided in this application constructs a cumulative probability function and sets a target probability threshold, so that the optimized layout statistically meets the manufacturing tolerance requirements of advanced processes, significantly reducing the risk of short circuits or performance deviations caused by random process fluctuations and improving manufacturing yield.

[0059] This application also provides an electronic device corresponding to the probability-driven layout optimization method provided in the foregoing embodiments. The electronic device may be an in-vehicle device, a mobile phone, a laptop computer, a tablet computer, a desktop computer, etc., to execute the above-mentioned probability-driven layout optimization method.

[0060] The electronic device provided in this application embodiment and the probability-driven layout optimization method provided in this application embodiment are based on the same inventive concept and have the same beneficial effects as the methods they adopt, operate or implement.

[0061] This application also provides a computer-readable storage medium corresponding to the probability-driven layout optimization method provided in the foregoing embodiments, wherein a computer program (i.e., a program product) is stored thereon, and the computer program, when run by a processor, executes the probability-driven layout optimization method provided in any of the foregoing embodiments.

[0062] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0063] The computer-readable storage medium provided in the above embodiments of this application and the probability-driven layout optimization method provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the applications stored therein.

[0064] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application.

Claims

1. A probability-driven layout optimization method, characterized in that, include: The target polygon to be optimized and its multiple neighboring polygons are determined from the integrated circuit layout file, and the vertex information of the target polygon and its multiple neighboring polygons is obtained. Calculate the interior angles of the vertices of the target polygon and identify convex points with interior angles smaller than a preset angle; The degree of protrusion of each protrusion is quantified based on the size of its outer corner, and the protrusions are sorted from largest to smallest. According to the set number of indentation points, determine the target convex points with the aforementioned number of indentation points from the convex point sort; according to the set indentation step size, perform a small step geometric indentation operation on each target convex point in the inward normal direction; For the latest target polygon after the indentation operation, the shortest distance critical interval between the latest target polygon and its neighboring polygons is searched using a bisection method to meet the minimum process spacing condition. The confidence probability of the shortest distance critical interval is calculated based on the cumulative probability function of the Gaussian distribution. Calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​its circumscribed rectangle; Using the target confidence probability and the minimum area ratio as constraints, the confidence probability and area ratio of the latest target polygon are iterated. After each iteration, the confidence probability and area ratio are updated until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, at which point the iteration stops. Output the optimized layout data and generate an iteration log that includes polygon identifiers, iteration count, area ratio, confidence probability, step size, and convergence status.

2. The probability-driven layout optimization method according to claim 1, characterized in that, The calculation of the interior angles of the vertices of the target polygon includes: The interior angles of the vertices of the target polygon are calculated using the cross product method.

3. The probability-driven layout optimization method according to claim 1, characterized in that, The calculation of the confidence probability of the shortest distance critical interval using the cumulative probability function based on the Gaussian distribution includes: Determine the critical interval [a, b] for the shortest distance; The cumulative probability function F(x) is used to calculate the probabilities of [-∞, a] and [-∞, b], and the two probabilities of F(x) are subtracted to obtain the cumulative probability of satisfying the minimum process spacing: P(a ≤X≤ b)=F(b)-F(a); Wherein, the cumulative probability P represents the confidence level that the current shape of the target polygon still satisfies the minimum process spacing under manufacturing deviation, i.e., the confidence probability.

4. The probability-driven layout optimization method according to claim 1, characterized in that, The preset angle is set to 180°.

5. A probability-driven layout optimization device, characterized in that, include: The layout parsing module is used to determine the target polygon to be optimized and its multiple neighboring polygons from the integrated circuit layout file, and to obtain the vertex information of the target polygon and its multiple neighboring polygons. The convex point recognition module is used to calculate the interior angles of the vertices of the target polygon and identify convex points whose interior angles are smaller than a preset angle. The degree of protrusion of each protrusion is quantified based on the size of its outer corner, and the protrusions are sorted from largest to smallest. The convex point indentation module is used to determine the target convex point with the set number of indentation points from the convex point sort; and to perform a small step geometric indentation operation on each target convex point in the inward normal direction according to the set indentation step size. The parameter calculation module is used to search for the shortest distance critical interval between the latest target polygon and its neighboring polygons using a bisection method, based on the condition of meeting the minimum process spacing, and to calculate the confidence probability of the shortest distance critical interval based on the cumulative probability function of Gaussian distribution; and to calculate the area ratio of the latest target polygon, where the area ratio is the ratio of the actual area of ​​the polygon to the area of ​​its circumscribed rectangle. The iterative indentation module is used to iterate the confidence probability and area ratio of the latest target polygon with the target confidence probability and minimum area ratio as constraints. After each iteration, the confidence probability and area ratio are updated until the confidence probability is greater than or equal to the target confidence probability or the area ratio is less than the minimum area ratio, at which point the iteration stops. The data output module is used to output the optimized layout data and generate an iteration log that includes polygon identifiers, iteration counts, area ratios, confidence probabilities, step size, and convergence status.

6. The probability-driven layout optimization device according to claim 5, characterized in that, The convexity recognition module is specifically used for: The interior angles of the vertices of the target polygon are calculated using the cross product method.

7. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the probability-driven layout optimization method as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, It stores computer-readable instructions that can be executed by a processor to implement the probability-driven layout optimization method as described in any one of claims 1 to 4.

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