Circuit pre-training method and device based on graph neural network and electronic equipment
By constructing a circuit network graph and using the node2vec model, high-quality feature representations of nodes are automatically learned, solving the problem of low efficiency in circuit feature extraction in existing technologies and improving the efficiency and generalization ability of circuit analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU SILINTECH INC
- Filing Date
- 2026-04-28
- Publication Date
- 2026-05-29
AI Technical Summary
Existing circuit feature extraction techniques are limited by local perspective and human experience, or have high computational complexity, making it difficult to effectively mine deep structural information of circuits. Furthermore, existing graph theory algorithms lack semantic understanding of circuits, resulting in low efficiency in circuit analysis.
We employ a pre-training method for graph neural networks. By constructing a circuit network graph and using the node2vec model, we generate random walk road samples and automatically learn high-quality feature representations of nodes. We then utilize the random walk strategy of graph neural networks to transform the graph structure into sequential data and learn low-dimensional dense vector representations of nodes.
It achieves efficient and automated extraction of deep structural information of circuits, provides high-quality node feature representation, improves the generalization ability and computational efficiency of circuit analysis, and is suitable for large-scale circuit analysis.
Smart Images
Figure CN122113833A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital integrated circuit analysis, and in particular to a circuit pre-training method, apparatus, and electronic device based on graph neural networks. Background Technology
[0002] Large-scale circuit analysis plays a crucial role in understanding and designing chips, encompassing circuit module extraction and classification, chip layout and routing, and more. Circuits are composed of standard cells, and circuit analysis requires feature construction and modeling of these standard cells. Traditional feature construction methods rely on the attributes of the standard cell itself and its neighbors, neglecting the characteristics of the circuit structure. Since circuit functionality is achieved through the connection of standard cells, circuit structure information is essential for classifying circuit modules. A simple method to extract circuit structure information is to manually aggregate information from surrounding neighbors using feature engineering. However, this traditional approach only obtains statistical information from local networks, lacking flexibility and generalization ability, and is computationally cumbersome and time-consuming.
[0003] To overcome the limitations of manual features, existing research has attempted to introduce traditional graph theory algorithms (such as PageRank and Betweenness Centrality) to analyze circuit netlists. While these methods can measure the importance of nodes from a global perspective, they still have the following problems:
[0004] Semantic gaps: These general graph algorithms only consider the connection relationships of the graph structure and lack an understanding of the circuit-specific semantics (such as logical functions and signal flow). The generated feature values are difficult to directly map to specific circuit behaviors.
[0005] High computational complexity: For modern chip designs containing millions of standard cells, the time complexity of calculating the centrality index of the entire graph is extremely high, making it difficult to meet the real-time requirements of EDA tools.
[0006] In summary, existing circuit feature extraction techniques are either limited by local perspective and human experience, or by the computational efficiency and semantic gap of general algorithms. Therefore, there is an urgent need for a pre-training method that can automatically mine deep structural information of circuits, take into account both global and local features, and efficiently process ultra-large-scale circuit diagrams, so as to provide high-quality general feature input for downstream circuit analysis and optimization tasks.
[0007] Graph Neural Networks (GNNs) and their derivative models (such as node2vec) offer potential solutions to the aforementioned problems. Node2vec transforms graph structures into sequential data through a random walk strategy, thereby learning low-dimensional dense vector representations (embeddings) of nodes, which theoretically can simultaneously preserve the first-order and second-order similarity of nodes. Summary of the Invention
[0008] The purpose of this invention is to provide a circuit pre-training method, device, and electronic device based on graph neural networks. The method constructs a network graph by using standard units in large-scale circuits as nodes. Based on the graph neural network pre-training model node2vec, the network graph is pre-trained to automatically learn and obtain high-quality node feature representations containing structural information. These features are then used for downstream tasks such as circuit module extraction and classification, chip layout and routing, thereby improving the generalization ability of downstream models.
[0009] The technical solution of this invention is:
[0010] The circuit pre-training method based on graph neural networks includes the following steps:
[0011] S1. For large-scale circuits, construct a circuit network graph and generate random walk paths as samples for model training.
[0012] S2. Train the node2vec model using the road samples generated in step S1; select the model with the smallest loss function value as the optimal model;
[0013] S3. Load the optimal model from step S2, output and save the representation vectors of all nodes.
[0014] Preferably, step S1 specifically includes:
[0015] S1-1. Using standard cells in large-scale circuits as nodes, construct a circuit network diagram and generate a netlist file; the standard cells include logic gates and basic devices.
[0016] S1-2. Read the circuit netlist data and construct an undirected graph G=(V, E), where V is the set of nodes in the circuit structure and E is the edge between neighboring nodes.
[0017] S1-3. In the circuit network diagram, start from any node and randomly walk K steps to neighboring nodes, repeat N times to generate N roads of length K, which are used as positive samples for model training.
[0018] In the circuit network diagram, K nodes are randomly selected to form a road, and this is repeated N times to serve as negative samples for model training.
[0019] Preferably, step S2 specifically includes:
[0020] S2-1, the node2vec model described above sets the representation vector length to D, and randomly initializes the representation vector for each node;
[0021] S2-2, the loss function mentioned above calculates the cosine of the angle between the vectors representing the starting node and the subsequent nodes of each road to measure their similarity; for each batch of nodes, the total loss of positive and negative sample pairs is calculated according to the loss function.
[0022] S2-3. Train the neural network with the goal of minimizing the loss function. After gradient backpropagation and iteration, the value of the loss function gradually decreases and converges, and the node representation vector is constructed in D-dimensional space.
[0023] S2-4. Save the model with the minimum loss function value as the optimal model and use it to output the node representation vector.
[0024] Preferably, the loss function described in S2-2 is expressed as:
[0025] ;
[0026] in, For the set of positive sample pairs, Let u be a set of negative sample pairs, v be a starting node, and v be the context node of u in a positive sample pair. Let represent the D-dimensional embedding vector of node u, and let n represent negative sample nodes that have no contextual relationship with u. This represents the Sigmoid function, which maps the dot product of vectors to probabilities.
[0027] Preferably, the gradient backpropagation described in S2-3 employs a stochastic gradient descent algorithm or the Adam optimizer.
[0028] Preferably, after outputting the representation vectors of all nodes in step S3, the representation vectors of all nodes are saved as a feature file for use by downstream models.
[0029] Preferably, the feature file is a CSV file or a binary file stored according to the node ID.
[0030] A graph neural network-based circuit pre-training apparatus is used to execute the circuit pre-training method, comprising:
[0031] The preprocessing module is used to construct circuit network graphs for large-scale circuits and generate random walk paths as samples for model training.
[0032] The model training module is used to train the node2vec model using the road samples generated by the preprocessing module, and select the model with the smallest loss function value as the optimal model.
[0033] The vector output module is used to load the optimal model, output and save the representation vectors of all nodes.
[0034] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned circuit pre-training method based on a graph neural network.
[0035] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the circuit pre-training method based on a graph neural network.
[0036] The advantages of this invention are:
[0037] 1. In this invention, the pre-trained graph neural network model node2vec is used to fully absorb the local circuit structure features by utilizing the information of distant standard units, and automatically learn the deep representation of nodes from the circuit structure, avoiding tedious manual feature engineering and providing high-quality representation vectors for downstream models.
[0038] 2. The node representations learned by the graph neural network pre-trained model node2vec of this invention are task-independent general features that can be flexibly applied to a variety of downstream tasks and have strong generalization ability, providing support for subsequent circuit analysis and optimization design.
[0039] 3. Based on efficient random walks and neural networks, this invention can process large-scale circuit diagrams containing millions of nodes, and efficiently meet the analysis needs of modern very large-scale integrated circuits. Attached Figure Description
[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0041] Figure 1 This is a flowchart of the circuit pre-training method based on graph neural networks of the present invention;
[0042] Figure 2 This is the circuit structure in the embodiment of the present invention;
[0043] Figure 3 For the corresponding Figure 2 The network diagram constructed from the circuit structure;
[0044] Figure 4 This is a schematic diagram illustrating the generation of positive and negative sample roads in an embodiment of the present invention. Detailed Implementation
[0045] like Figure 1 As shown, the circuit pre-training method based on graph neural networks of the present invention includes the following steps:
[0046] S1. For large-scale circuits, analyze the circuit netlist, construct the circuit network graph, and generate random walk paths as samples for model training.
[0047] S2. Train the node2vec model using the road samples generated in step S1; select the model with the smallest loss function value as the optimal model;
[0048] S3. Load the optimal model from step S2, output and save the representation vectors of all nodes.
[0049] In specific implementation, step S1 specifically includes:
[0050] S1-1. Using standard cells in large-scale circuits as nodes, construct a circuit network diagram and generate a netlist file; the standard cells include logic gates and basic devices.
[0051] S1-2. Read the circuit netlist data and construct an undirected graph G=(V, E), where V is the set of nodes in the circuit structure and E is the edge between neighboring nodes.
[0052] S1-3. In the circuit network graph, start from any node and randomly walk K steps to neighboring nodes, repeat N times to generate N roads of length K, which are used as positive samples for model training; in the circuit network graph, randomly select K nodes to form 1 road, repeat N times, which are used as negative samples for model training.
[0053] Step S2 specifically includes:
[0054] S2-1, the node2vec model is described, with the representation vector length set to D, and the representation vector is randomly initialized for each node.
[0055] S2-2, the aforementioned loss function calculates the cosine of the angle between the vectors representing the starting node and subsequent nodes of each road to measure their similarity; for each batch of nodes, the total loss for positive and negative sample pairs is calculated according to the loss function; the loss function is expressed as:
[0056] ;
[0057] in, For the set of positive sample pairs, Let u be a set of negative sample pairs, v be a starting node, and v be the context node of u in a positive sample pair. Let represent the D-dimensional embedding vector of node u, and let n represent negative sample nodes that have no contextual relationship with u. This represents the Sigmoid function, which maps the dot product of vectors to probabilities.
[0058] S2-3. The neural network is trained with the goal of minimizing the loss function. After gradient backpropagation and iteration, the value of the loss function gradually decreases and converges, and the node representation vector is constructed in D-dimensional space. The gradient backpropagation adopts the stochastic gradient descent algorithm or the Adam optimizer.
[0059] S2-4. Save the model with the minimum loss function value as the optimal model and use it to output the node representation vector.
[0060] After outputting the representation vectors of all nodes in step S3, the representation vectors of all nodes are saved as a feature file for use by downstream models. The feature file is a CSV file or a binary file stored according to the node IDs.
[0061] The present invention also proposes a circuit pre-training device based on a graph neural network for executing the circuit pre-training method, comprising:
[0062] The preprocessing module is used to construct circuit network graphs for large-scale circuits and generate random walk paths as samples for model training.
[0063] The model training module is used to train the node2vec model using the road samples generated by the preprocessing module, and select the model with the smallest loss function value as the optimal model.
[0064] The vector output module is used to load the optimal model, output and save the representation vectors of all nodes.
[0065] The present invention also proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the circuit pre-training method based on graph neural networks.
[0066] The present invention also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the circuit pre-training method based on graph neural networks.
[0067] Example 1
[0068] This embodiment is for the following: Figure 2 The circuit structure shown is used for circuit pre-training based on graph neural networks.
[0069] In step S1 of this embodiment, the netlist file (such as a DEF file) of the target circuit is first parsed to construct an undirected graph G=(V,E), as follows: Figure 3 As shown. Each standard unit in the circuit, such as AND gate, OR gate, NOT gate, etc., is abstracted as a node in the graph. These nodes constitute the node set V in the undirected graph. Figure 2, 3 In the diagram, nodes A, B, and M represent an XOR gate, an OR gate, and a buffer (BUF), respectively.
[0070] like Figure 3 As shown, if two standard units are connected by the same wire mesh, an undirected edge is added between their corresponding nodes, and these edges form the edge set E. Nodes A and B are connected by a wire mesh, so there is an edge e between them.
[0071] like Figure 4 On the constructed undirected graph G, positive and negative samples required for training are generated.
[0072] Set the path length k=10 for the random walk and the sample size N=10000. Starting from any node in the graph (e.g., node A), according to the biased random walk strategy of node2vec (the parameters can be adjusted to balance depth-first search (DFS) and breadth-first search (BFS), at each step, randomly select a neighbor node to move forward, and move 10 steps to form a path of length 10. Repeat this process to generate 10000 positive sample paths. Figure 4 The following is a possible positive sample path: A→B→C→F→J→L→I→K→L→M;
[0073] Additionally, 10 nodes (without any connection relationship) are randomly selected from the node set V to generate a negative sample road of length 10. This process is repeated 10,000 times to generate 10,000 negative sample roads. Figure 4 The diagram shows a possible negative sample road A→J→D→L→B→E→K→C→M→F, where nodes J, D, and L are not directly connected to node A in the graph, and L is not a nearest neighbor of A.
[0074] Step S2: Set the dimension D of the node representation vector to 128, and randomly initialize a 128-dimensional vector as the initial representation vector for each node v∈V in the graph. For each node in a batch, the total loss for positive and negative sample pairs is calculated using the aforementioned loss function. Then, an optimizer such as Stochastic Gradient Descent (SGD) or Adam is used to update the 128-dimensional representation vectors of all nodes. This process is iterated until the loss function converges. The model that minimizes the loss on the validation set during training is selected as the optimal model.
[0075] Step S3: After training is complete, load the optimal model saved in step S2, traverse all nodes, extract their corresponding 128-dimensional vectors, and store them as CSV files or other binary files according to the node IDs. This feature file is the final output of this invention, and this output feature can be used as the input feature for subsequent machine learning model tasks.
[0076] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A circuit pre-training method based on graph neural networks, characterized in that, Including the following steps: S1. For large-scale circuits, construct a circuit network graph and generate random walk paths as samples for model training. S2. Train the node2vec model using the road samples generated in step S1; select the model with the smallest loss function value as the optimal model; S3. Load the optimal model from step S2, output and save the representation vectors of all nodes.
2. The circuit pre-training method based on graph neural networks according to claim 1, characterized in that, Step S1 specifically includes: S1-1. Using standard cells in large-scale circuits as nodes, construct a circuit network diagram and generate a netlist file; the standard cells include logic gates and basic devices. S1-2. Read the circuit netlist data and construct an undirected graph G=(V, E), where V is the set of nodes in the circuit structure and E is the edge between neighboring nodes. S1-3. In the circuit network diagram, start from any node and randomly walk K steps to neighboring nodes, repeat N times to generate N roads of length K, which are used as positive samples for model training. In the circuit network diagram, K nodes are randomly selected to form a road, and this is repeated N times to serve as negative samples for model training.
3. The circuit pre-training method based on graph neural networks according to claim 1, characterized in that, Step S2 specifically includes: S2-1, the node2vec model described above sets the representation vector length to D, and randomly initializes the representation vector for each node; S2-2, the loss function mentioned above calculates the cosine of the angle between the vectors representing the starting node and the subsequent nodes of each road to measure their similarity; for each batch of nodes, the total loss of positive and negative sample pairs is calculated according to the loss function. S2-3. Train the neural network with the goal of minimizing the loss function. After gradient backpropagation and iteration, the value of the loss function gradually decreases and converges, and the node representation vector is constructed in D-dimensional space. S2-4. Save the model with the minimum loss function value as the optimal model and use it to output the node representation vector.
4. The circuit pre-training method based on graph neural networks according to claim 3, characterized in that, The loss function described in S2-2 is expressed as follows: ； in, For the set of positive sample pairs, Let u be a set of negative sample pairs, v be a starting node, and v be the context node of u in a positive sample pair. Let represent the D-dimensional embedding vector of node u, and let n represent negative sample nodes that have no contextual relationship with u. This represents the Sigmoid function, which maps the dot product of vectors to probabilities.
5. The circuit pre-training method based on graph neural networks according to claim 3, characterized in that, The gradient backpropagation described in S2-3 uses either the stochastic gradient descent algorithm or the Adam optimizer.
6. The circuit pre-training method based on graph neural networks according to claim 1, characterized in that, After outputting the representation vectors of all nodes in step S3, the representation vectors of all nodes are saved as a feature file for use by downstream models.
7. The circuit pre-training method based on graph neural networks according to claim 6, characterized in that, The feature file is a CSV file or a binary file stored according to the node ID.
8. A circuit pre-training apparatus based on a graph neural network, used to execute the circuit pre-training method according to any one of claims 1-7, characterized in that, include: The preprocessing module is used to construct circuit network graphs for large-scale circuits and generate random walk paths as samples for model training. The model training module is used to train the node2vec model using the road samples generated by the preprocessing module, and select the model with the smallest loss function as the optimal model. The vector output module is used to load the optimal model, output and save the representation vectors of all nodes.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the circuit pre-training method based on graph neural networks as described in any one of claims 1 to 7.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the circuit pre-training method based on graph neural networks as described in any one of claims 1 to 7.