Tile data acquisition method, processor, system, device, medium and product

Abstract

The application provides a tile data acquisition method, a processor, a system, a device, a medium and a product. The method comprises the following steps: in the case that the cache area has a first tile number same as the tile number of a to-be-read tile, taking the data of the first tile number in the cache area as the data of the to-be-read tile; in the case that the cache area does not have a first tile number same as the tile number of a to-be-read tile, determining a second tile number contained in the data segment where the to-be-read tile is located; issuing a tile data segment acquisition request to the memory space based on the second tile number, and receiving the data segment where the to-be-read tile is located returned by the memory space.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to a method, processor, system, device, medium and product for acquiring tile data. Background Technology

[0002] In a graphics rendering engine, image data input from software to the hardware processor via an application programming interface (API) is processed sequentially through the geometry pipeline and fragment pipeline before being displayed on the screen. Tile-based rendering divides the screen into multiple tiles and determines which rasterizer should process each tile based on the traversal order. Once the rasterizer for the current tile is determined, its data is read from video memory. This sequential traversal can lead to frequent memory accesses and impact overall rendering performance. Furthermore, existing solutions suffer from multiple fetches of the same tile data, resulting in unnecessary memory accesses, high bandwidth pressure, low tile data retrieval efficiency, and low resource utilization. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one method, processor, system, device, medium, and product for acquiring tile data.

[0004] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a method for acquiring tile data, the method comprising: when a first tile number in a cache region is identical to the tile number of the tile to be read, using the data of the first tile number in the cache region as the data of the tile to be read; when a first tile number in the cache region is not identical to the tile number of the tile to be read, determining a second tile number contained in the data segment where the tile to be read is located; sending a tile data segment acquisition request to the memory space based on the second tile number, and receiving the data segment where the tile to be read is located returned by the memory space.

[0005] In another aspect, embodiments of this application provide a graphics processor, which implements the following steps: when a first tile number with the same tile number as the tile to be read exists in a cache region, the data of the first tile number in the cache region is used as the data of the tile to be read; when a first tile number with the same tile number as the tile to be read does not exist in the cache region, a second tile number contained in the data segment where the tile to be read is located is determined; a tile data segment acquisition request is sent to the memory space based on the second tile number, and the data segment where the tile to be read is located is returned by the memory space.

[0006] In another aspect, embodiments of this application provide a tile-based graphics system, the graphics system comprising: a graphics processor, configured to: when a first tile number in a cache region is identical to the tile number of the tile to be read, use the data of the first tile number in the cache region as the data of the tile to be read; when a first tile number identical to the tile number of the tile to be read is not present in the cache region, determine a second tile number contained in the data segment containing the tile to be read; send a tile data segment acquisition request to the memory space based on the second tile number, and receive the data segment containing the tile to be read returned by the memory space; and a screen, configured to display the image corresponding to the tile to be read based on the tile to be read.

[0007] In another aspect, embodiments of this application provide a computer device, which includes: a memory for storing a computer program that can run on a processor, and a graphics processor for implementing some or all of the steps in the above method when the computer executable instructions or computer program stored in the memory are present.

[0008] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0009] In another aspect, embodiments of this application provide a computer program including computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above-described method.

[0010] In another aspect, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer device, it implements some or all of the steps in the above-described method.

[0011] In this embodiment, by adding a cache area to store the most recently accessed tile number and its corresponding data segment, when a first tile number with the same tile number as the tile to be read exists in the cache area, the data of the first tile number in the cache area can be directly used as the data of the tile to be read, without issuing another tile data segment acquisition request. This reduces invalid accesses during the tile data acquisition process, avoids repeated requests for the same data segment, thereby reducing the number of memory accesses and improving bandwidth utilization and overall performance. When a first tile number with the same tile number as the tile to be read does not exist in the cache area, a second tile number contained in the data segment of the tile to be read is determined, and a tile data segment acquisition request is issued to the memory space based on the second tile number. The data segment of the tile to be read is then received from the memory space. This batch reading method based on data segments can improve bandwidth utilization, maximizing the use of data transmission bandwidth compared to reading the data of a single tile.

[0012] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0014] Figure 1 A schematic diagram illustrating the implementation process of a method for acquiring map data provided in an embodiment of this application; Figure 2 This is a schematic diagram of the storage of data segments in a method for acquiring tile data provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the allocation of block numbers in a block data acquisition method provided in an embodiment of this application; Figure 4 This is a schematic diagram of a tile traversal method in a tile data acquisition method provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the determination of a block to be read in a block data acquisition method provided in an embodiment of this application. Figure 6 A schematic diagram of a graphical structure system provided in this application embodiment. Figure 1 ; Figure 7 A schematic diagram of the structure of a graphics processing system provided in this application embodiment. Figure 2 ; Figure 8 This is a schematic diagram of the raster allocation in a tile data acquisition method provided in an embodiment of this application; Figure 9 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0017] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0019] This application provides a method for acquiring tile data, which can be executed by the graphics processor of a computer device. The computer device refers to a device with data processing capabilities, such as a server, laptop, tablet, desktop computer, smart TV, set-top box, or mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device). Figure 1 As shown, the method includes the following steps 101 to 103: Step 101: Determine whether the cache region has a first tile number that is the same as the tile number of the tile to be read.

[0020] A cache region refers to a storage space within a graphics processor used to temporarily store the tile numbers and corresponding data segments accessed most recently. A cache region can also be called a temporary storage region. In some implementations, the cache region can be a portion of memory, a register set, or a small static random-access memory (SRAM).

[0021] In some implementations, the cache area includes a number cache area and a data cache area. The number cache area stores the tile numbers of the last accessed tiles, and the data cache area stores the data segments corresponding to the last accessed tile numbers. Since the data size of a tile number is smaller than the data size of a data segment, the size of the number cache area is smaller than the size of the second cache area. The size of the number cache area is greater than or equal to the number of tile numbers read in a single access. The size of the data cache area is greater than or equal to the number of tiles in a single data segment.

[0022] like Figure 2 As shown, tile numbers 0 to 3 are temporarily stored in the numbering cache area, and data segment 1 corresponding to tile numbers 0 to 3 is temporarily stored in the data cache area. Tile numbers 4 to 7 are temporarily stored in the numbering cache area, and data segment 2 corresponding to tile numbers 4 to 7 is temporarily stored in the data cache area.

[0023] The tile to be read refers to the tile currently being processed by the rasterizer. During graphics rendering, the screen is divided into multiple rectangular areas, each of which can be called a tile. Each tile contains a number of pixels and serves as the basic unit for rasterization and fragment processing. The tile number is a numerical code used to uniquely identify the corresponding tile; for example, the tile number of the tile to be read is used to uniquely identify the tile to be read. The tile number can be in two-dimensional coordinate form (e.g., (x, y)) or one-dimensional linear numbering form. By using the tile number, the tile data corresponding to that tile number can be accurately located. The first tile number refers to the tile number in the buffer area that is the same as the tile number of the tile to be read.

[0024] In some implementations, the tile number of each tile can be determined based on the traversal order of each tile on the screen. Alternatively, it can be determined based on the partitioning order of each tile on the screen. Or, it can be determined based on the spatial position of each tile on the screen. Figure 3 As shown, tile numbers are assigned to the 48 tiles on the screen in an incremental manner, following a row-by-row traversal.

[0025] In some implementations, the block number of each valid block can be determined based on the range data of valid blocks transmitted during the geometric stage. In this case, all blocks processed by the rasterizer are valid blocks, i.e., the blocks to be read are valid blocks. For example... Figure 4 As shown, the screen includes three valid blocks, which are encoded as block 1, block 2, and block 3 in an inverted Z-shape.

[0026] In some implementations, the block number of the block to be read can be compared one by one with multiple block numbers in the cache area to determine whether there is a first block number in the cache area that is the same as the block number of the block to be read.

[0027] Step 102: If there is a first tile number in the cache area that is the same as the tile number of the tile to be read, use the data of the first tile number in the cache area as the data of the tile to be read.

[0028] If the cached area contains a first tile number that is the same as the tile number of the tile to be read, it means that the data segment containing the tile to be read has already been obtained, and there is no need to read it again, that is, there is no need to issue another request to obtain the tile data segment.

[0029] For example, when scanning the screen line by line, if a tile has already been accessed, the tile number and data segment stored in the cache area can be used directly without having to send another request to the memory space to retrieve the tile data segment, thus avoiding repeated requests for the same data segment.

[0030] Step 103: If there is no first tile number in the cache area that is the same as the tile number of the tile to be read, determine the second tile number contained in the data segment where the tile to be read is located; based on the second tile number, send a tile data segment acquisition request to the memory space, and receive the data segment where the tile to be read is located returned by the memory space.

[0031] If the cache region does not contain a first tile number that matches the tile number of the tile to be read, it indicates that the data segment containing the tile to be read has not been retrieved. A data segment refers to a group of tiles arranged contiguously in memory space, with each data segment containing a fixed number of tile data. Due to hardware memory alignment requirements, tile data is not stored independently as individual tiles, but rather as a data segment consisting of multiple contiguous tiles. Therefore, when a tile needs to be accessed, the data segment containing that tile is retrieved, and after retrieving the data segment, the tile data is extracted from that segment.

[0032] The second tile number refers to all tile numbers contained in the data segment containing the tile to be read. This second tile number can be used for subsequent data updates in the cache area, allowing for quick determination of whether the data segment containing the tile to be read already exists in the cache area during subsequent accesses.

[0033] In some implementations, since the tile numbers are numbered according to the traversal order and the data segments of multiple tiles are stored in the memory space in the traversal order, the starting tile number and the ending tile number of the data segment containing the tile to be read can be determined based on the tile number of the tile to be read and the number of tiles in a single data segment; and the second tile number contained in the data segment containing the tile to be read can be determined based on the starting tile number and the ending tile number.

[0034] For example, if the block numbering is according to Figure 3 The encoding method shown is a row-by-row incrementing encoding, and one data segment contains 4 tiles. Therefore, when the tile number to be read is 1, the corresponding data segment contains data for tiles 1 to 4. For example, if the tile numbering is according to... Figure 4 The inverted Z-shaped valid block encoding method shown is used, and one data segment contains 4 blocks. When block 1 of the block to be read is to read data segment 1, which contains the data of the four blocks: block 1, invalid block 1, invalid block 2, and block 2. When block 3 of the block is to be read, the data segment to be read is data segment 2, which contains the data of the four blocks: invalid block 3, invalid block 4, and block 3, invalid block 4.

[0035] It should be noted that when processing tile 1, data segment 1 containing four tiles—tile 1, invalid tile 1, invalid tile 2, and tile 2—is read from memory. Similarly, when processing tile 2, data segment 1 containing the same four tiles is read from memory again. This results in redundant tile data segment retrieval requests and low data utilization. However, this application, after retrieving data segment 1 for tile 1, temporarily stores it in a cache area. This allows the data for tile 2 to be retrieved from the cache area when processing tile 2, eliminating the need for repeated data segment retrieval requests. This reduces invalid accesses during tile data retrieval, avoids duplicate requests for the same data segment, and improves data utilization.

[0036] like Figure 2 As shown, if the data segment corresponding to tile 0 has already been temporarily stored in the cache area, then when the tile to be read is tile 3, it can be determined whether tile 3 exists in the cache area. If tile 3 exists in the cache area, there is no need to send a tile data segment retrieval request; the data of tile 3 can be read directly from the cache area. If tile 3 does not exist in the cache area, then a tile data segment retrieval request needs to be sent.

[0037] It should be noted that this application can process multiple tiles in parallel. After obtaining the data segments containing multiple tiles, the tile numbers and data segments of the multiple tiles can be stored in the cache area respectively. Subsequently, when multiple new tiles need to be processed, steps 101 to 103 can be followed to process the new multiple tiles.

[0038] In this embodiment, by adding a cache area to store the most recently accessed tile number and its corresponding data segment, when a first tile number with the same tile number as the tile to be read exists in the cache area, the data of the first tile number in the cache area can be directly used as the data of the tile to be read, without issuing another tile data segment acquisition request. This reduces invalid accesses during the tile data acquisition process, avoids repeated requests for the same data segment, thereby reducing the number of memory accesses and improving bandwidth utilization and overall performance. When a first tile number with the same tile number as the tile to be read does not exist in the cache area, a second tile number contained in the data segment of the tile to be read is determined, and a tile data segment acquisition request is issued to the memory space based on the second tile number. The data segment of the tile to be read is then received from the memory space. This batch reading method based on data segments can improve bandwidth utilization, maximizing the use of data transmission bandwidth compared to reading the data of a single tile.

[0039] In some embodiments, the step 103 above, "determining the second tile number contained in the data segment where the tile to be read is located," can be achieved through the following steps A1 to A3: Step A1: Based on the block number of the block to be read and the number of blocks in a single data segment, determine the starting block number of the data segment where the block to be read is located.

[0040] The number of tiles in a single data segment refers to the number of consecutive tiles stored in each data segment. The number of tiles in a single data segment is determined by the memory alignment method (i.e., how the data segment is stored in memory space) or the storage structure.

[0041] In some implementations, the starting tile number of the data segment containing the tile to be read can be inferred based on the tile number of the tile to be read and the number of tiles in a single data segment, according to the way the data segment is stored in memory space.

[0042] In some implementations, the number offset of the block to be read is determined based on the block number of the block to be read and the number of blocks in a single data segment; the starting block number of the data segment where the block to be read is located is determined based on the block number of the block to be read and the number offset.

[0043] In some implementations, the modulo operation can be performed between the block number of the block to be read and the number of blocks in a single data segment to obtain the block number offset. The formula for calculating the block number offset can be: block number % number of blocks in a single data segment.

[0044] In some implementations, the starting block number of the data segment containing the block to be read can be obtained by subtracting the block number and the block number offset. The formula for calculating the starting block number can be: Block number – Block number % Number of blocks in a single data segment.

[0045] It's worth noting that, based on memory alignment requirements, organizing the data of multiple tiles into a fixed-size data segment helps improve storage access efficiency and bandwidth utilization. For example, if each data segment contains 4 tiles, all the tile data within a data segment containing 4 tiles can be loaded at once, avoiding the performance loss caused by multiple small-scale storage accesses.

[0046] Step A2: Based on the starting tile number, the number of tiles in a single data segment, and the target value, determine the ending tile number of the data segment containing the tile to be read; the target value is determined by the encoding method of the tile number.

[0047] The target value is a fixed value set according to the encoding method of the block number, used to help determine the boundary of the data segment. If the block number starts from 0, the target value is 1; if the block number starts from 1, the target value is 0.

[0048] In some implementations, the starting tile number of the data segment containing the tile to be read and the number of tiles in a single data segment can be added together to obtain the addition result; the addition result and the target value can then be subtracted to obtain the ending tile number. The formula for calculating the ending tile number can be: tile number – tile number % number of tiles in a single data segment + number of tiles in a single data segment – ​​1. For example, if the tile numbering starts from 0 and the starting tile number is 32, then if a single data segment contains 16 tiles, the ending tile number will be 47 (32 + 16 - 1 = 47).

[0049] Step A3: Based on the starting and ending tile numbers of the data segment containing the tile to be read, determine the second tile number contained in the data segment containing the tile to be read.

[0050] Since the tile numbers are encoded sequentially, the second tile number contained in the data segment containing the tile to be read can be determined based on the starting and ending tile numbers of the data segment containing the tile to be read.

[0051] For example, if the starting tile number of a data segment is 32 and the ending tile number is 47, then the data segment containing the tile to be read contains all tiles with tile numbers from 32 to 47.

[0052] In this embodiment, by combining the tile number, the number of tiles in a single data segment, and the target value, the starting and ending tile numbers of the data segment are determined, enabling the construction of a complete set of tile numbers for the data segment containing the tile to be read. This allows for rapid location of the storage area where the tile is located, avoiding duplicate requests and redundant data transmission, thereby improving tile acquisition efficiency and optimizing bandwidth utilization. Introducing a target value for the encoding method allows for accurate determination of the ending tile number under different encoding methods.

[0053] In some embodiments, if the cache region does not have a first tile number that is the same as the tile number of the tile to be read, the tile data acquisition method provided in this disclosure can also acquire the data segment where the tile to be read is located through the following steps B1 to B2: Step B1: Determine the data segment address of the block to be read based on the block number of the block to be read, the number of blocks in a single data segment, and the data segment base address of the screen.

[0054] The base address of a screen's data segment refers to the starting address in memory where tile data is stored. As the basis for calculating the location of a data segment, the base address, along with the tile number and the number of tiles in a single data segment, allows for quick location of the data segment containing a specific tile.

[0055] In some implementations, the starting address of the data segment of the block to be read can be determined first based on the block number of the block to be read, the number of blocks in a single data segment, and the base address of the data segment. Then, the ending address of the data segment of the block to be read can be determined based on the starting address of the data segment and the number of blocks in a single data segment. The data segment address includes the starting address and the ending address.

[0056] Step B2: Based on the second tile number and the data segment address of the tile to be read, send a tile data segment acquisition request to the memory space, and receive the data segment of the tile to be read returned by the memory space.

[0057] Memory space refers to the video memory area that stores tile data. Memory space can include main video memory or cache. To improve bandwidth utilization, data for multiple related tiles can be retrieved in batches instead of one by one. By sending tile data segment retrieval requests to the memory space, control data for multiple tiles can be read at once, reducing the number of memory accesses.

[0058] In some implementations, the data segment containing the acquired block to be read can be roughly verified based on the number of blocks in a single data segment; or, the data segment containing the acquired block to be read can be accurately verified based on the second block number; thus, the accuracy of the acquired data segment can be ensured.

[0059] In some implementations, when issuing a request to acquire a tile data segment, the second tile number of the data segment containing the tile to be read may also be carried in order to accurately acquire the data segment containing the tile to be read.

[0060] In this embodiment, the data segment address is calculated based on the tile number, the number of data segment tiles, and the base address of the screen's data segment. A tile data segment acquisition request is then sent to the memory space based on the calculation result. This can improve the efficiency of acquiring tile data segments, thereby reducing unnecessary storage access and further improving the performance and resource utilization of the graphics processor.

[0061] In some embodiments, step B1 above can be implemented by the following steps B11 to B13: Step B11: Based on the block number of the block to be read and the number of blocks in a single data segment, determine the starting block number of the data segment where the block to be read is located.

[0062] Here, the operation of step B11 is similar to that of step A1 above, and the specific implementation of step A1 above can be referred to when implementing it.

[0063] In some implementations, the number offset of the block to be read is determined based on the block number of the block to be read and the number of blocks in a single data segment; the starting block number of the data segment containing the block to be read is determined based on the block number of the block to be read and the number offset. The formula for calculating the starting block number can be: block number – block number % number of blocks in a single data segment.

[0064] Step B12: Determine the starting address of the data segment containing the block to be read based on the starting block number and the data segment base address.

[0065] The base address of a data segment refers to the starting physical or logical address of the first data segment in the memory space.

[0066] In some implementations, a linear calculation method can be used to derive the starting address of the data segment containing the tile to be read, based on the starting tile number and the base address of the data segment. The starting address of the data segment containing the tile to be read can be used for subsequent memory access operations, thereby allowing direct access to the data of all tiles contained in the data segment containing the tile to be read.

[0067] In some implementations, the address offset can be determined first based on the starting block number, and then the starting address of the data segment containing the block to be read can be determined based on the data segment base address and the address offset.

[0068] It should be noted that by using the tile number and data segment base address of the tile to be read, the storage area of ​​the data segment containing the tile to be read can be accurately located. This avoids the performance loss caused by querying one by one and improves the response speed of the graphics processor.

[0069] Step B13: Determine the data segment address of the block to be read based on the starting address of the data segment where the block to be read is located.

[0070] In some implementations, the data segment address of the block to be read can be determined based on the starting address of the data segment containing the block and the number of blocks in a single data segment. Alternatively, the data segment address of the block to be read can be determined based on the starting address of the data segment containing the block and the second block number.

[0071] In this embodiment, the starting block number of the data segment containing the block to be read is first determined based on the block number of the block to be read and the number of blocks in a single data segment. Then, the starting address of the data segment containing the block to be read is calculated based on the starting block number and the corresponding data segment base address. Finally, the specific data segment address is located by combining the number of blocks in a single data segment and the starting address of the data segment containing the block to be read. This calculation method is not only clear in structure but also significantly improves addressing efficiency and reduces latency during graphics rendering.

[0072] In some embodiments, step B12 above can be implemented by the following steps B121 to B122: Step B121: Determine the address offset based on the starting tile number and address alignment unit.

[0073] Address offset refers to the offset value relative to the base address of the data segment.

[0074] Due to hardware architecture limitations, data in memory space needs to be stored in a specific size alignment to improve access efficiency. The address alignment unit is the smallest alignment granularity. The address alignment unit is set to be consistent with the smallest memory allocation unit of the hardware platform, such as 4 bytes, 8 bytes, etc.

[0075] In some implementations, the address offset can be obtained by multiplying the starting tile number and the address alignment unit. The formula for calculating the address offset can be: starting tile number × address alignment unit.

[0076] Step B122: Determine the starting address of the data segment containing the block to be read based on the address offset and the data segment base address.

[0077] In some implementations, the address offset and the data segment base address can be added together to obtain the starting address of the data segment containing the block to be read. The formula for calculating the starting address of the data segment can be: data segment base address + (starting block number × address alignment unit).

[0078] In this embodiment, the address offset is determined based on the starting tile number and address alignment unit, which enables more accurate calculation of the relative position of the tile in the storage space. This avoids the discontinuity problem caused by directly using the tile number and reduces unnecessary cache misses. Based on the address offset and the data segment base address, the starting address of the data segment containing the tile to be read can be obtained, enabling quick location of the data segment without traversing the entire storage space one by one.

[0079] In some embodiments, the tile data acquisition method provided in this disclosure further includes the following steps 104 to 105: Step 104: Store the block number of the block to be read into the number cache area within the cache area.

[0080] The tile number cache refers to the storage space used to temporarily store tile numbers. The purpose of the tile number cache is to record the tile numbers that have already been requested. This allows for quick determination of whether the data for the tile to be read has already been obtained during subsequent traversal, avoiding unnecessary redundant requests, reducing wasted storage bandwidth, and speeding up tile data retrieval.

[0081] Step 105: Store the data segment containing the tile to be read into the data cache area within the cache area.

[0082] A data cache is a memory area used to temporarily store the data segments corresponding to a tile. By writing the data segment information of the tile to be read into the data cache, the required data can be retrieved directly from the data cache in subsequent processing without having to access the memory again. Because data is temporarily stored in the data cache, data access latency is reduced, improving the overall efficiency of tile processing.

[0083] There is a relationship between the numbered cache and the data cache: the numbered cache records which tiles have been requested, while the data cache stores the actual data segments of these tiles. When it is determined that a tile number already exists in the numbered cache, the tile data corresponding to that tile number can be read directly from the data cache without having to initiate a new storage access request. This mechanism effectively reduces redundant operations and improves graphics processing efficiency.

[0084] In this embodiment of the application, by storing the block number of the block to be read in the number cache area and storing the data segment where the block to be read is located in the data cache area, repeated requests for the same block can be avoided, thereby reducing the consumption of storage bandwidth and improving the efficiency of block acquisition and the performance of graphics processing.

[0085] In some embodiments, such as Figure 5 As shown, the method for acquiring tile data provided in this application embodiment further includes the following steps 501 to 504: Step 501: Obtain the range data of valid tiles in the image to be rendered.

[0086] The image to be rendered refers to the image currently being processed, which is about to be rendered to the screen. Valid tiles refer to visible tiles that can be used normally. Range data includes the minimum and maximum coordinate ranges (XMIN, XMAX, YMIN, YMAX) covered by all valid tiles, used to limit the area traversed subsequently, reducing tile traversal time and thus reducing power consumption and latency during graphics processing.

[0087] Step 502: Determine the initial valid blocks based on the range data of the valid blocks.

[0088] The initial valid tile refers to the tile located at the top-left corner of the range data (such as the tile corresponding to XMIN and YMIN), which serves as the starting point for subsequent traversal. Setting the initial valid tile at the top-left corner helps to unfold the tile processing flow step by step in a logical order, ensuring that the tile traversal process conforms to the natural order of screen display, and is beneficial for optimizing the data caching and prefetching mechanisms of downstream modules.

[0089] Step 503: Starting from the initial valid tiles, traverse each valid tile within the range data of the valid tiles in spatial order, and determine the rasterizer corresponding to each valid tile in sequence according to the preset allocation strategy; the spatial order matches the encoding method of the tile number; the preset allocation strategy refers to the method of allocating tiles to multiple rasterizers.

[0090] The spatial order can be a progressive scan, a zigzag scan, or an arrangement of tile numbers that corresponds to the scanning method, such as progressive scan or zigzag scan. For example, tiles can be accessed by ascending tile numbers. The preset allocation strategy refers to the method of allocating tiles to different rasterizers, such as polling, load balancing, or dynamic allocation after determining that the rasterizer is currently idle.

[0091] The mechanism of keeping the tile numbering consistent with the spatial order of traversal can improve cache hit rate and reduce memory access conflicts. At the same time, it makes the task distribution among multiple rasterizers more even, ensuring the efficiency of rasterizer scheduling and the locality of memory access, thereby improving running efficiency.

[0092] Step 504: When processing each valid block using the rasterizer corresponding to each valid block, treat each valid block as a block to be read.

[0093] In some implementations, the rasterizer to which each valid tile should be assigned can be determined using a polling method. Alternatively, a load balancing method can be used to determine the rasterizer to which each valid tile should be assigned.

[0094] In this embodiment, the range data of valid map tiles defines the boundaries of the regions to be processed subsequently; using the initial valid map tiles as the starting point ensures the orderliness of the processing flow; following spatial order and allocation strategies, map tiles are traversed only within the range data of valid map tiles, and mapping from map tiles to the rasterizer is performed, improving the efficiency of multi-threaded processing; finally, map tiles are marked as tiles to be read, ensuring that data is accurately loaded into the rasterizer and avoiding redundant operations. The entire process forms a closed loop, working together to improve graphics rendering efficiency and reduce system power consumption.

[0095] In some embodiments, step 501 above can be implemented by the following steps 5011 to 5013: Step 5011: Divide the image to be rendered into multiple tiles according to the screen size.

[0096] The screen size determines the resolution and layout of the image in screen space. To improve rendering efficiency, the graphics processor divides the entire screen into multiple small regions, each of which is a tile. A tile is a fixed-size rectangular area, which can be 64×64 pixels or 128×128 pixels, used to improve the parallelism of image processing and memory access efficiency through fragmentation. The graphics processor calculates how many tiles can be divided horizontally and vertically based on the width and height of the display screen, thus forming a two-dimensional tile matrix. Each tile corresponds to a part of the image, and the tiles are used for subsequent rasterization and fragment processing operations.

[0097] The method of dividing the image into tiles is closely related to the resolution of the display screen. For example, on a screen with a resolution of 1920×1080, if the tile size is 64×64, then it can be divided into 30 tiles horizontally (1920 / 64) and 17 tiles vertically (1080 / 64). Based on this tile division method, uniform segmentation of the image can be achieved, providing a foundation for subsequent tile numbering and processing logic.

[0098] Step 5012: Based on the positions of multiple tiles on the screen and the traversal method of multiple tiles, determine the tile number of each of the multiple tiles on the screen.

[0099] Traversal methods include line-by-line scanning, zigzag scanning, etc. Each traversal method affects the tile numbering. The tile number is a unique identifier used to distinguish different tiles and serves as the basis for tile acquisition, processing, and storage.

[0100] The generation of tile numbers depends on the tile's position on the screen and the traversal order. For example, ... Figure 3 As shown, in the line-by-line scanning mode, the tile numbers are sequentially increased according to the position and row number of each row; while as... Figure 4 As shown, in the inverted Z-shaped scanning mode, the tile numbers increase sequentially along the inverted Z-shaped path. Once the tile numbers are determined, they can be used for subsequent tile scheduling, cache management, and bandwidth optimization operations.

[0101] The block number is used not only to identify the block itself, but also to determine whether the block has been processed by other rasterizers. This avoids duplicate requests, thereby reducing redundant data transmission and processing overhead. Furthermore, the block number can also serve as an index for block data segments, allowing for quick location and retrieval of the corresponding control information and metadata.

[0102] There is a close relationship between the tile number and the tile position, especially when using zigzag scanning or other non-linear traversal methods. The tile number reflects the relative order of the tiles in the image, rather than the absolute coordinates of the tiles. This characteristic of the tile number reflecting the relative order of the tiles in the image, rather than the absolute coordinates of the tiles, helps to optimize the parallel processing flow.

[0103] Step 5013: Based on the visual features of multiple tiles, determine the valid tiles from the multiple tiles; the visual features are used to represent the content in the corresponding tiles.

[0104] Visual features refer to whether the content contained in a tile has actual rendering value, that is, whether it contains valid geometric primitives or pixel data. In graphics processing, not all tiles contain content that needs to be rendered. For example, some tiles may be completely located in the background area or occluded by other primitives, lacking any visibility. These tiles are called invalid tiles, and they do not need to participate in subsequent rasterization and fragment processing.

[0105] In some implementations, feature extraction can be performed on multiple tiles to obtain the visual features of the multiple tiles. For example, methods for extracting visual features include, but are not limited to, depth buffer testing, color transparency detection, and occlusion culling algorithms.

[0106] In some implementations, the visual features of the tiles can be evaluated, and valid tiles can be determined from multiple tiles based on the evaluation results. This reduces unnecessary consumption of computing resources and bandwidth usage.

[0107] In this embodiment, the image to be rendered is divided into multiple tiles according to the screen size, and each tile is assigned a unique number. Then, valid tiles are selected by combining visual features. In this way, only valid tiles are traversed, data is acquired, and rendered, which can reduce redundant requests and the processing of invalid tiles. This can significantly improve the performance and bandwidth utilization of the graphics processor, thereby achieving more efficient image rendering and lower power consumption.

[0108] This application provides a graphics processor that performs the following steps: if a first tile number in the cache region is the same as the tile number of the tile to be read, the data of the first tile number in the cache region is used as the data of the tile to be read; if a first tile number in the cache region is not the same as the tile number of the tile to be read, a second tile number is determined to be contained in the data segment of the tile to be read; a tile data segment acquisition request is sent to the memory space based on the second tile number, and the data segment of the tile to be read is returned by the memory space.

[0109] This application provides a tile-based graphics system, comprising: a graphics processor, configured to: use data of the first tile number in the cache region as data of the tile to be read when the cache region has a first tile number that is the same as the tile number of the tile to be read; determine a second tile number contained in the data segment of the tile to be read when the cache region does not have a first tile number that is the same as the tile number of the tile to be read; send a tile data segment acquisition request to the memory space based on the second tile number, and receive the data segment of the tile to be read returned by the memory space; and a screen for displaying the image corresponding to the tile to be read based on the tile to be read.

[0110] The descriptions of the graphics processor and graphics system embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the graphics processor and graphics system provided in this application can be used to execute the methods described in the method embodiments above. For technical details not disclosed in the graphics processor and graphics system embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0111] The following describes the application of the tile data acquisition method provided in the embodiments of this application in a real-world scenario.

[0112] In a graphics rendering engine, graphics data input from software to the hardware processor via an application programming interface (API) is processed in the order of the geometry pipeline and fragment pipeline before being displayed on the screen. The geometry pipeline primarily handles graphics processing, transforming and clipping the input primitives before sending them to the fragment pipeline for rendering. The fragment pipeline includes operations such as rasterization and pixel shading. In addition, graphics systems are categorized into two types: direct rendering systems and tile-based systems.

[0113] Tiled-based graphics systems also require a tile-based operation after the geometry pipeline, assigning primitives to tiles they can cover. The fragment pipeline processes each tile. Multiple processing hardware components can be connected to the fragment pipeline, allowing for parallel processing of different tiles.

[0114] Tile partitioning divides the screen into multiple tiles, and, given the different numbers of rasterizers and processing cores in the hardware, different tiles may be assigned to different rasterizers for processing.

[0115] An early depth test or a hidden face removal module can be set between the rasterizer and the fragment shader to remove primitives that will be occluded by other primitives in advance, thereby reducing the workload of fragment processing and improving performance.

[0116] After rasterization (and early depth testing and hidden face removal), the attribute data carried by primitives and other vertex-based data are interpolated to sampled pixels. This interpolation is passed to the fragment shader in the form of a plane equation or sampled values ​​and participates in pixel shading calculations in the fragment shader.

[0117] like Figure 6 As shown, the overall image processing workflow includes: geometric processing stage, tileization, fragment processing stage, and blending / writing; among which, the fragment processing stage includes tile acquisition, rasterization, early depth testing, and fragment shader processing. Figure 7 As shown, after tileization, three tiles can be processed in parallel through three fragment processing stages and three blending / writing stages at the same time.

[0118] In existing technologies, the fragment processing stage traverses all tiles across the entire screen area and determines the tile that the current rasterizer should process based on different allocation rules. Then, it retrieves the corresponding tile control flow and data from the buffer or video memory. However, existing technologies have the following drawbacks: 1. The amount of control information data for a single tile is small, failing to effectively utilize the performance potential of storage and transmission bandwidth. 2. Some tiles may not have valid information, but the tile acquisition module still needs to traverse and acquire all tiles. 3. Due to memory alignment requirements, when acquiring data for a certain tile, data for surrounding tiles may be obtained simultaneously, or redundant data requests may occur.

[0119] This application aims to efficiently traverse and acquire tiles during the tile acquisition stage, improve bandwidth utilization, and reduce duplicate requests. This application has two important improvements: first, it distributes the range data of valid tiles on the screen from the geometry processing stage, and in the tile acquisition module, it only traverses and acquires tiles from the valid range (the range of valid tiles); second, it stores the tile numbers of previously requested tiles in a cache area to deduplicate already acquired tiles.

[0120] Specifically, the tiles are numbered sequentially and without repetition in the traversal order. During the tile acquisition phase, the screen range XMIN, XMAX, YMIN, YMAX (the range of valid tiles) passed to the tile acquisition module from the geometry phase is first obtained. Then, traversal begins from the tiles corresponding to XMIN and YMIN, and it is determined whether the tile is assigned to the current rasterizer. If a tile needs to be acquired, its tile number is searched in the cache area. If the tile number is found in the cache area, no further data request is needed; instead, the corresponding data is obtained from the data returned in the previous request. If the tile number is not found in the cache area, the data segment containing this tile is requested to further increase bandwidth utilization.

[0121] The specific implementation methods of this application are as follows: 1. The geometry processing stage transmits the range data of valid blocks to the fragment processing stage. Within the valid block range, traversal, validity checks (to determine the rasterizer corresponding to the image), and block acquisition are performed. The valid block range data transmitted in the geometry stage is obtained in the form of bounding boxes, including the minimum x-coordinate (XMIN), maximum x-coordinate (XMAX), minimum y-coordinate (YMIN), and maximum y-coordinate (YMAX) of all blocks containing valid blocks. These values ​​can be pixel coordinates or block coordinates.

[0122] 2. Start from the bounding box's XMIN and XMAX values, traversing in a row-by-row or zigzag order. Determine whether each tile should be assigned to the current rasterizer. (Any effective assignment method can be used, including but not limited to simple polling, real-time downstream processing load, etc.). Figure 8As shown, during the row-by-row traversal, the rasterizer assigned to each tile is determined using a simple polling method. Specifically, there are currently three rasterizers: rasterizer 1, rasterizer 2, and rasterizer 3. Following the row-by-row traversal method, the first tile in the first row is assigned to rasterizer 1, the second tile to rasterizer 2, the third tile to rasterizer 3, the fourth tile to rasterizer 1, the fifth tile to rasterizer 2, the sixth tile to rasterizer 3, the seventh tile to rasterizer 1, the eighth tile to rasterizer 2, the first tile in the second row to rasterizer 3, the second tile to rasterizer 1, the third tile to rasterizer 2, the fourth tile to rasterizer 3, and so on, thus assigning each tile on the screen to its corresponding rasterizer.

[0123] 3. If a tile needs to be processed by the current rasterizer, then attempt to retrieve the tile data of the current tile. The first step in attempting to retrieve the data is to check the temporary tile number. If the tile number of the currently processed tile is among the temporary tile numbers, it means that the data segment accessed in the previous tile data segment retrieval request contained the data of that tile. Therefore, no additional request is sent, and the tile data is retrieved from the cache area.

[0124] If the currently processed tile number is not temporarily stored, the temporarily stored tile number is cleared, the tile numbers contained in the data segment containing the current tile are recalculated, and a tile data segment retrieval request is issued. Alternatively, the temporarily stored tile number can be left uncleared and overwritten with the newly determined tile number, so that the cache area always stores the most recently accessed tile number.

[0125] 4. Calculation of tile numbers in a data segment: Tile control information is fixed-size data, tightly aligned in memory. Therefore, by using the current tile number and rounding down the number of tiles in a single data segment, the starting position of the data segment can be obtained: Data segment start = Data segment base address corresponding to the screen + (Tile number – Tile number % Number of tiles in a single data segment) × Address alignment unit.

[0126] This application can temporarily store the tile numbers contained in the currently acquired data segment (tile numbers from the start tile to the end tile). (tile number – tile number % number of tiles in a single data segment) to (tile number – tile number % number of tiles in a single data segment + number of tiles in a single data segment - 1).

[0127] The method described in this application can be extended to request multiple data segments in a single request. This improves bandwidth utilization for tile acquisition, reduces tile traversal time, and minimizes redundant tile information retrieval requests.

[0128] This application embodiment includes at least the following pre-protection points: 1. Obtain multiple data segments containing the tile and temporarily store the tile number on the data segment. If a temporarily stored number exists in subsequent traversals, the data in the data segment returned by the previous request is directly obtained. 2. The tile acquisition operation is performed from the range of valid tiles.

[0129] It should be noted that, in the embodiments of this application, if the above-described tile data acquisition method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0130] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0131] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0132] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0133] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0134] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0135] It should be noted that, Figure 9 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 9 As shown, the hardware entity of the computer device 900 includes: a graphics processor 901, a communication interface 902, and a memory 903, wherein: The graphics processor 901 typically controls the overall operation of the computer device 900.

[0136] Communication interface 902 enables computer devices to communicate with other terminals or servers over a network.

[0137] The memory 903 is configured to store instructions and applications executable by the graphics processor 901, and can also cache data to be processed or already processed by the graphics processor 901 and various modules in the computer device 900 (e.g., image data, audio data, voice communication data, and video communication data). It can be implemented using flash memory or random access memory (RAM). Data transfer between the graphics processor 901, the communication interface 902, and the memory 903 can be performed via bus 904.

[0138] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0139] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0141] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0142] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0143] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0144] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0145] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for acquiring map tile data, characterized in that, The method includes: If a first tile number exists in the cache area that is the same as the tile number of the tile to be read, the data of the first tile number in the cache area shall be used as the data of the tile to be read. If the cache region does not contain a first block number that is the same as the block number of the block to be read, determine the second block number contained in the data segment where the block to be read is located; based on the second block number, send a block data segment acquisition request to the memory space, and receive the data segment where the block to be read is located returned by the memory space.

2. The method according to claim 1, characterized in that, Determining the second tile number contained in the data segment where the tile to be read is located includes: Based on the tile number of the tile to be read and the number of tiles in a single data segment, determine the starting tile number of the data segment where the tile to be read is located; Based on the starting tile number, the number of tiles in the single data segment, and the target value, the ending tile number of the data segment containing the tile to be read is determined; the target value is determined by the encoding method of the tile number. Based on the starting and ending tile numbers of the data segment containing the tile to be read, the second tile number contained in the data segment containing the tile to be read is determined.

3. The method according to claim 2, characterized in that, The step of determining the starting tile number of the data segment containing the tile to be read, based on the tile number of the tile to be read and the number of tiles in a single data segment, includes: Based on the tile number of the tile to be read and the number of tiles in the single data segment, determine the tile number offset. Based on the tile number and number offset of the tile to be read, the starting tile number of the data segment where the tile to be read is located is determined.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The data segment address of the block to be read is determined based on the block number of the block to be read, the number of blocks in a single data segment, and the base address of the data segment on the screen. Based on the second tile number and the data segment address of the tile to be read, a request to obtain the tile data segment is sent to the memory space, and the data segment where the tile to be read is located is received from the memory space.

5. The method according to claim 4, characterized in that, The step of determining the data segment address of the image block to be read based on the image block number on the screen, the number of images in a single data segment, and the base address of the data segment on the screen includes: Based on the tile number of the tile to be read and the number of tiles in a single data segment, determine the starting tile number of the data segment where the tile to be read is located; Based on the starting tile number and the data segment base address, determine the starting address of the data segment where the tile to be read is located; The data segment address of the block to be read is determined based on the starting address of the data segment containing the block to be read.

6. The method according to claim 5, characterized in that, Determining the starting address of the data segment containing the block to be read based on the starting block number and the data segment base address includes: The address offset is determined based on the starting tile number and address alignment unit; Based on the address offset and the data segment base address, the starting address of the data segment containing the image block to be read is determined.

7. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Obtain the range data of valid tiles in the image to be rendered; The initial valid blocks are determined based on the range data of the valid blocks; Starting from the initial valid map piece, each valid map piece within the range data of the valid map piece is traversed in spatial order, and the rasterizer corresponding to each valid map piece is determined sequentially according to a preset allocation strategy; the spatial order matches the encoding method of the map piece number; the preset allocation strategy refers to the method of allocating map pieces to multiple rasterizers; When processing each valid map block using the raster corresponding to each valid map block, each valid map block is used as the map block to be read.

8. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Store the tile number of the tile to be read into the number cache area within the cache area; The data segment containing the image block to be read is stored in the data cache area within the cache area.

9. The method according to claim 7, characterized in that, The process of obtaining the range data of valid tiles in the image to be rendered includes: The image to be rendered is divided into multiple tiles according to the screen size; Based on the positions of the multiple tiles on the screen and the traversal method of the multiple tiles, the tile number of each of the multiple tiles on the screen is determined; Based on the visual features of the plurality of tiles, the valid tiles are determined from the plurality of tiles; the visual features are used to represent the content in the corresponding tiles.

10. A graphics processor, characterized in that, The graphics processor is used to perform the following steps: If a first tile number exists in the cache area that is the same as the tile number of the tile to be read, the data of the first tile number in the cache area shall be used as the data of the tile to be read. If the cache region does not contain a first block number that is the same as the block number of the block to be read, determine the second block number contained in the data segment where the block to be read is located; based on the second block number, send a block data segment acquisition request to the memory space, and receive the data segment where the block to be read is located returned by the memory space.

11. A tile-based graphics system, characterized in that, The graphics system includes: A graphics processor is configured to: when a first tile number in a cache region is identical to the tile number of the tile to be read, use the data of the first tile number in the cache region as the data of the tile to be read; when a first tile number identical to the tile number of the tile to be read is not present in the cache region, determine a second tile number contained in the data segment containing the tile to be read; and, based on the second tile number, issue a tile data segment acquisition request to a memory space, and receive the data segment containing the tile to be read returned by the memory space. A screen is used to display the image corresponding to the image to be read based on the image to be read.

12. A computer device, characterized in that, The computer device includes: Memory is used to store executable instructions or computer programs. A graphics processor, when executing computer-executable instructions or computer programs stored in the memory, implements the method of any one of claims 1 to 9.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a graphics processor, it implements the steps of the method according to any one of claims 1 to 9.

14. A computer program product comprising a non-transitory computer-readable storage medium storing a computer program, wherein when the computer program is read and executed by a computer device, it implements the steps of the method according to any one of claims 1 to 9.

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