Display device

Abstract

Embodiments of the present disclosure relate to a display apparatus, and more particularly, to a display apparatus detecting a line defect using drivers disposed in a display area. The display apparatus includes a display panel including a plurality of main drivers disposed in each of a plurality of unit driving areas, and a timing controller providing a synchronization signal and a clock signal to each of the plurality of main drivers through at least one first signal line. The timing controller is configured to receive a test output signal through a second signal line, the test output signal based on test output pulses outputted at different timings from at least two of the plurality of main drivers.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0173702, filed on November 28, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device. Background Technology

[0004] Display devices are used in a variety of electronic devices, such as televisions, mobile phones, laptops, and tablets. Display devices can include self-emissive organic light-emitting display (OLED) devices and liquid crystal display (LCD) devices that require a separate light source.

[0005] Recently, display devices utilizing light-emitting diodes (LEDs) have garnered significant attention as the next generation of display devices. Because LEDs are made from inorganic rather than organic materials, they offer advantages over liquid crystal displays (LCDs) or organic light-emitting displays (OLEDs) such as faster startup, higher luminous efficiency, and the ability to display high-brightness images. Summary of the Invention

[0006] Embodiments of this disclosure may provide a display device capable of detecting circuit defects caused by bending cracks by using a driver disposed in the display area.

[0007] Embodiments of this disclosure may provide a display device capable of efficiently driving multiple light-emitting devices using a driver disposed in a display area.

[0008] Embodiments of this disclosure may provide a display device that enables process optimization by using existing wiring to detect and repair circuit defects, without the need for separate wiring or pads.

[0009] Embodiments of this disclosure may provide a display device that can easily detect defects and defect locations in a signal line by delaying test pulses at different timing points, thereby significantly reducing the time and cost required for defect analysis.

[0010] Embodiments of this disclosure may provide a display device, comprising: a display panel including a plurality of main drivers disposed in each of a plurality of unit driving regions; and a timing controller that provides a synchronization signal and a clock signal to each of the plurality of main drivers via at least one first signal line. The timing controller may receive a test output signal via a second signal line, the test output signal being based on test output pulses output at different timings from at least two of the plurality of main drivers.

[0011] Embodiments of this disclosure may provide a display device, comprising: a plurality of main drivers disposed in each of a plurality of unit driving regions and including a clock buffer for delaying a test pulse provided through at least one first signal line; and a plurality of sub-drivers disposed in each of the plurality of unit driving regions and electrically connected to a corresponding main driver among the plurality of main drivers.

[0012] According to embodiments of the present disclosure, a display device can be provided that can detect circuit defects caused by bending cracks by using a driver disposed in the display area.

[0013] According to embodiments of the present disclosure, a display device can be provided that can efficiently drive multiple light-emitting devices using a driver disposed in a display area.

[0014] According to embodiments of this disclosure, a display device can be provided that enables process optimization by using existing circuitry to detect and repair circuit defects, without the need for separate wiring or pads.

[0015] According to embodiments of this disclosure, a display device can be provided that can easily detect defects and defect locations in signal lines by delaying test pulses at different timing points, thereby significantly reducing the time and cost required for defect analysis. Attached Figure Description

[0016] Figure 1 and Figure 2 A display device according to an embodiment of the present disclosure is shown.

[0017] Figure 3 A display panel according to an embodiment of the present disclosure is shown.

[0018] Figure 4 A unit driving area of ​​a display panel according to an embodiment of the present disclosure is shown.

[0019] Figure 5 Subpixels of a display panel according to an embodiment of this disclosure are shown.

[0020] Figures 6 to 8 This is a view used to further illustrate an embodiment of the display panel according to the present disclosure.

[0021] Figure 9 and Figure 10 This is a view used to illustrate in more detail the display panel according to embodiments of the present disclosure.

[0022] Figure 11 and Figure 12 This is a view used to illustrate a driver configured in a display device according to an embodiment of the present disclosure.

[0023] Figure 13 and Figure 14 This is a view used to specifically illustrate the main driver configured in a display device according to embodiments of the present disclosure.

[0024] Figures 15 to 17 This is a view used to illustrate an example of detecting a circuit defect in a timing controller provided in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0025] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to designate them even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein are omitted where it is determined that the description might make the subject matter of some embodiments of this disclosure unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] This document may use terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0027] When referring to a first element as being "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly in contact with or overlap" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled to," "in contact with," or "overlapping" with each other.

[0028] When time-relative terms (e.g., “after,” “following,” “next,” “before,” etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “direct” or “immediate” are used simultaneously.

[0029] Furthermore, when referring to any dimension, relative size, etc., the numerical value or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0030] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0031] Figure 1 and Figure 2 A display device 100 according to an embodiment of the present disclosure is shown.

[0032] Specifically, Figure 1 A schematic configuration of a display device 100 according to an embodiment of the present disclosure is shown, and Figure 2 A plan view of a display device 100 according to an embodiment of the present disclosure is shown.

[0033] refer to Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110, a cover member 118 disposed on the display panel 110, a flexible printed circuit 102 connected to the display panel 110, and a printed circuit board 104 connected to the flexible printed circuit 102.

[0034] The display device 100 according to an embodiment of the present disclosure may further include a support substrate 106 disposed below the display panel 110 and supporting the lower part of the display panel 110, a polarizing layer 114 disposed on the display panel 110, a first adhesive layer 112 disposed between the display panel 110 and the polarizing layer 114, and a second adhesive layer 116 disposed between the polarizing layer 114 and the cover member 118.

[0035] Display panel 110 may include substrate 210. Substrate 210 may be a component on which various components (e.g., multiple metal layers and multiple insulating material layers) are formed. Substrate 210 may be made of an insulating material. For example, substrate 210 may be made of glass or resin. Alternatively, substrate 210 may be made of a flexible material. For example, substrate 210 may be made of a flexible plastic material, such as polyimide (PI). However, embodiments of this disclosure are not limited thereto.

[0036] Display panel 110 can display information, images, and / or images provided to a user. For example, display panel 110 may include a display area DA and a non-display area NDA. For example, substrate 210 may include display area DA and non-display area NDA. Display area DA and non-display area NDA are not limited to substrate 210, but may be described throughout display device 100.

[0037] The display area DA can be an area for displaying an image. The display area DA can include multiple pixels P. Each of the multiple pixels P can be composed of multiple sub-pixels. At least one light-emitting device can be arranged in each of the multiple sub-pixels. Depending on the type of display device 100, the light-emitting devices can be configured differently. For example, if the display device 100 is an inorganic light-emitting display device, the light-emitting device can be an inorganic-based light-emitting device, such as a light-emitting diode (LED), a micro LED, or a mini LED, but the embodiments of this disclosure are not limited thereto.

[0038] The non-display area NDA can be an area where no image is displayed. Various wiring and circuitry for driving the multiple pixels P of the display area DA can be arranged in the non-display area NDA. For example, various driving circuits and wiring can be arranged in the non-display area NDA, and pad portions 211 connecting integrated circuits and printed circuits can be arranged, but embodiments of this disclosure are not limited thereto.

[0039] For example, the driving circuit may include data driving circuitry and / or gate driving circuitry, but embodiments of this disclosure are not limited thereto. Wires or lines providing control signals for controlling the driving circuitry may be arranged on the substrate 210. For example, the control signals may include various timing signals, including clock signals, input data enable signals, and synchronization signals, but embodiments of this disclosure are not limited thereto. The control signals may be provided to the substrate 210 from the outside via pad portions 211. For example, circuit components such as flexible printed circuit 102 and printed circuit board 104 may be connected to the pad portions 211.

[0040] According to this embodiment, the non-display area NDA may include a first non-display area NDA1, a curved area BA, and a second non-display area NDA2. For example, the first non-display area NDA1 may be a region surrounding at least a portion of the display area DA. The curved area BA may be a region extending from at least one of a plurality of sides of the first non-display area NDA1, and may be a flexible region. The second non-display area NDA2 may be a region extending from the curved area BA, and may include a pad portion 211. For example, the curved area BA may be in a curved state, and the remaining region of the substrate 210 other than the curved area BA may be in a flat state. In this case, when the curved area BA is curved, the second non-display area NDA2 may be located on the rear surface of the display area DA. However, embodiments of this disclosure are not limited thereto.

[0041] Depending on the design of the display device 100, the substrate 210 or the display area DA of the display device 100 can be configured in various shapes. For example, the display area DA can be configured as a rectangle with rounded corners, but embodiments of this disclosure are not limited thereto. As another example, the display area DA can be configured as a rectangle with right angles, or as a circle, but embodiments of this disclosure are not limited thereto.

[0042] According to embodiments of this disclosure, the width of the second non-display area NDA2, where the pad portion 211 is arranged, may be wider than the width of the curved area BA. Additionally, the width of the display area DA may be wider than the width of the curved area BA. In the drawings, the width of the curved area BA is depicted as narrower than the width of other areas of the substrate 210, but the shape of the substrate 210 including the curved area BA is exemplary, and embodiments of this disclosure are not limited thereto.

[0043] refer to Figure 1 and Figure 2The flexible printed circuit 102 and the printed circuit board 104 can be disposed at the lower part of the display panel 110. The flexible printed circuit 102 and the printed circuit board 104 can be arranged at one edge of the display panel 100, but embodiments of this disclosure are not limited thereto. One side of the flexible printed circuit 102 can be connected to the display panel 110, and the other side can be connected to the printed circuit board 104, but embodiments of this disclosure are not limited thereto. The flexible printed circuit 102 can be a flexible film, but embodiments of this disclosure are not limited thereto.

[0044] The pad portion 211, located in the second non-display area NDA2, includes multiple pads and can be attached to or bonded to a driving assembly comprising one or more flexible printed circuits 102 and a printed circuit board 104. The multiple pads included in the pad portion 211 are electrically connected to one or more flexible printed circuits 102 and can transmit various signals (or power supplies) from the printed circuit board 104 and the one or more flexible printed circuits 102 to a driving circuit arranged in the display area DA (e.g., Figure 3 The driver in the DRV).

[0045] The flexible printed circuit 102 can be a film on which various components are arranged on a flexible base film. For example, a first circuit component 230 (e.g., a gate driver integrated circuit and / or a data driver integrated circuit) can be arranged on one or more flexible printed circuits 102, but embodiments of this disclosure are not limited thereto. The first circuit component 230 can be a component that processes data and drive signals for displaying images. Depending on the mounting method, the first circuit component 230 can be arranged in a manner such as chip-on-glass (COG), chip-on-film (COF), or tape-on-carrier (TCP), but embodiments of this disclosure are not limited thereto. The flexible printed circuit 102 can be attached or bonded to multiple pads via a conductive adhesive layer, but embodiments of this disclosure are not limited thereto.

[0046] The printed circuit board 104 may be a component electrically connected to the flexible printed circuit 102 and providing signals to the first circuit component 230. The printed circuit board 104 may be disposed on one side of the flexible printed circuit 102 and may be electrically connected to the flexible printed circuit 102. Various components for providing various signals to the first circuit component 230 may be disposed on the printed circuit board 104. For example, various second circuit components 240, such as timing controllers, power supplies, memory, or processors, may be disposed on the printed circuit board 104. For example, the second circuit component 240 disposed on the printed circuit board 104 may include a timing controller and / or a power management integrated circuit (PMIC), but embodiments of this disclosure are not limited thereto.

[0047] Printed circuit board 104 may include at least one hole, but embodiments of this disclosure are not limited thereto. Internal components for detecting ambient light or temperature (e.g., multiple sensors) may be arranged in the area corresponding to the at least one hole. For example, the internal components may include an ambient light sensor (ALS) or a temperature sensor, but embodiments of this disclosure are not limited thereto. For example, the hole may be a transmissive hole, but embodiments of this disclosure are not limited thereto.

[0048] refer to Figure 1 The polarizing layer 114 can be arranged on the display panel 110 and can prevent or reduce the light generated from external light sources from entering the display panel 110 and affecting the light-emitting device.

[0049] The covering member 118 can be arranged on the polarizing layer 114 and can be a member used to protect the display panel 110.

[0050] The second adhesive layer 116 can be disposed between the polarizing layer 114 and the cover member 118. The second adhesive layer 116 can attach the cover member 118 to the display panel 110 or the polarizing layer 114.

[0051] The first adhesive layer 112 can be disposed between the display panel 110 and the polarizing layer 114. The first adhesive layer 112 can attach the polarizing layer 114 to the display panel 110. The first adhesive layer 112 can be omitted.

[0052] Each of the first adhesive layer 112 and the second adhesive layer 116 may include an optically transparent adhesive (OCA), an optically transparent resin (OCR), or a pressure-sensitive adhesive (PSA), but the embodiments of this disclosure are not limited thereto.

[0053] A support substrate 106 is disposed between the display panel 110 and the printed circuit board 104 to enhance the rigidity of the display panel 110. The support substrate 106 may be a backplate, but the embodiments of this disclosure are not limited thereto.

[0054] Figure 3 A display panel 110 according to an embodiment of the present disclosure is shown, and Figure 4 The unit driving region UDA of a display panel 110 according to an embodiment of the present disclosure is shown.

[0055] refer to Figure 3 The display area DA of the display panel 110 according to the embodiments of the present disclosure may include a plurality of unit driving areas UDA.

[0056] refer to Figure 3The display panel 110 according to embodiments of the present disclosure may include a driver DRV in each of a plurality of unit driving regions UDA. For example, the driver DRV may be a driver chip fabricated on a semiconductor substrate using a MOSFET (metal-oxide-semiconductor field-effect transistor) fabrication process, but embodiments of the present disclosure are not limited thereto.

[0057] refer to Figure 3 Each of the multiple unit-driven regions (UDAs) can be a driven region driven by a single driver (DRV). That is, the multiple unit-driven regions (UDAs) can be independent driven regions driven by different drivers (DRVs).

[0058] The driver DRV may include at least one master driver connected to a timing controller via signal lines, and a plurality of sub-drivers electrically connected to at least one master driver.

[0059] Each of the multiple sub-drivers can be electrically connected to at least one pixel among the multiple pixels P.

[0060] refer to Figure 3 According to embodiments of the present disclosure, the display panel 110 may include a substrate 210, which includes a display area DA and a plurality of pixels P arranged in a matrix in the display area DA.

[0061] Multiple pixels P can be arranged in each of multiple unit driving regions UDA. Each pixel of the multiple pixels P may include multiple sub-pixels SP. Each sub-pixel of the multiple sub-pixels SP may include at least one light-emitting device.

[0062] For example, multiple sub-pixels SP may include a first sub-pixel SPa, a second sub-pixel SPb, and a third sub-pixel SPc, but are not limited thereto. The first sub-pixel SPa may include a first light-emitting device that emits a first color light, the second sub-pixel SPb may include a second light-emitting device that emits a second color light, and the third sub-pixel SPc may include a third light-emitting device that emits a third color light. For example, the first color light, the second color light, and the third color light may be red light, green light, and blue light, respectively, but are not limited thereto.

[0063] refer to Figure 4 The display panel 110 according to embodiments of the present disclosure may include a plurality of light-emitting devices ED. Each of the plurality of sub-pixels SP may include a light-emitting device ED.

[0064] For example, the first sub-pixel SPa may include a first light-emitting device EDa, the second sub-pixel SPb may include a second light-emitting device EDb, and the third sub-pixel SPc may include a third light-emitting device EDc.

[0065] refer to Figure 4 The display panel 110 according to embodiments of the present disclosure may include multiple row lines RL and multiple column lines CL.

[0066] Each of the multiple row lines RL can be arranged to extend along the row direction. The multiple row lines RL can be electrically connected to the first electrode of each of the multiple light-emitting devices ED.

[0067] Each column line in the multiple column lines CL can be arranged to extend along the column direction. The multiple column lines CL can be electrically connected to the second electrode of each of the multiple light-emitting devices ED.

[0068] For example, the first electrode of each of the multiple light-emitting devices (EDs) can be an anode, and the second electrode of each of the multiple light-emitting devices can be a cathode. As another example, the first electrode of each of the multiple light-emitting devices (EDs) can be a cathode, and the second electrode of each of the multiple light-emitting devices can be an anode.

[0069] Each of the multiple row lines RL can be electrically connected to the second electrode of each of the multiple light-emitting devices ED. That is, the second electrode of each of the multiple light-emitting devices ED can be connected to a single row line RL.

[0070] Each of the multiple column lines CL can be electrically connected to the first electrode of each of the multiple light-emitting devices ED. That is, the first electrode of each of the multiple light-emitting devices ED can be connected to a single column line CL.

[0071] refer to Figure 4 The line width of each row line in multiple row lines RL can be greater than the line width of each column line in multiple column lines CL.

[0072] refer to Figure 4 The display panel 110 according to embodiments of the present disclosure may include a plurality of drivers DRV. The plurality of drivers DRV can drive a plurality of light-emitting devices ED, a plurality of column lines CL, and a plurality of row lines RL.

[0073] Multiple driver DRVs can be integrated into the display panel 110. The multiple driver DRVs can be arranged in display areas DA and can be arranged on the substrate 210. The multiple driver DRVs can be arranged to correspond to multiple unit driving areas UDA. That is, one driver DRV can be arranged in one unit driving area UDA.

[0074] Each driver in the multiple driver DRV can drive multiple row lines RL and multiple column lines CL arranged in the corresponding unit driver area UDA, thereby causing multiple light-emitting devices ED arranged in the corresponding unit driver area UDA to emit light.

[0075] Multiple driver DRVs are set in the display area DA and can be placed closer to the substrate 210 than multiple light-emitting devices EDs.

[0076] For example, multiple line lines RL can be driven sequentially. As another example, multiple line lines RL can be driven simultaneously. Yet another example, two or more line lines RL can be driven simultaneously.

[0077] For example, during a specific display driving period, among the multiple row lines RL arranged in the unit driving area UDA, at least one row line RL can be driven, and the remaining row lines RL can be left undriven.

[0078] According to embodiments of this disclosure, the voltage applied to the horizontal line RL can be referred to as a low-potential voltage, and the low-potential voltage can also be referred to as the horizontal line voltage or cathode voltage. The low-potential voltage can have various voltage values ​​depending on the drive type or drive state. For example, the low-potential voltage can include a first low-potential voltage, a second low-potential voltage, and a third low-potential voltage.

[0079] Driving a row line RL can mean providing a first low potential voltage to the row line RL. Not driving a row line RL can mean providing a second low potential voltage to the row line RL that is higher than the first low potential voltage. Therefore, a light-emitting device ED that overlaps with a driving row line RL can emit light, and a light-emitting device ED that overlaps with a non-driving row line RL can not emit light.

[0080] For example, any one of the multiple row lines RL can be provided with a first low potential voltage during a first time period, and can be provided with a second low potential voltage higher than the first low potential voltage during a second time period different from the first time period. Therefore, a light-emitting device ED overlapping with the first row line RL can emit light during the first time period and may not emit light during the second time period different from the first time period. For example, the first and second time periods can be included in a single display driving period. As another example, the first and second time periods can be included in different display driving periods.

[0081] Figure 5 Subpixels SP of a display panel 110 according to an embodiment of the present disclosure are shown.

[0082] refer to Figure 5 According to embodiments of the present disclosure, a sub-pixel SP may include: a light-emitting device ED, which includes a first electrode Ecl and a second electrode Erl; a column driver C-DRV for driving column lines CL electrically connected to the first electrode Ecl of the light-emitting device ED; and a row driver R-DRV for driving row lines RL electrically connected to the second electrode Erl of the light-emitting device ED.

[0083] refer to Figure 5 A light-emitting device (ED) may include a first electrode Ecl and a second electrode Erl. The first electrode Ecl may be electrically connected to a column line CL, and the second electrode Erl may be electrically connected to a row line RL. For example, the first electrode Ecl may be an anode, and the second electrode Erl may be a cathode. As another example, the first electrode Ecl may be a cathode, and the second electrode Erl may be an anode.

[0084] refer to Figure 5 The column driver C-DRV included in the unit driving region UDA can be connected to and drive the multiple column lines CL included in the unit driving region UDA. Each of the multiple column lines CL can be connected to the first electrode Ecl of each of the multiple light-emitting devices ED included in the multiple sub-pixels SP arranged in the corresponding column.

[0085] refer to Figure 5 The row driver R-DRV included in the unit driving region UDA can be connected to and drive multiple row lines RL included in the unit driving region UDA. Each of the multiple row lines RL can be connected to the second electrode Erl of each of the multiple light-emitting devices ED included in the multiple sub-pixels SP arranged in the corresponding row.

[0086] refer to Figure 5 The column driver C-DRV may include master nodes, which include a first node N1, a second node N2, a third node N3, and a fourth node N4. The column driver C-DRV may include a driving transistor DRT and a first emitter control transistor EMT1.

[0087] The first node N1 can be a node to which a voltage Vg is applied to control the on / off state of the driving transistor DRT. The second node N2 can be a node electrically connected to the high-potential voltage node NVDD to which the high-potential voltage VDD is applied. The third node N3 can be a node to which the driving transistor DRT and the first emitter control transistor EMT1 are connected. The fourth node N4 can be a node to which the first emitter control transistor EMT1 and the light-emitting device ED are electrically connected, and can be a node to which the column line CL is electrically connected. Here, the source or drain electrode of the first emitter control transistor EMT1 and the first electrode Ecl of the light-emitting device ED can be jointly connected to the column line CL.

[0088] The driving transistor DRT provides driving current to make the light-emitting device ED emit light. It is connected between the second node N2 and the third node N3, and the connection between the second node N2 and the third node N3 can be controlled according to the voltage of the first node N1.

[0089] The gate electrode of the driving transistor DRT is electrically connected to the first node N1, and a gate voltage Vg can be applied to it. The drain or source electrode of the driving transistor DRT can be electrically connected to the second node N2. The source or drain electrode of the driving transistor DRT can be electrically connected to the third node N3.

[0090] The first emitter control transistor EMT1 can control the connection of the path through which the drive current flows, and can also control the emission of the light-emitting device ED.

[0091] If the driving transistor DRT and the first emitter control transistor EMT1 are turned on between the high potential voltage VDD and the low potential voltage VSS, then the driving current can be supplied to the light-emitting device ED through the driving transistor DRT and the first emitter control transistor EMT1. Therefore, the light-emitting device ED can emit light.

[0092] The first emitter control transistor EMT1 is connected between the third node N3 and the fourth node N4, and the connection between the third node N3 and the fourth node N4 can be controlled according to the first emitter control signal EM1. The first emitter control signal EM1 can be applied to the gate electrode of the first emitter control transistor EMT1. The drain electrode or source electrode of the first emitter control transistor EMT1 can be electrically connected to the third node N3. The source electrode or drain electrode of the first emitter control transistor EMT1 can be electrically connected to the fourth node N4.

[0093] The first transmit control signal EM1 may be a pulse width modulated signal that varies over a predetermined period of time (e.g., per frame, or each subframe included in a frame), but embodiments of this disclosure are not limited thereto.

[0094] The first transmit control signal EM1 can be generated by the driver DRV, or it can be provided to the driver DRV from drive-related circuitry such as a timing controller.

[0095] refer to Figure 5 The row driver R-DRV can drive at least one row line RL by providing a low potential voltage VSS to at least one row line RL.

[0096] The row driver R-DRV can perform display enable or display disable driving on a row line RL.

[0097] The line driver R-DRV can provide a low-potential voltage to a line line RL for display enable driving, thereby executing the display enable drive for that line line RL. The line driver R-DRV can also provide a low-potential voltage to a line line RL for display disable driving, thereby executing the display disable drive for that line line RL.

[0098] The low potential voltage used to indicate the power-on drive and the low potential voltage used to indicate the power-off drive can be different. For example, the low potential voltage used to indicate the power-on drive can be lower than the low potential voltage used to indicate the power-off drive. In embodiments of this disclosure, the "low potential voltage used to indicate the power-on drive" is also referred to as the "first low potential voltage," and the "low potential voltage used to indicate the power-off drive" is also referred to as the "second low potential voltage."

[0099] refer to Figure 5 In addition to the driving transistor DRT and the first emitter control transistor EMT1, the column driver C-DRV may also include at least one switching element and / or at least one transistor. Each transistor included in the column driver C-DRV may be an n-type transistor or a p-type transistor.

[0100] The column driver C-DRV may also include at least one capacitor.

[0101] The column driver C-DRV may also include at least one circuit element. For example, the at least one circuit element may include a power output buffer.

[0102] refer to Figure 5 The row driver R-DRV may include at least one switching element and / or at least one transistor. Each transistor included in the row driver R-DRV may be an n-type transistor or a p-type transistor.

[0103] The line driver R-DRV may also include at least one circuit element. For example, at least one circuit element may include a power output buffer.

[0104] refer to Figure 5The column driver C-DRV and the row driver R-DRV can be internal circuitry included in the driver DRV. Alternatively, the column driver C-DRV and the row driver R-DRV may not be included in the driver DRV and may be circuitry formed on the substrate 210 of the display panel 110.

[0105] Figures 6 to 8 This is a view for further illustrating the display panel 110 according to an embodiment of the present disclosure.

[0106] Specifically, Figure 6 This is a plan view of a display panel 110 according to an embodiment of the present disclosure, and Figure 7 and Figure 8 This is a plan view of a portion (i.e., a two-row, two-column area) 700 of a display panel 110 according to an embodiment of the present disclosure.

[0107] More specifically, Figure 7 It is a plan view that does not show the two row lines RL(1) and RL(2) arranged in the two-row, two-column region 700, and Figure 8 It is a plan view with two row lines RL(1) and RL(2) added to part 700 of the display panel 110.

[0108] refer to Figure 6 According to embodiments of the present disclosure, the substrate 210 of the display panel 110 may include a display area DA and a non-display area NDA, and the non-display area NDA may include a first non-display area NDA1, a curved area BA and a second non-display area NDA2.

[0109] refer to Figure 6 Multiple driver radii (DRVs) can be arranged in the display area DA. Each driver in the multiple driver radii can be a circuit for driving the light-emitting devices of multiple sub-pixels included in the corresponding unit driving area UDA. Each driver in the multiple driver radii can include a row driver R-DRV for driving multiple row lines and a column driver C-DRV for driving multiple column lines, so as to drive the multiple light-emitting devices ED included in the corresponding unit driving area UDA.

[0110] refer to Figure 6 The pad portion 211, which includes multiple pads PD, can be arranged in the second non-display area NDA2.

[0111] refer to Figure 6Multiple signal lines SL and multiple link lines LL, used for transmitting signals between multiple driver DRVs arranged in the display area DA and the pad portion 211, can be arranged on the substrate 210. The multiple signal lines SL can be electrically connected between the multiple link lines LL and the multiple driver DRVs. The multiple link lines LL can be electrically connected to multiple pads PD and the multiple signal lines SL.

[0112] refer to Figure 6 Multiple link lines LL can be arranged in the non-display area NDA, and all or part of each of the multiple signal lines SL can be arranged in the display area DA.

[0113] Each driver in a multi-driver DRV can receive various signals to perform drive operations via multiple link lines LL and multiple signal lines SL. These signals can include various power supply voltages and other signals required for the drive operation of each driver in the multi-driver DRV.

[0114] As the bending region BA is bent, a portion of the multiple connecting lines LL may also be bent. Stress may concentrate on a portion of the bent connecting lines LL, and therefore cracks may appear in the connecting lines LL. Therefore, the multiple connecting lines LL can be formed of a conductive material with excellent ductility to reduce cracking that occurs when the bending region BA is bent. For example, the multiple connecting lines LL can be formed of a conductive material with excellent ductility (e.g., gold (Au), silver (Ag), aluminum (Al)), but embodiments of this disclosure are not limited thereto. In addition, the multiple connecting lines LL can be made of one of the various conductive materials used in the display region DA. For example, the multiple connecting lines LL can be made of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or alloys thereof, but embodiments of this disclosure are not limited thereto. The multiple connecting lines LL can be made of a multilayer structure comprising various conductive materials. For example, multiple link lines LL can be composed of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments of this disclosure are not limited thereto.

[0115] Multiple link lines LL can be configured in various shapes to reduce stress. At least a portion of the multiple link lines LL arranged on the curved region BA can extend in the same direction as the extending direction of the curved region BA, or can extend in a direction different from the extending direction of the curved region BA, to reduce stress. For example, if the curved region BA extends in a direction from the first non-display region NDA1 to the second non-display region NDA2, then at least a portion of the multiple link lines LL arranged on the curved region BA can extend in a direction inclined to that direction. Furthermore, at least a portion of the multiple link lines LL can be configured as patterns of various shapes. For example, at least a portion of the multiple link lines LL arranged on the curved region BA can be a shape of repeatedly arranged conductive patterns having at least one of the following shapes: diamond shape, rhombus shape, trapezoidal waveform, triangular waveform, sawtooth waveform, sine waveform, circular shape, and omega (Ω) shape, but embodiments of this disclosure are not limited thereto. Therefore, in order to minimize stress concentrated on the multiple link lines LL and the resulting cracks, the shape of the multiple link lines LL can be formed in various shapes including the above-mentioned shapes, but embodiments of this disclosure are not limited thereto.

[0116] refer to Figure 7 and Figure 8 In a two-row, two-column region 700, four pixels P(1,1), P(1,2), P(2,1), and P(2,2) can be arranged in two rows and two columns. That is, in the two-row, two-column region 700, two pixels P(1,1) and P(1,2) can be arranged in the first row (e.g., the first pixel row), and two pixels P(2,1) and P(2,2) can be arranged in the second row (e.g., the second pixel row). Additionally, two pixels P(1,1) and P(2,1) can be arranged in the first column (e.g., the first pixel column), and two pixels P(1,2) and P(2,2) can be arranged in the second column (e.g., the second pixel column).

[0117] refer to Figure 7 and Figure 8 In the two-row, two-column region 700, each of the four pixels P(1,1), P(1,2), P(2,1), and P(2,2) arranged in two rows and two columns can include k sub-pixels. Here, k is the number of sub-pixels included in a pixel.

[0118] exist Figure 7 and Figure 8 The following description uses the case where k is 3 as an example. Therefore, in a two-row, two-column region 700, each of the four pixels P(1,1), P(1,2), P(2,1), and P(2,2) arranged in two rows and two columns can include three sub-pixels SPa, SPb, and SPc. In the following description, the case where k is 3 can be assumed.

[0119] The three sub-pixels may include: a first sub-pixel SPa, which includes a first light-emitting device EDa that emits light of a first color; a second sub-pixel SPb, which includes a second light-emitting device EDb that emits light of a second color; and a third sub-pixel SPc, which includes a third light-emitting device EDc that emits light of a third color.

[0120] If the display panel 110 according to an embodiment of this disclosure has a redundant structure, the sub-pixel redundancy structure is as follows.

[0121] The first sub-pixel SPa may include: a first main sub-pixel SPa_M, which includes a first main light-emitting device EDa_M; and a first redundant sub-pixel SPa_R, which includes a first redundant light-emitting device EDa_R; the second sub-pixel SPb may include: a second main sub-pixel SPb_M, which includes a second main light-emitting device EDb_M; and a second redundant sub-pixel SPb_R, which includes a second redundant light-emitting device EDb_R; and the third sub-pixel SPc may include: a third main sub-pixel SPc_M, which includes a third main light-emitting device EDc_M; and a third redundant sub-pixel SPc_R, which includes a third redundant light-emitting device EDc_R.

[0122] If the display panel 110 according to an embodiment of the present disclosure has a redundant structure, the light-emitting device redundancy structure is as follows.

[0123] The first light-emitting device EDa may include a first main light-emitting device EDa_M that emits light of the first color and a first redundant light-emitting device EDa_R that emits light of the first color; the second light-emitting device EDb may include a second main light-emitting device EDb_M that emits light of the second color and a second redundant light-emitting device EDb_R that emits light of the second color; and the third light-emitting device EDb may include a third main light-emitting device EDc_M that emits light of the third color and a third redundant light-emitting device EDc_R that emits light of the third color.

[0124] refer to Figure 7 and Figure 8 In a two-row, two-column region 700, a first row line RL(1) and a second row line RL(2) can be arranged. The first row line RL(1) can be arranged in the first row (i.e., the first pixel row), and the second row line RL(2) can be arranged in the second row (i.e., the second pixel row).

[0125] The first row line RL(1) can correspond to two pixels P(1,1) and P(1,2) arranged in the first row (or first pixel row), and can correspond to the three sub-pixels SPa, SPb and SPc included in each of the two pixels P(1,1) and P(1,2) arranged in the first row (or first pixel row).

[0126] Regarding the subpixel redundancy structure, the first row line RL(1) can be connected to the first principal subpixel SPa_M, the first redundant subpixel SPa_R, the second principal subpixel SPb_M, the second redundant subpixel SPb_R, the third principal subpixel SPc_M, and the third redundant subpixel SPc_R arranged in the first row (or the first pixel row).

[0127] At least a portion of the first row line RL(1) may overlap with the first principal sub-pixel SPa_M, the first redundant sub-pixel SPa_R, the second principal sub-pixel SPb_M, the second redundant sub-pixel SPb_R, the third principal sub-pixel SPc_M, and the third redundant sub-pixel SPc_R arranged in the first row (or the first pixel row).

[0128] From the perspective of the redundant structure of the light-emitting device, the first row line RL(1) can be connected to the second electrode Erl of each of the first main light-emitting device EDa_M, the first redundant light-emitting device EDa_R, the second main light-emitting device EDb_M, the second redundant light-emitting device EDb_R, the third main light-emitting device EDc_M and the third redundant light-emitting device EDc_R arranged in the first row (or the first pixel row).

[0129] At least a portion of the first row line RL(1) may overlap with the first main light-emitting device EDa_M, the first redundant light-emitting device EDa_R, the second main light-emitting device EDb_M, the second redundant light-emitting device EDb_R, the third main light-emitting device EDc_M, and the third redundant light-emitting device EDc_R arranged in the first row (or the first pixel row).

[0130] The second row line RL(2) can correspond to two pixels P(2,1) and P(2,2) arranged in the second row (or second pixel row), and can correspond to the three sub-pixels SPa, SPb and SPc included in each of the two pixels P(2,1) and P(2,2) arranged in the second row (or second pixel row).

[0131] Regarding the subpixel redundancy structure, the second row line RL(2) can be connected to the first principal subpixel SPa_M, the first redundant subpixel SPa_R, the second principal subpixel SPb_M, the second redundant subpixel SPb_R, the third principal subpixel SPc_M, and the third redundant subpixel SPc_R arranged in the second row (or the second pixel row).

[0132] At least a portion of the second row line RL(2) may overlap with the first principal sub-pixel SPa_M, the first redundant sub-pixel SPa_R, the second principal sub-pixel SPb_M, the second redundant sub-pixel SPb_R, the third principal sub-pixel SPc_M, and the third redundant sub-pixel SPc_R arranged in the second row (or the second pixel row).

[0133] Regarding the redundant structure of the light-emitting devices, the second row line RL(2) can be connected to the second electrode Erl of each of the first main light-emitting device EDa_M, the first redundant light-emitting device EDa_R, the second main light-emitting device EDb_M, the second redundant light-emitting device EDb_R, the third main light-emitting device EDc_M, and the third redundant light-emitting device EDc_R arranged in the second row (or the second pixel row).

[0134] At least a portion of the second row line RL(2) may overlap with the first main light-emitting device EDa_M, the first redundant light-emitting device EDa_R, the second main light-emitting device EDb_M, the second redundant light-emitting device EDb_R, the third main light-emitting device EDc_M, and the third redundant light-emitting device EDc_R arranged in the second row (or the second pixel row).

[0135] refer to Figure 7 and Figure 8 Multiple column lines CL can be arranged in the two-row, two-column area 700. The multiple column lines CL arranged in the two-row, two-column area 700 may include: multiple first column lines CL connected to two pixels P(1, 1) and P(2, 1) arranged in the first column (or first pixel column); and multiple second column lines CL connected to two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column).

[0136] refer to Figure 7 and Figure 8 From the perspective of subpixel redundancy, the multiple first column lines CL arranged in the first column (or first pixel column) may include: a first main column line CLa_M, which is jointly connected to the first main subpixel SPa_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or first pixel column); and a first redundant column line CLa_R, which is jointly connected to the first redundant subpixel SPa_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or first pixel column).

[0137] The first primary sub-pixel SPa_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a first primary light-emitting device EDa_M, and the first redundant sub-pixel SPa_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a first redundant light-emitting device (EDa_R).

[0138] The first main column line CLa_M arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two first main light-emitting devices EDa_M arranged in the first column (or first pixel column).

[0139] The first redundant column line CLa_R arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two first redundant light-emitting devices EDa_R arranged in the first column (or first pixel column).

[0140] Additionally, the multiple first column lines CL arranged in the first column (or first pixel column) may also include: a second main column line CLb_M, which is jointly connected to the second main sub-pixel SPb_M included in each of the two pixels P(1, 1) and P(2, 1) arranged in the first column (or first pixel column); and a second redundant column line CLb_R, which is jointly connected to the second redundant sub-pixel SPb_R included in each of the two pixels P(1, 1) and P(2, 1) arranged in the first column (or first pixel column).

[0141] The second primary sub-pixel SPb_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a second primary light-emitting device EDb_M, and the second redundant sub-pixel SPb_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a second redundant light-emitting device EDb_R.

[0142] The second main column line CLb_M arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two second main light-emitting devices EDb_M arranged in the first column (or first pixel column).

[0143] The second redundant column line CLb_R arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two second redundant light-emitting devices EDb_R arranged in the first column (or first pixel column).

[0144] Additionally, the multiple first column lines CL arranged in the first column (or first pixel column) may also include: a third main column line CLc_M, which is jointly connected to the third main sub-pixel SPc_M included in each of the two pixels P(1, 1) and P(2, 1) arranged in the first column (or first pixel column); and a third redundant column line CLc_R, which is jointly connected to the third redundant sub-pixel SPc_R included in each of the two pixels P(1, 1) and P(2, 1) arranged in the first column (or first pixel column).

[0145] The third main sub-pixel SPc_M included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a third main light-emitting device EDc_M, and the third redundant sub-pixel SPc_R included in each of the two pixels P(1,1) and P(2,1) arranged in the first column (or the first pixel column) may include a third redundant light-emitting device EDc_R.

[0146] The third main column line CLc_M arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two third main light-emitting devices EDc_M arranged in the first column (or first pixel column).

[0147] The third redundant column line CLc_R arranged in the first column (or first pixel column) can be connected together to the first electrode Ecl of the two third redundant light-emitting devices EDc_R arranged in the first column (or first pixel column).

[0148] refer to Figure 7 and Figure 8 From the perspective of subpixel redundancy, the multiple second column lines CL arranged in the second column (or second pixel column) may include: a first main column line CLa_M, which is jointly connected to the first main subpixel SPa_M included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column); and a first redundant column line CLa_R, which is jointly connected to the first redundant subpixel SPa_R included in each of the two pixels P(1,2) and P(2,2) arranged in the second column (or second pixel column).

[0149] The first primary sub-pixel SPa_M included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a first primary light-emitting device EDa_M, and the first redundant sub-pixel SPa_R included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a first redundant light-emitting device EDa_R.

[0150] The first main column line CLa_M arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two first main light-emitting devices EDa_M arranged in the second column (or second pixel column).

[0151] The first redundant column line CLa_R arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two first redundant light-emitting devices EDa_R arranged in the second column (or second pixel column).

[0152] Additionally, the multiple second column lines CL arranged in the second column (second pixel column) may also include: a second main column line CLb_M, which is jointly connected to the second main sub-pixel SPb_M included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column); and a second redundant column line CLb_R, which is jointly connected to the second redundant sub-pixel SPb_R included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column).

[0153] The second primary sub-pixel SPb_M included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a second primary light-emitting device EDb_M, and the second redundant sub-pixel SPb_R included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a second redundant light-emitting device EDb_R.

[0154] The second main column line CLb_M arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two second main light-emitting devices EDb_M arranged in the second column (or second pixel column).

[0155] The second redundant column line CLb_R arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two second redundant light-emitting devices EDb_R arranged in the second column (or second pixel column).

[0156] Additionally, the multiple first column lines CL arranged in the second column (or second pixel column) may also include: a third main column line CLc_M, which is jointly connected to the third main sub-pixel SPc_M included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column); and a third redundant column line CLc_R, which is jointly connected to the third redundant sub-pixel SPc_R included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column).

[0157] The third primary sub-pixel SPc_M included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a third primary light-emitting device EDc_M, and the third redundant sub-pixel SPc_R included in each of the two pixels P(1, 2) and P(2, 2) arranged in the second column (or second pixel column) may include a third redundant light-emitting device EDc_R.

[0158] The third main column line CLc_M arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two third main light-emitting devices EDc_M arranged in the second column (or second pixel column).

[0159] The third redundant column line CLc_R arranged in the second column (or second pixel column) can be connected together to the first electrode Ecl of the two third redundant light-emitting devices EDc_R arranged in the second column (or second pixel column).

[0160] refer to Figure 7 and Figure 8 In each of the first column (or first pixel column) and the second column (or second pixel column), each of the plurality of column lines CL may include at least one column connection electrode having a shape that protrudes above the embankment portion BNK. For example, the at least one column connection electrode may be an electrode electrically connected to each of the plurality of column lines CL, or it may be a portion protruding from each of the plurality of column lines C.

[0161] refer to Figure 7 and Figure 8 Each of the first main column line CLa_M, the second main column line CLb_M, and the third main column line CLc_M may include a main column connection electrode CCE_M that protrudes above the dike section BNK and extends above the dike section BNK.

[0162] The first main light-emitting device EDa_M, the second main light-emitting device EDb_M, and the third main light-emitting device EDc_M can be arranged on the main column connecting electrode CCE_M, which is arranged to extend above the embankment BNK.

[0163] refer to Figure 10 and Figure 11 In each of the first column (or first pixel column) and the second column (or second pixel column), each of the first redundant column line CLa_R, the second redundant column line CLb_R and the third redundant column line CLc_R may include a redundant column connection electrode CCE_R that protrudes toward and extends above the embankment BNK.

[0164] On the redundant column connection electrode CCE_R, which is arranged to extend above the embankment BNK, a first redundant light-emitting device EDa_R, a second redundant light-emitting device EDb_R, and a third redundant light-emitting device EDc_R can be arranged.

[0165] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the first column (or first pixel column) can be set between the first main column line CLa_M and the first redundant column line CLa_R.

[0166] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the second column (or second pixel column) can be set between the second main column line CLb_M and the second redundant column line CLb_R.

[0167] The main column connection electrode CCE_M and the redundant column connection electrode CCE_R arranged in the third column (or the third pixel column) can be set between the third main column line CLc_M and the third redundant column line CLc_R.

[0168] The display panel 110 according to an embodiment of the present disclosure may further include at least one row connection electrode for electrically connecting each of a plurality of row lines RL to a driver DRV.

[0169] refer to Figure 7 and Figure 8 The display panel 110 according to an embodiment of the present disclosure may further include: at least one first row connection electrode RCE (1) connected to a first row line RL (1) arranged in the first row (or first pixel row); and at least one second row connection electrode RCE (2) connected to a second row line RL (2) arranged in the second row (or second pixel row).

[0170] The first row line RL(1) may be perpendicularly overlapped with at least one first row connecting electrode RCE(1), and the second row line RL(2) may be perpendicularly overlapped with at least one second row connecting electrode RCE(2).

[0171] The first row line RL(1) can be electrically connected to the row driver R-DRV of the corresponding driver DRV through at least one first row connection electrode RCE(1). The second row line RL(2) can be electrically connected to the row driver R-DRV of the corresponding driver DRV through at least one second row connection electrode RCE(2).

[0172] According to embodiments of this disclosure, embankment BNKs can be arranged in each of a plurality of sub-pixels SP. The plurality of embankment BNKs can be structures on which a plurality of light-emitting devices EDs are mounted. During panel manufacturing, during the transfer process of transferring the plurality of light-emitting devices EDs to the display device 100, the plurality of embankment BNKs can guide the position of the plurality of light-emitting devices EDs. That is, during panel manufacturing, during the transfer process of the plurality of light-emitting devices EDs, the plurality of light-emitting devices EDs can be transferred onto the plurality of embankment BNKs. The plurality of embankment BNKs can be organic insulating layers, embankment patterns, or structures, but embodiments of this disclosure are not limited thereto.

[0173] The embankment BNK of each subpixel in the plurality of subpixels SP can be arranged spaced apart from each other. The embankment BNK of each subpixel in the plurality of subpixels SP can be configured to be separated from each other. Therefore, the embankment BNK of the first subpixel SP1, the embankment BNK of the second subpixel SP2, and the embankment BNK of the third subpixel SP3, which have transferred different types of light-emitting devices ED, can be easily identified.

[0174] The dam portion BNK of the first primary sub-pixel SPa_M and the dam portion BNK of the first redundant sub-pixel SPa_R can be connected to each other, or they can be spaced apart or separated. For example, considering the design requirements of the transfer process, the dam portion BNK of the first primary sub-pixel SPa_M and the dam portion BNK of the first redundant sub-pixel SPa_R (where light-emitting devices EDa_M and EDa_R of the same type (e.g., those emitting the same color of light) are arranged) can be connected to each other, or they can be spaced apart or separated. Furthermore, the dam portion BNK of the second primary sub-pixel SPb_M and the dam portion BNK of the second redundant sub-pixel SPb_R can be connected to each other, or they can be spaced apart or separated. The dam portion BNK of the third primary sub-pixel SPc_M and the dam portion BNK of the third redundant sub-pixel SPc_R can be connected to each other, or they can be spaced apart or separated.

[0175] The embankment BNK of the first principal sub-pixel SPa_M and the first redundant sub-pixel SPa_R, the embankment BNK of the second principal sub-pixel SPb_M and the second redundant sub-pixel SPb_R, and the embankment BNK of the third principal sub-pixel SPc_M and the third redundant sub-pixel SPc_R can be formed in various ways, and the embodiments of this disclosure are not limited thereto.

[0176] For example, multiple dammed BNKs can be formed of organic insulating materials. Multiple dammed BNKs can be formed of single-layer or multi-layer organic insulating materials. For example, multiple dammed BNKs can be made of photoresist, polyimide (PI), or acrylic materials, but the embodiments of this disclosure are not limited thereto.

[0177] Multiple row lines RL can be formed of a transparent conductive material, but embodiments of this disclosure are not limited thereto. The multiple row lines RL can be made of a transparent conductive material so that light emitted from the light-emitting device ED can be guided upwards through the row lines RL. For example, the multiple row lines RL can be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but embodiments of this disclosure are not limited thereto.

[0178] Multiple column lines CL can be made of conductive materials. For example, multiple column lines CL can be formed of conductive materials (e.g., titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO)), but the embodiments of this disclosure are not limited thereto. As another example, multiple column lines CL can have a multilayer structure of conductive materials. For example, multiple column lines CL can be made of a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0179] For example, if the light-emitting device (ED) is a device manufactured using semiconductor processes, such as micro-LEDs, multiple EDs can be formed on a wafer, and the EDs can be transferred to the substrate 210 of the display panel 110 to manufacture the display panel 110. During the transfer of multiple EDs of micro-sized dimensions from the wafer to the substrate 210, various defects may occur. For example, non-transfer defects may occur, where the ED is not transferred in some sub-pixel SPs; and misalignment defects may occur, where the ED is transferred outside its correct position due to alignment errors in other sub-pixel SPs. Additionally, the transfer process may proceed normally, but the transferred ED itself may be defective. Therefore, considering the defects that occur during the transfer process of the ED (including non-transfer defects), a main ED and redundant EDs of the same type (e.g., EDs emitting the same color of light) can be transferred to a single sub-pixel SP. Illumination tests can be performed on the main ED and redundant EDs of the same type, and only the one ultimately determined to be normal can be used.

[0180] For example, the first primary light-emitting device EDa_M and the first redundant light-emitting device EDa_R can be transferred together to a first sub-pixel SPa, and defects in the first primary light-emitting device EDa_M and the first redundant light-emitting device EDa_R can be checked. If the check determines that both the first primary light-emitting device EDa_M and the first redundant light-emitting device EDa_R are normal, then only the first primary light-emitting device EDa_M can be used, and the first redundant light-emitting device EDa_R can be omitted. If the check results show that only the first redundant light-emitting device EDa_R is normal, then the first primary light-emitting device EDa_M is not used, and only the first redundant light-emitting device EDa_R can be used. Therefore, even if the same first primary light-emitting device EDa_M and the first redundant light-emitting device EDa_R are transferred to a first sub-pixel SPa, ultimately only one of the first primary light-emitting device EDa_M and the first redundant light-emitting device EDa_R can be used.

[0181] Therefore, among the main light-emitting device and the redundant light-emitting device arranged in a sub-pixel SP, the redundant light-emitting device can be a backup light-emitting device that is transferred in preparation for the failure of the main light-emitting device. If the main light-emitting device fails, it can be replaced by the redundant light-emitting device. Therefore, by transferring the main light-emitting device and the redundant light-emitting device together to a sub-pixel SP, the degradation of display quality due to the defect of one of the main light-emitting device and the redundant light-emitting device can be minimized.

[0182] In the embodiments of this disclosure, the first principal sub-pixel SPa_M and the first redundant sub-pixel SPa_R can also be referred to as sub-pixel 1-1 and sub-pixel 1-2, respectively; the second principal sub-pixel SPb_M and the second redundant sub-pixel SPb_R can also be referred to as sub-pixel 2-1 and sub-pixel 2-2, respectively; and the third principal sub-pixel SPc_M and the third redundant sub-pixel SPc_R can also be referred to as sub-pixel 3-1 and sub-pixel 3-2, respectively.

[0183] In the embodiments of this disclosure, the first main light-emitting device EDa_M and the first redundant light-emitting device EDa_R can also be referred to as light-emitting device 1-1 and light-emitting device 1-2, the second main light-emitting device EDb_M and the second redundant light-emitting device EDb_R can also be referred to as light-emitting device 2-1 and light-emitting device 2-2, and the third main light-emitting device EDc_M and the third redundant light-emitting device EDc_R can also be referred to as light-emitting device 3-1 and light-emitting device 3-2.

[0184] refer to Figure 7 and Figure 8The display panel 110 according to an embodiment of the present disclosure may further include multiple communication lines NL. The multiple communication lines NL may be arranged so as not to overlap with the metal layer in the vertical direction. For example, the multiple communication lines NL may be arranged between the first row line RL(1) and the second row line RL(2).

[0185] For example, multiple communication lines NL can be wires used for short-range communication (e.g., NFC (Near Field Communication) and Bluetooth). Multiple communication lines NL can be used as signal transmission lines and / or antennas, but embodiments of this disclosure are not limited thereto.

[0186] refer to Figure 8 The first row line RL(1) can be arranged above the multiple light-emitting devices arranged in the first row (or the first pixel row) and can be arranged as a strip that overlaps with all the multiple light-emitting devices arranged in the first row (or the first pixel row).

[0187] The second row line RL(2) can be arranged above the multiple light-emitting devices arranged in the second row (or the second pixel row) and can be arranged as a strip that overlaps with all the multiple light-emitting devices arranged in the second row (or the second pixel row).

[0188] Figure 9 and Figure 10 This is a view for more specifically illustrating the display panel 110 according to an embodiment of the present disclosure.

[0189] Specifically, Figure 9 It is along Figure 6 A detailed cross-sectional view of the display panel 110 according to an embodiment of the present disclosure, taken by the AB cutting line, and Figure 10 This is an enlarged cross-sectional view of the sub-pixel SP of the display panel 110 according to an embodiment of the present disclosure.

[0190] Meanwhile, for ease of explanation, Figure 6 The AB cut line is shown as not overlapping with signal line SL and link line LL, but Figure 6 The AB cut line is intended to indicate the same position as the adjacent signal line SL and link line LL.

[0191] refer to Figure 9 A buffer layer 911 may be disposed on the substrate 210. The buffer layer 911 may include a first buffer layer 911a and a second buffer layer 911b. The first buffer layer 911a and the second buffer layer 911b may be disposed in the display area DA, the first non-display area NDA1 and the second non-display area NDA, and may not be disposed in all or part of the curved area BA. However, the present disclosure is not limited thereto.

[0192] The first buffer layer 911a and the second buffer layer 911b can reduce the permeation of moisture or impurities through the substrate 210. The first buffer layer 911a and the second buffer layer 911b can be made of inorganic insulating materials. For example, the first buffer layer 911a and the second buffer layer 911b can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments of this disclosure are not limited thereto.

[0193] For example, portions of the first buffer layer 911a and the second buffer layer 911b located on the curved region BA can be removed. The area where the first buffer layer 911a and the second buffer layer 911b have been removed (e.g., an opening) can expose the upper surface of the substrate 210 located on the curved region BA.

[0194] By removing the first buffer layer 911a and the second buffer layer 911b from the bending region BA, the occurrence of cracks in the first buffer layer 911a and the second buffer layer 911b that may occur during bending can be minimized.

[0195] Multiple alignment keys MK can be arranged between the first buffer layer 911a and the second buffer layer 911b. The multiple alignment keys MK can be configured to identify the position of the driver DRV during the manufacturing process of the display panel 110. For example, the multiple alignment keys MK can be configured to align the position of the driver DRV transferred to the adhesive layer 912. In another example, the multiple alignment keys MK can be omitted.

[0196] Adhesive layer 912 may be disposed on second buffer layer 911b. Adhesive layer 912 may be disposed in display area DA, first non-display area NDA1, curved area BA, and second non-display area NDA2. For example, in non-display area NDA including curved area BA, at least a portion of adhesive layer 912 may be removed. For example, adhesive layer 912 may be made of any of the following: adhesive polymer, epoxy resin, UV-curable resin, polyimide series, acrylate series, polyurethane series, and polydimethylsiloxane (PDMS), but the embodiments of this disclosure are not limited thereto.

[0197] The driver DRV can be disposed on the adhesive layer 912 in the display area DA. If the driver DRV is implemented as a driver chip (e.g., a driver integrated circuit), the driver can be mounted on the adhesive layer 912 by a transfer process, but embodiments of this disclosure are not limited thereto.

[0198] The display panel 110 may further include a side protective layer 913 disposed on the sides of the plurality of driver DRVs, and an upper protective layer 914 disposed on the plurality of driver DRVs and the side protective layer 913. For example, the side protective layer 913 may include at least one of a first protective layer 913a and a second protective layer 913b disposed on the sides of the plurality of driver DRVs, and in some cases may also include at least one additional protective layer. The first protective layer 913a and the second protective layer 913b may be disposed on the adhesive layer 912. The first protective layer 913a and the second protective layer 913b may be configured to surround the side surface of the driver DRV, but embodiments of the present disclosure are not limited thereto. For example, the second protective layer 913b may be arranged to cover at least a portion of the upper surface of the driver DRV. For example, at least one of the first protective layer 913a and the second protective layer 913b disposed on the curved region BA may be omitted. For example, the first protective layer 913a may be completely disposed on the display area DA and the non-display area NDA, and the second protective layer 913b may be partially disposed on the display area DA, the first non-display area NDA1, and the second non-display area NDA2. For example, at least a portion of the second protective layer 913b may be removed from all or part of the curved area BA. However, embodiments of this disclosure are not limited thereto.

[0199] For example, the side protective layer 913, which includes at least one of the first protective layer 913a and the second protective layer 913b, may be composed of an organic insulating material (i.e., an organic layer), but embodiments of this disclosure are not limited thereto. For example, the first protective layer 913a and the second protective layer 913b may be composed of photoresist, polyimide (PI), or photoacrylic acid-based materials, but embodiments of this disclosure are not limited thereto. For example, the first protective layer 913a and the second protective layer 913b may be an outer coating or an insulating layer, but embodiments of this disclosure are not limited thereto.

[0200] According to embodiments of this disclosure, in the display area DA, a plurality of line connection patterns (LCPs) may be arranged on the second protective layer 913b. The plurality of line connection patterns (LCPs) may be wiring for electrically connecting the driver DRV to other components. For example, the driver DRV may be electrically connected via the plurality of line connection patterns (LCPs) to a plurality of column lines (CL), a plurality of row lines (RL), and a plurality of row connection electrodes (RCE).

[0201] For example, multiple line connection patterns (LCPs) may include a first line connection pattern (LCP1), a second line connection pattern (LCP2), a third line connection pattern (LCP3), and a fourth line connection pattern (LCP4), but the embodiments of this disclosure are not limited thereto. For example, the first line connection pattern (LCP1), the second line connection pattern (LCP2), the third line connection pattern (LCP3), and the fourth line connection pattern (LCP4) may be arranged in different metal layers.

[0202] For example, a plurality of first line connection patterns LCP1 may be arranged on the second protective layer 913b. The plurality of first line connection patterns LCP1 may be electrically connected to the driver DRV. The plurality of first line connection patterns LCP1 may transmit the voltage output from the driver DRV to the column line CL or the row line RL.

[0203] For example, the upper protective layer 914 may include a third protective layer 914, and in some cases, may also include at least one additional protective layer. The third protective layer 914 may be disposed on the second protective layer 913b and a plurality of first line connection patterns LCP1. The third protective layer 914 may be completely disposed in the display area DA and the non-display area NDA. In the curved area BA, the third protective layer 914 may cover or surround the side surfaces of the second protective layer 913b and the upper surface of the first protective layer 913a.

[0204] For example, the third protective layer 914 may be made of an organic insulating material. For example, the third protective layer 914 may be made of photoresist, polyimide (PI), or photoacrylic acid-based materials, but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 913a, the second protective layer 913b, and the third protective layer 914 may be made of the same insulating material, or at least one of the first protective layer 913a, the second protective layer 913b, and the third protective layer 914 may be made of an insulating material different from the other protective layers. However, the embodiments of this disclosure are not limited thereto.

[0205] Multiple second line connection patterns LCP2 may be arranged on the third protective layer 914. The multiple second line connection patterns LCP2 may be electrically connected or directly connected to the driver DRV. For example, some of the second line connection patterns LCP2 may be directly or indirectly connected to the driver DRV through contact holes in the third protective layer 914. Other portions of the second line connection patterns LCP2 may be electrically connected to the first line connection pattern LCP1 through contact holes in the third protective layer 914. However, embodiments of this disclosure are not limited thereto. The voltage output from the driver DRV may be transmitted to the column line CL or row line RL through the multiple second line connection patterns LCP2 and other connection patterns.

[0206] The first insulating layer 915a may be disposed on a plurality of second line connection patterns LCP2. The first insulating layer 915a may be completely disposed above the display area DA and the non-display area NDA, but embodiments of this disclosure are not limited thereto. The first insulating layer 915a may be made of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the first insulating layer 915a may be made of photoresist, polyimide (PI), or photoacrylic acid-based materials, but embodiments of this disclosure are not limited thereto.

[0207] Multiple third line connection patterns LCP3 may be disposed on the first insulating layer 915a. The multiple third line connection patterns LCP3 may be electrically connected to multiple second line connection patterns LCP2. For example, the third line connection patterns LCP3 may be electrically connected to the second line connection patterns LCP2 through contact holes in the first insulating layer 915a.

[0208] The second insulating layer 915b may be disposed on a plurality of third line connection patterns LCP3. The second insulating layer 915b may be disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and may not be disposed in all or part of the curved area BA, but embodiments of this disclosure are not limited thereto. For example, the second insulating layer 915b may be removed from all or part of the curved area BA. The second insulating layer 915b may be made of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the second insulating layer 915b may be made of photoresist, polyimide (PI), or photoacrylic acid-based materials, but embodiments of this disclosure are not limited thereto.

[0209] Multiple fourth line connection patterns LCP4 may be arranged on the second insulating layer 915b. The multiple fourth line connection patterns LCP4 may be electrically connected to multiple third line connection patterns LCP3. For example, the fourth line connection patterns LCP4 may be electrically connected to the third line connection patterns LCP3 through contact holes in the second insulating layer 915b.

[0210] refer to Figure 9 According to embodiments of this disclosure, in the non-display area NDA, multiple pad connection patterns PCPs can be arranged on the second protective layer 913b. The multiple pad connection patterns PCPs can be wiring for transmitting signals from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area DA. For example, the multiple pad connection patterns PCPs can be electrically connected to multiple pads PD and can receive signals from the flexible printed circuit 102 through the multiple pads PD. The flexible printed circuit 102 can be connected to the printed circuit board 104 (see...). Figure 1 and Figure 2 ).

[0211] For example, multiple pad connection patterns PCP can extend from pad portion 211 to display area DA and transmit signals to the wiring of display area DA. In this case, multiple pad connection patterns PCP can be used as link wiring LL( Figure 6 (LL in the text). Multiple pad connection patterns PCP may include a first pad connection pattern PCP1, a second pad connection pattern PCP2, a third pad connection pattern PCP3, and a fourth pad connection pattern PCP4.

[0212] Multiple first pad connection patterns PCP1 can be disposed on the second protective layer 913b. Each of the multiple first pad connection patterns PCP1 can be arranged to span the second non-display area NDA2, the curved area BA, and the first non-display area NDA1. Each of the multiple first pad connection patterns PCP1 may include a first portion disposed in the curved area BA, a second portion extending from the first portion to the first non-display area NDA1, and a third portion extending from the first portion to the second non-display area NDA2. Each of the multiple first pad connection patterns PCP1 may extend from the first non-display area NDA1 to a portion of the display area DA. The multiple first pad connection patterns PCP1 can transmit signals from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area DA.

[0213] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the pad PD of the pad portion 211 via a connection pattern arranged in the second non-display area NDA2. Here, the connection pattern that electrically connects each of the plurality of first pad connection patterns PCP1 to the pad PD may include at least one of the second pad connection pattern PCP2, the third pad connection pattern PCP3, and the fourth pad connection pattern PCP4 arranged in the second non-display area NDA2.

[0214] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the driver DRV via a connection pattern arranged in the display area DA. Here, the connection pattern that electrically connects each of the plurality of first pad connection patterns PCP1 to the driver DRV may include at least one of the second pad connection pattern PCP2, the third pad connection pattern PCP3, and the fourth pad connection pattern PCP4 arranged in the display area DA.

[0215] Multiple second pad connection patterns PCP2 can be arranged on the third protective layer 914. Multiple second pad connection patterns PCP2 can be arranged in the second non-display area NDA2. The second pad connection patterns PCP2 can be electrically connected to the first pad connection pattern PCP1 through contact holes in the third protective layer 914. Therefore, signals provided from the flexible printed circuit 102 can be transmitted to the first pad connection pattern PCP1 through the second pad connection patterns PCP2.

[0216] The third pad connection pattern PCP3 can be disposed on the first insulating layer 915a. The third pad connection pattern PCP3 can be disposed in the second non-display area NDA2. The third pad connection pattern PCP3 can be electrically connected to the second pad connection pattern PCP2 through the contact holes of the first insulating layer 915a. Therefore, signals provided from the flexible printed circuit 102 can be transmitted to the second pad connection pattern PCP2 through the third pad connection pattern PCP3, and signals transmitted to the second pad connection pattern PCP2 can be transmitted back to the first pad connection pattern PCP1.

[0217] The fourth pad connection pattern PCP4 can be disposed on the second insulating layer 915b. The fourth pad connection pattern PCP4 can be disposed in the second non-display area NDA2. The fourth pad connection pattern PCP4 can be electrically connected to the third pad connection pattern PCP3 through the contact holes of the second insulating layer 915b. The pad PD of the pad portion 211 can be electrically connected to the fourth pad connection pattern PCP4 through the contact holes of the third insulating layer 915c.

[0218] Signals from the flexible printed circuit 102 are input to pads PD of the pad portion 211, and the signals input to pads PD are transmitted to the third pad connection pattern PCP3 via the fourth pad connection pattern PCP4. Signals transmitted to the third pad connection pattern PCP3 can be transmitted again to the first pad connection pattern PCP1 via the second pad connection pattern PCP2. Signals transmitted to the first pad connection pattern PCP1 can be transmitted to the driver DRV via connection patterns arranged in the display area DA.

[0219] refer to Figure 9 Multiple line connection patterns (LCPs) and multiple pad connection patterns (PCPs) can be arranged in various metal layers. The multiple line connection patterns (LCPs) and multiple pad connection patterns (PCPs) can be formed from any of the conductive materials with excellent ductility or various conductive materials used in the display area (DA).

[0220] For example, the metal pattern (e.g., the first pad connection pattern PCP1) at least partially disposed in the curved region BA can be made of a conductive material with excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but embodiments of this disclosure are not limited thereto. As another example, the multiple line connection patterns LCP and the multiple pad connection patterns PCP can be made of alloys of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or alloys thereof, but embodiments of this disclosure are not limited thereto.

[0221] The third insulating layer 915c may be disposed on multiple line connection patterns LCP and multiple pad connection patterns PCP. The third insulating layer 915c is disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and may be disposed in all or part of the curved area BA, but embodiments of this disclosure are not limited thereto. In the curved area BA, a portion of the third insulating layer 915c may be removed. The third insulating layer 915c may be made of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the third insulating layer 915c may be made of photoresist, polyimide (PI), or photoacrylic acid-based materials, but embodiments of this disclosure are not limited thereto.

[0222] Multiple embankment BNKs can be disposed on the third insulating layer 915c in the display area DA. The multiple embankment BNKs can be arranged to overlap at least a portion of each of the multiple sub-pixels SPa, SPb, and SPc. For example, the first sub-pixel SPa may include a first light-emitting device EDa that emits a first color light, the second sub-pixel SPb may include a second light-emitting device EDb that emits a second color light, and the third sub-pixel SPc may include a third light-emitting device EDc that emits a third color light.

[0223] As an example, one light-emitting device (ED) can be arranged on top of each of the multiple embankment sections (BNK). As another example, two or more light-emitting devices (EDs) can be arranged on top of each of the multiple embankment sections (BNK). The two or more light-emitting devices (EDs) arranged on top of each of the multiple embankment sections (BNK) can be of the same type. For example, light-emitting devices of the same type can be light-emitting devices that emit the same color of light. For example, the two or more light-emitting devices (EDs) arranged on top of each of the multiple embankment sections (BNK) can include a main light-emitting device and redundant light-emitting devices.

[0224] In the display area DA, multiple row connection electrodes RCE can be arranged on the third insulating layer 915c. The multiple row connection electrodes RCE can transfer the low potential voltage VSS output from the driver DRV to the row line RL.

[0225] In the display area DA, multiple column lines CL can be arranged on the third insulating layer 915c. Multiple column lines CL can be arranged in the area between multiple dikes BNK. For example, multiple column lines CL can be arranged adjacent to one of the multiple dikes BNK.

[0226] Each of the multiple column lines CL may include a wiring portion and a column connection electrode CCE protruding from the wiring portion. The wiring portion and column connection electrode CCE included in each of the multiple column lines CL may be integrally formed or may be different metals electrically connected.

[0227] For example, each of the multiple column lines CL may include a column connection electrode CCE, which is a projection above an adjacent embankment BNK among the multiple embankment BNKs. The column connection electrode CCE of each column line CL may be arranged to extend along the side and top surface of the embankment BNK. The column connection electrode CCE may be an electrode electrically connected to each of the multiple column lines CL, or it may be a projection from each of the multiple column lines CL.

[0228] refer to Figure 10 The column connection electrode CCE of the column line CL can be composed of one or more conductive layers. For example, the column connection electrode CCE electrically connected to or protruding from the column line CL may include a first conductive layer 1001, a second conductive layer 1002, a third conductive layer 1003, and a fourth conductive layer 1004, but the embodiments of this disclosure are not limited thereto.

[0229] A first conductive layer 1001 may be disposed on the embankment BNK. A second conductive layer 1002 may be disposed on the first conductive layer 1001. A third conductive layer 1003 may be disposed on the second conductive layer 1002, and a fourth conductive layer 1004 may be disposed on the third conductive layer 1003. For example, each of the first conductive layer 1001, the second conductive layer 1002, the third conductive layer 1003, and the fourth conductive layer 1004 may be made of titanium (Ti), molybdenum (Mo), aluminum (Al), titanium (Ti), or indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0230] According to embodiments of this disclosure, among the multiple conductive layers constituting the column connection electrode CCE, some conductive layers with good reflectivity can be configured as alignment keys and / or reflectors for aligning the light-emitting device ED. For example, among the multiple conductive layers constituting the column connection electrode CCE, the second conductive layer 1002 may include a reflective material. For example, the second conductive layer 1002 may include aluminum (Al), but embodiments of this disclosure are not limited thereto. Therefore, the second conductive layer 1002 can be configured as a reflector. In addition, since the second conductive layer 1002 has high reflectivity, it is easily identifiable during manufacturing, and therefore the position of the light-emitting device ED can be aligned or its position moved based on the second conductive layer 1002.

[0231] For example, to configure the second conductive layer 1002 as a reflector, the third conductive layer 1003 and the fourth conductive layer 1004 disposed on the second conductive layer 1002 can be partially removed or etched. For example, a portion of the third conductive layer 1003 and the fourth conductive layer 1004 disposed on the embankment BNK can be removed or etched to expose the upper surface of the second conductive layer 1002. That is, the openings of the third conductive layer 1003 and the fourth conductive layer 1004 can overlap with a portion of the upper surface of the second conductive layer 1002. For example, in the third conductive layer 1003 and the fourth conductive layer 1004, the central portion and the edge portion where the solder pattern SDP is disposed can be retained, and the remaining portion other than these portions (e.g., the central portion and the edge portion) can be removed. For example, the edge portions of each of the third conductive layer 1003 made of titanium (Ti) and the fourth conductive layer 1004 made of indium tin oxide (ITO) can be left unetched. Therefore, it is possible to prevent other conductive layers of the column connection electrode CCE of the column line CL from being corroded by the TMAH (tetramethylammonium hydroxide) solution used in the masking process of the column connection electrode CCE.

[0232] According to embodiments of this disclosure, the first conductive layer 1001 and the third conductive layer 1003 may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer 1002 may comprise aluminum (Al). The fourth conductive layer 1004 may comprise a transparent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has good adhesion to the solder pattern SDP and is corrosion-resistant and acid-resistant. However, embodiments of this disclosure are not limited thereto.

[0233] The first conductive layer 1001, the second conductive layer 1002, the third conductive layer 1003 and the fourth conductive layer 1004 may be deposited sequentially and then patterned by performing photolithography and etching processes, but the embodiments of this disclosure are not limited thereto.

[0234] According to embodiments of this disclosure, two or more of the column connection electrodes (CCE), column lines (CL), row connection electrodes (RCE), and pads (PD) can be arranged on the same layer. The column connection electrodes (CCE), column lines (CL), row connection electrodes (RCE), and pads (PD) can be composed of a single layer or multiple layers of conductive material, but embodiments of this disclosure are not limited thereto. For example, two or more of the column connection electrodes (CCE), column lines (CL), row connection electrodes (RCE), and pads (PD) can be composed of multiple layers of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of this disclosure are not limited thereto.

[0235] According to embodiments of this disclosure, a solder pattern SDP can be disposed on a column connection electrode CCE in each of a plurality of sub-pixels. The solder pattern SDP can bond the light-emitting device ED to the column connection electrode CCE. The column connection electrode CCE and the light-emitting device ED can be electrically connected by eutectic bonding using the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, if the solder pattern SDP is made of indium (In) and the first electrode Ecl of the light-emitting device ED is made of gold (Au), the solder pattern SDP and the first electrode Ecl of the light-emitting device ED can be bonded by applying heat and pressure during the transfer of the light-emitting device ED. Through eutectic bonding, the light-emitting device ED can be bonded to the solder pattern SDP and the column connection electrode CCE without the need for a separate adhesive. For example, the solder pattern SDP can be made of indium (In), tin (Sn) or an alloy thereof, but embodiments of this disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad, but embodiments of this disclosure are not limited thereto.

[0236] According to embodiments of the present disclosure, the passivation layer 916 may be disposed on multiple column lines CL, multiple column connection electrodes CCE, multiple row connection electrodes RCE, and a third insulating layer 915c.

[0237] For example, a passivation layer 916 may be disposed on the display area DA, the first non-display area NDA1, and the second non-display area NDA2. In all or part of the curved area BA, at least a portion of the passivation layer 916 covering the multiple pads PD may be removed. A portion of the passivation layer 916 covering the multiple pads PD in the second non-display area NDA2 may be removed. Additionally, as... Figure 10 As shown, the passivation layer 916 can be removed from the area where the solder pattern SDP is arranged.

[0238] Because the passivation layer 916 is arranged to cover the remaining area except for the curved region BA, the multiple pads PD, and the area where the solder pattern SDP is arranged, moisture or impurities can be reduced from penetrating into the light-emitting device ED. For example, the passivation layer 916 can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of this disclosure are not limited thereto. For example, the passivation layer 916 can be a protective layer or an insulating layer, but embodiments of this disclosure are not limited thereto. For example, as... Figure 10 As shown, the passivation layer 916 may include holes through which the solder pattern SDP is exposed. That is, the holes in the passivation layer 916 may overlap with the solder pattern SDP.

[0239] refer to Figure 10The light-emitting device (ED) can be arranged on the solder pattern SDP in each of the multiple sub-pixels SP. The ED can be formed on a silicon wafer by methods such as metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PDCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPD), or sputtering, but the embodiments of this disclosure are not limited thereto.

[0240] refer to Figure 10 The light-emitting device ED may include a first electrode Ecl, a first semiconductor layer 1011, an active layer 1012, a second semiconductor layer 1013, a second electrode Erl, and an encapsulation film 1014, but the embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 1014 may not be included in the light-emitting device ED.

[0241] The first semiconductor layer 1011 may be disposed on the solder pattern SDP. The second semiconductor layer 1013 may be disposed on the first semiconductor layer 1011.

[0242] For example, one of the first semiconductor layer 1011 and the second semiconductor layer 1013 can be implemented as a III-V or II-VI compound semiconductor and can be doped with impurities (or dopants). For example, one of the first semiconductor layer 1011 and the second semiconductor layer 1013 can be a semiconductor layer doped with n-type impurities, while the other can be a semiconductor layer doped with p-type impurities, but the embodiments of this disclosure are not limited thereto. For example, at least one of the first semiconductor layer 1011 and the second semiconductor layer 1013 can be a layer doped with n-type or p-type impurities in a material such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but the embodiments of this disclosure are not limited thereto. For example, n-type impurities can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), or tin (Sn), but the embodiments of this disclosure are not limited thereto. For example, p-type impurities can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or beryllium (Be), but the embodiments of this disclosure are not limited thereto.

[0243] For example, the first semiconductor layer 1011 and the second semiconductor layer 1013 may be a nitride semiconductor including n-type impurities and a nitride semiconductor including p-type impurities, respectively, but the embodiments of this disclosure are not limited thereto. For example, the first semiconductor layer 1011 may be a nitride semiconductor including p-type impurities, and the second semiconductor layer 1013 may be a nitride semiconductor including n-type impurities, but the embodiments of this disclosure are not limited thereto.

[0244] An active layer 1012 may be disposed between a first semiconductor layer 1011 and a second semiconductor layer 1013. The active layer 1012 may receive holes and electrons from the first semiconductor layer 1011 and the second semiconductor layer 1013 to emit light. For example, the active layer 1012 may be configured as a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but embodiments of this disclosure are not limited thereto. For example, the active layer 1012 may be configured as indium gallium nitride (InGaN) or gallium nitride (GaN), but embodiments of this disclosure are not limited thereto.

[0245] For example, the active layer 1012 may include a multiple quantum well (MQW) structure having a well layer and a barrier layer with a band gap higher than the well layer. For example, the active layer 1012 may be formed by using an InGaN layer as the well layer and an AlGaN layer as the barrier layer, but the embodiments of this disclosure are not limited thereto.

[0246] The first electrode Ecl of the light-emitting device ED can be disposed between the first semiconductor layer 1011 and the solder pattern SDP. For example, the first electrode Ecl of the light-emitting device ED can be electrically connected to the first semiconductor layer 1011 and the column connection electrode CCE. The column line voltage (e.g., anode voltage) output from the driver DRV can be applied to the first semiconductor layer 1011 through the column line CL, the column connection electrode CCE and the first electrode Ecl. For example, the first electrode Ecl can be made of a conductive material capable of eutectic bonding with the solder pattern SDP, but the embodiments of this disclosure are not limited thereto. For example, the first electrode Ecl of the light-emitting device ED can be made of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), copper (Cu), or alloys thereof, but the embodiments of this disclosure are not limited thereto.

[0247] The second electrode Erl of the light-emitting device ED can be disposed on the second semiconductor layer 1013. For example, the second electrode Erl of the light-emitting device ED can be electrically connected to the second semiconductor layer 1013 and the row line RL. The row line voltage (e.g., referred to as the low potential voltage VSS, as the cathode voltage) output from the driver DRV can be applied to the second semiconductor layer 1013 through the row connection electrode RCE, the row line RL, and the second electrode Erl. The second electrode Erl of the light-emitting device ED can be made of a transparent conductive material, so that light emitted from the light-emitting device ED can be guided to the upper part of the light-emitting device ED, but the embodiments of this disclosure are not limited thereto. For example, the second electrode Erl can be made of materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto.

[0248] The encapsulation film 1014 may be disposed on at least a portion of the first semiconductor layer 1011, the active layer 1012, the second semiconductor layer 1013, the first electrode Ecl, and the second electrode Erl. For example, the encapsulation film 1014 may surround at least a portion of the first semiconductor layer 1011, the active layer 1012, the second semiconductor layer 1013, the first electrode Ecl, and the second electrode Erl.

[0249] For example, the encapsulation film 1014 can protect the first semiconductor layer 1011, the active layer 1012, and the second semiconductor layer 1013. For example, the encapsulation film 1014 can be disposed on the side surface of the first semiconductor layer 1011, the side surface of the active layer 1012, and the side surface of the second semiconductor layer 1013.

[0250] For example, the encapsulation film 1014 may be disposed on at least a portion of the first electrode Ecl and the second electrode Erl of the light-emitting device ED. For example, the encapsulation film 1014 may be disposed on the edge portion (or one side) of the first electrode Ecl and the edge portion (or one side) of the second electrode Erl of the light-emitting device ED. At least a portion of the first electrode Ecl may be exposed from the encapsulation film 1014 so that the first electrode Ecl can be connected to the solder pattern SDP. For example, at least a portion of the second electrode Erl may be exposed from the encapsulation film 1014 so that the second electrode Erl can be connected to the row line RL. For example, the encapsulation film 1014 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of this disclosure are not limited thereto.

[0251] For example, the encapsulation film 1014 may have a structure in which reflective material is dispersed in a resin layer, but the embodiments of this disclosure are not limited thereto. For example, the encapsulation film 1014 may be manufactured as a reflector with various structures, but the embodiments of this disclosure are not limited thereto. Light emitted from the active layer 1012 can be reflected upwards by the encapsulation film 1014, thereby improving light extraction efficiency. For example, the encapsulation film 1014 may be a reflective layer, but the embodiments of this disclosure are not limited thereto.

[0252] According to embodiments of this disclosure, the light-emitting device (ED) is described as having a vertical structure, but embodiments of this disclosure are not limited thereto. For example, the ED may have a lateral structure or a flip-chip structure.

[0253] Figure 10 The illustrated light-emitting device (ED) structure can be applied substantially equivalently to all first light-emitting devices EDa, second light-emitting devices EDb, and third light-emitting devices EDc. According to embodiments of this disclosure, a first optical layer 917a can be arranged to surround a plurality of light-emitting devices ED in a display area DA. For example, the first optical layer 917a can be arranged to cover a plurality of light-emitting devices ED and a dam BNK in a region of a plurality of sub-pixels SP. For example, the first optical layer 917a can cover the dam BNK, a portion of the passivation layer 916, and the region between the plurality of light-emitting devices ED. The first optical layer 917a can be arranged or cover the regions between the plurality of light-emitting devices ED and the plurality of dam BNK included in a pixel. For example, the first optical layer 917a can be arranged to extend along a first direction (X) and spaced apart from each other along a second direction (Y). For example, the first optical layer 917a can be arranged to surround the dam BNK between the passivation layer 916 and the row line RL and the sides of the light-emitting devices ED, but embodiments of this disclosure are not limited thereto. For example, the first optical layer 917a may be a diffusion layer or a sidewall diffusion layer, but the embodiments of this disclosure are not limited thereto.

[0254] The first optical layer 917a may include an organic insulating material in which fine particles are dispersed, but embodiments of this disclosure are not limited thereto. For example, the first optical layer 917a may be composed of a siloxane in which fine metal particles (e.g., titanium dioxide (TiO2) particles) are dispersed, but embodiments of this disclosure are not limited thereto. Light from multiple light-emitting devices (EDs) can be scattered by the fine particles dispersed in the first optical layer 917a and emitted to the outside of the display device 100. Therefore, the first optical layer 917a can improve the extraction efficiency of light emitted from multiple light-emitting devices (EDs).

[0255] For example, the first optical layer 917a may be disposed on each of a plurality of pixels, or may be disposed together on some pixels disposed in the same row, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 917a may be disposed on each of a plurality of pixels, or a plurality of pixels may share a first optical layer 917a. As another example, each of a plurality of sub-pixels may individually include the first optical layer 917a, but embodiments of the present disclosure are not limited thereto.

[0256] According to embodiments of the present disclosure, in the display area DA, a second optical layer 917b may be disposed on a passivation layer 916. For example, the second optical layer 917b may be disposed around a first optical layer 917a. For example, the second optical layer 917b may contact a side surface of the first optical layer 917a. For example, the second optical layer 917b may be disposed in a region between a plurality of pixels. However, embodiments of the present disclosure are not limited thereto. For example, the second optical layer 917b may be a diffusion layer, a diffusion layer window, or a window diffusion layer, but embodiments of the present disclosure are not limited thereto.

[0257] The second optical layer 917b may be made of an organic insulating material, but the embodiments of this disclosure are not limited thereto. The second optical layer 917b may be made of the same material as the first optical layer 917a, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 917a may include fine particles, and the second optical layer 917b may not include fine particles. For example, the second optical layer 917b may be made of siloxane, but the embodiments of this disclosure are not limited thereto.

[0258] For example, the thickness of the first optical layer 917a may be less than the thickness of the second optical layer 917b, but embodiments of this disclosure are not limited thereto. Therefore, when viewed from a plan view, the area where the first optical layer 917a is disposed may include a recess that is recessed inward from the upper surface of the second optical layer 917b.

[0259] According to embodiments of this disclosure, a row line RL may be disposed on a first optical layer 917a and a second optical layer 917b. For example, the row line RL may be electrically connected to multiple row connection electrodes RCE through contact holes in the second optical layer 917b. For example, the row line RL may be disposed on multiple light-emitting devices ED. For example, the row line RL may comprise a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto. For example, the row line RL may be arranged to contact a second electrode Erl of the light-emitting device ED. For example, the row line RL may overlap with the first optical layer 917a. For example, the row line RL may cover a plane outside the first optical layer 917a.

[0260] The row lines RL can extend continuously along a first direction (X) of the substrate 210. Therefore, the row lines RL can be collectively connected to multiple pixels arranged along the first direction (X) of the substrate 210. For example, the row lines RL can be collectively connected to multiple pixels.

[0261] According to embodiments of this disclosure, the line line RL can extend continuously on the first optical layer 917a, the second optical layer 917b, and the light-emitting device ED. The region where the first optical layer 917a is disposed may include a recess that is recessed inward from the upper surface of the second optical layer 917b. Therefore, a first portion of the line line RL disposed on the first optical layer 917a may be disposed along the recess, and thus may be disposed at a lower position than a second portion of the line line RL disposed on the second optical layer 917b.

[0262] The third optical layer 917c can be disposed on the row lines RL. The third optical layer 917c can be configured to overlap with the plurality of light-emitting devices ED and the first optical layer 917a. Since the third optical layer 917c is disposed on the row lines RL and the plurality of light-emitting devices ED, it can improve the color difference (mura) that may occur in some of the plurality of light-emitting devices ED. For example, when transferring the plurality of light-emitting devices ED onto the substrate 210 of the display panel 110, due to process variations, areas with inconsistent spacing between the plurality of light-emitting devices ED may appear. If the spacing between the plurality of light-emitting devices ED is inconsistent, the emission area of ​​each of the plurality of light-emitting devices ED may be unevenly arranged, and thus the user may see color difference. Therefore, since the third optical layer 917c is disposed to uniformly diffuse light over the plurality of light-emitting devices ED, the color difference that is seen from the light emitted from some of the light-emitting devices ED can be reduced. Therefore, since the light emitted from the plurality of light-emitting devices ED is uniformly diffused and extracted to the outside of the display device 100 by the third optical layer 917c, the brightness uniformity of the display device 100 can be improved.

[0263] The third optical layer 917c may be composed of an organic insulating material in which fine particles are dispersed, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 917c may be composed of a siloxane in which fine metal particles (e.g., titanium dioxide (TiO2) particles) are dispersed, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 917c may be composed of the same material as the first optical layer 917a, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 917c may be a diffusion layer or an upper diffusion layer, but the embodiments of this disclosure are not limited thereto.

[0264] According to embodiments of this disclosure, light from multiple light-emitting devices (EDs) can be scattered by fine particles dispersed in a third optical layer 917c and emitted to the exterior of the display device 100. The third optical layer 917c can uniformly mix the light emitted from the multiple EDs, thereby further improving the brightness uniformity of the display device 100. Furthermore, the light extraction efficiency of the display device 100 can be improved by the light scattered from the multiple fine particles, enabling the display device 100 to be driven at low power.

[0265] The black matrix BM can be arranged on the row lines RL, the first optical layer 917a, the second optical layer 917b, and the third optical layer 917c in the display area DA. For example, the black matrix BM can fill the contact holes of the second optical layer 917b. The black matrix BM can be configured to cover the display area DA, thereby reducing color mixing of light and external light reflection from multiple sub-pixels. For example, the black matrix BM can also be arranged in the contact holes where the row lines RL are connected to the row connection electrodes RCE, thereby preventing light leakage between multiple adjacent sub-pixels.

[0266] For example, the black matrix BM can be made of an opaque material, but the embodiments of this disclosure are not limited thereto. For example, the black matrix BM can be an organic insulating material with added black pigment or black dye, but the embodiments of this disclosure are not limited thereto.

[0267] A cover layer 918 may be disposed on the black matrix BM in the display area DA. The cover layer 918 may protect the configuration beneath it. For example, the cover layer 918 may be made of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the cover layer 918 may be made of photoresist, polyimide (PI), or photoacrylic-based materials, but embodiments of this disclosure are not limited thereto. For example, the cover layer 918 may be an outer coating or an insulating layer, but embodiments of this disclosure are not limited thereto.

[0268] The polarizing layer 114 may be disposed on the cover layer 918 via the first adhesive layer 112. The cover member 118 may be disposed on the polarizing layer 114 via the second adhesive layer 116. For example, the first adhesive layer 112 and the second adhesive layer 116 may include optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA), but the embodiments of this disclosure are not limited thereto.

[0269] According to embodiments of this disclosure, a plurality of pads (PDs) may be disposed on a third insulating layer 915c in a second non-display area (NDA2). For example, at least a portion of the plurality of pads (PDs) may be exposed from a passivation layer 916. For example, the plurality of pads (PDs) may be electrically connected to a fourth pad connection pattern (PCP4) through contact holes in the third insulating layer 915c.

[0270] An adhesive layer ACF can be disposed on multiple pads PD. The adhesive layer ACF may be an adhesive layer in which conductive balls are dispersed in an insulating material, but embodiments of this disclosure are not limited thereto. When heat or pressure is applied to the adhesive layer ACF, the conductive balls may become electrically connected at the points where heat or pressure is applied, thereby acquiring conductive properties. The adhesive layer ACF may be disposed between the multiple pads PD and the flexible printed circuit 102, such that the flexible printed circuit 102 can be attached or bonded to the multiple pads PD. For example, the adhesive layer ACF may be an anisotropic conductive film ACF, but embodiments of this disclosure are not limited thereto.

[0271] The flexible printed circuit 102 can be disposed on the adhesive layer ACF. The flexible printed circuit 102 can be electrically connected to multiple pads PD through the adhesive layer ACF. Therefore, the signal provided from the flexible printed circuit 102 can be transmitted to the driver DRV of the display area DA through the multiple pads PD, the fourth pad connection pattern PCP4, the third pad connection pattern PCP3, the second pad connection pattern PCP2, and the first pad connection pattern PCP1.

[0272] refer to Figure 9 The display panel 110 according to an embodiment of the present disclosure may include a substrate 210, a layer stack disposed on a plurality of driver DRVs disposed on the substrate 210, an optical layer 917a disposed between a plurality of light-emitting devices EDa, EDb and EDc disposed on the layer stack, an adhesive layer 116 disposed on the plurality of light-emitting devices EDa, EDb and EDc and the optical layer 917a, and a cover member 118 disposed on the adhesive layer 116.

[0273] refer to Figure 9 Multiple column lines CL can be set between the stacked layers and multiple light-emitting devices EDa, EDb and EDc.

[0274] refer to Figure 9 Multiple line lines RL can be arranged on multiple light-emitting devices EDa, EDb, and EDc, as well as on optical layer 917a. Multiple line lines RL can be arranged between multiple light-emitting devices EDa, EDb, and EDc, optical layer 917a, and adhesive layer 116.

[0275] refer to Figure 9 The stacked body may include a plurality of protective layers 913a, 913b and 914 disposed on the side and top surfaces of each of the plurality of drivers DRVs, a plurality of insulating layers 915a, 915b and 915c disposed on the plurality of protective layers 913a, 913b and 914, and a dam BNK disposed on the plurality of insulating layers.

[0276] The side protection layer 913 disposed on each side of the plurality of driver DRVs may include a first protection layer 913a disposed on the substrate 210 and a second protection layer 913b disposed on the first protection layer 913a.

[0277] The upper protective layer 914 disposed on the upper surface of each of the multiple driver DRVs may include a third protective layer 914 disposed on the multiple driver DRVs and the second protective layer 913b.

[0278] The plurality of insulating layers 915a, 915b and 915c may include a first insulating layer 915a disposed on the upper protective layer 914 and a second insulating layer 915b disposed on the first insulating layer 915a. The plurality of insulating layers 915a, 915b and 915c may also include a third insulating layer 915c disposed on the second insulating layer 915b.

[0279] Each of the multiple light-emitting devices EDa, EDb and EDc can be mounted on the embankment BNK and located in the opening of the optical layer 917a.

[0280] At least a portion of each of the multiple column lines CL may extend to the embankment BNK on the multiple insulating layers 915a, 915b and 915c. Each of the multiple row lines RL may be arranged on the optical layer 917a and the multiple light-emitting devices EDa, EDb and EDc.

[0281] The first electrode Ecl of each of the plurality of light-emitting devices EDa, EDb, and EDc is electrically connected to at least a portion of the column line CL that extends onto the embankment BNK. The second electrode Erl of each of the plurality of light-emitting devices EDa, EDb, and EDc is electrically connected to one of the plurality of row lines RL.

[0282] Reference Figure 9 According to embodiments of the present disclosure, the display panel 110 may include a plurality of line connection patterns LCP, which connect each of a plurality of lines including a plurality of row lines RL and a plurality of column lines CL to a plurality of drivers DR.

[0283] The multiple line connection patterns (LCPs) may include: a first line connection pattern (LCP1) disposed on the side protective layer 913; a second line connection pattern (LCP2) disposed on the upper protective layer 914 and electrically connected to the first line connection pattern (LCP1) through a hole in the upper protective layer 914; a third line connection pattern (LCP3) disposed on the first insulating layer 915a and electrically connected to the second line connection pattern (LCP2) through a hole in the first insulating layer 915a; and a fourth line connection pattern (LCP4) disposed on the second insulating layer 915b and electrically connected to the third line connection pattern (LCP3) through a hole in the second insulating layer 915b.

[0284] The first line connection pattern LCP1 can be electrically connected to one of the multiple drivers DRV. The fourth line connection pattern LCP4 can be electrically connected to at least one second electrode Erl of the multiple light-emitting devices EDa, EDb and EDc, or can be electrically connected to at least one first electrode Ecl of the multiple light-emitting devices EDa, EDb and EDc.

[0285] The side protection layer 913 arranged on each side of the multiple drive DRVs may include two or more organic layers.

[0286] The first and second protective layers 913a and 913b, which serve as the side protective layer 913, the third protective layer 914, which serves as the upper protective layer 914, and the first to third insulating layers 915a, 915b and 915c may each be composed of organic layers.

[0287] Figure 11 and Figure 12 This is a view used to illustrate the driver DRV provided in a display device 100 according to an embodiment of the present disclosure.

[0288] Specifically, Figure 11 A plan view of a display panel 110 according to an embodiment of the present disclosure, showing a plurality of driver DRVs disposed therein, and Figure 12 A plan view of the master driver DRVM among a plurality of driver DRVs arranged in a display panel 110 according to an embodiment of the present disclosure is shown.

[0289] refer to Figure 11 According to embodiments of the present disclosure, multiple driver DRVs may be provided in the display panel 110, and the multiple driver DRVs may include multiple master drivers DRVMs and multiple sub-drivers DRVSs connected to each of the multiple master drivers DRVMs.

[0290] Multiple master drivers DRVM and multiple sub-drivers DRVS corresponding to each master driver DRVM can be grouped into at least one driver group DRV_G.

[0291] although Figure 11 Only three drive groups DRV_G are shown in the document, but embodiments of this disclosure are not limited thereto, and multiple master drives DRVM and multiple child drives DRVS may be grouped into two or fewer, or four or more drive groups DRV_G.

[0292] according to Figure 11 For example, in each driver group DRV_G, M master drivers DRVMs (where M is a positive integer greater than or equal to 2) can be arranged in a column, and multiple sub-drivers DRVSs corresponding to each master driver in the M master drivers DRVMs arranged in a column can be connected.

[0293] That is, in each driver group DRV_G, the first to the Mth master drivers DRVM_1 to DRVM_M can be set in a column.

[0294] The driver group DRV_G can be divided into k subgroups (where k is a positive integer), and... Figure 11 In the example, only three subgroups DRV_SG1, DRV_SG2 and DRV_SG3 are shown for ease of illustration, but the embodiments of this disclosure are not limited thereto, and a driver group DRV_G may consist of two or fewer subgroups, or four or more subgroups.

[0295] Each of the subgroups DRV_SG1, DRV_SG2, and DRV_SG3 may include a first to an nth master driver (where n is a positive integer of 2 or greater, and n ≤ N) that receives synchronization signals and clock signals with different phases.

[0296] That is, the number N of master drive DRVMs arranged in a row can be k×n. According to... Figure 11 For example, since k=3 and n=6, a total of 18 master drive DRVMs can be set in one column.

[0297] refer to Figure 12 In the display panel 110 according to an embodiment of the present disclosure, multiple driver DRVs can be set for each row, and the number of driver DRVs set can be variably adjusted according to the size of the display panel or the number of pixels allocated to each driver DRV.

[0298] The timing controller 1200 can appropriately process the externally input image data RGB according to the size and resolution of the display panel 110, and provide the processed data to each of the multiple driver DRVs. The timing controller 1200 can use externally input synchronization signals (e.g., dot clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) to generate control signals for controlling the operation of each of the multiple driver DRVs, and provide the generated control signals to each of the multiple driver DRVs arranged in each row.

[0299] The multiple drivers DRV may include: multiple master drivers DRVM, which receive control signals from the timing controller 1200; and multiple sub-drivers DRVS, which are electrically connected to a corresponding master driver among the multiple master drivers DRVM and control the light emission operation of the corresponding pixel among the multiple pixels P according to the control signals.

[0300] For example, in the first row, a first master driver DRVM_1 electrically connected to the timing controller 1200 and receiving control signals can be configured, and at least one first sub-driver DRVS_1 electrically connected to the first master driver DRVM_1 can be configured.

[0301] In the second row, a second master driver DRVM_2 electrically connected to the timing controller 1200 and receiving control signals, and at least one second sub-driver DRVS_2 electrically connected to the second master driver DRVM_2 can be configured.

[0302] In the third row, a third master driver DRVM_3 electrically connected to the timing controller 1200 and receiving control signals, and at least one third sub-driver DRVS_3 electrically connected to the third master driver DRVM_3 can be configured.

[0303] In the fourth row, a fourth master driver DRVM_4 electrically connected to the timing controller 1200 and receiving control signals can be configured, as well as at least one fourth sub-driver DRVS_4 electrically connected to the third master driver DRVM_4.

[0304] In the nth row, an nth master driver DRVM_n electrically connected to the timing controller 1200 and receiving control signals, and at least one nth sub-driver DRVS_n electrically connected to the nth master driver DRVM_n can be configured.

[0305] Each of the main drivers DRVM_1 to DRVM_n can be electrically connected to the timing controller 1200 via at least one first signal line 1210, a second signal line 1220, and a third signal line 1230.

[0306] Each of the main drivers DRVM_1 to DRVM_n can receive a synchronization signal and a clock signal from the timing controller 1200 through at least one first signal line 1210.

[0307] Specifically, each driver in a multi-driver DRV can drive a light-emitting device (e.g., a micro LED) connected to each driver in the multi-driver DRV. However, to prevent peak currents exceeding a threshold, instead of driving all light-emitting devices simultaneously, the light-emitting devices can be divided into n groups, and the operation of each group can be controlled by time differences.

[0308] Therefore, each of at least one first signal line 1210 may include n clock signal lines CLK_1 to CLK_n and n synchronization signal lines Sync_1 to Sync_n with different phases.

[0309] For example, in normal mode, the timing controller 1200 can provide synchronization signals for the first to nth phases through n synchronization signal lines Sync_1 to Sync_n, and can provide phase image data CLK_R / G / B for the first to nth phases through n clock signal lines CLK_1 to CLK_n.

[0310] Here, the synchronization signal can be a signal used as a reference for the emission timing of the light-emitting device, and the phase image data can be a signal used as a reference for generating the light-emitting pulse.

[0311] For example, the second signal line 1220 can be a data line through which the timing controller 1200 outputs R / G / B image data in normal mode, and the third signal line 1230 can be a data clock line through which the timing controller 1200 outputs a recovery clock in normal mode.

[0312] according to Figure 12 For example, the first master driver DRVM_1 can be connected to the first synchronization signal line Sync_1 and the first clock signal line CLK_1, and the second master driver DRVM_2 can be connected to the second synchronization signal line Sync_2 and the second clock signal line CLK_2.

[0313] The third master driver DRVM_3 can be connected to the third synchronization signal line Sync_3 and the third clock signal line CLK_3, and the fourth master driver DRVM_4 can be connected to the fourth synchronization signal line Sync_4 and the fourth clock signal line CLK_4.

[0314] The nth master driver DRVM_n can be connected to the nth synchronization signal line Sync_n and the nth clock signal line CLK_n.

[0315] refer to Figure 11 and Figure 12 The first master driver DRVM_1 in each of the subgroups DRV_SG1, DRV_SG2, and DRV_SG3 can be connected to the same first synchronization signal line Sync_1 and the first clock signal line CLK_1, and the nth master driver DRVM_n in each of the subgroups DRV_SG1, DRV_SG2, and DRV_SG3 can be connected to the same nth synchronization signal line Sync_n and the nth clock signal line CLK_n.

[0316] Meanwhile, in the display device 100 according to the embodiments of this disclosure, such as Figure 6 As shown, as the bending region BA bends, portions of multiple link lines LL connected to at least one of the first to third signal lines 1210, 1220, and 1230 may also bend together. Therefore, stress may concentrate on a portion of the bent link line LL, and cracks (i.e., bending cracks) may appear in the link line LL, potentially leading to wiring defects in the signal lines.

[0317] In addition, the display device 100 may have a line defect in at least one of the first signal lines 1210.

[0318] Therefore, the display device 100 according to embodiments of this disclosure can detect and repair the aforementioned circuit defects through a test mode. Furthermore, the display device 100 can detect and repair circuit defects by utilizing existing wiring and pads without adding separate wiring or pads, thereby minimizing the increased cost and time required for testing.

[0319] For example, a test mode can be performed during the module inspection phase, but embodiments of this disclosure are not limited thereto.

[0320] Reference Figure 11 and Figure 12 In test mode, the timing controller 1200 can provide test pulses to at least two of the multiple master driver DRVMs through at least one first signal line 1210.

[0321] For example, the test pulse can be a single pulse, and each master driver DRVM can receive the same test pulse through at least one first signal line 1210.

[0322] The timing controller 1200 can receive a test output signal based on test output pulses from each of two or more master drivers DRVMs that receive test pulses via the second signal line 1220 at different timings, and the timing controller 1200 can determine whether there is a defect in the line and / or the location of the defect based on the test output signal received via the second signal line 1220.

[0323] For example, if the first to the Mth master drivers DRVM_1 to DRVM_M are arranged in a column, the timing controller 1200 can provide test pulses to the first to the Mth master drivers DRVM_1 to DRVM_M and receive test output signals including test output pulses from the first to the Mth master drivers DRVM_1 to DRVM_M at different timings through the second signal line 1220, thereby determining whether the line has defects due to bending cracks and / or line defects of the first signal line 1210 itself, and detecting the location of the defects.

[0324] Furthermore, if the first to the Mth master drivers DRVM_1 to DRVM_M are arranged in a column, the timing controller 1200 can provide test pulses to the first to the nth drivers DRVM_1 to DRVM_n arranged in the subgroup closest to the timing controller 1200 (e.g., the first subgroup DRV_SG1), and can receive test output signals based on test output pulses from the first to the nth drivers DRVM_1 to DRVM_n at different timings via the second signal line 1220, thereby determining whether a circuit defect has occurred due to bending cracks.

[0325] For a more specific example, when the timing controller 1200 provides test pulses to the first to Mth master drivers, the timing controller 1200 can receive test output signals, which include test output pulses output from the first master driver DRVM_1 in the first timing, test output pulses output from the second master driver DRVM_2 in the second timing, and test output pulses output from the Mth master driver DRVM_M in the Mth timing.

[0326] Furthermore, when the timing controller 1200 provides test pulses to the first to nth master drivers, the timing controller 1200 can receive test output signals, which include test output pulses output from the first master driver DRVM_1 in the first timing, test output pulses output from the second master driver DRVM_2 in the second timing, and test output pulses output from the nth master driver DRVM_n in the nth timing.

[0327] Figure 13 and Figure 14This is a view illustrating the main driver DRVM provided in a display device 100 according to an embodiment of the present disclosure.

[0328] Specifically, Figure 13 An example is illustrated of the main driver DRVM provided in a display device 100 according to an embodiment of the present disclosure, and Figure 14 This is a view used to further illustrate the clock buffer CB equipped in the main driver DRVM.

[0329] refer to Figure 13 Each of the multiple master drivers DRVM may include a clock buffer CB and a first multiplexer Mux1 electrically connected to the clock buffer CB.

[0330] Each of the multiple master drivers DRVM may also include a switching element 1330 that controls the connection between the input of the master driver DRVM and the general path 1310.

[0331] For example, switch element 1330 can be turned on in normal mode to control the transmission of synchronization and clock signals provided from a corresponding signal line in the first signal line 1210 to the general path 1310. Switch element 1330 can be turned off in test mode to prevent the transmission of test pulse Test_input provided from a corresponding signal line in the first signal line 1210 to the general path 1310.

[0332] The clock buffer CB can be set on test path 1320 to receive the test pulse Test_input from timing controller 1200 and delay the test pulse Test_input. In test mode, the clock buffer CB can receive the reference clock signal Data_CLK via the third signal line 1230 and delay the test pulse Test_input.

[0333] The first multiplexer, Mux1, can output a delayed test pulse, Test_delay, as a test output pulse, Test_out, via the clock buffer CB.

[0334] For example, the clock buffer CB set in the first master driver DRVM_1 can delay the test pulse Test_input, so that the test output pulse Test_out can be output in the first timing sequence.

[0335] In addition, the clock buffer CB set in the second master driver DRVM_2 can delay the test pulse Test_input, so that the test output pulse Test_out is output in the second timing sequence.

[0336] In addition, the clock buffer CB set in the nth master driver DRVM_n can delay the test pulse Test_input and output the test output pulse Test_out at the nth timing output.

[0337] In addition, the clock buffer CB set in the Mth master driver can delay the test pulse Test_input and output the test output pulse Test_out at the Mth timing output.

[0338] refer to Figure 14 The clock buffer CB set in each of the multiple master drivers DRVM may include at least one D flip-flop 1410, and at least one D flip-flop 1410 may be used to delay the test pulse Test_input.

[0339] For example, at least two master drivers DRVMs that receive the test pulse Test_input from the timing controller 1200 may include different numbers of D flip-flops 1410 to provide the test output pulse Test_out at different timings.

[0340] For example, the clock buffer CB arranged in the first master driver DRVM_1 may include a D flip-flop to output a test output pulse Test_out in the first timing sequence; the clock buffer CB arranged in the second master driver DRVM_2 may include two D flip-flops to output a test output pulse Test_out in the second timing sequence; the clock buffer CB arranged in the nth master driver DRVM_n may include n D flip-flops to output a test output pulse Test_out in the nth timing sequence; and the clock buffer CB arranged in the Mth master driver may include M D flip-flops to output a test output pulse Test_out in the Mth timing sequence.

[0341] Meanwhile, the clock buffer CB may include: a second multiplexer Mux2 connected to the output of at least one D flip-flop 1410 to control the delay of the test pulse Test_input by at least one D flip-flop 1410; and a buffer circuit 1420 connected to the output of the second multiplexer Mux2 to amplify and / or stabilize the signal output from the second multiplexer Mux2.

[0342] If the clock buffer CB includes a second multiplexer Mux2, then each of the multiple master drivers DRVM can have the same number of D flip-flops.

[0343] For example, a second multiplexer 1420 arranged in the first master driver DRVM_1 can provide a delayed test pulse Test_delay output through the output (e.g., Q terminal) of the first D flip-flop 1410, such that a test output pulse Test_out is output in the first timing sequence.

[0344] Furthermore, the second multiplexer 1420 arranged in the nth master driver DRVM_n can provide a delayed test pulse Test_delay output through the output terminal (e.g., Q terminal) of the nth D flip-flop 1410, so that the test output pulse Test_out is output in the nth timing sequence.

[0345] Furthermore, the second multiplexer 1420 arranged in the Mth master driver can provide a delayed test pulse Test_delay output through the Q terminal of the Mth D flip-flop 1410, so that the Mth timing output test output pulse Test_out is generated.

[0346] Figures 15 to 17 This is a view used to illustrate an example of detecting a circuit defect in a timing controller 1200 provided in a display device 100 according to an embodiment of the present disclosure.

[0347] Specifically, Figure 15 An implementation example of a timing controller 1200 including circuitry for determining line defects is shown, and Figure 16 and Figure 17 A timing diagram is shown for determining whether a circuit defect exists in the timing controller 1200.

[0348] refer to Figure 15 According to embodiments of this disclosure, the timing controller 1200 can receive a test output signal Data1 via a second signal line 1220, count the number of pulses in the test output signal, and determine line defects of a plurality of master drivers DRVMs based on the counted number of pulses. For this purpose, the timing controller may include a counting circuit 1210 and a defect determination circuit 1220.

[0349] according to Figure 15 For example, the second signal line 1220 can be the first data line, but the embodiments of this disclosure are not limited thereto.

[0350] The counting circuit 1210 can count each of the multiple test output pulses Test_out included in the test output signal Data1.

[0351] For example, the test output signal Data1 may include at least one of the test output pulses Test_out from the first to the Mth master drivers DRVM_1 to DRVM_M arranged in the same column.

[0352] In addition, the test output signal may include at least one of the test output pulses Test_out from the first to the nth master drivers DRVM_1 to DRVM_n, which are arranged closest to the timing controller 1200.

[0353] However, embodiments of this disclosure are not limited thereto, and the test output signal Data1 may include test output pulses Test_out provided from the first to the (M-1)th master drivers.

[0354] For ease of explanation, the following example illustrates that the test output signal includes at least one of the test output pulses Test_out output from the first to the Mth master drivers DRVM_1 to DRVM_M.

[0355] The counting circuit 1210 can count the multiple test output pulses Test_out included in the test output signal Data1 within a preset counting period.

[0356] For example, the preset counting period can be from the first counting time C1 to the Mth counting time CM, but the embodiments of this disclosure are not limited to this.

[0357] The defect determination circuit 1220 can compare the number of counted pulses of the test output signal Data1 with a preset reference number, and determine whether there is a defect in the circuit based on the comparison result.

[0358] For example, if the test output signal Data1 corresponds to the first to the Mth master drivers DRVM_1 to DRVM_M, the reference number can be set to M; and if the test output signal corresponds to the first to the nth master drivers DRVM_1 to DRVM_n, the reference number can be set to n.

[0359] That is, if the number of counted pulses of the test output signal Data1 is equal to the reference number, the defect determination circuit 1220 can determine that no line defect has occurred, and if the number of counted pulses of the test output signal is less than the reference number, the defect determination circuit 1220 can determine that a line defect has occurred.

[0360] according to Figure 16 and Figure 17 For example, if the test output signal Data1 is a signal corresponding to the 1st to 26th master drivers, and the counted number of pulses of the test output signal is 26 (which is equal to the reference value 26), then the defect determination circuit 1220 can determine that no line defect has occurred and can output a pass flag as the result of line defect determination.

[0361] If the number of counted pulses of the test output signal Data1 is 25 (which is less than the reference number 26), the defect determination circuit 1220 can determine that a line defect has occurred and output a fault flag as the result of the line defect determination.

[0362] Meanwhile, the defect determination circuit 1220 can also detect the location of a line defect based on the comparison between the counted number of pulses of the test output signal Data1 and the reference number.

[0363] For example, if the test output signal Data1 is the test output signal corresponding to the 1st to 26th master drivers, and the counted number of pulses of the test output signal Data1 is 9, then the defect determination circuit 1220 can determine that a defect has occurred in the line corresponding to the 10th master driver, and can output information about the location of the defect and a fault flag.

[0364] Furthermore, if the number of counted pulses of the test output signal Data1 is 25, the defect determination circuit 1220 can determine that a defect has occurred in the line corresponding to the 26th master driver, and can output information about the location of the line defect and a fault flag.

[0365] Embodiments of this disclosure can be described as follows.

[0366] A display device according to embodiments of this disclosure may include: a display panel including a plurality of main drivers disposed in each of a plurality of unit driving regions; and a timing controller that provides a synchronization signal and a clock signal to each of the plurality of main drivers via at least one first signal line. Here, the timing controller may receive a test output signal via a second signal line, the test output signal being based on test output pulses output at different timings from at least two of the plurality of main drivers.

[0367] The timing controller can provide test pulses to each of at least two master drivers via at least one first signal line in test mode.

[0368] At least one of the multiple master drivers may include: a clock buffer for receiving a test pulse from a timing controller and delaying the test pulse; and a first multiplexer for outputting the delayed test pulse as a test output pulse.

[0369] A clock buffer may include at least one D flip-flop.

[0370] Each clock buffer in at least two master drives may include a different number of D flip-flops.

[0371] The clock buffer may also include a second multiplexer connected to the output of at least one D flip-flop.

[0372] Each of the clock buffers in at least two master drivers can receive a reference clock signal from the timing controller via a third signal line.

[0373] At least two master drivers may include first to M drivers, where M is a positive integer of 2 or greater, and the test output signal may include a test output pulse output from each of the first to M drivers in each of the first to M timing sequences.

[0374] The timing controller can count the number of pulses of the test output signals output from at least two master drivers via a second signal line, and determine the defects in the lines connected to at least two master drivers based on the counted number of pulses.

[0375] The timing controller can compare the counted number of pulses with a reference number and determine the defects in the lines connected to at least two master drivers based on the comparison result.

[0376] If the counted number of pulses is less than the reference number, the timing controller can determine that a defect has occurred in the lines connected to at least two master drivers.

[0377] The timing controller can determine the location of a defective line among the lines connected to at least two master drives based on the results of the comparison.

[0378] Each of the plurality of master drivers can receive a corresponding synchronization signal from the first to the nth synchronization signals and a corresponding clock signal from the first to the nth clock signals through at least one first signal line, wherein n is a positive integer greater than or equal to 2 and n≤M.

[0379] The display panel may also include multiple sub-drivers, which are disposed in each of multiple unit driving areas and receive synchronization signals and clock signals from a corresponding master driver among multiple master drivers.

[0380] Multiple master drives can be located in a display area that is divided into multiple unit drive areas.

[0381] A display device according to an embodiment of the present disclosure may include: a plurality of main drivers disposed in each of a plurality of unit driving regions and including a clock buffer for delaying a test pulse provided through at least one first signal line; and a plurality of sub-drivers disposed in each of the plurality of unit driving regions and electrically connected to a corresponding main driver among the plurality of main drivers.

[0382] At least one of the multiple master drivers may also include a multiplexer that outputs a delayed test pulse as a test output pulse.

[0383] The display device according to embodiments of the present disclosure may further include a timing controller that provides test pulses to at least two of a plurality of master drivers and receives, via a second signal line, a test output signal based on test output pulses output from the at least two master drivers at different timings.

[0384] The timing controller may include: a counting circuit for counting the number of pulses of test output signals from at least two master drivers; and a defect determination circuit for comparing the counted number of pulses with a reference number and determining a defect in the lines connected to at least two master drivers based on the comparison result.

[0385] The above description is intended to enable those skilled in the art to implement and use the technical concepts of this disclosure, and is provided in the context of a specific application and its requirements. Those skilled in the art will readily understand various modifications, additions, and substitutions to the described embodiments, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and accompanying drawings are provided for illustrative purposes only, illustrating the technical concepts of this disclosure. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

Claims

1. A display device, comprising: The display panel includes a plurality of main drivers disposed in each of a plurality of unit driving regions; as well as A timing controller provides a synchronization signal and a clock signal to each of the plurality of master drivers via at least one first signal line. The timing controller is configured to receive a test output signal via a second signal line, the test output signal being based on test output pulses output from at least two of the plurality of master drivers at different timings.

2. The display device according to claim 1, wherein, In test mode, the timing controller provides test pulses to each of the at least two master drivers via the at least one first signal line.

3. The display device according to claim 1, wherein, At least one of the plurality of master drives includes: A clock buffer, the clock buffer being used to receive test pulses from the timing controller and delay the test pulses; and A first multiplexer is used to output a delayed test pulse as the test output pulse.

4. The display device according to claim 3, wherein, The clock buffer includes at least one D flip-flop.

5. The display device according to claim 3, wherein, Each of the clock buffers located in the at least two master drives comprises a different number of D flip-flops.

6. The display device according to claim 4, wherein, The clock buffer also includes a second multiplexer connected to the output of the at least one D flip-flop.

7. The display device according to claim 3, wherein, Each of the clock buffers located in the at least two master drivers receives a reference clock signal from the timing controller via a third signal line.

8. The display device according to claim 1, wherein, The at least two master drives include a first drive through an M-th drive, where M is a positive integer of 2 or greater. The test output signal includes the test output pulses output from each of the first driver to the Mth driver in each of the first timing sequence to the Mth timing sequence.

9. The display device according to claim 1, wherein, The timing controller counts the number of pulses of the test output signal output from the at least two master drivers via the second signal line, and determines the defects in the lines connected to the at least two master drivers based on the counted number of pulses.

10. The display device according to claim 9, wherein, The timing controller compares the counted number of pulses with a reference number and determines, based on the comparison result, any defects in the lines connected to the at least two master drivers.

11. The display device according to claim 10, wherein, If the counted number of pulses is less than the reference number, the timing controller determines that the defect has occurred in the lines connected to the at least two master drivers.

12. The display device according to claim 10, wherein, The timing controller determines the location of the defective line among the lines connected to the at least two master drives based on the comparison results.

13. The display device according to claim 1, wherein, Each of the plurality of master drivers receives a corresponding synchronization signal from the first synchronization signal to the nth synchronization signal and a corresponding clock signal from the first clock signal to the nth clock signal via the at least one first signal line, wherein n is a positive integer greater than or equal to 2 and n≤M.

14. The display device according to claim 1, wherein, The display panel also includes a plurality of sub-drivers, which are disposed in each of the plurality of unit driving areas and receive the synchronization signal and the clock signal from the corresponding master driver among the plurality of master drivers.

15. The display device according to claim 1, wherein, The plurality of master drivers are located in the display area which is divided into the plurality of unit drive areas.

16. A display device, comprising: Multiple master drivers are disposed in each of multiple unit drive regions, and include a clock buffer for delaying test pulses provided through at least one first signal line; as well as Multiple sub-drivers are disposed in each of the multiple unit drive regions and electrically connected to the corresponding master driver among the multiple master drivers.

17. The display device according to claim 16, wherein, At least one of the plurality of master drivers further includes a multiplexer that outputs a delayed test pulse as a test output pulse.

18. The display device of claim 16, further comprising a timing controller that provides the test pulse to at least two of the plurality of master drivers and receives, via a second signal line, a test output signal based on test output pulses output from the at least two master drivers at different timings.

19. The display device according to claim 18, wherein, The timing controller includes: A counting circuit, the counting circuit being used to count the number of pulses of the test output signal output from the at least two master drivers; and A defect determination circuit is provided for comparing a counted number of pulses with a reference number and determining, based on the comparison result, a defect in the lines connected to the at least two master drivers.

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