Display panel, driving method thereof and display device

Abstract

Embodiments of the present application provide a display panel, a driving method thereof and a display device. The shift register of the display panel comprises a plurality of shift register units connected in cascade, each of the shift register units comprising a control module, a first output module and a second output module, the first output module being connected to at least one output terminal of the control module, the second output module being connected to at least one output terminal of the control module and / or an output terminal of the first output module; the control module is configured to output a control signal based on at least a first input signal; the first output module is configured to output a first scan signal based on at least the control signal output by the control module, the high level of the first scan signal being an enable level; the second output module is configured to output at least one second scan signal based on at least the control signal output by the control module and / or the signal output by the first output module, the low level of the second scan signal being the enable level. The present application can narrow the frame of the display panel and reduce power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, its driving method, and a display device. Background Technology

[0002] In existing technologies, pixel circuits that simultaneously incorporate IGZO (Indium Gallium Zinc Oxide) transistors and LTPS (Low Temperature Poly-Silicon) transistors have become the mainstream design. This type of pixel circuit requires multiple sets of drive signals for operation; currently, it is designed with three sets of drive circuits per side, totaling six sets across both sides. These multiple drive circuits limit further reduction in panel bezel size and also result in excessive power consumption. Summary of the Invention

[0003] This invention provides a display panel, its driving method, and a display device to solve the technical problems of narrowing the bezel and reducing power consumption.

[0004] In a first aspect, embodiments of the present invention provide a display panel including a shift register, the shift register including a plurality of cascaded shift register units, the shift register unit including a control module, a first output module and a second output module, the first output module being connected to at least one output terminal of the control module, and the second output module being connected to at least one output terminal of the control module and / or to the output terminal of the first output module. The control module is configured to output a control signal based at least on the first input signal; The first output module is configured to output a first scan signal based on at least the control signal output by the control module, wherein the high level in the first scan signal is an enable level; The second output module is configured to output at least one second scan signal based on the control signal output by the control module and / or the signal output by the first output module, wherein the low level in the second scan signal is an enable level.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0006] Thirdly, based on the same inventive concept, the present invention also provides a driving method for a display panel. The display panel includes a shift register, which includes a plurality of cascaded shift register units. Each shift register unit includes a control module, a first output module, and a second output module. The first output module is connected to at least one output terminal of the control module, and the second output module is connected to at least one output terminal of the control module and / or to the output terminal of the first output module. The driving methods include: A first input signal is provided to the control module in the shift register unit, and the control module outputs a control signal based on at least the first input signal. The first output module is controlled to output a first scan signal based on the control signal output by the control module, wherein a high level in the first scan signal is an enable level. The control second output module outputs at least one second scan signal based on the control signal output by the control module and / or the signal output by the first output module, wherein the low level in the second scan signal is the enable level.

[0007] The display panel, driving method, and display device provided in this invention have the following advantages: The shift register unit in the display panel includes a control module, a first output module, and a second output module. After receiving a first input signal, the control module enables the first and second output modules to output a driving signal respectively. The first scan signal output by the first output module can drive an n-type transistor, and the second scan signal output by the second output module can drive a p-type transistor. The shift register composed of multiple cascaded shift register units can act as a driving circuit to drive the two types of transistors in the pixel circuit. This reduces the number of driving circuits in the display panel, saves wiring space, facilitates narrowing of the display panel bezel, reduces the number of clock signals, and helps reduce the power consumption of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2 for Figure 1 A timing diagram of the operation of a mid-pixel circuit; Figure 3 for Figure 1 Another timing diagram for the operation of the mid-pixel circuit; Figure 4 This is a schematic diagram of the circuit layout of a display panel in related technologies; Figure 5 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 8 A timing diagram of a shift register unit provided in an embodiment of the present invention; Figure 9 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a cascaded shift register unit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of a cascaded shift register unit provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 14 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 15 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 24 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 25 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 26 A schematic diagram of another cascaded shift register unit provided for implementation of the present invention; Figure 27 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 28 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 29 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention; Figure 30 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 31 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 32 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 33 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 34 This is a timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 35 A schematic diagram of another cascaded shift register unit provided for implementation of the present invention; Figure 36 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 37 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 38 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 39 A timing diagram of another shift register unit provided in an embodiment of the present invention; Figure 40 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 41 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention; Figure 42 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 43 A schematic diagram of the circuit layout of a display panel provided in an embodiment of the present invention; Figure 44 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 45 A schematic diagram of the circuit layout of another display panel provided in an embodiment of the present invention; Figure 46 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0013] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 for Figure 1 A timing diagram for the operation of a mid-pixel circuit. Figure 3 for Figure 1 Another timing diagram for the operation of the mid-pixel circuit. For example... Figure 1As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor T1, a data writing transistor T2, a threshold compensation transistor T3, an electrode reset transistor T4, a bias transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a storage capacitor Cst. The driving transistor Tm is connected in series between the first light-emitting control transistor T6 and the second light-emitting control transistor T7. The first light-emitting control transistor T6 receives a first power supply voltage Pvdd. The second light-emitting control transistor T7 and the electrode reset transistor T4 are respectively connected to one terminal of the light-emitting device PD, and the other terminal of the light-emitting device PD receives a second power supply voltage Pvee. The active layers of the threshold compensation transistor T3 and the gate reset transistor T1 are metal oxides, and both are n-type transistors. The active layers of the other transistors in the pixel circuit are silicon, and they are p-type transistors. This configuration reduces the leakage current from the threshold compensation transistor T3 and the gate reset transistor T1 to the gate of the driving transistor Tm, improving the gate potential stability of the driving transistor Tm. Additionally, bias transistor T5 is used to write the bias signal DVH to one terminal of drive transistor Tm to adjust the bias state of drive transistor Tm and improve the hysteresis effect of drive transistor Tm. The bias signal DVH can be a constant voltage signal.

[0014] In one implementation, combined with Figure 2 The operation of the pixel circuit includes a gate reset stage, a data writing stage, a bias stage, and a light emission stage. During time period t1, the scan signal S1n provides an enable signal to control the gate reset transistor T1 to turn on, writing the reset signal Vref to the gate of the driving transistor Tm to reset the gate of Tm. During time period t2, the scan signal S2n and the scan signal Sp provide enable signals, the threshold compensation transistor T3 and the data writing transistor T2 turn on, and the data voltage Data is written to the gate of the driving transistor Tm. During time period t3, the scan signal SpX provides an enable signal to control the bias transistor T5 to turn on, writing the bias signal DVH to the first terminal of the driving transistor Tm to adjust the bias state of Tm. During time period t4, the light emission control signal Em provides an enable signal, the first light emission control transistor T6 and the second light emission control transistor T7 turn on, and the driving transistor Tm generates a driving current under its gate control, providing the driving current to the light-emitting device PD to control the light emission of the PD.

[0015] In another implementation, combined Figure 3In the pixel circuit operation, time period t1 is the first bias stage, time period t2 is the gate reset stage, time period t3 is the data writing stage, time period t4 is the second bias stage, and time period t5 is the light emission stage. During time period t1, the scan signal S2n and scan signal SpX provide enable signals. Threshold compensation transistor T3 and bias transistor T5 are turned on, writing the bias signal DVH to the gate of the driving transistor Tm to optimize the hysteresis effect of the driving transistor Tm. Electrode reset transistor T4 is turned on, writing the reset signal Vref to the electrode of the light-emitting device PD. During time period t2, the scan signal S1n provides enable signals, and the gate reset transistor T1 is turned on, writing the reset signal Vref to the gate of the driving transistor Tm to reset the gate of the driving transistor Tm. During time period t3, the scan signal S2n and scan signal Sp provide enable signals. Threshold compensation transistor T3 and data writing transistor T2 are turned on, writing the data voltage Data to the gate of the driving transistor Tm. During time period t4, the scan signal SpX again provides an enable signal to control the bias transistor T5 to turn on, writing the bias signal DVH to the first terminal of the driving transistor Tm to adjust the bias state of the driving transistor Tm. During time period t5, the light emission control signal Em provides an enable signal, turning on the first light emission control transistor T6 and the second light emission control transistor T7. The driving transistor Tm generates a driving current under its gate control and provides the driving current to the light-emitting device PD to control the light emission of the light-emitting device PD.

[0016] The pixel circuit includes n-type and p-type transistors. For example, the gate reset transistor T1 and the threshold compensation transistor T3 are enabled at a high level, while other transistors, such as the data write transistor T2, are enabled at a low level. The scan signal using a low level as the enable level and the scan signal using a high level as the enable level need to be provided by different drive circuits. To... Figure 1 If the pixel circuit provided in the embodiment is used for driving, then multiple sets of driving circuits need to be set in the display panel.

[0017] Figure 4 This is a schematic diagram of the circuit layout of a display panel in related technologies, such as... Figure 4As shown, the display panel has a light-emitting driving circuit Em, a first scanning driving circuit S1n, a second scanning driving circuit S2n, a third scanning driving circuit Sp, and a fourth scanning driving circuit SpX arranged on the left and right sides of the display area AA. The light-emitting driving circuit Em and the light-emitting control signal Em use the same marking, and the scanning circuit and the scanning signal it provides use the same marking, such as the first scanning driving circuit S1n providing the scanning signal S1n. Specifically, the left side of the display area AA has the light-emitting driving circuit Em, the first scanning driving circuit S1n, and the third scanning driving circuit Sp, while the right side has the second scanning driving circuit S2n, the third scanning driving circuit Sp, and the fourth scanning driving circuit SpX. That is, three sets of driving circuits are arranged on each side, which limits the further reduction of the panel bezel, and also requires multiple sets of clock signals for multiple sets of driving circuits, increasing the power consumption of the display panel.

[0018] To address the problems existing in related technologies, embodiments of the present invention provide a display panel in which a shift register unit is provided. This shift register unit can output a scan signal with a high enable level and a scan signal with a low enable level. One set of shift register units can output two types of drive signals, which can reduce the number of drive circuits in the display panel, save wiring space, and facilitate narrowing of the display panel bezel. Furthermore, it can reduce the number of clock signals required, thereby reducing the power consumption of the display panel.

[0019] Figure 5 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention. Figure 5 As shown, the shift register unit VSR includes a control module 00, a first output module 10, and a second output module 20. The first output module 10 is connected to at least one output terminal of the control module 00, and the second output module 20 is connected to at least one output terminal of the control module 10 and / or to the output terminal of the first output module 10.

[0020] Control module 00 is configured to output a control signal based at least on the first input signal IN-1. The pulse level of the first input signal IN-1 is either high or low, and the type of the first input signal IN-1 is set according to the specific connection method between each module and the adapted structure.

[0021] The first output module 10 is configured to output a first scan signal sn based on at least the control signal output by the control module 00, wherein a high level in the first scan signal sn is an enable level. The first scan signal sn can drive an n-type transistor. Figure 1 Gate reset transistor T1 and / or threshold compensation transistor T3 in the pixel circuit.

[0022] The second output module 20 is configured to output at least one second scan signal sp based on at least the control signal output by the control module 00 and / or the signal output by the first output module 10, wherein a low level in the second scan signal sp is an enable level. The second scan signal sp is capable of driving a p-type transistor, such as driving... Figure 1 In the pixel circuit, data is written to transistor T2. In this embodiment of the invention, the second output module 20 can output one, two, or multiple second scan signals. When the second output module 20 outputs two second scan signals sp, there is a phase difference between the two output second scan signals sp. When the display panel is driven line by line, the two second scan signals sp output by the second output module 20 can drive the data writing transistor T2 in one pixel row respectively.

[0023] This invention provides a display panel in which a shift register unit (VSR) includes a control module 00, a first output module 10, and a second output module 20. After receiving a first input signal IN-1, the control module 00 enables the first output module 10 and the second output module 20 to output a driving signal respectively. The first scan signal sn output by the first output module 10 can drive an n-type transistor, and the second scan signal sp output by the second output module 20 can drive a p-type transistor. The shift register, composed of multiple cascaded shift register units (VSRs), can act as a driving circuit to drive both types of transistors in the pixel circuit. This reduces the number of driving circuits in the display panel, saves wiring space, facilitates narrowing of the display panel bezel, reduces the number of clock signals, and helps lower the power consumption of the display panel.

[0024] This invention also provides a driving method for a display panel, which can be used to drive the display panel provided in this invention. (In conjunction with...) Figure 5 The driving methods include: A first input signal IN-1 is provided to the control module 00 in the shift register unit VSR, and the control module 00 outputs a control signal based at least on the first input signal IN-1; The first output module 10 outputs a first scan signal sn based on the control signal output by the control module 00, wherein a high level in the first scan signal sn is an enable level. The control second output module 20 outputs at least one second scan signal sp based on the control signal output by the control module 00 and / or the signal output by the first output module 10, wherein the low level of the second scan signal sp is the enable level.

[0025] The driving method provided in this embodiment of the invention enables the control module 00 in the shift register unit VSR to control the first output module 10 and the second output module 20 to output a driving signal respectively after receiving the first input signal IN-1. The two driving signals output by the shift register unit VSR can drive two types of transistors in the pixel circuit. In applications, this reduces the number of driving circuits in the display panel, saves display panel wiring space, facilitates narrowing of the display panel bezel, and also reduces the number of clock signals, thus lowering the power consumption of the display panel.

[0026] In some embodiments of the present invention, by configuring the structure of the first output module 10 and the signals it receives, the first output module 10 can output a constant voltage signal under the control of the control signal output by the control module 00. At this time, the second output module 20 normally outputs the second scan signal sp, thus enabling the shift register unit VSR to have two operating modes. In the first mode, the shift register unit VSR outputs a first scan signal sn and at least one second scan signal sp; in the second mode, the shift register unit VSR outputs a constant voltage signal and at least one second scan signal sp. When the first scan signal sn is used to drive the gate reset transistor and / or the threshold compensation transistor, the display panel can achieve a partitioned refresh function. In other embodiments, the first output module 10 only has the function of outputting the first scan signal sn, then the shift register unit VSR has only one operating mode, i.e., the operating mode that outputs two driving signals.

[0027] The following describes the implementation of a shift register unit with only one operating mode.

[0028] In some implementations... Figure 6 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 6 As shown, control module 00 is configured to output a control signal based on a first input signal IN-1, a first clock signal CK1, a first voltage signal VGL, and a second voltage signal VGH; optionally, the voltage value of the second voltage signal VGH is greater than the voltage value of the first voltage signal VGL. First output module 10 is configured to output a first scan signal sn based on the control signal output by control module 00, the first voltage signal VGL, and the second voltage signal VGH. Optionally, to ensure the signal output performance of first output module 10, the first voltage signal VGL and the second voltage signal VGH received by it can be provided by separately configured signal lines. Second output module 20 is configured to output at least one second scan signal sp based on the first voltage signal VGL, the second voltage signal VGH, at least one clock signal, and the control signal output by control module 00 and the signal output by first output module 10. Figure 6The clock signals received by the second output module 20 include the second clock signal CK2 and the third clock signal CK3. Therefore, it outputs two second scan signals sp, namely the first sub-scan signal sp1 and the second sub-scan signal sp2.

[0029] In other implementations, Figure 7 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 7 As shown, control module 00 is configured to output a control signal based on the first input signal IN-1, the first clock signal CK1, the first voltage signal VGL, and the second voltage signal VGH. First output module 10 is configured to output a first scan signal sn based on the control signal output by control module 00, the first voltage signal VGL, and the second voltage signal VGH. Second output module 20 is configured to output two second scan signals sp based on the first voltage signal VGL, the second voltage signal VGH, the second clock signal CK2, the third clock signal CK3, and the signal output by first output module 10 and the second input signal IN-2. The two second scan signals sp are the first sub-scan signal sp1 and the second sub-scan signal sp2, respectively.

[0030] Regarding the structure and connection method of the first output module 10 and the control module 00, such as... Figure 6 and Figure 7As shown, the first output module 10 includes a first inverter 1; the input terminal of the first inverter 1 is connected to the output terminal of the control module 00, and the first inverter 1 outputs a first scan signal sn based on the control signal output by the control module 00. The output terminal of the first inverter 1 is the output terminal of the first output module 10. The first inverter 1 is a CMOS inverter, which includes an n-type transistor and a p-type transistor. The ground terminal of the first inverter 1 receives a first voltage signal VGL, and the power supply terminal receives a second voltage signal VGH. Specifically, one end of the p-type transistor in the first inverter 1 receives the second voltage signal VGH, and one end of the n-type transistor receives the first voltage signal VGL. The control module 00 includes a first submodule 2 and a second inverter 3. The first submodule 2 receives a first input signal IN-1, and the input terminals of the first submodule 2 and the second inverter 3 are connected to a first node N1. The output terminal of the second inverter 3 and the input terminal of the first inverter 1 are connected to a second node N2. The first submodule 2 is configured to write the first input signal IN-1 to the input terminal of the second inverter 3 under the control of the first clock signal CK1. The second inverter 3 outputs the first input signal IN-1 after inverting its phase. The second inverter 3 is a CMOS inverter, which includes an n-type transistor and a p-type transistor. The ground terminal of the second inverter receives the first voltage signal VGL, and the power supply terminal receives the second voltage signal VGH. The first output module 00 also includes a first capacitor C1, which is used to stabilize the potential of the first node N1. One plate of the first capacitor C1 is connected to the first node N1, and the other plate receives the first voltage signal VGL.

[0031] There are multiple ways to connect the second output module 20 to the control module 00 and / or the first output module 10. Figure 6 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1, and at least one input terminal of the second output module 20 is connected to the input terminal of the first inverter 1, that is, to the output terminal of the control module 00. Figure 7 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1, and at least one input terminal of the second output module 20 receives the second input signal IN-2.

[0032] Optionally, the second output module 20 includes a submodule configured to output a second scan signal sp based at least on a first voltage signal VGL, a second voltage signal VGH, and a clock signal. Figure 6 and Figure 7The embodiment takes the second output module 20, which includes two sub-modules, sub-module 21 and sub-module 22, as an example. Sub-module 21 is configured to output a first sub-scan signal sp1 based at least on a first voltage signal VGL, a second voltage signal VGH, and a second clock signal CK2. Sub-module 22 is configured to output a second sub-scan signal sp2 based at least on a first voltage signal VGL, a second voltage signal VGH, and a third clock signal CK3. Specifically, as shown... Figure 6 As illustrated, each submodule includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a third capacitor C3.

[0033] This invention also provides another driving method for a display panel, which can be used to drive a display panel including... Figure 6 In this embodiment, the display panel of the shift register unit is driven. The driving method includes: The control module 00 is provided with a first input signal IN-1, a first clock signal CK1, a first voltage signal VGL, and a second voltage signal VGH, and the control module 00 is controlled to output control signals. During the period when the pulse of the first input signal IN-1 overlaps with the first low level of the first clock signal CK1, the first output module 10 starts outputting a high-level signal of the first scan signal sn based at least on the control signal output by the control module 00. During the period when the non-pulse of the first input signal IN-1 overlaps with the second low level of the first clock signal CK1, the first output module 10 ends outputting a high-level signal of the first scan signal sn based at least on the control signal output by the control module 00. The second low level is the s-th pulse signal after the first low level, where s is a positive integer. s can be 1, 2, 3, etc., and the magnitude of s affects the pulse width of the first scan signal sn. In some embodiments, the pulse of the first input signal IN-1 is a high-level pulse, and the non-pulse of the first input signal IN-1 is a low-level signal. In other embodiments, the pulse of the first input signal IN-1 is a low-level pulse, and the non-pulse of the first input signal IN-1 is a high-level signal.

[0034] During the period when the first clock signal CK1 provides a first low level and a second low level, the control second output module 20 outputs at least one low level signal of the second scan signal sp based on the control signal output by the control module 00 and / or the signal output by the first output module 10.

[0035] In the driving method provided by this embodiment of the invention, the overlap between the pulse / non-pulse state of the first input signal IN-1 and the high / low level of the first clock signal CK1 affects the control signal output by the control module 00, and thus affects the signal output of the first output module 10 and the second output module 20. Specifically, during the overlap period between the pulse of the first input signal IN-1 and a low level of the first clock signal CK1, the first output module 10 starts outputting a high-level signal of the first scan signal sn based on the control signal output by the control module 00. Then, at the overlap time between another low level of the first clock signal CK1 and a non-pulse state of the first input signal IN-1, the first output module 10 ends outputting the high-level signal of the first scan signal sn. The high-level pulse width of the first scan signal sn output by the first output module 10 is related to the period of the first clock signal CK1; for example, when s=1, the high-level pulse width of the first scan signal sn is the same as the period of the first clock signal CK1. Furthermore, during the first low level and the second low level of the first clock signal CK1, the second output module 20 is controlled to output at least one low-level signal of the second scan signal sp. This causes the high-level period of the first scan signal sn to overlap with the low-level period of the second scan signal sp, making it easier to coordinate the timing of the first scan signal sn and the second scan signal sp with the signal timing required by the pixel circuit in applications.

[0036] The driving method provided by the embodiments of the present invention can be understood in conjunction with the timing diagram below.

[0037] Figure 8 This is a timing diagram of a shift register unit provided in an embodiment of the present invention. Figure 8 The provided timing diagrams can be applied to Figure 6 The shift register unit provided in the embodiment. Combined with... Figure 8 and Figure 6 As can be seen, the pulse level of the first input signal IN-1 is high, and the pulse level of the first input signal IN-1 and the low level period of the first clock signal CK1 at least partially overlap.

[0038] During time period t11, when the first clock signal CK1 provides a low level, the first submodule 2 is turned on, writing the high level of the first input signal IN-1 to the first node N1, making the potential of the first node N1 high. The second inverter 3 has a high input level and a low output level, so the potential of the second node N2 is low. The input of the first inverter 1 is connected to the second node N2. When the second node N2 is at a low potential, the output of the first inverter 1 outputs a high-level signal. That is, starting from time period t11, the first output module 10 outputs a high-level signal for the first scan signal sn. During time periods t12 and t13, the first clock signal CK1 is high, controlling the first submodule 2 to turn off. The first node N1 remains at a high potential, the second node N2 remains at a low potential, and the first output module 10 continuously outputs a high-level signal for the first scan signal sn. During the t14 period, the first clock signal CK1 is low again, which controls the first submodule 2 to open and write the low level of the first input signal IN-1 to the first node N1. Then the potential of the first node N1 is low and the potential of the second node N2 is high. The output of the first inverter 1 outputs a low level signal, which means that from the t12 period, the first output module 10 outputs the low level signal of the first scan signal sn.

[0039] Additionally, at least one control terminal of the second output module 20 is connected to the output terminal of the first output module 10, and at least one input terminal is connected to the output terminal of the control module 00. During the t11 period, the second node N2 is at a low potential. The second node N2 writes a low-level signal to the third node N3 through the ninth transistor M9 in the submodule 21, and writes a low-level signal to the fourth node N4 through the ninth transistor M9 in the submodule 22. During the t12 period, when the second clock signal CK2 is at a low level, the second node N2 maintains a low potential, and the third node N3 maintains a low potential to control the tenth transistor M10 to turn on and output the low-level signal of the second clock signal CK2. At the same time, the output terminal of the first output module 10 outputs a high-level signal to control the eleventh transistor M11 to turn off. At this time, the second output module 20 outputs a low-level signal of the first sub-scan signal sp1. Submodules 22 and 21 have the same operating mode. During the t13 period when the third clock signal CK3 is low, the fourth node N4 is low, which controls the tenth transistor M10 to turn on and output the low-level signal of the third clock signal CK3. At the same time, the output terminal of the first output module 10 outputs a high-level signal to control the eleventh transistor M11 to turn off. At this time, the second sub-scan signal sp2 output by the second output module 20 is low.

[0040] During the time interval t11 to t14, the shift register unit outputs a first scan signal sn, a first sub-scan signal sp1, and a second sub-scan signal sp2. The low-level start time of the second sub-scan signal sp2 is later than the low-level start time of the first sub-scan signal sp1. That is, when the shift register unit outputs two or more second scan signals, there is a phase difference between the different second scan signals.

[0041] In some embodiments of the present invention Figure 8 The embodiment illustrates that the first clock signal CK1 provides a first low level and a second low level, which are two adjacent pulse signals, i.e., s=1. Combined with... Figure 8 As shown in the schematic timing diagram, during the period when the first clock signal CK1 provides a first low level (the first low level overlapping with the high level pulse of the first input signal IN-1) and a second low level, the second output module 20 is controlled to output at least one low level signal of the second scan signal sp. This includes controlling the second output module 20 to output at least one low level signal of the second scan signal sp based on at least one clock signal, wherein the low level period of the clock signal received by the second output module 20 corresponds to the low level period of the second scan signal sp. Figure 8 In this embodiment, taking the output of two second scan signals sp by the second output module 20 as an example, the low level of the second clock signal CK2 controls the output of the low level signal of the first sub-scan signal sp1, and the low level of the third clock signal CK3 controls the output of the low level signal of the second sub-scan signal sp2. That is, when the second output module 20 outputs two second scan signals sp, it needs to input at least two clock signals.

[0042] like Figure 7 As shown, the shift register unit also includes a second input module 23. One input terminal of submodule 21 and one input terminal of submodule 22 respectively receive the second input signal IN-2 through the second input module 23. The second input module 23 is configured to write the second input signal IN-2 to one input terminal of submodule 21 and one input terminal of submodule 22 based on the control of the first clock signal CK1. Specifically, the second input module 23 includes a twelfth transistor M12. The control terminal of this transistor receives the first clock signal CK1, its first electrode receives the second input signal IN-2, and its second electrode is connected to one input terminal of submodule 21 and one input terminal of submodule 22.

[0043] The embodiments of the present invention also provide the ability to […]. Figure 7The method for driving the shift register unit provided in the embodiment includes controlling the second output module 20 to output at least one low-level signal of the second scan signal sp based on at least the second input signal IN-2, the control signal output by the control module 00, or the signal output by the first output module 10. During the period when the first clock signal CK1 provides a low level, the second input signal IN-2 is written to the second output module 20. The period during which the pulse level of the second input signal IN-2 is written to the second output module 20 can be the period when the first clock signal CK1 provides a first low level, or it can be a low-level period after the first low level. The following timing diagram illustrates the method by writing the pulse level of the second input signal IN-2 to the second output module 20 during the period when the first clock signal CK1 provides a first low level. The driving method will be understood in conjunction with the timing diagram below.

[0044] Figure 9 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 9 The provided timing diagrams can be applied to Figure 7 The provided shift register unit. Combined with... Figure 9 and Figure 7 As shown, the pulse level of the first input signal IN-1 is high, and the pulse level of the second input signal IN-2 is low. During time period t11, the first clock signal CK1 provides a low level, the first submodule 2 is turned on, and the high level of the first input signal IN-1 is written to the first node N1. The first node N1 is at a high potential, the second node N2 is at a low potential, and the first output module 10 outputs a high-level signal of the first scan signal sn. During time periods t12 and t13, the first node N1 remains at a high potential, the second node N2 remains at a low potential, and the first output module 10 continuously outputs a high-level signal of the first scan signal sn. During time period t14, the first clock signal CK1 provides a low level, the first submodule 2 is turned on, and the low level of the first input signal IN-1 is written to the first node N1. The first node N1 is at a low potential, the second node N2 is at a high potential, and the first output module 10 outputs a low-level signal of the first scan signal sn. The low-level pulse of the second input signal IN-2 coincides at least partially with the low level of the first clock signal CK1. During the t11 period, the first clock signal CK1 controls the second input module 23 to open and write the low level of the second input signal IN-2 to the third node N3 of the sub-module 21 and the fourth node N4 of the sub-module 23, respectively. This makes the first sub-scan signal sp1 output by the second output module 20 low during the t12 period when the second clock signal CK2 is low, and the second sub-scan signal sp2 output by the second output module 20 low during the t13 period when the third clock signal CK3 is low.

[0045] In some implementations... Figure 10This is a schematic diagram of a cascaded shift register unit provided in an embodiment of the present invention. Figure 10 The middle indicates Figure 6 Cascading of intermediate shift register units. Figure 6 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1, and at least one input terminal of the second output module 20 is connected to the input terminal of the first inverter 1. The pulse level of the first input signal IN-1 is high. Figure 10 The diagram illustrates three cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1), the ith stage shift register unit VSR(i), and the (i+1)th stage shift register unit VSR(i+1). Figure 10 It can be seen that the input terminal of the first submodule 2 in the i-th level shift register unit VSR(i) is connected to the output terminal of the first inverter 1 in the (i-1)-th level shift register unit VSR(i-1), where i is an integer and i≥2. When driving multiple cascaded shift register units in this embodiment, four clock signal lines need to be set in the display panel, namely the first clock signal line K1, the second clock signal line K2, the third clock signal line K3, and the fourth clock signal line K4. The clock signals provided by the four clock signal lines have the same period. Taking i as an even number as an example, i-1 is an odd number. For the odd-numbered level shift register unit, the first clock signal line K1 provides it with the first clock signal CK1, the second clock signal line K2 provides it with the second clock signal CK2, and the third clock signal line K3 provides it with the third clock signal CK1. For the even-numbered shift register unit, the third clock signal line K3 provides it with the first clock signal CK1, the fourth clock signal line K4 provides it with the second clock signal CK2, and the first clock signal line K1 provides it with the third clock signal CK1.

[0046] In other implementations, Figure 11 This is a schematic diagram of a cascaded shift register unit provided in an embodiment of the present invention. Figure 11 The middle indicates Figure 7 Cascading of intermediate shift register units. Figure 7 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1, and at least one input terminal of the second output module 20 receives the second input signal IN-2. The pulse level of the first input signal IN-1 is high, and the pulse level of the second input signal IN-2 is low. Figure 9 As shown in the schematic timing diagram, the low-level start time of the second sub-scan signal sp2 is later than the low-level start time of the first sub-scan signal sp1. Figure 11The diagram illustrates three cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1), the ith stage shift register unit VSR(i), and the (i+1)th stage shift register unit VSR(i+1). Figure 11 It can be seen that the input terminal of the first submodule 2 in the i-th stage shift register unit (i) is connected to the output terminal of the first inverter 1 in the (i-1)-th stage shift register unit VSR (i-1). The input terminal of the second output module 20 in the i-th stage shift register unit VSR (i) receives the second sub-scan signal sp2 output by the (i-1)-th stage shift register unit VSR (i-1), where i is an integer and i≥2. That is, when the shift register unit outputs two or more second scan signals sp, there is a phase difference between the different second scan signals sp. The second scan signal with the latest low-level start time is used as the second input signal IN-2 received by the next stage shift register unit. When driving multiple cascaded shift register units in this embodiment, four clock signal lines need to be set in the display panel, namely the first clock signal line K1, the second clock signal line K2, the third clock signal line K3, and the fourth clock signal line K4. The clock signals provided by the four clock signal lines have the same period. Taking i as an even number as an example, i-1 is an odd number. For the odd-numbered shift register unit, the first clock signal line K1 provides it with the first clock signal CK1, the second clock signal line K2 provides it with the second clock signal CK2, and the third clock signal line K3 provides it with the third clock signal CK1. For the even-numbered shift register unit, the third clock signal line K3 provides it with the first clock signal CK1, the fourth clock signal line K4 provides it with the second clock signal CK2, and the first clock signal line K1 provides it with the third clock signal CK1.

[0047] In other implementations, Figure 12 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 12 As shown, control module 00 is configured to output a control signal based on the first input signal IN-1, the first clock signal CK1, the first voltage signal VGL, and the second voltage signal VGH. First output module 10 is configured to output a first scan signal sn based on the control signal output by control module 00, the first voltage signal VGL, and the second voltage signal VGH. Second output module 20 is configured to output two second scan signals sp based on the first voltage signal VGL, the second voltage signal VGH, the second clock signal CK2, the third clock signal CK3, and the signal output by control module 00. The two second scan signals sp are the first sub-scan signal sp1 and the second sub-scan signal sp2, respectively.

[0048] In other implementations, Figure 13 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 13 As shown, control module 00 is configured to output a control signal based on the first input signal IN-1, the first clock signal CK1, the first voltage signal VGL, and the second voltage signal VGH; first output module 10 is configured to output a first scan signal sn based on the control signal output by control module 00, the first voltage signal VGL, and the second voltage signal VGH. Second output module 20 is configured to output a first sub-scan signal sp1 and a second sub-scan signal sp2 based at least on the first voltage signal VGL, the second voltage signal VGH, the second clock signal CK2, the third clock signal CK3, and the signal output by control module 00 and the second input signal IN-2. Figure 12 and Figure 13 As shown, the control module 00 includes a first submodule 2, a first inverter 1, and a second inverter 3. The first submodule 2 receives a first input signal IN-1. The input terminals of the first submodule 2 and the second inverter 3 are connected to a first node N1. The output terminal of the second inverter 3 and the input terminal of the first inverter 1 are connected to a second node N2. The first submodule 2 is configured to write the first input signal IN-1 to the input terminal of the second inverter 3 under the control of a first clock signal CK1. The input terminal of the first inverter 1 is connected to the output terminal of the second inverter 3. The first output module 10 includes a third inverter 4. The input terminal of the third inverter 4 is connected to the output terminal of the control module 00. The third inverter 4 outputs a first scan signal sn based at least on the control signal output by the control module 00. The third inverter 4 is a CMOS inverter, which includes an n-type transistor and a p-type transistor. One end of the n-type transistor receives a first voltage signal VGL, and one end of the p-type transistor receives a second voltage signal VGH.

[0049] Figure 12 In this embodiment, the input terminal of the second inverter 3 is connected to the first node N1, and the input terminal of the second inverter 3 is connected to the output terminal of the first inverter 1 to form a latch structure. At least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. Additionally, Figure 12 The embodiment illustrates that the control module 00 further includes a reset submodule 01. The reset submodule 01 is configured to write the second voltage signal VGH to the first node N1 under the control of the reset control signal RST, thereby resetting the first node N1. Specifically, the reset submodule 01 includes a p-type transistor, whose control terminal receives the reset control signal RST, its first terminal receives the second voltage signal VGH, and its second terminal is connected to the first node N1.

[0050] Figure 13In this embodiment, a first capacitor C1 is provided. One plate of the first capacitor C1 is connected to the first node N1, and the other plate receives the first voltage signal VGL. The signal from the output of the first inverter 1 is required when the shift register units are cascaded. Figure 13 The embodiment is configured such that the signals at the output of the first node N1 and the first inverter 1 are not correlated, thus preventing the potential of the first node N1 from being interfered with by the next-stage shift register unit. Figure 13 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 receives the second input signal IN-2.

[0051] In addition, such as Figure 12 The structure of the second output module 20 and Figure 6 The same applies to the embodiments. Figure 13 The structure of the second output module 20 and Figure 7 The same applies to the embodiments, and the structure of the second output module 20 will not be described again here.

[0052] Figure 14 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 14 The provided timing diagrams can be applied to Figure 12 The shift register unit provided in the embodiment. Combined with... Figure 14 and Figure 12 The pulse level of the first input signal IN-1 is low, and the pulse level of the first input signal IN-1 and the low level of the first clock signal CK1 at least partially overlap. During period t21: the first clock signal CK1 provides a low level to control the first submodule 2 to open and write the low level of the first input signal IN-1 into the first node N1, making the potential of the first node N1 low; the second inverter 3 inputs a low level and outputs a high level, so the potential of the second node N2 is high; the first inverter 1 inputs a high level and outputs a low level, so the input terminal of the first output module 10 receives a low level; the third inverter 4 in the first output module 10 processes the signal, and when its input terminal is a low level signal, its output terminal outputs a high level signal. At this time, the first output module 10 outputs a high level signal for the first scan signal sn. During periods t22 and t23, the first node N1 maintains a low potential, the second node N2 maintains a high potential, and the first output module 10 outputs a high level signal for the first scan signal sn. During the t24 period, the first clock signal CK1 provides a low level to control the first submodule 2 to open and write the high level of the first input signal IN-1 to the first node N1. The potential of the first node N1 is high, and the potential of the corresponding second node N2 is low. The input terminal of the third inverter 4 receives the high level signal, and the output terminal of the third inverter 4 outputs the low level signal. During this period, the first output module 10 outputs the low level signal of the first scan signal sn.

[0053] Additionally, during period t21, the first inverter 1 outputs a low-level signal, which is written to the third node N3 via the ninth transistor M9 in submodule 21 and to the fourth node N4 via the ninth transistor M9 in submodule 22. During period t22, when the second clock signal CK2 is low, the first inverter 1 continues to output a low-level signal. The third node N3 maintains a low potential, controlling the tenth transistor M10 to turn on and output the low-level signal of the second clock signal CK2. Simultaneously, the second node N2 is at a high potential, controlling the eleventh transistor M11 to turn off. At this time, the first sub-scan signal sp1 output by the second output module 20 is low. Submodule 22 and submodule 21 have the same operating mode. During period t23, when the third clock signal CK3 is low, the fourth node N4 is at a low potential, controlling the tenth transistor M10 to turn on and output the low-level signal of the third clock signal CK3. Simultaneously, the second node N2 is at a high potential, controlling the eleventh transistor M11 to turn off. At this time, the second sub-scan signal sp2 output by the second output module 20 is low.

[0054] Figure 12 As illustrated in this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. In another embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first output module 10, and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. Other connection methods are the same as... Figure 12 The same applies, and no further illustrations are provided here. The shift register unit provided in this embodiment can also employ... Figure 14 The timing shown is used for driving.

[0055] like Figure 13 As shown, the shift register unit also includes a second input module 23. One input terminal of submodule 21 and one input terminal of submodule 22 respectively receive the second input signal IN-2 through the second input module 23. The second input module 23 is configured to write the second input signal IN-2 to one input terminal of submodule 21 and one input terminal of submodule 22 respectively based on the control of the first clock signal CK1.

[0056] Figure 15 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 15 The provided timing diagrams can be applied to Figure 13 The provided shift register unit. Combined with... Figure 15 and Figure 13As can be seen, the pulse level of the first input signal IN-1 is high, and the pulse level of the second input signal IN-2 is low. During time period t21, the first clock signal CK1 provides a low level, the first submodule 2 is turned on, and the high level of the first input signal IN-1 is written to the first node N1. The first node N1 is at a high potential, the second node N2 is at a low potential, the first inverter 1 outputs a high-level signal, and the third inverter 4 outputs a low-level signal. That is, the first output module 10 outputs the high-level signal in the first scan signal sn. During time periods t22 and t23, the first node N1 maintains a high potential, the second node N2 maintains a low potential, and the first output module 10 outputs the high-level signal of the first scan signal sn. During the t24 period, the first clock signal CK1 provides a low level, the first submodule 2 opens and writes the low level of the first input signal IN-1 into the first node N1, the first node N1 is at a low potential, the second node N2 is at a high potential, the first inverter 1 outputs a low level signal, then the third inverter 4 outputs a high level signal, and the first output module 10 starts to output the high level signal of the first scan signal sn.

[0057] Furthermore, the low-level pulse of the second input signal IN-2 at least partially overlaps with the low level of the first clock signal CK1. During period t21, the first clock signal CK1 controls the second input module 23 to open, writing the low level of the second input signal IN-2 to the third node N3 and the fourth node N4 of submodule 21 respectively. During period t22, when the second clock signal CK2 is low, the third node N3 remains low, and the first sub-scan signal sp1 output by the second output module 20 is low. During period t23, when the third clock signal CK3 is low, the fourth node N4 remains low, and the second sub-scan signal sp2 output by the second output module 20 is low.

[0058] Figure 13 In one embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 receives the second input signal IN-2 through the second input module 23. In another embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the first output module 10, and at least one input terminal of the second output module 20 receives the second input signal IN-2 through the second input module 23. Other connection methods are the same as described above. Figure 13 The same applies, and no further illustrations are provided here. The shift register unit provided in this embodiment can also employ... Figure 15 The timing shown is used for driving.

[0059] In some implementations... Figure 16 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention. Figure 16 The middle indicates Figure 12Cascading of intermediate shift register units. Figure 12 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. Combined with... Figure 14 From the timing diagram, the pulse level of the first input signal IN-1 is low, and the low level start time of the second sub-scan signal sp2 in the second scan signal is later than the low level start time of the first sub-scan signal sp1.

[0060] Figure 16 The diagram illustrates two cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1) and the ith stage shift register unit VSR(i). The input terminal of the first submodule 2 in the ith stage shift register unit VSR(i) receives the third scan signal sp2 output by the (i-1)th stage shift register unit VSR(i-1), where i is an integer, i ≥ 2. When driving multiple cascaded shift register units in this embodiment, four clock signal lines are required in the display panel: a first clock signal line K1, a second clock signal line K2, a third clock signal line K3, and a fourth clock signal line K4. The clock signals provided by these four clock signal lines have the same period. Taking an even number as an example, i-1 is an odd number. For the odd-numbered stage shift register unit, the first clock signal line K1 provides the first clock signal CK1, the second clock signal line K2 provides the second clock signal CK2, and the third clock signal line K3 provides the third clock signal CK1. For the even-numbered shift register unit, the third clock signal line K3 provides it with the first clock signal CK1, the fourth clock signal line K4 provides it with the second clock signal CK2, and the first clock signal line K1 provides it with the third clock signal CK1.

[0061] In other implementations, Figure 17 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention. Figure 17 The middle indicates Figure 13 Cascading of intermediate shift register units. Figure 13 In this embodiment, at least one control terminal of the second output module 20 is connected to the output terminal of the second inverter 3, and at least one input terminal of the second output module 20 receives the second input signal IN-2 through the second input module 23. Combined with... Figure 15 From the timing diagram, the pulse level of the first input signal IN-1 is high, the pulse level of the second input signal IN-2 is low, and the low level start time of the second sub-scan signal sp2 in the second scan signal is later than the low level start time of the first sub-scan signal sp1.

[0062] Figure 17The diagram illustrates two cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1) and the i-th stage shift register unit VSR(i). The input terminal of the first sub-module 2 in the i-th stage shift register unit VSR(i) is connected to the output terminal of the first inverter 1 in the (i-1)th stage shift register unit VSR(i-1). The input terminal of the second output module 20 in the i-th stage shift register unit VSR(i) receives the second sub-scan signal sp2 output by the (i-1)th stage shift register unit VSR(i-1), where i is an integer, i≥2. When driving multiple cascaded shift register units in this embodiment, four clock signal lines need to be set in the display panel, namely the first clock signal line K1, the second clock signal line K2, the third clock signal line K3, and the fourth clock signal line K4. The clock signals provided by the four clock signal lines have the same period.

[0063] In some embodiments of the present invention, the first output module 10 is configured to output a first scan signal based at least on a first level signal of the refresh control signal and a control signal output by the control module 10, and to output a low-level constant voltage signal based at least on a second level signal of the refresh control signal and the control module 10, wherein one of the first level signal and the second level signal is a high-level signal and the other is a low-level signal. This allows the shift register unit VSR to have two operating modes. Taking the shift register unit outputting two second scan signals as an example, in the first mode, the shift register unit VSR outputs a first scan signal sn, a first sub-scan signal sp1, and a second sub-scan signal sp2; in the second mode, the shift register unit VSR outputs a low-level constant voltage signal, the first sub-scan signal sp1, and the second sub-scan signal sp2. Using the shift register unit provided in the embodiments of the present invention, partitioned refresh display of the display panel can be achieved. Taking the example that the shift register in the display panel includes N levels of shift register units, where N is an integer. The display panel includes a first refresh frame. In the first refresh frame: the j-th to q-th shift register units receive the first-level signal of the refresh control signal, and the j-th to q-th shift register units are in the first mode; j and q are integers, 1 ≤ j < q < N; the (q + 1)-th to w-th shift register units receive the second-level signal of the refresh control signal, and the (q + 1)-th to w-th shift register units are in the second mode; w is an integer, q + 1 < w ≤ N. For example, when the first scan signal sn output by the shift register unit is used to drive the threshold compensation transistor, the shift register unit VSR can write the data voltage to the gate of the driving transistor when it works in the first mode, and the shift register unit VSR cannot write the data voltage to the gate of the driving transistor when it works in the second mode. Taking j = 1 and w = N as an example. By setting the refresh control signal, the 1st to q-th shift register units VSR among the cascaded N shift register units VSR work in the second mode, and the (q + 1)-th to N-th shift register units work in the first mode. In this way, in one frame, no data voltage is written and the image is not refreshed in the upper display area of the display panel, while data voltage is written and the image is refreshed in the lower display area, and the display panel realizes partitioned refreshing.

[0064] The following describes an implementation manner in which the shift register unit has two working modes.

[0065] Figure 18 Another schematic diagram of the shift register unit provided by the embodiment of the present invention. As Figure 18 shown, the control module 00 is configured to output a control signal based on the first input signal IN-1, the first clock signal CK1, the first voltage signal VGL, and the second voltage signal VGH; the control module 00 includes a first input module 02 and a first inverter 1. The input end of the first input module 02 receives the first input signal IN-1, and the output end of the first input module 02 is connected to the input end of the first inverter 1; the first inverter 1 is a CMOS inverter, its ground terminal receives the first voltage signal VGL, and its power supply terminal receives the second voltage signal VGH. Among them, the first output module 10 and the second output module 20 are respectively connected to the first inverter 1. In the embodiment of the present invention, being connected to the input end of the first inverter 1 or being connected to the output end of the first inverter 1 can both be referred to as being connected to the first inverter 1, or being indirectly connected to the first inverter 1 through other structures can also be referred to as being connected to the first inverter 1. Figure 18As illustrated, the first output module 10 is connected to the output terminal of the first inverter 1, and the second output module 20 is connected to both the input terminal and the output terminal of the first inverter 1. Other connection relationships between the first output module 10, the second output module 20, and the first inverter 1 will also be discussed in the following embodiments, and will be explained when relevant features are involved.

[0066] In this embodiment of the invention, the control module 00 includes an input module 02 and a first inverter 1. The first inverter 1 can invert the phase of the input signal and output it. When the input terminal of the first inverter 1 receives a high-level signal, its output terminal outputs a low-level signal; when the input terminal of the first inverter 1 receives a low-level signal, its output terminal outputs a high-level signal. Connecting the input and output terminals of the first inverter 1 within the same time period can yield two signals with opposite phases. A first output module 10 and a second output module 20 are respectively connected to the first inverter 1. The connection between the first output module 10 and the second output module 20 can be configured to either connect to the input terminal or the output terminal of the first inverter 1, depending on their respective structures. This allows the first output module 10 to output a first scan signal sn with a high level as an enable level, and the second output module 20 to output a second scan signal sp with a low level as an enable level.

[0067] Figure 18 The diagram illustrates one possible structure for the control module 00. For example... Figure 18 As shown, the control module includes a first input module 02 and a first inverter 1. The first input module 02 includes a first sub-module 2 and a second inverter 3. The first sub-module 2 receives a first input signal IN-1. The output terminal of the first sub-module 2 and the input terminal of the second inverter 3 are connected to a first node N1. The output terminal of the second inverter 3 and the input terminal of the first inverter 1 are connected to a second node N2. The output terminal of the first inverter 1 is connected to the input terminal of the second inverter 3. The first inverter 1 and the second inverter 3 form a latch structure, which can stabilize the potential of the first node N1, thereby ensuring the stability of the output signal of the control module 00.

[0068] In this embodiment of the invention, the control module 00 can also be of other structures. Figure 19 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 19As shown, the control module 00 includes a first input module 02 and a first inverter 1. The input terminal of the first input module 02 receives a first input signal IN-1, and the output terminal of the first input module 02 is connected to the input terminal of the first inverter 1. The first input module 02 includes a first sub-module 2, a second inverter 3, and a first capacitor C1. The first sub-module 2 receives the first input signal IN-1, and the input terminals of the first sub-module 2 and the second inverter 3 are connected to a first node N1. The output terminal of the second inverter 3 is connected to the input terminal of the first inverter 1 at a second node N2. One plate of the first capacitor C1 is connected to the input terminal of the second inverter 3, and the other plate receives a first voltage signal VGL. The first output module 10 is connected to the output terminal of the first inverter 1, and the second output module 20 is connected to the input terminal of the first inverter 1. The second output module 20 also receives a second input signal IN-2. In this embodiment, the first capacitor C1 is used to stabilize the potential of the first node N1, ensuring the stability of the output signal of the control module 00.

[0069] like Figure 18 or Figure 19 As shown, the first submodule 2 includes a first transistor M1, which is a p-type transistor. The control terminal of the first transistor M1 receives a first clock signal CK1, the first terminal receives a first input signal IN-1, and the second terminal is connected to the input terminal of the second inverter 3.

[0070] The second inverter 2 includes a second transistor M2 and a third transistor M3. The second transistor M2 is a p-type transistor, and the third transistor M3 is an n-type transistor. The control terminals of the second transistor M2 and the third transistor M3 are the input terminals of the second inverter 2. The first terminal of the third transistor M3 receives a first voltage signal VGL, and the first terminal of the second transistor M2 receives a second voltage signal VGH. The second terminals of the second transistor M2 and the second terminals of the third transistor M3 are the output terminals of the second inverter 2.

[0071] The first inverter 1 includes a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 is a p-type transistor, and the fifth transistor M5 is an n-type transistor. The control terminals of the fourth transistor M4 and the fifth transistor M5 are the input terminals of the first inverter 1. The first terminal of the fifth transistor M5 receives a first voltage signal VGL, and the first terminal of the fourth transistor M4 receives a second voltage signal VGH. The second terminals of the fourth transistor M4 and the fifth transistor M5 are the output terminals of the first inverter 1.

[0072] like Figure 18As shown, the control module 00 also includes a reset submodule 01. The reset submodule 01 is configured to write the second voltage signal VGH to the first node N1 under the control of the reset control signal RST, thereby resetting the first node N1. Specifically, the reset submodule 01 includes a thirteenth transistor M13. Optionally, the thirteenth transistor M13 is a p-type transistor, whose control terminal receives the reset control signal RST, its first terminal receives the second voltage signal VGH, and its second terminal is connected to the first node N1.

[0073] In this embodiment of the invention, the first output module 10 and the second output module 20 are respectively connected to the first inverter 1 in the control module 00. The connection methods between the two output modules and the first inverter 1 include various cases. Examples are as follows: In some implementations, such as Figure 18 As shown, at least one control terminal of the first output module 10 is connected to the output terminal of the first inverter 1; at least one control terminal of the second output module 20 is connected to the input terminal of the first inverter 1; and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. This embodiment utilizes the signal from the output terminal of the first inverter 1 to control the first output module 10 to output a first scan signal sn, and utilizes the signal from the output terminal of the first inverter 1 and the signal from the input terminal of the first inverter 1 to control the second output module 20 to output a second scan signal sp.

[0074] In some implementations, such as Figure 19 As shown, at least one control terminal of the first output module 10 is connected to the output terminal of the first inverter 1; at least one control terminal of the second output module 20 is connected to the input terminal of the first inverter 1, and at least one input terminal of the second output module 20 receives the second input signal IN-2. This embodiment utilizes the signal from the output terminal of the first inverter 1 to control the first output module 10 to output a first scan signal sn, and utilizes the signal from the input terminal of the first inverter 1 and the second input signal IN-2 to control the second output module 20 to output a second scan signal sp.

[0075] In some implementations... Figure 20 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 20 As shown, at least one control terminal of the first output module 10 is connected to the output terminal of the first inverter 1; at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1; and at least one input terminal of the second output module 20 is connected to the input terminal of the first inverter 1. This embodiment utilizes the signal from the output terminal of the first inverter 1 to control the first output module 10 to output a first scan signal sn, and utilizes the signals from the input terminal and the output terminal of the first inverter 1 to control the second output module 20 to output a second scan signal sp.

[0076] In some implementations... Figure 21 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 21 As shown, at least one control terminal of the first output module 10 is connected to the output terminal of the first inverter 1; at least one control terminal of the second output module 20 is connected to the output terminal of the first inverter 1; and at least one input terminal of the second output module 20 receives the second input signal IN-2. This embodiment utilizes the signal from the output terminal of the first inverter 1 to control the first output module 10 to output a first scan signal sn, and utilizes the signal from the output terminal of the first inverter 1 and the second input signal IN-2 to control the second output module 20 to output a second scan signal sp.

[0077] In other implementations, Figure 22 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 23 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 22 and Figure 23 As shown, the control module 00 also includes a third inverter 4, the input of which is connected to the output of the first inverter 1. At least one control terminal of the first output module 10 is connected to the output of the third inverter 4, i.e., connected to the output of the first inverter 1 via the third inverter 4. At least one control terminal of the second output module 20 is connected to the output of the third inverter 4, and at least one input terminal of the second output module 20 is connected to the output of the first inverter 1. The third inverter 4 is a CMOS inverter. In this embodiment, the signal from the output of the third inverter 4 is used to control the first output module 10 to output a first scan signal sn, and the signals from the outputs of the third inverter 4 and the first inverter 1 are used to control the second output module 20 to output a second scan signal sp.

[0078] Figure 22 In this embodiment, a third inverter 4 is added to the control module 00, and the first output module 10 is connected to the output terminal of the third inverter 4. In the application, the pulse level of the first input signal IN-1 is low, so the first node N1, where the first submodule 2 and the second inverter 3 are connected, is low most of the time. This mitigates the impact on power consumption caused by the third transistor M3 in the second inverter 3 failing to turn off when the first node N1 is high most of the time, which would lead to a short circuit at the high / low voltage receiving end of the second inverter 3. In this embodiment, the signal at the output terminal of the first inverter 1 can be used as the cascading signal next. During cascading, the output terminal of the first inverter 1 is connected to the input terminal of the first submodule 2 in the next stage shift register unit.

[0079] Figure 22 and Figure 23The difference between them is that, Figure 22 A first capacitor C1 is provided, with one plate of the first capacitor C1 connected to the first node N1 and the other plate receiving the first voltage signal VGL. Figure 23 Without setting the first capacitor C1, the first node N1 is connected to the output terminal of the first inverter 1, so that the first inverter 1 and the second inverter 3 form a latch structure. Figure 23 In the embodiment, the pulse level of the first input signal IN-1 is low. When cascaded, the input terminal of the first submodule 2 in the shift register unit receives a second scan signal output by the previous shift register unit.

[0080] Front Figure 18 and Figure 19 The embodiments illustrate the optional structures of the control module 00. The optional structures of the second output module 20 in the embodiments of the present invention are illustrated below.

[0081] In some embodiments of the present invention, the second output module 20 is configured to output a second scan signal sp based on a first voltage signal VGL, a second voltage signal VGH, at least one clock signal, and a control signal output by the control module 00. For example... Figure 18 and Figure 20 In this embodiment, the control signal received by the second output module 20 from the control module 00 includes the signal from the output terminal of the first inverter 1 and the signal from the input terminal of the first inverter 1. For example... Figure 22 and Figure 23 In this embodiment, the control signal received by the second output module 20 from the control module 00 includes the signal from the output terminal of the first inverter 1 and the signal from the output terminal of the third inverter 4.

[0082] In some embodiments of the present invention, the second output module 20 is configured to output a second scan signal sp based on a first voltage signal VGL, a second voltage signal VGH, at least one clock signal, and a control signal output by the control module 00 and a second input signal IN-2. For example... Figure 19 In this embodiment, the control signal received by the second output module 20 from the control module 00 includes the signal from the input terminal of the first inverter 1. For example... Figure 21 In this embodiment, the control signal received by the second output module 20 from the control module 00 includes the signal from the output terminal of the first inverter 1.

[0083] In other embodiments of the present invention, the second output module 20 is configured to output a second scan signal sp based on a first voltage signal VGL, a second voltage signal VGH, at least one clock signal, and a control signal output by the control module 00 and a signal output by the first output module 10, or the output signal of the first output module 10 and the second input signal IN-2. See above. Figure 6 , Figure 7 , Figure 12 and Figure 13 Related descriptions in the examples.

[0084] In this embodiment of the invention, the second output module 20 includes at least one sub-module. The sub-module is configured to operate based at least on a first voltage signal VGL, a second voltage signal VGH, and at least on a control signal output by the control module 00 and a signal output by the first output module 10 (such as...). Figure 6 (Example), or the output signal of the first output module 10 and the second input signal IN-2 (such as...) Figure 7 (Example), or control signals output by control module 00 (such as...) Figure 12 , Figure 18 , Figure 20 , Figure 22 , Figure 23 (Example), or the control signal output by the control module 00 and the second input signal IN-2 (such as...) Figure 13 , Figure 19 , Figure 21 (Example), outputs at least one second scan signal sp.

[0085] Taking the second output module 20, which includes submodules 21 and 22, as an example, in this embodiment of the invention, at least one control terminal of submodule 21 and at least one control terminal of submodule 22 are connected to control module 00 or first output module 10; at least one input terminal of submodule 21 and at least one input terminal of submodule 22 are connected to control module 00 or to first output module 10, or receive the second input signal IN-2. Figure 6 In this embodiment, at least one control terminal of submodule 21 and at least one control terminal of submodule 22 are connected to control module 00 (specifically connected to the output terminal of the second inverter 3), and at least one input terminal of submodule 21 and at least one input terminal of submodule 22 are connected to the first output module 10 (specifically connected to...). Figure 6 (The output of the first inverter 1). Figure 18 In this embodiment, at least one control terminal of submodule 21 and at least one control terminal of submodule 22 are connected to control module 00 (specifically connected to the input terminal of the first inverter 1), and at least one input terminal of submodule 21 and at least one input terminal of submodule 22 are connected to control module 00 (specifically connected to the output terminal of the first inverter 1). Figure 19In this embodiment, at least one control terminal of submodule 21 and at least one control terminal of submodule 22 are connected to control module 00 (specifically, connected to the input terminal of the first inverter 1), and at least one input terminal of submodule 21 and at least one input terminal of submodule 22 receive the second input signal IN-2. The connection relationships between submodules 21 and 22 and control module 00 and / or the first output module 10 in other embodiments can be understood by reference and will not be elaborated further here.

[0086] by Figure 18 For example, in the implementation example, Figure 18 As shown, submodules 21 and 22 in the second output module 20 respectively include a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. The control terminal of the ninth transistor M9 receives a first voltage signal VGL. The first terminal of the ninth transistor M9 is connected to the output terminal of the first inverter 1 in the control module 00. The second terminal of the ninth transistor M9 is connected to the control terminal of the tenth transistor M10. The first terminal of the tenth transistor M10 receives a second clock signal CK2. The control terminal of the eleventh transistor M11 is connected to the input terminal of the first inverter 1 in the control module 00. The first terminal of the eleventh transistor M11 receives a second voltage signal VGH. In submodule 21, the output terminals of the tenth transistor M10 and the eleventh transistor M11 are connected to the output terminal of submodule 21. In submodule 22, the output terminals of the tenth transistor M10 and the eleventh transistor M11 are connected to the output terminal of submodule 22.

[0087] In addition, submodules 21 and 22 each include a third capacitor C3. In submodule 21, the ninth transistor M9 and the tenth transistor M10 are connected to the third node N3, and one plate of the third capacitor C3 is connected to the third node N3, while the other plate is connected to the output terminal of submodule 21. In submodule 22, the ninth transistor M9 and the tenth transistor M10 are connected to the fourth node N4, and one plate of the third capacitor C3 is connected to the fourth node N4, while the other plate is connected to the output terminal of submodule 22.

[0088] In some implementations, such as Figure 19As shown, one input terminal of submodule 21 and one input terminal of submodule 22 respectively receive the second input signal IN-2 through the second input module 23. The second input module 23 is configured to write the second input signal IN-2 to one input terminal of submodule 21 and one input terminal of submodule 22 respectively based on the control of the first clock signal CK1. In this embodiment, the operation of the shift register unit requires the first input signal IN-1 and the second input signal IN-2. The second output signal IN-2 participates in controlling the second output module 20 to output the second scan signal sp1 and the third scan signal sp2, so that the output signal of the second output module 20 is not affected by the number of pulses of the first input signal IN-1. When the first input signal IN-1 is multi-pulse, it can make the first scan signal sn output by the first output module 10 multi-pulse, without affecting the output of the second output module 20. The operation mode of the second input module 23 and the scheme of the first scan signal sn being multi-pulse will be explained in the following related embodiments.

[0089] Specifically, such as Figure 19 As shown, the second input module 23 includes a twelfth transistor M12. The control terminal of the twelfth transistor M12 receives the first clock signal CK1, the input terminal of the twelfth transistor M12 receives the second input signal IN-2, and the output terminal of the twelfth transistor M12 is connected to sub-module 21 and sub-module 22 respectively.

[0090] The above-described embodiments have provided examples illustrating the structure of the control module 00 and the structure of the second output module 20. The following describes the function and structure of the first output module 10 in this embodiment, and further explains the operation of the shift register unit VSR in conjunction with specific embodiments.

[0091] In some implementations, one port of the first output module 10 receives a refresh control signal CTRL. In a specific embodiment, the port of the first output module 10 receiving the refresh control signal CTRL can be a control terminal, such as the gate of a transistor, or an input terminal, such as the source or drain of a transistor. The first output module 10 is configured to output a first scan signal sn based at least on the control signal output by the control module 00 and a first-level signal of the refresh control signal CTRL, and to output a low-level constant voltage signal based at least on the control signal output by the control module 00 and a second-level signal of the refresh control signal CTRL; one of the first-level signal and the second-level signal is a high-level signal, and the other is a low-level signal. In this implementation, the first output module 10 can output a low-level constant voltage signal or output the first scan signal sn depending on the level of the refresh control signal CTRL. In applications, by setting the refresh control signal CTRL, the shift register unit can have two operating modes. In the first mode, the first output module 10 outputs the first scan signal sn, and the second output module 20 outputs the second scan signal sp; in the second mode, the first output module 10 outputs the low-level constant voltage signal, and the second output module 20 outputs the second scan signal sp. For example, during a single frame display on the display panel, the first to kth levels of the cascaded N shift register units (VSRs) are configured to operate in the second mode, while the (k+1)th to Nth levels operate in the first mode. N and k are both positive integers, with k less than N. This way, the upper display area of ​​the panel does not receive data voltage and is not refreshed, while the lower display area can receive data voltage and be refreshed, thus achieving partitioned refresh of the display panel.

[0092] In some implementations, such as Figure 18 and Figure 19 As shown, the first output module 10 includes a sixth transistor M6 and a seventh transistor M7. The sixth transistor M6 is a p-type transistor, and the seventh transistor M7 is an n-type transistor. The control terminals of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the output terminals of the first inverter 1. The first terminal of the sixth transistor M6 receives the refresh control signal CTRL, and the first terminal of the seventh transistor M7 receives the first voltage signal VGL. The second terminals of the sixth transistor M6 and the second terminal of the seventh transistor M7 are respectively connected to the output terminals of the first output module 10. The first level signal of the refresh control signal CTRL is a high-level signal, and the second level signal is a low-level signal. That is, when the refresh control signal CTRL is high, the shift register unit operates in the first mode; when the refresh control signal CTRL is low, the shift register unit operates in the second mode.

[0093] In addition, Figure 18 and Figure 19In this embodiment, the seventh transistor M7, being a transistor directly connected to the output terminal of the first output module 10, can have its first voltage signal VGL received by a separate signal line. That is, both the first terminal of the seventh transistor M7 and the first terminal of a transistor such as the fifth transistor M5 receive the first voltage signal VGL, but these two transistors are connected to different signal lines. This arrangement ensures the signal output performance of the first output module 10.

[0094] This invention also provides another driving method for a display panel, which can be used to drive a display panel including... Figure 18 In this embodiment, the display panel of the shift register unit is driven. The driving method includes: providing a first input signal IN-1, a first clock signal CK1, a first voltage signal VGL, and a second voltage signal VGH to the control module 00, and controlling the control module 00 to output a control signal; during the period when the pulse of the first input signal IN-1 and the first low level of the first clock signal CK1 overlap, controlling the first output module 10 to start outputting a high-level signal of the first scan signal sn based at least on the control signal output by the control module 00, and during the period when the non-pulse of the first input signal IN-1 and the second low level of the first clock signal CK1 overlap, controlling the first output module 10 to end outputting the high-level signal of the first scan signal sn based at least on the control signal output by the control module 00, where the second low level is the s-th pulse signal after the first low level, and s is a positive integer. During the period when the first clock signal CK1 provides the first low level and the second low level, controlling the second output module 20 to output at least a low-level signal of the second scan signal sp based at least on the control signal output by the control module 00 and / or the signal output by the first output module 10.

[0095] Furthermore, in the driving method provided in this embodiment of the invention, during the period when the first clock signal CK1 provides a first low level (the first low level overlapping with the high-level pulse of the first input signal IN-1) and a second low level, the second output module 20 is controlled to output at least one low-level signal of a second scan signal sp based on at least one clock signal. The low-level period of the clock signal received by the second output module 20 corresponds to the low-level period of the second scan signal sp. Taking the second output module 20 outputting two second scan signals sp as an example, at least two clock signals need to be input to control the second output module 20.

[0096] Furthermore, in this embodiment of the invention, controlling the first output module 10 to output a first scan signal sn based at least on the control signal output by the control module 00 includes: controlling the first output module 10 to output the first scan signal sn based at least on a first-level signal of the refresh control signal CTRL and the control signal output by the control module 00; the driving method further includes: controlling the first output module 10 to output a low-level constant voltage signal based at least on a second-level signal of the refresh control signal CTRL and the control signal output by the control module 00; one of the first-level signal and the second-level signal is a high-level signal and the other is a low-level signal. The driving method provided by this embodiment of the invention enables the shift register unit to have two operating modes, thereby realizing the partitioned refresh function of the display panel. The driving method provided by this embodiment is applicable to embodiments where the first output module 10 receives the refresh control signal CTRL. The driving method can be understood in conjunction with the following timing diagram.

[0097] Figure 24 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 24 The provided timing diagrams can be applied to Figure 18 The provided shift register unit. Figure 24 In the timing sequence, the refresh control signal CTRL is a high-level signal, and the pulse level of the first input signal IN-1 is a low-level signal. Combined with... Figure 18 and Figure 24 The working process of the shift register unit is as follows: During time period t31, the first clock signal CK1 is low, controlling the first transistor M1 in the first submodule 2 to turn on, writing the low level of the first input signal IN-1 to the first node N1, making the first node N1 a low potential. The input of the second inverter 3, composed of the second transistor M2 and the third transistor M3, receives a low-level signal, and its output outputs a high-level signal, making the second node N2 a high potential. The first inverter 1, composed of the fourth transistor M4 and the fifth transistor M5, receives a high-level signal at input and outputs a low-level signal, so the control terminal of the first output module 10 receives a low-level signal. The low-level signal controls the sixth transistor M6 to turn on, providing the high level of the refresh control signal CTRL to the output terminal of the first output module 10. During this time period, the output terminal of the first output module 10 outputs the high level of the first scan signal sn. Furthermore, when the input of the first inverter 1 is high and the output is low, the high level at the input of the first inverter 1 turns off the eleventh transistor M11 in submodules 21 and 22. The low level at the output of the first inverter 1 is written to the third node N3 and the fourth node N4 through the ninth transistor M9 in submodules 21 and 22, respectively, and the tenth transistor M10 in submodules 21 and 22 turns on. When the tenth transistor M10 in submodule 21 turns on, it provides the high level of the second clock signal CK2 to the output of submodule 21, and submodule 21 outputs the high level signal of the first sub-scan signal sp1. When the tenth transistor M10 in submodule 22 turns on, it provides the high level of the third clock signal CK3 to the output of submodule 22, and submodule 22 outputs the high level signal of the second sub-scan signal sp2.

[0098] During time period t32, when the first clock signal CK1 is high, the first transistor M1 is off, the first node N1 remains low, the second node N2 remains high, the input of the first inverter 1 is high, and the output is low. The output of the first output module 10 outputs a high-level signal for the first scan signal sn. In the second submodule 21, the eleventh transistor M11 is off, and the third node N3 remains low, controlling the tenth transistor 10 to turn on, providing the low level of the second clock signal CK2 to the output of the second submodule 21. The second submodule 21 outputs a low-level signal for the second scan signal sp1. In the third submodule 22, the eleventh transistor M11 is off, the fourth node N4 remains low, controlling the tenth transistor 10 to turn on, the third clock signal CK3 is high, and the third submodule 22 outputs a high-level signal for the third scan signal sp2.

[0099] During time period t33, when the first clock signal CK1 is high, the first transistor M1 is off, the first node N1 remains low, the second node N2 remains high, the input of the first inverter 1 is high, and the output is low. The output of the first output module 10 outputs a high-level signal for the first scan signal sn. In the second submodule 21, the eleventh transistor M11 is off, the third node N3 remains low to control the tenth transistor 10 to turn on, the second clock signal CK2 is high, and the second submodule 21 outputs a high-level signal for the second scan signal sp1. In the third submodule 22, the eleventh transistor M11 is off, the fourth node N4 remains low to control the tenth transistor 10 to turn on, the third clock signal CK3 is low, and the third submodule 22 outputs a low-level signal for the third scan signal sp2.

[0100] During time period t34, the first clock signal CK1 is low, controlling the first transistor M1 to turn on. The first node N1 receives a high-level signal from the first input signal IN-1, making node N1 high. The second node N2 is low, and the input of the first inverter 1 is low while its output is high. The high-level signal at the output of the first inverter 1 controls the sixth transistor M6 in the first output module 10 to turn off and the seventh transistor M7 to turn on. The seventh transistor M7 provides a low-level signal of the first voltage signal VGL to the output of the first output module 10, resulting in the first output module 10 outputting a low-level signal of the first scan signal sn. The high-level signal at the second node N2 controls the eleventh transistor M11 in the second submodule 21 and the third submodule 22 to turn on. The high potential at the output of the first inverter 1 causes the third node N3 in the second submodule 21 to be high, controlling the tenth transistor M10 to turn off, and the fourth node N4 in the third submodule 22 to be high, controlling the tenth transistor M10 to turn off. In the second submodule 21, the eleventh transistor M11 is turned on, providing a high-level signal of the second voltage signal VGH to the output terminal of the second submodule 21, and the second submodule 21 outputs a high-level signal of the second scan signal sp1. In the third submodule 22, the eleventh transistor M11 is turned on, providing a high-level signal of the second voltage signal VGH to the output terminal of the third submodule 22, and the third submodule 22 outputs a high-level signal of the third scan signal sp2.

[0101] use Figure 24 When driven by the provided timing, the shift register unit outputs the first scan signal sn, the second scan signal sp1, and the third scan signal sp2.

[0102] Figure 25 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 25 The provided timing diagrams can be applied to Figure 18 The provided shift register unit. Figure 25In the timing sequence, the refresh control signal CTRL is a low-level signal, and the pulse level of the first input signal IN-1 is also low. Combined with... Figure 18 and Figure 25 The working process of the shift register unit is as follows: During time period t31, the first clock signal CK1 is low, controlling the first transistor M1 in the first submodule 2 to turn on, writing the low level of the first input signal IN-1 to the first node N1, making the first node N1 a low potential. The input of the second inverter 3, composed of the second transistor M2 and the third transistor M3, receives a low-level signal and outputs a high-level signal, making the second node N2 a high potential. The first inverter 1, composed of the fourth transistor M4 and the fifth transistor M5, receives a high-level signal and outputs a low-level signal. The control terminal of the first output module 10 receives a low-level signal and controls the sixth transistor M6 to turn on and the seventh transistor M7 to turn off. The sixth transistor M6, when turned on, provides the low level of the refresh control signal CTRL to the output terminal of the first output module 10, causing the first output module 10 to output a low-level signal. Additionally, during this period, the high level at the input of the first inverter 1 turns off the eleventh transistor M11 in the second submodule 21 and the third submodule 22. The low level at the output of the first inverter 1 is written to the third node N3 and the fourth node N4 through the ninth transistor M9 in the second submodule 21 and the third submodule 22, respectively. The tenth transistor M10 in the second submodule 21 and the third submodule 22 turns on. The second submodule 21 outputs a high-level signal for the second scan signal sp1, and the third submodule 22 outputs a high-level signal for the third scan signal sp2.

[0103] During time period t32, the first clock signal CK1 is high, so the first transistor M1 is off, the first node N1 remains low, the second node N2 remains high, the input of the first inverter 1 is high, and the output is low. In the first output module 10, the sixth transistor M6 is on, and the refresh control signal CTRL is low, causing the output of the first output module 10 to output a low-level signal. In submodule 21, the eleventh transistor M11 is off, and the third node N3 remains low, controlling the tenth transistor 10 to turn on, providing the low level of the second clock signal CK2 to the output of submodule 21. Submodule 21 outputs the low-level signal of the first sub-scan signal sp1. In submodule 22, the eleventh transistor M11 is off, the fourth node N4 remains low, controlling the tenth transistor 10 to turn on, and the third clock signal CK3 is high, causing submodule 22 to output the high-level signal of the second sub-scan signal sp2.

[0104] During time period t33, when the first clock signal CK1 is high, the first transistor M1 is off, the first node N1 remains low, the second node N2 remains high, the input of the first inverter 1 is high, and the output is low. The output of the first output module 10 continues to output a low-level signal. In submodule 21, the third node N3 remains low, controlling the tenth transistor 10 to turn on, the second clock signal CK2 is high, and submodule 21 outputs a high-level signal for the first sub-scan signal sp1. In submodule 22, the fourth node N4 remains low, controlling the tenth transistor 10 to turn on, the third clock signal CK3 is low, and submodule 22 outputs a low-level signal for the second sub-scan signal sp2.

[0105] During time period t34, the first clock signal CK1 is low, controlling the first transistor M1 to turn on. The first node N1 receives a high-level signal from the first input signal IN-1, making node N1 high. The second node N2 is low, and the input of the first inverter 1 is low while its output is high. In the first output module 10, the sixth transistor M6 is off and the seventh transistor M7 is on. The seventh transistor M7 provides a low-level signal from the first voltage signal VGL to the output of the first output module 10, resulting in a low-level output signal. During this time period, the operating states of sub-modules 21 and 22 are the same as in time period t31. Sub-module 21 outputs a high-level signal from the first sub-scan signal sp1, and sub-module 22 outputs a high-level signal from the second sub-scan signal sp2.

[0106] use Figure 25 When driven by the provided timing, the shift register unit outputs a low-level constant voltage signal, the first sub-scan signal sp1, and the second sub-scan signal sp2.

[0107] Figure 18 The shift register unit provided in the embodiment adopts the above-described... Figure 24 When driven by the signal timing, it operates in the first mode, and when using the above... Figure 25 When driven by the signal timing, the system operates in the second mode. Specifically, when the refresh control signal CTRL is high, the first output module 10 outputs the first scan signal sn, the shift register unit operates in the first mode, and the shift register unit outputs the first scan signal sn and the second scan signal sp. When the refresh control signal CTRL is low, the first output module 10 outputs a low-level constant voltage signal, the shift register unit operates in the second mode, and the shift register unit outputs a low-level constant voltage signal and the second scan signal sp.

[0108] Figure 18In this embodiment, the input module 02 in the control module 00 includes a first submodule 2 and a second inverter 3. The first submodule 2 receives a first input signal IN-1. The output of the first submodule 2 and the input of the second inverter 3 are connected to a first node N1. The output of the second inverter 3 and the input of the first inverter 1 are connected to a second node N2. The output of the first inverter 1 is connected to the input of the second inverter 3. The first inverter 1 and the second inverter 3 constitute a latch structure. The first output module 10 is connected to the output of the first inverter 1, and the second output module 20 is connected to both the output and input of the first inverter 1. In application, the shift register units can be cascaded in the following manner.

[0109] Figure 26 This is a schematic diagram of another cascaded shift register unit provided for the implementation of the present invention. Figure 26 The middle indicates Figure 18 The cascading method of intermediate shift register units. Combined with... Figure 24 and Figure 25 As can be seen, the pulse level of the first input signal IN-1 required by the shift register unit during operation is low, and the low-level start time of the second sub-scan signal sp2 in the second scan signal sp is later than the low-level start time of the first sub-scan signal sp1. Figure 26 The diagram illustrates two cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1) and the ith stage shift register unit VSR(i). The first submodule 2 in the ith stage shift register unit VSR(i) (see...) Figure 18 The input terminal of the current stage shift register (shown in the diagram) receives the second sub-scan signal sp2 output by the (i-1)th stage shift register unit VSR(i-1), where i is an integer, i≥2. That is, the first input signal IN-1 received by the current stage shift register unit is the second sub-scan signal sp2 output by the previous stage shift register unit.

[0110] In the Figure 26When driving multiple cascaded shift register units, the display panel needs to be equipped with four clock signal lines and two refresh control lines. The clock signal lines are designated as the first clock signal line K1, the second clock signal line K2, the third clock signal line K3, and the fourth clock signal line K4, and the clock signals provided by the four clock signal lines have the same period. The two refresh control lines are designated as the first refresh control line CTRL1 and the second refresh control line CTRL2. Taking i as an even number, i-1 is an odd number. For the odd-numbered shift register unit, the first clock signal line K1 provides it with the first clock signal CK1, the second clock signal line K2 provides it with the second clock signal CK2, and the third clock signal line K3 provides it with the third clock signal CK1. For the even-numbered shift register unit, the third clock signal line K3 provides it with the first clock signal CK1, the fourth clock signal line K4 provides it with the second clock signal CK2, and the first clock signal line K1 provides it with the third clock signal CK1. In the odd-numbered shift register unit, the first output module 10 is connected to the first refresh control line CTRL1, and in the even-numbered shift register unit, the first output module 10 is connected to the second refresh control line CTRL2.

[0111] Taking the first refresh frame of the display panel, where the upper half of the display area refreshes image data while the lower half does not, as an example, driving multiple shift register units in the upper half of the display area is the first mode, and driving multiple shift register units in the lower half of the display area is the second mode. Combined with... Figure 24 and Figure 25 According to the timing diagram, the shift register unit operates in the first mode when the refresh control signal CTRL is high, and in the second mode when the refresh control signal CTRL is low. It can be understood that by controlling the first refresh control line CTRL1 and the second refresh control line CTRL2 to start as high-level signals and then transition to low-level signals at a certain time, the first refresh frame of the display panel can be achieved.

[0112] exist Figure 19 In this embodiment, the shift register unit further includes a second input module 23, which receives a second input signal IN-2, and the second output module 20 is connected to the control module 00. The driving method provided in this embodiment includes controlling the second output module 20 to output at least one low-level signal of a second scan signal based on the second input signal IN-2 and a control signal output by the control module 00. Specifically, during the period when the first clock signal CK1 provides a first low level (i.e., the first low-level period where the pulses of the first clock signal CK1 and the first input signal IN-1 overlap), the second input signal IN-2 is written to the second output module 20. This driving method is applicable to embodiments of the present invention that include the second input module 23.

[0113] Embodiments of the present invention also provide a method for driving Figure 19 Signal timing of the intermediate shift register unit Figure 27 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 27 In the timing sequence, the refresh control signal CTRL is a high-level signal, the pulse level of the first input signal IN-1 is low, and the pulse level of the second input signal IN-2 is low. The first input signal IN-1 consists of two pulses. (Combined with...) Figure 19 and Figure 27 The working process of the shift register unit is as follows: During time period t41, the first clock signal CK1 is low, controlling the first transistor M1 to turn on and write the low level of the first input signal IN-1 to the first node N1, making the first node N1 a low potential. The low potential of the first node N1 controls the second transistor M2 to turn on and write the high level of the second voltage signal VGH to the second node N2, making the second node N2 a high potential. The high potential of the second node N2 controls the fifth transistor M5 to turn on and provide the low level signal of the first voltage signal VGL to the output of the control module 00. The control terminal of the first output module 10 receives the low level signal, which controls the sixth transistor M6 to turn on and provide the high level of the refresh control signal CTRL to the output of the first output module 10. During this time period, the output of the first output module 10 outputs the high level of the first scan signal sn. In addition, the high level signal of the second node N2 controls the eleventh transistor M11 in the second sub-module 21 and the third sub-module 22 to turn off. The low level of the first clock signal CK1 controls the twelfth transistor M12 to turn on and write the low level of the second input signal IN-2 to the fifth node N5, making the fifth node N5 a low potential. The low-level signal of the fifth node N5 is written to the third node N3 and the fourth node N4 through the ninth transistor M9 in submodules 21 and 22, respectively. The third node N3 and the fourth node N4 are at low potentials, respectively controlling the tenth transistor M10 in submodules 21 and 22 to turn on. In submodule 21, the high level of the second clock signal CK2 is provided to the output terminal of submodule 21 through the tenth transistor M10, and submodule 21 outputs the high-level signal of the first sub-scan signal sp1. In submodule 22, the high level of the third clock signal CK3 is provided to the output terminal of submodule 22 through the tenth transistor M10, and submodule 22 outputs the high-level signal of the second sub-scan signal sp2.

[0114] During time period t42, when the first clock signal CK1 is high, the first transistor M1 is off, the first node N1 remains low, the second node N2 remains high, the output of control module 00 is low, and the output of the first output module 10 continues to output the high-level signal of the first scan signal sn. The twelfth transistor M12 is off, the third node N3 and the fourth node N4 remain low, and the tenth transistor 10 in submodule 21 is on, providing the low level of the second clock signal CK2 to the output of submodule 21. Submodule 21 outputs the low-level signal of the first sub-scan signal sp1. In submodule 22, the tenth transistor 10 is on, and the third clock signal CK3 is high, so submodule 22 outputs the high-level signal of the second sub-scan signal sp2.

[0115] During time period t43, the first clock signal CK1 is high, controlling the first transistor M1 to turn off. The first node N1 remains low, the second node N2 remains high, the output of control module 00 is low, and the output of the first output module 10 continues to output the high-level signal of the first scan signal sn. The twelfth transistor M12 is off, the third node N3 and the fourth node N4 remain low. In submodule 21, the tenth transistor 10 is on, the second clock signal CK2 is high, and submodule 21 outputs the high-level signal of the first sub-scan signal sp1. In submodule 22, the tenth transistor 10 is on, the clock signal CK3 is low, and submodule 22 outputs the low-level signal of the second sub-scan signal sp2.

[0116] During time period t44, the first clock signal CK1 is low, controlling the first transistor M1 to turn on. The first node N1 receives a high-level signal from the first input signal IN-1, making node N1 a high potential. The second node N2 is low, and the output of control module 00 is high. In the first output module 10, the sixth transistor M6 is off, and the seventh transistor M7 is on. The seventh transistor M7 provides a low-level signal from the first voltage signal VGL to the output of the first output module 10, resulting in the first output module 10 outputting a low-level signal from the first scan signal sn. During this period, the first clock signal CK1 controls the twelfth transistor M12 to turn on, writing the high level of the second input signal IN-2 to the fifth node N5. The fifth node N5 is at a high potential, making the third node N3 and the fourth node N4 at a high potential. The tenth transistor M10 in submodules 21 and 22 is turned off, and the eleventh transistor M11 in submodules 21 and 22 is turned on under the control of the low potential of the second node N2. Submodule 21 outputs the high level signal of the first sub-scan signal sp1, and submodule 22 outputs the high level signal of the second sub-scan signal sp2.

[0117] During the time period from t41 to t44, the first output module 10 completed the output of the first high-level pulse of the first scan signal sn, and the second output module 20 completed the output of the low-level pulse of the first sub-scan signal sp1 and the low-level pulse of the second sub-scan signal sp2.

[0118] During time period t45, the first clock signal CK1 is low, controlling the first transistor M1 to turn on and write the low level of the first input signal IN-1 to the first node N1. The first node N1 is at a low potential, the second node N2 is at a high potential, and the output of control module 00 is at a low potential. The control terminal of the first output module 10 receives the low-level signal and controls the sixth transistor M6 to turn on, providing the high level of the refresh control signal CTRL to the output of the first output module 10. The first output module 10 then outputs the high level of the first scan signal sn again. Additionally, the high-level signal of the second node N2 controls the eleventh transistor M11 in sub-modules 21 and 22 to turn off. Furthermore, during this time period, the second input signal IN-2 is high, and the first clock signal CK1 turns on, causing the fifth node N5 to write a high-level signal, which in turn controls the third node N3 and the fourth node N4 to be at a high potential. Therefore, the tenth transistor M10 in sub-modules 21 and 22 turns off. Sub-module 21 maintains the high-level output of the first sub-scan signal sp1, and sub-module 22 maintains the high-level output of the second sub-scan signal sp2.

[0119] During time period t46, the first node N1 maintains a low potential, the second node N2 maintains a high potential, the fifth node N5 maintains a high potential, and the third node N3 and the fourth node N4 maintain high potentials. The first output module outputs a high-level signal of the first scan signal sn, and the second output control module 20 outputs a high-level signal of the first sub-scan signal sp1 and a high-level signal of the second sub-scan signal sp2.

[0120] During time period t47, the first clock signal CK1 is low, controlling the first transistor M1 and the twelfth transistor M12 to turn on. During this period, the first input signal IN-1 is high, and the second input signal IN-2 is high. The first transistor M1 turns on, a high-level signal is written to the first node N1, the second node N2 is low, and the output terminal connected to the first output module 10 of the control module 00 outputs a high level. The first output module 10 outputs a low-level signal for the first scan signal sn. The twelfth transistor M12 turns on, writing a high level to the fifth node N5, and the third node N3 and the fourth node N4 are at high potentials. In the second output module 20, the eleventh transistor M11 turns on under the control of the second node N2. Submodule 21 outputs a high-level signal for the first sub-scan signal sp1, and submodule 22 outputs a high-level signal for the second sub-scan signal sp2.

[0121] During the period from t45 to t47, the first output module 10 completed the output of the second high-level pulse of the first scan signal sn, and the second output module 20 output the high-level signal of the first sub-scan signal sp1 and the high-level signal of the second sub-scan signal sp2.

[0122] Figure 19 The shift register unit provided in the embodiment uses Figure 27 When the signal timing provided in the embodiment is used for driving, the first scan signal sn includes two high-level pulse signals, and the second scan signal sp includes one low-level pulse signal. Figure 19 The embodiment enables the first scan signal sn to have multiple pulses. In application, the first scan signal sn output by this shift register unit can provide the above-mentioned... Figure 3 The scanning signal S2n in the timing diagram.

[0123] Understandable Figure 19 The shift register unit provided in the embodiment, when the pulse signal of the first input signal IN-1 is a low-level pulse, the pulse signal of the second input signal IN-2 is a low-level pulse, and the refresh control signal CTRL is a high-level signal, outputs a first scan signal sn consisting of a high-level pulse signal and a second scan signal sp consisting of a low-level pulse signal. In other words, by setting the input signals and the refresh control signal... Figure 19 The first scan signal sn output by the shift register unit provided in the embodiment can be a single pulse or multiple pulses.

[0124] Figure 19 The embodiment enables the first scan signal sn to have multiple pulses. The setting of the first input signal IN-1 does not need to consider compatibility with the output of the second output module 20, and can support more flexible waveform settings for the first scan signal sn, such as a multi-pulse first scan signal sn or a first scan signal sn with a longer pulse width.

[0125] Figure 28 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 28 In the timing sequence, the refresh control signal CTRL is a low-level signal, the pulse level of the first input signal IN-1 is low, and the pulse level of the second input signal IN-2 is low. Figure 28 Provided signal timing driver Figure 19 When the shift register is in the middle, the first output module 10 in the shift register outputs a low-level constant voltage signal, and the second output module 20 outputs the first sub-scan signal sp1 and the second sub-scan signal sp2.

[0126] Figure 19 The shift register unit provided in the embodiment adopts the above-described... Figure 27When driven by the signal timing, it operates in the first mode, outputting the first scan signal sn and the second scan signal sp. Figure 28 When driven by the signal timing, it operates in the second mode, outputting a low-level constant voltage signal and a second scan signal sp.

[0127] Figure 19 In this embodiment, the shift register unit receives a first input signal IN-1 and a second input signal IN-2. The control terminal of the first output module 10 is connected to the output terminal of the first inverter 1, and at least one control terminal of the second output module 20 is connected to the input terminal of the first inverter 1. At least one input terminal of the second output module 20 receives the second input signal IN-2 through the second input module 23. The shift register units are cascaded in the following manner.

[0128] Figure 29 This is a schematic diagram of another cascaded shift register unit provided in an embodiment of the present invention. Figure 29 The middle indicates Figure 19 The cascading method of intermediate shift register units. Combined with... Figure 27 and Figure 28 From the timing diagram, the shift register unit requires a low pulse level for the first input signal IN-1 and a low pulse level for the second input signal IN-2. The low-level start time of the second sub-scan signal sp2 in the second scan signal sp is later than the low-level start time of the first sub-scan signal sp1. Figure 29 The diagram illustrates two cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1) and the ith stage shift register unit VSR(i). The first submodule 2 in the ith stage shift register unit VSR(i) (see...) Figure 19 The input terminal of the schematic is connected to the first inverter 1 in the (i-1)th stage shift register unit VSR(i-1) (see diagram). Figure 19 The output terminal of the schematic (i.e., i is an integer, i≥2). That is, the transmission signal next output from the output terminal of the first inverter 1 in the first stage shift register unit is used as the first input signal IN-1 of the next stage shift register unit. In addition, the input terminal of the second output module 20 in the i-th stage shift register unit VSR(i) (i.e., Figure 19 The input terminal of the second input module 23 receives the second sub-scan signal sp2 output by the (i-1)th stage shift register unit VSR(i-1). That is, when the shift register unit outputs two or more second scan signals sp, there is a phase difference between the different second scan signals sp. The second scan signal with the latest low-level start time is used as the second input signal IN-2 received by the next stage shift register unit.

[0129] Figure 19In this embodiment, the first node N1 is connected to the first capacitor C1, which is used to stabilize the potential of the first node N2, and the signal at the output of the first inverter 1 is used as the next stage signal. The first node N1 is not connected to the output of the first inverter 1, which can reduce the risk of interference from the next stage shift register unit to the first node N1.

[0130] In the Figure 29 When driving multiple cascaded shift register units, the display panel needs to be equipped with four clock signal lines and two refresh control lines. The clock signal lines are designated as first clock signal line K1, second clock signal line K2, third clock signal line K3, and fourth clock signal line K4, and all four clock signal lines provide clock signals with the same period. The two refresh control lines are designated as first refresh control line CTRL1 and second refresh control line CTRL2. The connection method between the clock signal lines and refresh control lines and the shift register units is as described above. Figure 26 The implementation methods are the same and will not be repeated here.

[0131] Figure 29 A shift register, composed of multiple shift register units, can drive the display panel to perform zone refresh. Combined with... Figure 27 and Figure 28 According to the timing diagram, the shift register unit operates in the first mode when the refresh control signal CTRL is high, and in the second mode when the refresh control signal CTRL is low. It can be understood that by controlling the first refresh control line CTRL1 and the second refresh control line CTRL2 to start as high-level signals and then transition to low-level signals at a certain time, multiple shift register units in the upper half of the display area are driven in the first mode, and multiple shift register units in the lower half of the display area are driven in the second mode. This allows the display panel to refresh image data in the upper half of the display area and not refresh the image in the lower half of the display area within one refresh frame.

[0132] Figure 18 and Figure 19 The first output module 10 illustrated in this embodiment includes two transistors. In this embodiment, the first output module 10 may also have other structures.

[0133] In other implementations, Figure 30 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 30As shown, the control module 00 includes a first inverter 1, a first sub-module 2, and a second inverter 3. The first output module 10 includes a sixth transistor M6, a seventh transistor M7, and a fourth inverter 5. The sixth transistor M6 is a p-type transistor, and the seventh transistor M7 is an n-type transistor. The control terminals of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the output terminals of the first inverter 1. The first terminal of the sixth transistor M6 receives a second voltage signal VGH, and the first terminal of the seventh transistor M7 receives a refresh control signal CTRL. The second terminals of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the input terminals of the fourth inverter 5. The output terminal of the fourth inverter 5 is the output terminal of the first output module 10. The first port (e.g., ground terminal) of the fourth inverter 5 receives a first voltage signal VGL, and the second port (e.g., power supply terminal) receives the second voltage signal VGH. The fourth inverter 5 is a CMOS inverter, which includes a fourteenth transistor M14 and a fifteenth transistor M15. The fourteenth transistor M14 is a p-type transistor, and the fifteenth transistor M15 is an n-type transistor. At least one control terminal of the second output module 20 is connected to the input terminal of the first inverter 1, and at least one input terminal of the second output module 20 receives the second input signal IN-2. The first level signal of the refresh control signal CTRL is a high level signal, and the second level signal is a low level signal. That is, when the refresh control signal CTRL is a high level signal, the shift register unit operates in the first mode, and when the refresh control signal CTRL is a low level signal, the shift register unit operates in the second mode.

[0134] In the first output module 10 provided in this embodiment, the refresh control signal CTRL is not directly connected to the fourth inverter 5, and therefore the refresh control signal CTRL is not directly connected to the output transistor (the transistor directly connected to the output terminal of the first output module 10) in the first output module 10. Since the refresh control signal CTRL serves as a control signal for the output transistor rather than an output signal, the fluctuations in the refresh control signal CTRL (such as transitions between high and low levels) can be avoided from affecting the output signal of the first output module 10.

[0135] In addition, Figure 30In this embodiment, the fourteenth transistor M14 and the fifteenth transistor M15 are transistors directly connected to the output terminal of the first output module 10. The second voltage signal VGH received by the fourteenth transistor M14 can be provided by a separate signal line, and the first voltage signal VGL received by the fifteenth transistor M15 can be provided by a separate signal line. For example, the first terminal of the fifteenth transistor M15 and the first terminal of the fifth transistor M5 both receive the first voltage signal VGL, but these two transistors are connected to different signal lines. The first terminal of the fourteenth transistor M14 and the first terminal of the fourth transistor M4 both receive the second voltage signal VGH, but these two transistors are connected to different signal lines. This arrangement can ensure the signal output performance of the first output module 10. In other related embodiments of the present invention, the constant voltage signal lines connected to the output transistors in the first output module 10 can be individually configured with reference to the description herein.

[0136] Figure 31 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 31 The provided timing diagrams can be applied to Figure 30 The provided shift register unit. Figure 31 In the timing sequence, the refresh control signal CTRL is a high-level signal, the pulse level of the first input signal IN-1 is high, and the pulse level of the second input signal IN-2 is low. Combined with... Figure 30 and Figure 31 The working process of the shift register unit is as follows: During time period t51, the first clock signal CK1 controls the first transistor M1 to turn on, writing the high level of the first input signal IN-1 to the first node N1. The first node N1 is at a high potential, the second node N2 is at a low potential, and the output of the first inverter 1 is at a high potential. The control terminals of the sixth transistor M6 and the seventh transistor M7 in the first output module 10 receive the high-level signal. The high-level signal controls the seventh transistor M7 to turn on, providing the low level of the refresh control signal CTRL to the input of the fourth inverter 5. The output of the fourth inverter 5 outputs a high level, that is, the output of the first output module 10 outputs the high-level signal of the first scan signal sn. In addition, the high-level signal at the output of the first inverter 1 controls the eleventh transistor M11 in submodules 21 and 22 to turn off. The low level of the first clock signal CK1 controls the twelfth transistor M12 to turn on, writing the low level of the second input signal IN-2 to the third node N3 of submodule 21 and the fourth node N4 of submodule 22. The third node N3 and the fourth node N4 are at low potentials, respectively controlling the tenth transistor M10 in submodule 21 and submodule 22 to turn on. During this period, the second clock signal CK2 and the third clock signal CK3 are both at high levels. Submodule 21 outputs a high-level signal for the first sub-scan signal sp1, and submodule 22 outputs a high-level signal for the second sub-scan signal sp2.

[0137] During time period t52, the first transistor M1 is off, the first node N1 is at a high potential, the second node N2 is at a low potential, and the output of the first inverter 1 is at a high potential. The output of the first output module 10 continues to output the high-level signal of the first scan signal sn. The third node N3 and the fourth node N4 remain at a low potential, the second clock signal CK2 is at a low level, the sub-module 21 outputs the low level of the first sub-scan signal sp1, the third clock signal CK3 is at a high level, and the sub-module 22 outputs the high level of the second sub-scan signal sp2.

[0138] During time period t53, the first transistor M1 is off, the first node N1 is at a high potential, the second node N2 is at a low potential, and the output of the first inverter 1 is at a high potential. The output of the first output module 10 continues to output the high-level signal of the first scan signal sn. The third node N3 and the fourth node N4 remain at a low potential, the second clock signal CK2 is at a high level, the sub-module 21 outputs the high-level signal of the first sub-scan signal sp1, the third clock signal CK3 is at a low level, and the sub-module 22 outputs the low-level signal of the second sub-scan signal sp2.

[0139] During time period t54, the first clock signal CK1 goes low again, the first transistor M1 turns on and writes the low level of the first input signal IN-1 to the first node N1, the second node N2 goes high, and the output of the first inverter 1 goes low. The low level at the output of the first inverter 1 controls the sixth transistor M6 to turn on, the input of the fourth inverter 5 receives a high-level signal and outputs a low-level signal, so the first output module 10 outputs the low level of the first scan signal sn. During this stage, the first clock signal CK1 controls the twelfth transistor M12 to turn on, the third node N3 and the fourth node N4 write high levels, and control the tenth transistor M10 in submodule 21 and submodule 22 to turn off, respectively. The low level at the output of the first inverter 1 controls the eleventh transistor M11 in submodule 21 and submodule 22 to turn on, and the second output module 20 outputs the high level of the first sub-scan signal sp1 and the high level of the second sub-scan signal sp2.

[0140] During the time intervals from t51 to t54, the first output module 10 outputs the first high-level pulse of the first scan signal sn, and the second output module 20 outputs the low-level pulse of the first sub-scan signal sp1 and the low-level pulse of the second sub-scan signal sp2.

[0141] During time period t55, the first clock signal CK1 is low, controlling the first transistor M1 to turn on and write the high level of the first input signal IN-1 to the first node N1. The first node N1 is at a high potential, the second node N2 is at a low potential, and the output of the first inverter 1 is at a high potential. The first output module 10 operates in the same way as during time period t51, outputting the high level of the first scan signal sn. In the second output module 20, since the second input signal IN-2 is high, the third node N3 and the fourth node N4 are at a high potential, causing the tenth transistor M10 to turn off, and the eleventh transistor M11 to also turn off. The second output module 20 outputs the high level of the first sub-scan signal sp1 and the high level of the second sub-scan signal sp2.

[0142] During the t56 time period, the first output module outputs a high-level signal of the first scan signal sn, and the second output control module 20 outputs a high-level signal of the first sub-scan signal sp1 and a high-level signal of the second sub-scan signal sp2.

[0143] During time period t57, the first clock signal CK1 is low, controlling the first transistor M1 and the twelfth transistor M12 to turn on. During this period, the first input signal IN-1 is low, and the second input signal IN-2 is high. The first transistor M1 turns on, the first node N1 is written with a low level, the second node N2 is high, the output of the first inverter 1 is low, and the first output module 10 outputs a low-level signal for the first scan signal sn. The twelfth transistor M12 turns on, writing a high level to the fifth node N5, and the third node N3 and the fourth node N4 are at high potentials. In the second output module 20, the eleventh transistor M11 turns on under the control of the low level at the output of the first inverter 1, and the second output module 20 outputs high-level signals for the first sub-scan signal sp1 and the second sub-scan signal sp2.

[0144] During the period from t55 to t57, the first output module 10 completed the output of the second high-level pulse of the first scan signal sn, and the second output module 20 output the high-level signal of the first sub-scan signal sp1 and the high-level signal of the second sub-scan signal sp2.

[0145] Figure 30 The shift register unit provided in the embodiment uses Figure 31 When the signal timing provided in the embodiment is used for driving, the first scan signal sn includes two high-level pulse signals, and the second scan signal sp includes one low-level pulse signal. Figure 30 The embodiment enables the first scan signal sn to have multiple pulses. In application, the first scan signal sn output by this shift register unit can provide the above-mentioned... Figure 3 The scanning signal S2n in the timing diagram.

[0146] Figure 30 The embodiment enables the first scan signal sn to have multiple pulses. The setting of the first input signal IN-1 does not need to consider compatibility with the output of the second output module 20, and can support more flexible waveform settings for the first scan signal sn, such as a multi-pulse first scan signal sn or a first scan signal sn with a longer pulse width.

[0147] Figure 31 The diagram illustrates the timing when the refresh control signal CTRL is high. The first output module 10 of the shift register unit outputs a first scan signal sn consisting of two high-level pulses, while the second output module 20 outputs a first sub-scan signal sp1 and a second sub-scan signal sp2, each consisting of a low-level pulse. It can be understood that when the refresh control signal CTRL is low, the first output module 10 outputs a low-level constant voltage signal for the first scan signal sn, and the second output module 20 outputs a first sub-scan signal sp1 and a second sub-scan signal sp2, each consisting of a low-level pulse. In other words, the shift register unit operates in the first mode when the refresh control signal CTRL is high, and in the second mode when the refresh control signal CTRL is low.

[0148] in addition, Figure 30 In this embodiment, the signal at the output of the first inverter 1 can be used as the next stage signal to provide the first input signal IN-1 required by the next stage shift register unit. Figure 30 The shift register unit provided in the embodiment can adopt the above-described... Figure 29 The cascading method shown in the illustration will not be elaborated further here.

[0149] In other implementations, Figure 32 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 32 The structure of the middle control module 00 and the second control module 20 are similar to Figure 30 The implementation methods are the same and will not be repeated here. Figure 32As shown, the first output module 10 includes a sixth transistor M6, a seventh transistor M7, a fourth inverter 5, and a fifth inverter 6. The sixth transistor M6 is a p-type transistor, and the seventh transistor M7 is an n-type transistor. The control terminals of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the output terminals of the first inverter 1. The first terminal of the sixth transistor M6 receives the refresh control signal CTRL, and the first terminal of the seventh transistor M7 receives the first voltage signal VGL. The second terminals of the sixth transistor M6 and the seventh transistor M7 are respectively connected to the input terminals of the fourth inverter 5. The output terminal of the fourth inverter 5 is connected to the input terminal of the fifth inverter 6, and the output terminal of the fifth inverter 6 is the output terminal of the first output module 10. The first ports of the fourth inverter 5 and the fifth inverter 6 receive the first voltage signal VGL, and the second ports of the fourth inverter 5 and the fifth inverter 6 receive the second voltage signal VGH. The first port of the inverter is used as the ground terminal, and the second port is used as the power supply terminal for illustration. The fourth inverter 5 and the fifth inverter 6 are CMOS inverters. The fourth inverter 5 includes the fourteenth transistor M14 and the fifteenth transistor M15, and the fifth inverter 6 includes the sixteenth transistor M16 and the seventeenth transistor M17. The refresh control signal CTRL has a low-level signal as its first level and a high-level signal as its second level.

[0150] In the first output module 10 provided in this embodiment, the refresh control signal CTRL is not directly connected to the fifth inverter 6, that is, the refresh control signal CTRL is not directly connected to the output transistor in the first output module 10. Since the refresh control signal CTRL serves as a control signal for the output transistor rather than an output signal, the fluctuations in the refresh control signal CTRL (such as transitions between high and low levels) can be avoided from affecting the output signal of the first output module 10.

[0151] Will Figure 27 If the refresh control signal CTRL is replaced with a low-level signal, then... Figure 32 The shift register unit provided in the embodiment can employ Figure 27The implementation uses a signal timing sequence for driving. In this sequence, the refresh control signal CTRL is low, the pulse level of the first input signal IN-1 is low, the pulse level of the second input signal IN-2 is low, and the shift register unit can output a first scan signal sn and two second scan signals sp (first sub-scan signal sp1 and second sub-scan signal sp2, respectively). The first scan signal sn includes two high-level pulses, and the first sub-scan signal sp1 and the second sub-scan signal sp2 each include one low-level pulse. Alternatively, in the same sequence, the refresh control signal CTRL is high, the pulse level of the first input signal IN-1 is low, the pulse level of the second input signal IN-2 is low, and the shift register unit can output a low-level constant voltage signal and two second scan signals sp.

[0152] in addition, Figure 32 In this embodiment, the signal at the output of the first inverter 1 can be used as the next stage signal to provide the first input signal IN-1 required by the next stage shift register unit. Figure 32 The shift register unit provided in the embodiment can adopt the above-described... Figure 29 The cascading method shown in the illustration will not be elaborated further here.

[0153] In other implementations, Figure 33 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 33As shown, control module 00 includes a first inverter 1, a first submodule 2, and a second inverter 3. The first submodule 2 receives a first input signal IN-1. The output terminal of the first submodule 2 and the input terminal of the second inverter 3 are connected to a first node N1. The output terminal of the second inverter 3 and the input terminal of the first inverter 1 are connected to a second node N2. The first output module 10 includes a NAND gate 11 and a sub-output module 12. The first input terminal of the NAND gate 11 is connected to the output terminal of the first inverter 1. The second input terminal of the NAND gate 11 receives a refresh control signal CTRL. The output terminal of the NAND gate 11 and the sub-output module 12 are connected to a seventh node N7. The NAND gate 11 is configured to output a first control signal when the refresh control signal CTRL is a first level signal, and to output a second control signal when the refresh control signal CTRL is a second level signal. The sub-output module 12 is configured to output a first scan signal sn based on the first control signal, the first voltage signal VGL, and the second voltage signal VGH output by the NAND gate 11, and to output a low-level constant voltage signal based on the second control signal, the first voltage signal VGL, and the second voltage signal VGH output by the NAND gate 11. Optionally, the first level signal of the refresh control signal CTRL is a high-level signal, and the second level signal is a low-level signal. In this embodiment, the signal at the output of the first inverter 1 is used as the cascading signal next, that is, as the first input signal IN-1 required by the next stage shift register unit during cascading.

[0154] in addition, Figure 33 The second output module 20 is illustrated to include two sub-modules, namely sub-module 21 and sub-module 22. Sub-module 21 is used to output the first sub-scan signal sp1, and sub-module 22 is used to output the second sub-scan signal sp2. One control terminal of sub-module 21 and one control terminal of sub-module 22 are connected to the output terminal of the first inverter 1, and one input terminal of sub-module 21 and one input terminal of sub-module 22 are connected to the input terminal of the first inverter 1.

[0155] Specifically, such as Figure 33As shown, NAND gate 11 includes an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21. The eighteenth transistor M18 and the twentieth transistor M20 are p-type transistors, while the nineteenth transistor M19 and the twenty-first transistor M21 are n-type transistors. The control terminals of the eighteenth transistor M18 and the nineteenth transistor M19 are connected to the output of the first inverter 1. The control terminals of the twentieth transistor M20 and the twenty-first transistor M21 receive the refresh control signal CTRL. The first terminals of the eighteenth transistor M18 and the twentieth transistor M20 receive the second voltage signal VGH, and the second terminals of the eighteenth transistor M18 and the twentieth transistor M20 are connected to the output of NAND gate 11. The first terminal of the twenty-first transistor M21 receives the first voltage signal VGL, and its second terminal is connected to the first terminal of the nineteenth transistor M19. The second terminal of the nineteenth transistor M19 is connected to the output of NAND gate 11. The sub-output module 12 includes a twenty-second transistor M22 and a twenty-third transistor M23. The control terminals of the twenty-second transistor M22 and the twenty-third transistor M23 are connected to the output terminals of the NAND gate 11. The first terminal of the twenty-second transistor M22 receives a second voltage signal VGH, and the first terminal of the twenty-third transistor M23 receives a first voltage signal VGL. The second terminals of the twenty-second transistor M22 and the second terminals of the twenty-third transistor M23 are connected to the output terminals of the first output module 10. The twenty-second transistor M22 is a p-type transistor, and the twenty-third transistor M23 is an n-type transistor.

[0156] Figure 34 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 34 The signal timing in the code can be used to drive Figure 33 The shift register unit provided in the embodiment. Figure 34 This indicates that the refresh control signal CTRL is high, and the pulse level of the first input signal IN-1 is high. The shift register unit operates as follows: During time period t61, the first clock signal CK1 controls the first transistor M1 to turn on, and the first node N1 is written with a high level of the first input signal IN-1. The input of the second inverter 3 receives a high level and the output outputs a low level. The second node N2 is at a low potential. When the input of the first inverter 1 is connected to the second node N2, its output outputs a high level signal. For NAND gate 11, when its first input and second input (provided by the refresh control signal CTRL) are both high level signals, its output outputs a low level, and the seventh node N7 is at a low potential. The low potential of the seventh node N7 controls the twenty-second transistor M22 in the sub-output module 12 to turn on, and the first output module 10 outputs a high level signal of the first scan signal sn. In addition, when the second node N2 is at a low potential, the third node N3 in sub-module 21 is written with a low level signal, and the fourth node N4 in sub-module 22 is written with a low level signal. Sub-module 21 outputs a high level of the first sub-scan signal sp1, and sub-module 22 outputs a high level of the second sub-scan signal sp2.

[0157] During time period t62, the first node N1 maintains a high potential, the second node N2 maintains a low potential, the output of the first inverter 1 outputs a high-level signal, and the first output module 10 outputs a high-level signal for the first scan signal sn. The third node N3 maintains a low potential, the second clock signal CK2 is low, and the sub-module 21 outputs a low-level signal for the first sub-scan signal sp1. The fourth node N4 maintains a low potential, the third clock signal CK3 is high, and the sub-module 22 outputs a high-level signal for the second sub-scan signal sp2.

[0158] During time period t63, the first node N1 maintains a high potential, the second node N2 maintains a low potential, the output of the first inverter 1 outputs a high-level signal, and the first output module 10 outputs a high-level signal for the first scan signal sn. The third node N3 maintains a low potential, the second clock signal CK2 is high, and the sub-module 21 outputs a high-level signal for the first sub-scan signal sp1. The fourth node N4 maintains a low potential, the third clock signal CK3 is low, and the sub-module 22 outputs a low-level signal for the second sub-scan signal sp2.

[0159] During time period t64, the first clock signal CK1 controls the first transistor M1 to turn on, the first node N1 is written with a low level of the first input signal IN-1, the second node N2 is at a high level, and the output of the first inverter 1 outputs a low level signal. For NAND gate 11, if its first input is low and its second input is high (provided by the refresh control signal CTRL), its output will be high, and the seventh node N7 will be at a high level. The high level of the seventh node N7 controls the twenty-third transistor M23 in the sub-output module 12 to turn on, and the first output module 10 outputs a low level signal of the first scan signal sn. In addition, the low level signal at the output of the first inverter 1 controls the eleventh transistor M11 in sub-modules 21 and 22 to turn on, so that sub-module 21 outputs a high level of the first sub-scan signal sp1, and sub-module 22 outputs a high level of the second sub-scan signal sp2.

[0160] During the period from t61 to t64, the first output module 10 outputs the high-level pulse of the first scan signal, and the second output module 20 outputs the low-level pulse of the first sub-scan signal sp1 and the low-level pulse of the second sub-scan signal sp2. The shift register unit operates in the first mode.

[0161] When the refresh control signal CTRL is low, it goes through... Figure 35 During the timing sequence from time t61 to t64, the first output module 10 outputs a low-level constant voltage signal, and the second output module 20 outputs the first sub-scan signal sp1 and the second sub-scan signal sp2. The shift register unit operates in the second mode. Figure 33 When the shift register unit provided in the embodiment is working, it operates in the first mode when the refresh control signal CTRL is a high-level signal, and in the second mode when the refresh control signal CTRL is a low-level signal.

[0162] In some implementations, the display panel includes a first signal line for providing a refresh control signal CTRL; the second input of the NAND gate 11 is connected to the first signal line. Figure 33 In this implementation, the control terminals of the twentieth transistor M20 and the twenty-first transistor M21 are directly connected to the first signal line. In this embodiment, when the shift register units are cascaded, two refresh control lines need to be set up. These two refresh control lines are alternately connected to the cascaded shift register units to avoid abnormal signal output at certain locations due to voltage jumps on the refresh control lines during partitioned refresh display.

[0163] Figure 33In this embodiment, the control module 00 includes a first submodule 2, a second inverter 3, and a first inverter 1. The first submodule 2 receives a first input signal IN-1. The output of the first submodule 2 and the input of the second inverter 3 are connected to a first node N1. The output of the second inverter 3 and the input of the first inverter 1 are connected to a second node N2. A first output module 10 is connected to the output of the first inverter 1, and a second output module 20 is connected to both the output and input of the first inverter 1. In application, the shift register units can be cascaded in the following manner.

[0164] Figure 35 This is a schematic diagram of another cascaded shift register unit provided for the implementation of the present invention. Figure 35 The middle indicates Figure 33 The cascading method of intermediate shift register units. Combined with... Figure 33 and Figure 34 The shift register unit requires the pulse level of the first input signal IN-1 when it is working. The input terminal of the first submodule 2 receives the first input signal IN-1, and the signal at the output terminal of the first inverter 1 is used as the transmission signal next. Figure 35 The diagram illustrates two cascaded shift register units (VSRs), namely the (i-1)th stage shift register unit VSR(i-1) and the ith stage shift register unit VSR(i). The first submodule 2 in the ith stage shift register unit VSR(i) (see...) Figure 33 The input terminal of the signal (shown in the diagram) is connected to the output terminal of the first inverter 1 in the (i-1)th stage shift register unit VSR(i-1). That is, the first input signal IN-1 received by the current stage shift register unit is the next signal output by the first inverter 1 in the previous stage shift register unit.

[0165] In the Figure 35 When driving multiple cascaded shift register units, the display panel needs to be equipped with four clock signal lines and two refresh control lines. The clock signal lines are designated as first clock signal line K1, second clock signal line K2, third clock signal line K3, and fourth clock signal line K4, and all four clock signal lines provide clock signals with the same period. The two refresh control lines are designated as first refresh control line CTRL1 and second refresh control line CTRL2, and these two refresh control lines are alternately connected to the cascaded shift register units. The connection method between the shift register units and the clock signal lines is the same as described above. Figure 26 The same applies to the embodiments, and will not be repeated here.

[0166] In other implementations, Figure 36 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 36 The structure of the control module 00 and the second output module 20 are similar to Figure 33The embodiments are the same, the difference lies in the structure of the first output module 10. For example... Figure 36 As shown, the first output module 10 includes an input unit 13. The input terminal of the input unit 13 receives the refresh control signal CTRL, and the output terminal of the input unit 13 is connected to the second input terminal of the NAND gate 11. The input unit 13 is configured to write the refresh control signal CTRL to the second input terminal of the NAND gate 11 when it is enabled. Figure 36 As shown in the diagram, the second input terminal of NAND gate 11 is connected to the input unit 13 at the sixth node N6.

[0167] Figure 36 The embodiments can adopt the above. Figure 34 The shift register is driven by the provided signal timing. When the refresh control signal CTRL is high, the shift register unit is in the first mode, outputting the first scan signal sn and two second scan signals sp (including the first sub-scan signal sp1 and the second sub-scan signal sp2). When the refresh control signal CTRL is low, the shift register unit is in the second mode, outputting a low-level constant voltage signal and two second scan signals sp.

[0168] When cascading Figure 36 In implementation, the signal at the output of the first inverter 1 can be used as the stage transfer signal next. That is, the input of the first submodule 2 in the i-th stage shift register unit VSR(i) is connected to the output of the first inverter 1 in the (i-1)-th stage shift register unit VSR(i-1). In other words, the first input signal IN-1 received by the current stage shift register unit is the stage transfer signal next output by the output of the first inverter 1 in the previous stage shift register unit.

[0169] In multiple cascades Figure 37 In this embodiment, when the shift register unit is driven, four clock signal lines and one refresh control line need to be set in the display panel.

[0170] In one implementation, such as Figure 36 As shown, input unit 13 includes an eighth transistor M8, which is a p-type transistor. The control terminal of the eighth transistor M8 is connected to the output terminal of the first inverter 1. The output terminal of the first inverter 1 outputs a pass-through signal next, meaning the control terminal of the eighth transistor M8 receives the pass-through signal next output from the output terminal of the first inverter 1 in this stage of the shift register unit. Alternatively, the control terminal of the eighth transistor M8 is connected to the output terminal of the first submodule 2, meaning the first submodule 2 is connected to the first node N1.

[0171] In another embodiment, the input unit 13 includes an eighth transistor M8, which is an n-type transistor; the control terminal of the eighth transistor M8 is connected to the input terminal of the first inverter 1. This is not illustrated in the accompanying drawings. In this embodiment, when the refresh control signal CTRL is low, the low level written to the second input terminal of the NAND gate 11 is closer to the voltage value provided by the refresh control signal CTRL, resulting in more precise control of the transistors in the latch 14.

[0172] like Figure 36 As shown, the first output module 10 includes a second capacitor C2. The first plate of the second capacitor C2 is connected to the second input terminal of the NAND gate 11, and the second plate of the second capacitor C2 is connected to the constant voltage signal terminal VG1. The constant voltage signal terminal VG1 can output a first voltage signal VGL or a second voltage signal VGH. The second capacitor C2 can stabilize the potential of the sixth node N6, making the signal at the second input terminal of the NAND gate 11 more stable, thereby ensuring the stability of the output signal of the first output module 10.

[0173] In another implementation, Figure 37 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 37 The structure of the control module 00 and the second output module 20 are similar to Figure 33 The embodiments are the same, the difference lies in the structure of the first output module 10. For example... Figure 37 As shown, the first output module 10 includes a latch 14, whose input and output terminals are respectively connected to the second input terminal of the NAND gate 11. That is, the latch 14 and the second input terminal of the NAND gate 11 are connected to the sixth node N6. The latch 14 includes a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, and a twenty-seventh transistor M27. The twenty-fourth transistor M24 and the twenty-fifth transistor M25 form an inverter, and the twenty-sixth transistor M26 and the twenty-seventh transistor M27 form another inverter. The twenty-fourth transistor M24 and the twenty-sixth transistor M26 are p-type transistors, and the twenty-fifth transistor M25 and the twenty-seventh transistor M27 are n-type transistors. In this embodiment, the latch 14 enables a more stable voltage at the second input terminal of the NAND gate 11. When the refresh control signal CTRL is low, the low level written to the second input terminal of the NAND gate 11 can be closer to the voltage value provided by the refresh control signal CTRL, resulting in more precise control of the transistors in the NAND gate 11.

[0174] Figure 37 The embodiments can adopt the above. Figure 34The shift register is driven by the provided signal timing. When the refresh control signal CTRL is high, the shift register unit is in the first mode, outputting the first scan signal sn, the first sub-scan signal sp1, and the second sub-scan signal sp2. When the refresh control signal CTRL is low, the shift register unit is in the second mode, outputting a low-level constant voltage signal, the first sub-scan signal sp1, and the second sub-scan signal sp2.

[0175] When cascading Figure 37 In implementation, the signal at the output of the first inverter 1 can be used as the stage transfer signal next. That is, the input of the first submodule 2 in the i-th stage shift register unit VSR(i) is connected to the output of the first inverter 1 in the (i-1)-th stage shift register unit VSR(i-1). In other words, the first input signal IN-1 received by the current stage shift register unit is the stage transfer signal next output by the output of the first inverter 1 in the previous stage shift register unit.

[0176] In multiple cascades Figure 37 In this embodiment, when the shift register unit is driven, four clock signal lines and one refresh control line need to be set in the display panel.

[0177] The above Figures 33 to 37 In the embodiments, the control module 00 has the same structure, the second output module 20 has the same structure, and the connection method between the second output module 20 and the control module 00 is the same as described above. Figure 20 The same applies to the embodiments. Figures 33 to 37 The difference in the embodiments lies in the structure of the first output module 10. (The above...) Figures 33 to 37 The structure of the first output module 10 in the embodiment can also be applied to Figure 21 In the example, using... Figure 36 The first output module 10 is applied to Figure 21 For example, see the implementation details.

[0178] Figure 38 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 38As shown, the control module 00 includes a first inverter 1, a first sub-module 2, and a second inverter 3. The first output module 10 includes a NAND gate 11, a sub-output module 12, and an input unit 13; the first input terminal of the NAND gate 11 is connected to the output terminal of the first inverter 1, and the output terminal of the input unit 13 is connected to the second input terminal of the NAND gate 11; the input unit 13 is configured to write the refresh control signal CTRL to the second input terminal of the NAND gate 11 when enabled. The output terminal of the NAND gate 11 is connected to the sub-output module 12; the NAND gate 11 is configured to output a first control signal when the refresh control signal CTRL is a first level signal, and to output a second control signal when the refresh control signal CTRL is a second level signal. The sub-output module 12 is configured to output a first scan signal sn based on the first control signal, the first voltage signal VGL, and the second voltage signal VGH output by the NAND gate 11, and to output a low-level constant voltage signal based on the second control signal, the first voltage signal VGL, and the second voltage signal VGH output by the NAND gate 11. The second output module 20 includes submodule 21 and submodule 22. Submodule 21 is used to output the second scan signal sp1, and submodule 22 is used to output the third scan signal sp2. One control terminal of submodule 21 and one control terminal of submodule 22 are connected to the output terminal of the first inverter 1. One input terminal of submodule 21 and one input terminal of submodule 22 respectively receive the second input signal IN-2 through the second input module 23.

[0179] Figure 39 This is a timing diagram of another shift register unit provided in an embodiment of the present invention. Figure 39 The provided signal timing can be used for driving Figure 38 The shift register unit provided in this embodiment has a high-level pulse for the first input signal IN-1 and a low-level pulse for the second input signal IN-2. When the refresh control signal CTRL is high, the shift register unit operates in a first mode, outputting a first scan signal sn, a first sub-scan signal sp1, and a second sub-scan signal sp2. When the first input signal IN-1 includes two high-level pulses, the first scan signal sn includes two high-level pulses. When the refresh control signal CTRL is low, the shift register unit operates in a second mode, outputting a low-level constant voltage signal, the first sub-scan signal sp1, and the second sub-scan signal sp2. This implementation allows the first scan signal sn to have multiple pulses. The setting of the first input signal IN-1 does not need to consider compatibility with the output of the second output module 20, enabling more flexible waveform settings for the first scan signal sn, such as a multi-pulse first scan signal sn or a first scan signal sn with a longer pulse width.

[0180] When cascading Figure 38In implementation, the input terminal of the first submodule 2 in the i-th stage shift register unit VSR(i) is connected to the output terminal of the first inverter 1 in the (i-1)-th stage shift register unit VSR(i-1). That is, the first input signal IN-1 received by the current stage shift register unit is the next signal output by the first inverter 1 in the previous stage shift register unit. In addition, the low-level start time of the second sub-scan signal sp2 is later than the low-level start time of the first sub-scan signal sp1. The input terminal of the second output module 20 in the i-th stage shift register unit VSR(i) (i) Figure 38 The input terminal of the second input module 23 receives the second sub-scan signal sp2 output by the (i-1)th stage shift register unit VSR(i-1). The second sub-scan signal sp2 is the one with the latest low-level start time among the two second scan signals output by the second output module 20.

[0181] In multiple cascades Figure 38 In this embodiment, when the shift register unit is driven, four clock signal lines and one refresh control line need to be set in the display panel.

[0182] The above Figures 33 to 37 The structure of the first output module 10 in the embodiment can also be applied to Figure 22 In the example, using... Figure 33 The first output module 10 is applied to Figure 22 For example, see the implementation details. Figure 40 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 40 As shown, control module 00 includes a first inverter 1, a second inverter 3, a third inverter 4, and a first submodule 2. The input terminal of the first submodule 2 receives a first input signal IN-1, and its output terminal and the input terminal of the second inverter 3 are connected to the first node N1. The output terminal of the second inverter 3 is connected to the input terminal of the first inverter 1, and the input terminal of the third inverter 4 is connected to the output terminal of the first inverter 1. Specifically, the third inverter 4 includes a twenty-eighth transistor M28 and a twenty-ninth transistor M29, where the twenty-eighth transistor M28 is a p-type transistor and the twenty-ninth transistor M29 is an n-type transistor. At least one control terminal of the first output module 10 is connected to the output terminal of the third inverter 4, i.e., connected to the output terminal of the first inverter 1 via the third inverter 4. At least one control terminal of the second output module 20 is connected to the output terminal of the third inverter 4, and at least one input terminal of the second output module 20 is connected to the output terminal of the first inverter 1. The structure of the first output module 10 is the same as described above. Figure 34 The same applies here, so it will not be repeated. In this embodiment, a third inverter 4 is added to the output of the first inverter 1 of the control module 00. Compared to... Figure 33 In this case, when driving the shift register unit, the pulse level of the first input signal IN-1 needs to be inverted. Figure 40 In this embodiment, the pulse level of the first input signal IN-1 required for the shift register unit to operate is low. This ensures that the first node N1, where the first submodule 2 and the second inverter 3 are connected, is low most of the time. This mitigates the impact on power consumption caused by the third transistor M3 in the second inverter 3 failing to turn off when the first node N1 is high most of the time, which could lead to a short circuit at the high / low voltage receiving end. In this embodiment, the signal at the output of the first inverter 1 can be used as the cascading signal next. When cascaded, the output of the first inverter 1 is connected to the input of the first submodule 2 in the next stage shift register unit.

[0183] The above Figures 33 to 37 The structure of the first output module 10 in the embodiment can also be applied to Figure 23 In the example, using... Figure 33 The first output module 10 is applied to Figure 23 For example, see the implementation details. Figure 41 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 41 Examples and Figure 40 The difference in the embodiment is that the output of the first inverter 1 is connected to the first node N1, so that the first inverter 1 and the second inverter 2 are connected end to end to form a latch structure, thus eliminating the need for... Figure 40 The first capacitor C1 in the first node N1 has a low potential voltage that can reach the voltage value provided by the first voltage signal VGL. In addition, in this embodiment, in order to avoid the latch structure affecting the cascading, the signal at the output of the first inverter 1 is no longer used as the transmission signal. Instead, the pulse level of the first input signal IN-1 is changed to a low level, and a second scan signal output by the second output module 20 of the previous stage is used as the transmission signal when the shift register units are cascaded.

[0184] In the above embodiment, the second output module 20 is illustrated by comprising two sub-modules (sub-module 21 and sub-module 22), and the second output module 20 outputs two second scan signals sp. It can be understood that by setting the number of sub-modules in the second output module 20, the number of second scan signals sp output by the shift register unit can be adjusted. If the second output module 20 includes one sub-module, it can output one second scan signal sp. If the second output module 20 includes three sub-modules, with the coordination of a clock signal, it can output three second scan signals sp, and there is a phase difference between the three second scan signals sp. Further illustration is not provided here.

[0185] In some embodiments of the present invention, the first scan signal sn output by the shift register unit includes a high-level pulse, such as... Figure 18Example. In this embodiment, the first scan signal sn output by the shift register unit can be used as... Figure 2 The required scan signal S1n or S2n in the timing sequence.

[0186] In other embodiments, the first scan signal sn output by the shift register unit may include one high-level pulse or two high-level pulses, such as... Figure 19 Example. When the first scan signal sn includes two high-level pulses, it can be used as... Figure 3 The required scan signal S2n in the timing sequence. When the first scan signal sn includes a high-level pulse, it can be used as... Figure 2 The required scan signal S1n or S2n in the timing sequence.

[0187] In some implementations... Figure 42 This is a schematic diagram of a display panel provided in an embodiment of the present invention. (In conjunction with...) Figure 1 To understand the schematic pixel circuit, multiple pixel circuits 40 are arranged in a pixel circuit row 40H in the first direction x; Figure 42 Four pixel circuit rows 40H are illustrated, namely the first pixel circuit row 40H1, the second pixel circuit row 40H2, the third pixel circuit row 40H3, and the fourth pixel circuit row 40H4. The display panel includes a first scan line S1n, a second scan line S2n, and a third scan line Sp. The scan lines and the scan signals they provide to the pixel circuits are marked with the same symbols. The first scan line S1n is connected to multiple gate reset transistors T1 in pixel circuit row 40H, the second scan line S2n is connected to multiple threshold compensation transistors T3 in pixel circuit row 40H, and the third scan line Sp is connected to multiple data write transistors T5 in pixel circuit row 40H. Figure 42 As shown, the shift register unit VSR outputs a first scan signal sn and two second scan signals sp. The second scan signal sp includes a first sub-scan signal sp1 and a second sub-scan signal sp2; the low-level start time of the second sub-scan signal sp2 is later than the low-level start time of the first sub-scan signal sp1.

[0188] At least a partial shift register unit VSR outputs a first scan signal sn to the two second scan lines S2n driving the row 40H of two adjacent pixel circuits, and outputs a first sub-scan signal sp1 and a second sub-scan signal sp2 to the two third scan lines Sp driving the row 40H of the two adjacent pixel circuits, respectively. The 0th level shift register unit VSR(0) outputs a first scan signal sn to the first scan line S1n driving the first pixel circuit row 40H and the first scan line S1n driving the second pixel circuit row 40H. The first scan signal sn serves as the scan signal S1n driving the gate reset transistor T1.

[0189] The p-th shift register unit VSR(p) outputs a first scan signal sn (as the scan signal S2n driving the threshold compensation transistor T3) to the second scan line S2n driving the first pixel circuit row 40H and the second scan line S2n driving the second pixel circuit row 40H. It outputs a first sub-scan signal sp1 (as the scan signal Sp driving the data write transistor T5) to the third scan line Sp driving the first pixel circuit row 40H. It outputs a second sub-scan signal sp2 (as the scan signal Sp driving the data write transistor T5) to the third scan line Sp driving the second pixel circuit row 40H. It outputs a first scan signal sn (as the scan signal S1n driving the gate reset transistor T1) to the first scan line sn driving the 2p+1 pixel circuit row 40H and the first scan line sn driving the 2p+2 pixel circuit row 40H. p is an integer, p≥1.

[0190] by Figure 18 Taking the shift register unit provided in the embodiment as an example, combined with Figure 24 As can be seen, when the shift register unit is working, the high-level pulse period of the first scan signal sn covers the low-level pulse periods of the two second scan signals sp. Therefore, the first scan signal sn and the two second scan signals sp output by the first-level shift register unit VSR can be used to drive two pixel circuit rows 40H. The first scan signal sn drives the threshold compensation transistor T3 in the two pixel circuit rows 40H, and each of the two pixel circuit rows 40H is driven by a second scan signal sp to drive the data writing transistor T5. Furthermore, when using the above... Figure 2 When the pixel circuit is driven by the schematic timing, the first scan signal sn output by this shift register unit VSR can also be used to drive the gate reset transistor T1 in the other two pixel circuit rows 40H.

[0191] Since the scan signals S1n and S2n required by a pixel circuit are not synchronized, their high-level periods cannot overlap. Therefore, in this embodiment of the invention, a pre-amplifier circuit is provided to provide the scan signal S1n required by the gate reset transistor T1. When p=1, a first-stage pre-amplifier shift register unit is set. Figure 42 The diagram uses p=1 as an example. When p=2, a two-stage pre-shift register unit is required. The pre-shift register unit outputs the first scan signal sn, which is provided to the corresponding scan line; the second scan line sp is not used. In practice, the number of pre-shift circuits is set according to the relationship between the pulse width of the first scan signal sn and the pulse width of the clock signal.

[0192] In this embodiment, a first scan signal sn drives two pixel circuit rows 40H, and a second scan signal sp drives one pixel circuit row 40H.

[0193] In one implementation, Figure 43 This is a schematic diagram of the circuit layout of a display panel provided in an embodiment of the present invention, as shown below. Figure 43 As shown, a light-emitting driving circuit Em and a merging driving circuit 50 are arranged on one side of the display area AA of the display panel, and a merging driving circuit 50 and a scan driving circuit SpX are arranged on the other side. Each level of shift register units in the light-emitting driving circuit Em is used to provide the light-emitting control signal Em required by the pixel circuit, and each level of shift register units in the scan driving circuit SpX is used to provide the scan signal SpX required by the pixel circuit. The merging driving circuits 50 on both sides of the display area AA have the same structure, and the merging driving circuit 50 is a shift register composed of multiple shift register units provided in the embodiments of the present invention. The merging driving circuit 50 provides the scan signal S1n, scan signal S2n, and scan signal Sp required by the pixel circuit. The connection method between each level of shift register units in the merging driving circuit 50 and the pixel circuit row can be referred to... Figure 42 The diagram illustrates this. Scan signals S1n and S2n drive two pixel circuit rows per signal, while scan signal Sp drives one pixel circuit row per signal. In this embodiment, two sets of driving circuits are arranged on one side of the display panel, thereby narrowing the panel bezel. Furthermore, the number of clock signals required by the display panel as a whole is reduced, thus lowering the power consumption of the display panel.

[0194] In some implementations... Figure 44 This is a schematic diagram of another display panel provided in an embodiment of the present invention. (In conjunction with...) Figure 1 To understand the schematic pixel circuit, Figure 44 The connection relationship between the first scan line S1n, the second scan line S2n, and the third scan line Sp and the transistors in pixel circuit row 40H is as follows: Figure 42 The same applies here, and will not be repeated. Multiple pixel circuits 40 are arranged in pixel circuit row 40H in the first direction x; Figure 44 The diagram illustrates four pixel circuits in row 40H. (Example) Figure 45 As shown, the shift register includes a first shift register and a second shift register. The first shift register includes multiple cascaded first shift register units 1VSR, and the second shift register includes multiple cascaded second shift register units 2VSR.

[0195] Both the first shift register unit 1 (VSR) and the second shift register unit 2 (VSR) output a first scan signal sn and two second scan signals sp. The second scan signal sp includes a first sub-scan signal sp1 and a second sub-scan signal sp2; the low-level start time of the second sub-scan signal sp2 is later than the low-level start time of the first sub-scan signal sp1. Wherein, The first shift register 1VSR provides the scan signal S2n and scan signal Sp required by the pixel circuit. The first shift register unit 1VSR(m) of the m-th stage outputs a first scan signal sn to the second scan line S2n driving the 40H row of the 2m-1 pixel circuit and the second scan line S2n driving the 40H row of the 2m pixel circuit, respectively outputs a first sub-scan signal sp1 to the third scan line Sp driving the 40H row of the 2m-1 pixel circuit, and outputs a second sub-scan signal sp2 to the third scan line Sp driving the 40H row of the 2m pixel circuit; m is an integer, m≥1; if m=1, the first shift register unit 1VSR(1) of the first stage outputs a first scan signal sn to the second scan line S2n driving the 40H1 row of the 1st pixel circuit and the 40H2 row of the 2nd pixel circuit, and outputs a first sub-scan signal sp1 to the third scan line Sp driving the 40H1 row of the 1st pixel circuit and a second sub-scan signal sp2 to the third scan line Sp driving the 40H2 row of the 2nd pixel circuit.

[0196] The second shift register unit 2VSR provides the scan signal S1n and scan signal Sp required by the pixel circuit. At least part of the second shift register unit 2VSR outputs the first scan signal sn to the two first scan lines S1n driving two adjacent pixel circuit rows 40H, and outputs the first sub-scan signal sp1 and the second sub-scan signal sp2 to the two third scan lines Sp driving two other adjacent pixel circuit rows 40H, respectively.

[0197] The 0th level second shift register unit 2VSR(0) outputs the first scan signal s1n to the first scan line S1n driving the first pixel circuit row 40H and the first scan line S1n driving the second pixel circuit row 40H. The p-th stage second shift register unit 2VSR(p) outputs a first sub-scan signal sp1 to the third scan line Sp driving the first pixel circuit row 40H, outputs a second sub-scan signal sp2 to the third scan line Sp driving the second pixel circuit row 40H, and outputs a first scan signal sn to the first scan line S1n driving the 2p+1 pixel circuit row 40H and the first scan line S1n driving the 2p+2 pixel circuit row 40H. p is an integer, p≥1.

[0198] Combination Figure 42As can be understood from the related descriptions of the embodiments, the first shift register unit 1VSR provides the scan signals S2n and Sp required by the pixel circuit, and the second shift register unit 2VSR provides the scan signals S1n and Sp required by the pixel circuit. However, in the embodiments of the present invention, the high-level pulse period of the first scan signal sn output by the shift register unit covers the low-level pulse periods of the two second scan signals sp. When the second shift register unit 2VSR is configured to provide the scan signals S1n and Sp required by the pixel circuit, the first scan signal sn and the second scan signal sp output by the second shift register unit 2VSR cannot provide the same pixel circuit row. Figure 44 In this embodiment, a preceding shift register unit needs to be set for the second shift register unit 2VSR. Figure 44 Taking p=1 as an example, that is, a first-level pre-positioned second shift register unit 2VSR is set in the second shift register. The first scan signal sn output by the pre-positioned second shift register unit 2VSR provides the scan signal S1n required for the first pixel circuit row 40H1 and the second pixel circuit row 40H2.

[0199] In another implementation, Figure 45 This is a schematic diagram of another circuit layout of a display panel provided in an embodiment of the present invention, as shown below. Figure 45 As shown, the display panel has a light-emitting driving circuit Em and a first merging driving circuit 51 on one side of the display area AA, and a second merging driving circuit 52 and a scanning driving circuit SpX on the other side. Both the first merging driving circuit 51 and the second merging driving circuit 52 are shift registers composed of multiple shift register units provided in embodiments of the present invention. For example, the first merging driving circuit 51 is... Figure 44 In this embodiment, the first shift register provides the scan signal S2n and scan signal Sp required by the pixel circuit. The second merging drive circuit 52 is... Figure 44 In this embodiment, the second shift register provides the scan signal S1n and scan signal Sp required by the pixel circuit.

[0200] Figure 45 In the embodiment, the first merging drive circuit 51 and the second merging drive circuit 52 can be as follows: Figure 18 The shift register unit in this embodiment outputs a first scan signal sn, which includes a high-level pulse. The first merging drive circuit 51 and the second merging drive circuit 52 can be... Figure 19 In the embodiment, the shift register unit sets the signal timing so that the first scan signal sn output by the first merging drive circuit 51 includes two high-level pulses, while the first scan signal sn output by the second merging drive circuit 52 includes one high-level pulse.

[0201] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 46 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 46 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The display panel includes a shift register unit provided in the embodiments of the present invention. The structure of the shift register unit has been described in the above embodiments and will not be repeated here. The display panel provided in the embodiments of the present invention may be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

Claims

1. A display panel, characterized in that, The system includes a shift register, which comprises multiple cascaded shift register units. Each shift register unit includes a control module, a first output module, and a second output module. The first output module is connected to at least one output terminal of the control module, and the second output module is connected to at least one output terminal of the control module and / or to the output terminal of the first output module. The control module is configured to output a control signal based at least on a first input signal; The first output module is configured to output a first scan signal based at least on the control signal output by the control module, wherein a high level in the first scan signal is an enable level; The second output module is configured to output at least one second scan signal based on the control signal output by the control module and / or the signal output by the first output module, wherein the low level in the second scan signal is an enable level.

2. The display panel according to claim 1, characterized in that, The control module is configured to output a control signal based on the first input signal, the first clock signal, the first voltage signal, and the second voltage signal; The first output module is configured to output the first scan signal based on the control signal output by the control module, the first voltage signal, and the second voltage signal; The second output module is configured to output at least one second scan signal based on the first voltage signal, the second voltage signal, at least one clock signal, and the control signal output by the control module and the signal output by the first output module, or the output signal and the second input signal of the first output module, or the control signal output by the control module, or the control signal and the second input signal output by the control module.

3. The display panel according to claim 2, characterized in that, The first output module includes a first inverter; the input terminal of the first inverter is connected to the output terminal of the control module, and the first inverter outputs the first scan signal based on the control signal output by the control module. The control module includes a first submodule and a second inverter. The first submodule receives the first input signal. The first submodule is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the first inverter. The first submodule is configured to write the first input signal to the input terminal of the second inverter under the control of a first clock signal. At least one control terminal of the second output module is connected to the output terminal of the first inverter, and at least one input terminal of the second output module is connected to the input terminal of the first inverter or receives a second input signal.

4. The display panel according to claim 3, characterized in that, At least one input terminal of the second output module receives the second input signal; the pulse level of the first input signal is high, and the pulse level of the second input signal is low; the input terminal of the first sub-module in the i-th stage shift register unit is connected to the output terminal of the first inverter in the (i-1)-th stage shift register unit, and the input terminal of the second output module in the i-th stage shift register unit receives a second scan signal output by the (i-1)-th stage shift register unit, where i is an integer and i≥2; Alternatively, at least one input terminal of the second output module is connected to the input terminal of the first inverter; the pulse level of the first input signal is high, and the input terminal of the first sub-module in the i-th stage shift register unit is connected to the output terminal of the first inverter in the (i-1)-th stage shift register unit, where i is an integer and i≥2.

5. The display panel according to claim 2, characterized in that, The control module includes a first submodule, a first inverter, and a second inverter. The first submodule receives the first input signal. The first submodule is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the first inverter. The first submodule is configured to write the first input signal to the input terminal of the second inverter under the control of a first clock signal. The first output module includes a third inverter, the input of which is connected to the output of the control module, and the third inverter outputs the first scan signal based at least on the control signal output by the control module. At least one control terminal of the second output module is connected to the output terminal of the second inverter or to the output terminal of the first output module, and at least one input terminal of the second output module is connected to the output terminal of the first inverter or receives a second input signal.

6. The display panel according to claim 5, characterized in that, At least one input terminal of the second output module is connected to the output terminal of the first inverter, and the pulse level of the first input signal is low; the input terminal of the first sub-module in the i-th stage shift register unit receives a second scan signal output by the (i-1)-th stage shift register unit, where i is an integer and i≥2; At least one input terminal of the second output module receives a second input signal, wherein the pulse level of the first input signal is high and the pulse level of the second input signal is low; the input terminal of the first sub-module in the i-th stage shift register unit is connected to the output terminal of the first inverter in the (i-1)-th stage shift register unit, and the input terminal of the second output module in the i-th stage shift register unit receives a second scan signal output by the (i-1)-th stage shift register unit, where i is an integer and i≥2.

7. The display panel according to claim 1, characterized in that, The first output module is configured to output the first scan signal based at least on the first level signal of the control signal and the refresh control signal output by the control module, and to output a low-level constant voltage signal based at least on the second level signal of the control signal and the refresh control signal output by the control module. The first level signal and the second level signal are respectively a high level signal and a low level signal.

8. The display panel according to claim 1, characterized in that, The control module is configured to output a control signal based on the first input signal, the first clock signal, the first voltage signal, and the second voltage signal; The control module includes a first input module and a first inverter. The input terminal of the first input module receives the first input signal, and the output terminal of the first input module is connected to the input terminal of the first inverter. The first output module and the second output module are respectively connected to the first inverter.

9. The display panel according to claim 8, characterized in that, The first input module includes a first submodule and a second inverter. The first submodule receives the first input signal. The output terminal of the first submodule is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter.

10. The display panel according to claim 9, characterized in that, The pulse level of the first input signal is low. The input terminal of the first submodule in the i-th level shift register unit receives a second scan signal output by the (i-1)-th level shift register unit, where i is an integer and i ≥ 2.

11. The display panel according to claim 8, characterized in that, The first input module includes a first submodule, a second inverter, and a first capacitor. The first submodule receives the first input signal. The first submodule is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. One plate of the first capacitor is connected to the input terminal of the second inverter, and the other plate receives the first voltage signal.

12. The display panel according to claim 11, characterized in that, The pulse level of the first input signal is either high or low. The input terminal of the first submodule in the i-th stage shift register unit is connected to the output terminal of the first inverter in the (i-1)-th stage shift register unit, where i is an integer and i≥2.

13. The display panel according to claim 9 or 10, characterized in that, The display panel includes multiple pixel circuits, which are arranged in a pixel circuit row in a first direction; each pixel circuit includes a gate reset transistor, a data write transistor, and a threshold compensation transistor, wherein the gate reset transistor and the threshold compensation transistor are n-type transistors, and the data write transistor is a p-type transistor; The display panel includes a first scan line, a second scan line, and a third scan line. The first scan line is connected to a plurality of gate reset transistors in the pixel circuit row. The second scan line is connected to a plurality of threshold compensation transistors in the pixel circuit row. The third scan line is connected to a plurality of data write transistors in the pixel circuit row. The second scan signal includes a first sub-scan signal and a second sub-scan signal; the low-level start time of the second sub-scan signal is later than the low-level start time of the first sub-scan signal; At least a portion of the shift register units output the first scan signal to two second scan lines driving two adjacent pixel circuit rows, and respectively output the first sub-scan signal and the second sub-scan signal to two third scan lines driving the two adjacent pixel circuit rows; wherein, The shift register unit at level 0 outputs the first scan signal to the first scan line driving the first pixel circuit row and the first scan line driving the second pixel circuit row. The shift register unit of the p-th stage outputs the first scan signal to the second scan line driving the first pixel circuit row and the second scan line driving the second pixel circuit row, outputs the first sub-scan signal to the third scan line driving the first pixel circuit row, outputs the second sub-scan signal to the third scan line driving the second pixel circuit row, and outputs the first scan signal to the first scan line driving the (2p+1)-th pixel circuit row and the first scan line driving the (2p+2)-th pixel circuit row, where p is an integer and p≥1.

14. The display panel according to claim 12, characterized in that, The second output module is configured to output at least one second scan signal based on at least the second input signal and the control signal output by the control module; The pulse level of the second input signal is low. The input terminal of the second output module in the i-th stage shift register unit receives a second scan signal output by the (i-1)-th stage shift register unit.

15. The display panel according to claim 14, characterized in that, The display panel includes multiple pixel circuits, which are arranged in a pixel circuit row in a first direction; each pixel circuit includes a gate reset transistor, a data write transistor, and a threshold compensation transistor, wherein the gate reset transistor and the threshold compensation transistor are n-type transistors, and the data write transistor is a p-type transistor; The display panel includes a first scan line, a second scan line, and a third scan line. The first scan line is connected to a plurality of gate reset transistors in the pixel circuit row. The second scan line is connected to a plurality of threshold compensation transistors in the pixel circuit row. The third scan line is connected to a plurality of data write transistors in the pixel circuit row. The shift register includes a first shift register and a second shift register. The first shift register includes a plurality of cascaded first shift register units, and the second shift register includes a plurality of cascaded second shift register units; wherein, The second scan signal includes a first sub-scan signal and a second sub-scan signal; the low-level start time of the second sub-scan signal is later than the low-level start time of the first sub-scan signal; The first shift register unit of the m-th stage outputs the first scan signal to the second scan line driving the (2m-1)-th pixel circuit row and the second scan line driving the 2m-th pixel circuit row, respectively outputs the first sub-scan signal to the third scan line driving the (2m-1)-th pixel circuit row, and outputs the second sub-scan signal to the third scan line of the 2m-th pixel circuit row; m is an integer, m≥1; At least a portion of the second shift register unit outputs the first scan signal to the two first scan lines driving two adjacent pixel circuit rows, and outputs the first sub-scan signal and the second sub-scan signal to the two third scan lines driving another two adjacent pixel circuit rows, respectively. The second shift register unit of level 0 outputs the first scan signal to the first scan line driving the first pixel circuit row and the first scan line driving the second pixel circuit row; The second shift register unit of the p-th stage outputs the first sub-scan signal to the third scan line driving the first pixel circuit row, outputs the second sub-scan signal to the third scan line driving the second pixel circuit row, and outputs the first scan signal to the first scan line driving the (2p+1)th pixel circuit row and the first scan line driving the (2p+2)th pixel circuit row, where p is an integer and p≥1.

16. The display panel according to claim 8, characterized in that, The first input module includes a first submodule and a second inverter; The first submodule includes a first transistor, which is a p-type transistor. The control terminal of the first transistor receives a first clock signal, the first terminal receives the first input signal, and the second terminal is connected to the input terminal of the second inverter. The second inverter includes a second transistor and a third transistor. The second transistor is a p-type transistor, and the third transistor is an n-type transistor. The control terminals of the second transistor and the third transistor are the input terminals of the second inverter. The first terminal of the third transistor receives a first voltage signal, and the first terminal of the second transistor receives a second voltage signal. The second terminals of the second transistor and the second terminals of the third transistor are the output terminals of the second inverter. The first inverter includes a fourth transistor and a fifth transistor. The fourth transistor is a p-type transistor, and the fifth transistor is an n-type transistor. The control terminals of the fourth transistor and the fifth transistor are the input terminals of the first inverter. The first terminal of the fifth transistor receives the first voltage signal, and the first terminal of the fourth transistor receives the second voltage signal. The second terminals of the fourth transistor and the second terminals of the fifth transistor are the output terminals of the first inverter.

17. The display panel according to claim 8, characterized in that, At least one control terminal of the first output module is connected to the output terminal of the first inverter; At least one control terminal of the second output module is connected to the input terminal of the first inverter; at least one input terminal of the second output module is connected to the output terminal of the first inverter or receives a second input signal.

18. The display panel according to claim 8, characterized in that, At least one control terminal of the first output module is connected to the output terminal of the first inverter; At least one control terminal of the second output module is connected to the output terminal of the first inverter; at least one input terminal of the second output module is connected to the input terminal of the first inverter or receives a second input signal.

19. The display panel according to claim 8, characterized in that, The control module further includes a third inverter, the input of which is connected to the output of the first inverter. At least one control terminal of the first output module is connected to the output terminal of the third inverter; At least one control terminal of the second output module is connected to the output terminal of the third inverter, and at least one input terminal of the second output module is connected to the output terminal of the first inverter.

20. The display panel according to claim 8, characterized in that, One port of the first output module receives a refresh control signal; The first output module is configured to output the first scan signal based at least on the control signal output by the control module and the first level signal of the refresh control signal, and to output a low-level constant voltage signal based at least on the control signal output by the control module and the second level signal of the refresh control signal; The first level signal and the second level signal are respectively a high level signal and a low level signal.

21. The display panel according to claim 20, characterized in that, The first output module includes a sixth transistor and a seventh transistor, wherein the sixth transistor is a p-type transistor and the seventh transistor is an n-type transistor; The control terminals of the sixth transistor and the seventh transistor are respectively connected to the output terminal of the first inverter. The first terminal of the sixth transistor receives a refresh control signal, the first terminal of the seventh transistor receives a first voltage signal, and the second terminals of the sixth transistor and the seventh transistor are respectively connected to the output terminal of the first output module. The first level signal of the refresh control signal is a high level signal, and the second level signal is a low level signal.

22. The display panel according to claim 20, characterized in that, The first output module includes a sixth transistor, a seventh transistor, and a fourth inverter. The sixth transistor is a p-type transistor, and the seventh transistor is an n-type transistor. The control terminals of the sixth transistor and the seventh transistor are respectively connected to the output terminal of the first inverter. The first terminal of the sixth transistor receives a second voltage signal, and the first terminal of the seventh transistor receives a refresh control signal. The second terminals of the sixth transistor and the second terminals of the seventh transistor are respectively connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is the output terminal of the first output module. The first port of the fourth inverter receives a first voltage signal, and the second port receives the second voltage signal. The first level signal of the refresh control signal is a high level signal, and the second level signal is a low level signal.

23. The display panel according to claim 20, characterized in that, The first output module includes a sixth transistor, a seventh transistor, a fourth inverter, and a fifth inverter. The sixth transistor is a p-type transistor, and the seventh transistor is an n-type transistor. The control terminals of the sixth transistor and the seventh transistor are respectively connected to the output terminal of the first inverter. The first terminal of the sixth transistor receives a refresh control signal, the first terminal of the seventh transistor receives a first voltage signal, and the second terminals of the sixth transistor and the seventh transistor are respectively connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter. The output terminal of the fifth inverter is the output terminal of the first output module. The first port of the fourth inverter and the first port of the fifth inverter receive the first voltage signal. The second port of the fourth inverter and the second port of the fifth inverter receive the second voltage signal. The first level signal of the refresh control signal is a low level signal, and the second level signal is a high level signal.

24. The display panel according to claim 20, characterized in that, The first output module includes a NAND gate and a sub-output module; The first input terminal of the NAND gate is connected to the output terminal of the first inverter, the second input terminal of the NAND gate receives the refresh control signal, and the output terminal of the NAND gate is connected to the sub-output module; the NAND gate is configured to output a first control signal when the refresh control signal is a first level signal, and to output a second control signal when the refresh control signal is a second level signal. The sub-output module is configured to output the first scan signal based on the first control signal, the first voltage signal, and the second voltage signal output by the NAND gate, and to output a low-level constant voltage signal based on the second control signal, the first voltage signal, and the second voltage signal output by the NAND gate.

25. The display panel according to claim 24, characterized in that, The display panel includes a first signal line, which is used to provide the refresh control signal; the second input terminal of the NAND gate is connected to the first signal line.

26. The display panel according to claim 24, characterized in that, The first output module includes an input unit, the input terminal of which receives the refresh control signal, and the output terminal of which is connected to the second input terminal of the NAND gate; the input unit is configured to write the refresh control signal to the second input terminal of the NAND gate when it is enabled.

27. The display panel according to claim 26, characterized in that, The input unit includes an eighth transistor, which is a p-type transistor; the control terminal of the eighth transistor is connected to the output terminal of the first inverter; or, the input module includes a first sub-module and a second inverter, the first sub-module receives the first input signal, the output terminal of the first sub-module is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the first inverter, and the control terminal of the eighth transistor is connected to the output terminal of the first sub-module. Alternatively, the input unit may include an eighth transistor, which is an n-type transistor; The control terminal of the eighth transistor is connected to the input terminal of the first inverter.

28. The display panel according to claim 26, characterized in that, The first output module includes a second capacitor, the first plate of which is connected to the second input terminal of the NAND gate, and the second plate of which is connected to the constant voltage signal terminal.

29. The display panel according to claim 26, characterized in that, The first output module includes a latch, the input and output of which are respectively connected to the second input of the NAND gate.

30. The display panel according to claim 1, characterized in that, The second output module is configured to output at least one second scan signal based on a first voltage signal, a second voltage signal, at least one clock signal, and a control signal output by the control module and a signal output by the first output module, or the output signal of the first output module and a second input signal, or the control signal output by the control module, or the control signal output by the control module and a second input signal.

31. The display panel according to claim 30, characterized in that, The second output module includes at least one sub-module; One control terminal of the submodule is connected to the control module or the first output module; One input terminal of the submodule is connected to the control module or the first output module, or receives a second input signal.

32. The display panel according to claim 31, characterized in that, The submodule includes a ninth transistor, a tenth transistor, and an eleventh transistor; The control terminal of the ninth transistor receives a first voltage signal. The first terminal of the ninth transistor is connected to the control module, or connected to the first output module, or receives the second input signal. The second terminal of the ninth transistor is connected to the control terminal of the tenth transistor. The first terminal of the tenth transistor receives a second clock signal. The control terminal of the eleventh transistor is connected to the control module or the first output module. The first terminal of the eleventh transistor receives a second voltage signal. The output terminals of the tenth transistor and the eleventh transistor are connected to the output terminal of the sub-module.

33. The display panel according to claim 31, wherein One input terminal of the sub-module receives the second input signal through a second input module; The second input module is configured to write the second input signal to the sub-module based on the control of the first clock signal.

34. The display panel according to claim 33, wherein The second input module includes a twelfth transistor. The control terminal of the twelfth transistor receives the first clock signal. The input terminal of the twelfth transistor receives the second input signal. The output terminal of the twelfth transistor is respectively connected to the sub-module.

35. The display panel according to claim 7, wherein The shift register unit includes a first mode and a second mode; In the first mode, the first output module outputs the first scan signal, and the second output module outputs at least one of the second scan signals; In the second mode, the first output module outputs a low-level constant voltage signal, and the second output module outputs at least one of the second scan signals.

36. The display panel according to claim 35, wherein The refresh control signal includes a first level signal and a second level signal; The shift register includes N levels of the shift register unit, where N is an integer; The display panel includes a first refresh frame. In the first refresh frame: The j-th level to the q-th level of the shift register unit receive the first level signal of the refresh control signal, and the j-th level to the q-th level of the shift register unit are in the first mode; j and q are integers, 1 ≤ j < q < N; the (q + 1)-th level to the w-th level of the shift register unit receive the second level signal of the refresh control signal, and the (q + 1)-th level to the w-th level of the shift register unit are in the second mode; w is an integer, q + 1 < w ≤ N.

37. A display device, characterized in that, Including the display panel according to any one of claims 1 to 36.

38. A driving method for a display panel, characterized in that, The display panel includes a shift register. The shift register includes a plurality of cascaded shift register units. The shift register unit includes a control module, a first output module, and a second output module. The first output module is connected to at least one output terminal of the control module. The second output module is connected to at least one output terminal of the control module and / or connected to the output terminal of the first output module; The driving method includes: A first input signal is provided to the control module in the shift register unit, and the control module is controlled to output a control signal based at least on the first input signal. The first output module is controlled to output a first scan signal based on at least the control signal output by the control module, wherein a high level in the first scan signal is an enable level; The second output module is controlled to output at least one second scan signal based on the control signal output by the control module and / or the signal output by the first output module, wherein the low level in the second scan signal is an enable level.

39. The driving method according to claim 38, characterized in that, Providing a first input signal to the control module and controlling the control module to output a control signal based at least on the first input signal includes: providing the control module with the first input signal and a first clock signal, and controlling the control module to output a control signal; Controlling the first output module to output a first scan signal based at least on the control signal output by the control module includes: during the period when the pulse of the first input signal and the first low level of the first clock signal overlap, controlling the first output module to start outputting a high level signal of the first scan signal, and during the period when the non-pulse of the first input signal and the second low level of the first clock signal overlap, controlling the first output module to stop outputting a high level signal of the first scan signal, wherein the second low level is the s-th pulse signal after the first low level, and s is a positive integer; Controlling the second output module to output at least one second scan signal based on the control signal output by the control module and / or the signal output by the first output module includes: during the period when the first clock signal provides the first low level and the second low level, controlling the second output module to output at least one low-level signal of the second scan signal.

40. The driving method according to claim 39, characterized in that, During the period when the first clock signal provides the first low level and the second low level, controlling the second output module to output at least one low level signal of the second scan signal includes: controlling the second output module to output at least one low level signal of the second scan signal based on at least one clock signal, wherein the low level period of the clock signal received by the second output module corresponds to the low level period of the second scan signal.

41. The driving method according to claim 40, characterized in that, Controlling the second output module to output at least one low-level signal of a second scan signal based at least on the control signal output by the control module and / or the signal output by the first output module includes: controlling the second output module to output at least one low-level signal of a second scan signal based at least on the second input signal, the control signal output by the control module, or the signal output by the first output module, wherein the second input signal is written to the second output module during the period when the first clock signal provides a low level.

42. The driving method according to claim 38, characterized in that, Controlling the first output module to output a first scan signal based at least on the control signal output by the control module includes: controlling the first output module to output the first scan signal based at least on a first level signal of a refresh control signal and the control signal output by the control module; The driving method further includes: controlling the first output module to output a low-level constant voltage signal based at least on the second-level signal of the refresh control signal and the control signal output by the control module; one of the first-level signal and the second-level signal is a high-level signal and the other is a low-level signal.

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