Method of controlling micro light emitting cell array display, display and program product

Abstract

The application discloses a control method of a micro light-emitting unit array display, the display and a computer program product. By improving the display structure, a control module and a scanning drive are additionally arranged on the basis of connecting with a liquid crystal panel driving board, so that the display has fine regulation and control ability on the pixel scanning timing. In the current frame display process, the control module generates a scanning instruction according to a preset display timing, and controls the scanning drive to perform zone-by-zone scanning on the pixels of each subzone of the liquid crystal panel in the timing. For the target subzone pixels to be scanned, after completing the conventional display scanning, the scanning drive is used for shutdown control, so that the corresponding liquid crystal is quickly restored to a low light transmission state after completing the gray scale deflection. In this way, the display and non-display periods of the pixels are reasonably distributed in a single frame period, the effective display time of the pixels can be effectively shortened, the trailing and residual image phenomena in the motion picture can be inhibited, and the picture definition and overall display quality in the dynamic scene are improved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a control method for a micro light-emitting unit array display, a micro light-emitting unit array display, and a computer program product. Background Technology

[0002] In existing display panel driving methods, pixels typically maintain their display state continuously within one frame cycle. When the displayed content contains fast-moving targets or significant scene changes, due to the persistence and tracking characteristics of human vision, problems such as blurred images, increased ghosting, and decreased dynamic clarity can easily occur, thus affecting the user's ability to recognize moving images.

[0003] Currently, most related technologies improve the above phenomenon by increasing the refresh rate or enhancing the pixel driving capability. However, such methods are often limited by panel hardware conditions and power consumption costs, and their improvement effect is limited. Moreover, it is difficult to reduce the visual ghosting effect caused by the continuous retention of pixels from the display mechanism level. Summary of the Invention

[0004] This application provides a control method for a micro light-emitting unit array display, a micro light-emitting unit array display, and a computer program product. By rationally allocating the display and non-display periods of pixels within a single frame cycle, the effective display time of pixels can be effectively shortened, and trailing and ghosting phenomena in moving images can be suppressed, thereby improving the image clarity and overall display quality in dynamic scenes.

[0005] In a first aspect, this application provides a control method for a micro-light-emitting unit array display, applied to the processor of the display, wherein the display is provided with a control module and a scanning driver connected to the driver board of the display's liquid crystal panel;

[0006] During the display of the current frame, the control module generates a scanning command according to the determined display timing and sends the scanning command to the scanning driver; The scanning driver scans the pixels of each zone of the LCD panel of the display according to a preset timing sequence. For each target partition pixel being scanned, the scan driver sequentially performs a regular scan and a black-insertion scan on the partition pixels based on the scan command.

[0007] This control method is applied to the processor of a display. The display is equipped with a control module and a scan driver connected to the LCD panel driver board, enabling the display to perform fine-grained timing control of the pixel scanning process. In general displays, the liquid crystal maintains a grayscale state continuously during the display of a single frame until the next frame is scanned, at which point it flips. If the liquid crystal does not return to its initial state in time, the information displayed in the previous and next frames will be visually superimposed, resulting in dynamic display problems such as ghosting and trailing. To solve this problem, during the display of the current frame, the control module generates a scan command according to a preset display timing and drives the scanning unit to perform zone-by-zone scanning control on multiple pre-divided pixel partitions in the LCD panel. For each target pixel partition being scanned, after the normal display scan is completed, the scan driver controls the pixel partition to be turned off, so that the corresponding liquid crystal returns to a low-transmittance state for the remaining time of the current frame, visually achieving grayscale "zeroing" and effectively shortening the effective display time of the pixel. Compared to the full-screen synchronous black insertion technique, the partition-by-partition scanning method ensures that the display or non-display duration of pixels in each area is strictly consistent, thus guaranteeing image consistency. In other words, this control method does not have the problem of not following the LCD gate scan, which can easily cause inconsistent display or black insertion durations in different areas and exacerbate visual unevenness. On this basis, combined with the time-sharing display and shutdown of pixels in the same partition, it can also significantly suppress ghosting and trailing phenomena in dynamic scenes, improving the overall image clarity and dynamic display quality.

[0008] Furthermore, the control method for dividing the backlight of the display into different zones based on the pixels of each zone also includes: When the scanning driver scans the pixels of each zone of the LCD panel based on a preset timing sequence, it also scans the backlight of each zone synchronously based on the preset timing sequence. For the target partition backlight corresponding to the target partition pixel, perform regular scanning and black insertion scanning on the partition pixel in sequence based on the scanning driver, and turn the target partition backlight on or off.

[0009] The processor incorporates backlight black insertion control while performing panel black insertion, ensuring that the backlight black insertion's on / off state strictly follows the panel black insertion scan sequence. When a panel pixel enters a non-display state, the corresponding area's backlight is simultaneously turned off to prevent amplified light transmission during the liquid crystal flip-flop phase. When the pixel resumes display, the backlight is turned on again, thus improving effective brightness utilization while maintaining consistent black insertion results. Through the coordinated operation of panel black insertion and backlight black insertion, dynamic sharpness is significantly improved while maintaining brightness performance and visual stability, further enhancing the overall display experience in high-speed motion scenarios.

[0010] Furthermore, before turning the target zone backlight on or off, the following steps are also included: Get the input refresh rate of the current frame; If the input refresh rate falls within the first refresh rate range, the preset refresh rate will be set as the target refresh rate. If the input refresh rate falls within the second refresh rate range, the input refresh rate is multiplied to obtain the target refresh rate; the minimum value of the second refresh rate range is greater than the maximum value of the first refresh rate range. If the input refresh rate is greater than the preset refresh rate, the input refresh rate will be set as the target refresh rate. Accordingly, turning the target zone backlight on or off includes: Turn the target partition backlight on or off based on the target refresh rate.

[0011] In VRR mode, the actual refresh rate of the display always remains consistent with the input refresh rate, thus achieving synchronization between input and display output under variable refresh rate conditions and avoiding screen tearing. Addressing the issue of difficulty in executing black insertion at low refresh rates, the micro-LED array display dynamically generates a target refresh rate for backlight black insertion based on the input refresh rate. By dividing different refresh rate ranges and determining corresponding generation strategies, backlight black insertion meets the execution conditions throughout the entire VRR operating range, thereby avoiding backlight black insertion failure, flickering, or brightness abrupt changes caused by excessively low or fluctuating refresh rates. Based on the target refresh rate and combined with the liquid crystal response stage corresponding to the backlight in the current frame cycle, the display can precisely control the backlight to be turned off in non-lit windows and turned on at the target brightness in lit windows, achieving coordinated matching of the backlight black insertion window, backlight brightness, and refresh timing. Through this control method, not only can the backlight illumination time be effectively shortened, liquid crystal residue suppressed to improve dynamic image clarity and reduce motion blur, but the stability and overall display performance of the display in variable refresh rate scenarios can also be significantly improved while maintaining refresh synchronization.

[0012] Furthermore, the target zone backlight is illuminated, including: Obtain the partition image data of the target partition backlight in the current frame; Brightness feature analysis is performed on partitioned image data to obtain the corresponding brightness feature parameters; Find the backlight control parameters corresponding to the brightness characteristic parameters from the preset mapping table; The target zone backlight is illuminated based on the backlight control parameters.

[0013] To improve overall display quality by implementing differentiated backlight compensation for different pixel zones, the processor acquires the image data of the target zone's backlight in the current frame, performs brightness feature analysis on the data, and extracts brightness feature parameters reflecting the area's brightness distribution. Then, based on these parameters, it matches corresponding backlight control parameters in a preset mapping table and independently controls the backlight illumination of the target zone. This method ensures precise matching between the brightness output of each backlight zone and its corresponding pixel content, maintaining contrast in dark areas and detail in bright areas while reducing unnecessary backlight over-illumination. This effectively improves the uniformity and depth of the image contrast, and enhances visual consistency and overall display performance in high dynamic range scenes.

[0014] Furthermore, when the dimming current of the display backlight is changed from DC dimming to high-frequency PWM dimming, if the difference between the first current value of DC dimming and the second current value of high-frequency PWM dimming is greater than a preset current threshold, then a variable drive current for each frame is generated based on the time information corresponding to a specified number of frames to be processed, and the brightness of each frame to be processed is adjusted based on the corresponding variable drive current.

[0015] This frame-by-frame current transition strategy enables smooth switching between DC dimming and high-frequency PWM dimming, avoiding brightness jumps or flickering caused by sudden current changes, thereby effectively improving image stability and user viewing comfort when switching dimming modes.

[0016] Furthermore, before the control module generates the scanning command according to the determined display timing, it also includes: Get the input refresh rate of the current frame; Determine the frame time corresponding to the current frame based on the input refresh rate; Determine the matching pixel response acceleration parameters based on the input refresh rate or frame time; Generate corresponding pixel driving signals based on pixel response acceleration parameters; The display timing of the current frame is determined based on the frame time and the preset black-and-white interpolation ratio. Accordingly, the control module generates scanning instructions based on the determined display timing, including: Scan commands are generated based on display timing and pixel drive signals.

[0017] Based on the current frame input refresh rate and the corresponding frame time, the processor dynamically matches pixel response acceleration parameters that are compatible with the refresh rate or frame time, and generates corresponding pixel drive signals accordingly. This allows the pixels to achieve a more sufficient voltage transition before the display and panel black-insertion transition. By considering the pixel response acceleration parameters in conjunction with the current frame display timing and panel black-insertion ratio, the return speed and consistency of the LCD during the panel black-insertion stage can be effectively improved, reducing the interference of residual grayscale on the display of subsequent frames. This results in a stable enhancement of the panel black-insertion effect under different refresh rate conditions, reducing ghosting and trailing problems, and improving the clarity and visual stability of dynamic images.

[0018] Furthermore, the partitioned pixels are row partitioned pixels, and the scan driver scans each partitioned pixel of the display's LCD panel area by area based on a preset timing sequence, including: The LCD scanning direction of the micro-light-emitting unit array display scans the pixels of each row partition based on the preset timing.

[0019] The processor sets the partitioned pixels as row partitioned pixels and causes the scan driver to scan each row partitioned pixel area by area according to a preset timing sequence consistent with the LCD scanning direction. This ensures that after each row of pixels completes normal display, it enters the non-display state under the same timing conditions. Through this row-level partitioned scanning method, the effective display time and black insertion time of each row of pixels are kept highly consistent, thereby avoiding regional timing deviations caused by full-screen or asynchronous black insertion. This significantly improves the spatial consistency and stability of dynamic images and further enhances the image clarity and display quality in high-speed motion scenes.

[0020] Secondly, this application provides a miniature light-emitting unit array display, including a processor, a memory, a driver board for the display liquid crystal panel, a control module, and a scan driver. The processor is connected to the driver board, and the driver board is connected to the control module and the scan driver. When the processor runs the computer program stored in the memory, it can implement some of the steps of the method described in the first aspect above.

[0021] Furthermore, it also includes a backlight control system controlled by a processor, which, when running a computer program stored in memory, can follow the steps of the method described in the first aspect above. The backlight control system includes: Main control board used to generate backlight zone brightness data; A micro-light-emitting unit array backlight driver board that communicates with the main control board; Multiple driver ICs are cascaded through the OWC bus, and these driver ICs are used to drive the corresponding micro light-emitting units to output backlight brightness.

[0022] Thirdly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0023] Fourthly, this application provides a computer program product comprising a computer program that, when executed by one or more processors, implements the steps of the method described in the first aspect.

[0024] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of the driving board of the liquid crystal panel provided in the embodiments of this application; Figure 2 This is a flowchart illustrating the control method for a micro-light-emitting unit array display provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the micro-light-emitting unit array display provided in the embodiments of this application; Figure 4 This is a schematic diagram of the backlight processing system of the micro-light-emitting unit array display provided in the embodiments of this application. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] Related technologies often improve the above phenomenon by increasing the refresh rate or enhancing the pixel driving capability. However, such methods are often limited by panel hardware conditions and power consumption costs, and their improvement effect is limited. Moreover, it is difficult to reduce the visual ghosting effect caused by the continuous retention of pixels from the display mechanism level.

[0029] To address the aforementioned issues, this application improves the display structure by adding a control module and a scan driver to the existing connection with the LCD panel driver board, enabling the display to finely control the pixel scanning timing. During the display of the current frame, the control module generates scan commands based on a preset display timing and controls the scan driver to scan each zone of the LCD panel sequentially. For the target zone pixel being scanned, after completing the regular display scan, the newly added scan driver controls its shutdown, allowing the corresponding liquid crystal to return to a low-transmittance state after completing grayscale deflection. By rationally allocating the display and non-display periods of pixels within a single frame cycle, the effective display time of pixels can be effectively shortened, suppressing trailing and ghosting phenomena in moving images, thereby improving image clarity and overall display quality in dynamic scenes.

[0030] The control method for a micro-light-emitting unit array display provided in this application is applicable to various display devices employing micro-light-emitting unit arrays, such as Mini / Micro LED displays; it can also be applied to electronic devices that are communicatively connected to the display, including but not limited to mobile phones, tablets, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). This application does not limit the specific type of the aforementioned electronic devices.

[0031] In some embodiments, Figure 1 A schematic diagram of the LCD panel driver board is shown. The display signal enters the LCD panel driver board, which outputs the main scan signal Li / Sc1. This signal is then sent to the first gate driver unit G / A1 in the LCD panel via the panel driver interface. G / A1 performs a conventional line-by-line charging scan on the pixel rows to complete the image display. Simultaneously, a control module and an auxiliary scan driver are added to the LCD panel driver board. The control module, which can be implemented by an MCU, generates an auxiliary scan control signal Li / Sc2 based on the synchronously acquired main scan timing and sends it to the second gate driver unit G / A2. After each zone pixel completes its display scan, G / A2 performs a shutdown scan on the corresponding zone pixel to achieve black-insertion control of the zoned panel. By ensuring a strict timing correspondence between Li / Sc2 and Li / Sc1, a row-level zoned scan mechanism of paired execution of "display scan - shutdown scan" is formed. This ensures that the display time and non-display time of each row pixel on the LCD panel are consistent, avoiding differences in display duration between different row areas caused by full-screen black-insertion or asynchronous panel black-insertion, thereby improving the spatial consistency and visual stability of dynamic images.

[0032] To illustrate the technical solutions proposed in this application, the following description will use the processor of a Mini LED display as the execution subject to illustrate various embodiments.

[0033] Figure 2 A schematic flowchart of a control method for a micro-light-emitting unit array display provided in this application is shown. The control method for the micro-light-emitting unit array display includes: Step 210: During the display of the current frame, the processor generates a scan instruction through the control module according to the determined display timing, and sends the scan instruction to the scan driver.

[0034] To achieve precise pixel scanning and panel black-insertion control during the display of the current frame, the processor first determines the frame time of the current frame (e.g., based on the input refresh rate), and then, in conjunction with the LCD's partitioned pixels, scanning direction, and preset black-insertion ratio, divides the current frame into display and black-insertion periods, thus determining the complete frame-level display timing. The black-insertion ratio limits the proportion of time a pixel is in display and non-display states; different black-insertion ratios correspond to different effective display time lengths, thus affecting the clarity of dynamic images. After the display timing is determined, the processor generates a scan command matching the current frame through the control module and sends the scan command to the scan driver.

[0035] Step 220: The processor scans the pixels of each zone of the display's LCD panel according to a preset timing using a scan driver.

[0036] Step 230: For each target partition pixel being scanned, the processor performs a regular scan and a black-insertion scan on the partition pixels sequentially based on the scan instructions through the scan driver.

[0037] The processor uses a scan driver to perform zone-by-zone scanning control on multiple pre-divided pixel partitions in the LCD panel according to a preset scanning timing sequence. By dividing the entire screen pixels into multiple scanning partitions and scanning them sequentially, the scanning process of each partition pixel is matched with the actual gate scanning direction and response characteristics of the LCD, avoiding timing deviations introduced by full-screen synchronous control and improving the consistency of display control in the spatial dimension.

[0038] For each target partition pixel, during the execution of the scanning instruction, the processor controls the first gate driving unit G / A1 to generate a start signal STV for regular display scanning, and performs partition-by-partition display scanning on the LCD panel pixels through Li / Sc1; at the same time, it controls the second gate driving unit G / A2 to generate a start signal DSTV for black insertion scanning, and performs a shutdown scan on the corresponding row pixel after it is displayed through Li / Sc2, so that the corresponding liquid crystal returns to a low transmittance state in the remaining time of the current frame, visually achieving grayscale regression and effectively shortening the effective display time of the pixel.

[0039] Compared to full-screen synchronous panel black insertion technology, this scanning method does not have the problem of not strictly following the LCD gate scan, which can easily lead to inconsistent display time or black insertion time in different row areas, thus aggravating visual unevenness. The processor coordinates the timing relationship of the two scanning signals according to the black insertion ratio within the same frame cycle, so that the display time of each partition pixel is consistent with the black insertion time. This provides a unified, accurate and adjustable timing reference for partition scanning and black insertion control, significantly improving the clarity and display stability of dynamic images.

[0040] The black insertion ratio of the panel can be dynamically adjusted according to display requirements. When the black insertion ratio increases, the time that pixels are in a non-display state within a single frame cycle is correspondingly extended, and the effective display time of the liquid crystal is further compressed. This helps to accelerate pixel grayscale return and significantly suppress ghosting and trailing phenomena in fast-moving scenes, thereby improving the clarity of dynamic images. However, at the same time, due to the reduction in effective light-emitting time, the overall brightness of the image decreases accordingly, and an excessively large black insertion ratio may also introduce perceptible flicker. Conversely, when the black insertion ratio decreases, the effective display time of pixels increases, and the brightness and stability of the image are improved. However, the ability to suppress liquid crystal grayscale residue is relatively weakened, and the trailing phenomenon may increase in fast-moving scenes.

[0041] Based on the aforementioned trade-offs, the display period and black insertion period can be adjusted within each frame cycle to achieve dynamic control of the panel's black insertion ratio. Specifically, the timing ratio of display scan and black insertion scan within a frame time can be dynamically adjusted according to the current input refresh rate, screen motion intensity, or brightness requirements, thereby achieving a balance between dynamic clarity, brightness performance, and visual stability, ensuring that the monitor maintains good display performance in different application scenarios.

[0042] In this embodiment, in a typical display, the liquid crystal maintains a grayscale state continuously during a single frame display until the next frame is scanned, at which point it flips. The liquid crystal fails to return to its initial state in time, causing visual superposition of information from previous and subsequent frames, resulting in dynamic display problems such as ghosting and trailing. To solve this problem, during the display of the current frame, the control module generates scanning instructions according to a preset display sequence and drives the scanning unit to perform zone-by-zone scanning control on multiple pre-divided pixel partitions in the liquid crystal panel. For each scanned target pixel partition, after completing the regular display scan, the scanning driver controls the pixel partition to be turned off, causing the corresponding liquid crystal to return to a low-transmittance state for the remaining time of the current frame, visually achieving grayscale "zeroing" and effectively shortening the effective display time of the pixel. Compared to the technology of full-screen synchronous panels, it is less likely to have problems such as black insertion not following the LCD gate scan, which can easily cause inconsistent display time or black insertion time in different areas and exacerbate visual unevenness. The partition scanning method can ensure that the display or non-display time of pixels in each area is strictly consistent, thereby significantly suppressing afterimages and trailing phenomena in dynamic scenes while ensuring image consistency, and improving the overall image clarity and dynamic display quality.

[0043] In some embodiments, although black pixel insertion control on the panel side can shorten the effective display time of the liquid crystal from the pixel driving level, thereby suppressing ghosting and trailing phenomena in dynamic scenes at the source, the overall effective light emission time is compressed because the pixels are in a non-display state during the black pixel insertion phase, which can easily lead to a decrease in screen brightness. Furthermore, when only panel black pixel insertion is performed, the liquid crystal is still in the flip-up or recovery process during the insertion period, and its light transmission state is not completely stable, which may still produce residual visual artifacts in high-speed motion scenes. To solve this problem, the processor can divide the backlight of the display into different zones based on the pixels in each zone and perform the following steps: Step A1: When the scanning driver scans the pixels of each zone of the LCD panel of the display according to the preset timing, the backlight of each zone is scanned synchronously according to the preset timing.

[0044] During the scanning process of the LCD panel, which scans each pixel zone according to a preset timing sequence, the backlight corresponding to each pixel zone is simultaneously scanned and controlled. This establishes a timing relationship between pixel scanning and backlight control, ensuring that the illumination and deactivation of the backlight zones strictly follow the scanning rhythm of the pixel zones. This provides a foundation for precise backlight control during the subsequent display and panel black-out stages.

[0045] Step A2: For the target partition backlight corresponding to the target partition pixel, perform regular scanning and black insertion scanning on the partition pixel in sequence based on the scanning driver, and turn the target partition backlight on or off.

[0046] For the target partition backlight corresponding to the target partition pixels, during the scanning drive's sequential execution of regular display scanning and panel black insertion scanning of the partition pixels, the target partition backlight is controlled to be lit during the display scanning phase and turned off during the panel black insertion scanning phase. Specifically, when performing line-by-line display scanning of each row of pixels on the LCD panel via Li / Sc1, the corresponding target partition backlight is simultaneously lit; when performing a shutdown scan after the corresponding row of pixels has been displayed via Li / Sc2, the target partition backlight is simultaneously turned off. By ensuring that the backlight's lighting and turning-off sequence is strictly consistent with the display and non-display states of the partition pixels, it is possible to effectively prevent the LCD from being illuminated by the backlight during the flip-out or recovery phase, reducing the impact of LCD residue on visual imaging, thereby suppressing artifacts, trailing, and ghosting phenomena in dynamic images, and improving overall display clarity and visual stability.

[0047] In this embodiment, the processor introduces backlight black insertion control while performing panel black insertion, and ensures that the activation and deactivation of backlight black insertion strictly follow the scanning sequence of panel black insertion. When a panel pixel enters a non-display state, the backlight of the corresponding area is simultaneously turned off to prevent amplification of light transmission during the liquid crystal flip-flop phase; when the pixel resumes display, the backlight is turned on again, thereby improving the effective brightness utilization while ensuring the consistency of black insertion effect. Through the coordinated operation of panel black insertion and backlight black insertion, dynamic clarity can be significantly improved while also taking into account brightness performance and visual stability, further enhancing the overall display experience in high-speed motion scenes.

[0048] In some embodiments, before turning the target partition backlight on or off, the method further includes: Step B1: The processor obtains the input refresh rate of the current frame.

[0049] It can receive synchronization signals and image data from image signal sources (GPUs, game consoles, home consoles, etc.) through interface circuits (such as HDMI, DP, eDP, etc.), and then detect the time interval between the vertical synchronization signals (Vsync) of two adjacent frames, or parse the timing control information at the input end, to calculate the input refresh rate corresponding to the current frame in real time. For example, using the frame period T as the unit, the current frame refresh rate f_in = 1 / T can be obtained, and this refresh rate can be used as the basic parameter for subsequent timing generation and VRR mode control.

[0050] By dynamically acquiring the input refresh rate of each frame, the display can accurately sense the real-time changes in the output frame rate of the signal source, providing the prerequisite for "source-driven" refresh control in VRR mode. This avoids the input-output asynchrony problem caused by using a fixed refresh rate, laying the foundation for subsequent suppression of screen tearing and reduction of stuttering.

[0051] For example, after obtaining the current frame input refresh rate f_in, considering the inherent row scanning characteristics and row clock parameters of the panel, the timing controller can determine the panel scanning timing for that frame. The panel scanning timing can include the start time of line-by-line scanning, the row period, and the time required for the entire frame scan. Simultaneously, to match the total panel frame period with 1 / f_in, while keeping the panel row scanning timing essentially unchanged, the duration of the inter-frame blank interval (Vblank) is adjusted so that the sum of "scan time + blank interval" equals the current frame period. This allows for the generation of a corresponding set of timing parameters for each frame input refresh rate, enabling dynamic adjustment of the frame period.

[0052] Based on the adaptive generation of the input refresh rate, the panel scanning timing and inter-frame blanking interval are generated, so that the physical refresh cycle of the panel can accurately follow the output rhythm of the signal source. This enables the basic framework of VRR to be implemented at the hardware level, ensuring that the display cycle of each frame corresponds one-to-one with the input frame cycle and eliminating the time mismatch caused by fixed timing.

[0053] Then, the processor drives the row and column drive circuits according to the panel scanning timing to scan and write the current frame image data row by row. Within the predetermined inter-frame blank interval, it stops writing valid images, performs row / column resets, or performs other backlight control operations. By strictly following this timing to perform scanning and blank switching, the display completes the display refresh of the current frame and continues the above process in the next frame according to the updated input refresh rate.

[0054] By performing actual refresh based on panel scanning timing and inter-frame blanking intervals, the actual refresh rate of the display is kept synchronized with the input refresh rate, achieving input and output synchronization in VRR mode and fundamentally suppressing screen tearing. On the other hand, due to the smooth transition of each frame refresh cycle and the absence of redundant duplicate frames or forced frame drops, stuttering and input latency can be significantly reduced. This ensures smoothness of the image while improving overall display stability, providing a reliable timing foundation for the subsequent overlay of advanced display algorithms such as BFI, LocalDimming, and / or SDR / HDR in VRR mode.

[0055] Step B2: If the input refresh rate falls within the first refresh rate range, the processor determines the preset refresh rate as the target refresh rate.

[0056] In VRR mode, the processor first obtains the input refresh rate f_in of the current frame, which may be in a wide variable range (e.g., 48Hz to 500Hz). Since effective backlight black insertion (BFI) usually requires a refresh rate no lower than a preset threshold (e.g., 100Hz), otherwise an excessively long black insertion period will cause flickering and make it difficult to achieve the expected dynamic sharpness improvement, this step does not directly use f_in as the driving frequency of BFI. Instead, f_in is converted to generate a target refresh rate f_target specifically for BFI control.

[0057] The first refresh rate range falls within the low refresh rate segment of VRR mode. When the processor detects that the input refresh rate falls within this range (e.g., 48Hz~50Hz), directly performing backlight black insertion based on the input refresh rate can easily lead to insufficient brightness maintenance time due to excessively long frame periods, resulting in a significant decrease in brightness, increased flickering, and failure of BFI to start normally. To ensure that black insertion remains feasible within this refresh rate range, the processor directly selects the preset refresh rate as the target refresh rate and uses it as the driving timing for backlight black insertion. By using a fixed refresh rate with a minimum black insertion execution threshold as the control basis for BFI, the black insertion failure problem caused by low refresh rates can be effectively avoided, ensuring stable BFI operation can still be maintained in the lowest refresh rate segment of VRR mode.

[0058] Step B3: If the input refresh rate falls within the second refresh rate range, the processor performs a frequency multiplication calculation on the input refresh rate to obtain the target refresh rate.

[0059] The second refresh rate range falls within the low to medium refresh rate range. Although its input refresh rate is higher than that of the first refresh rate range, it is still insufficient to meet the minimum refresh rate requirement of BFI. If the input refresh rate is used directly for black line insertion, it may still cause flickering, sudden drops in brightness, or excessively long black line insertion intervals. Therefore, when the input refresh rate falls into the second refresh rate range (e.g., 50Hz to 100Hz), the processor performs a frequency multiplication calculation on the input refresh rate and uses the multiplied result as the target refresh rate for backlight black line insertion. By generating a target refresh rate that follows the same trend as the input refresh rate but with a higher value, BFI can obtain sufficient execution frequency in this range, while avoiding discontinuous brightness or dynamic performance caused by directly jumping to a fixed threshold, thus achieving stable operation of backlight black line insertion timing in the low to medium refresh rate range.

[0060] It's understandable that for input refresh rates falling within the first refresh rate range, a fixed refresh rate is used as the target refresh rate, while for input refresh rates falling within the second refresh rate range, a frequency multiplication is used to calculate the target refresh rate. This is determined based on the characteristics of the input refresh rate and the differentiated requirements of backlight insertion execution conditions within different ranges. The first refresh rate range belongs to the extremely low refresh segment of VRR mode. The input refresh rate is not only far below the backlight insertion execution threshold, but also typically exhibits a large proportion of jitter between adjacent frames. If a frequency multiplication method is used, the multiplied target refresh rate will jitter synchronously with the input refresh rate, causing frequent changes in key parameters such as backlight insertion timing, brightness compensation, and backlight windowing, making it difficult to establish a stable cycle for backlight insertion. Therefore, directly using a fixed preset refresh rate equal to the minimum execution threshold in this range can provide a stable timing basis for insertion, avoiding flickering and brightness jumps.

[0061] In contrast, while the second refresh rate range is still below the backlight black insertion threshold, its input refresh rate changes more gently, and the inter-frame jitter is significantly smaller than that of the first range. At this point, by multiplying the input refresh rate, the target refresh rate can meet the backlight black insertion requirements while maintaining a trend consistent with the input refresh rate. This avoids the brightness discontinuity caused by a direct jump to a fixed value and ensures a smooth transition in the backlight black insertion timing. Therefore, the hierarchical strategy of using a fixed refresh rate in the first range and a multiplied target refresh rate in the second range can simultaneously ensure backlight black insertion stability and timing continuity in the low and medium refresh rate ranges, achieving better dynamic image quality performance.

[0062] Step B4: If the input refresh rate is greater than the preset refresh rate, the input refresh rate is set as the target refresh rate.

[0063] When the input refresh rate is already greater than the preset refresh rate threshold, it indicates that the current refresh conditions are sufficient to support the normal execution of BFI. Forcibly increasing or doubling the input refresh rate at this point could easily disrupt the real-time synchronization characteristics of VRR mode, affecting display stability and brightness consistency. Therefore, when the input refresh rate exceeds the preset threshold, the processor directly uses the input refresh rate as the target refresh rate for backlight black-insertion control. By keeping the target refresh rate consistent with the input refresh rate, the dynamic sharpness advantage of BFI can be maximized in the high refresh range, and the backlight black-insertion timing can be completely synchronized with the panel refresh, achieving optimal motion picture quality performance.

[0064] Accordingly, once the target refresh rate is obtained, the target partition backlight can be turned on or off based on the target refresh rate, thereby ensuring that backlight black insertion can still be performed stably in VRR mode.

[0065] In this embodiment, a target refresh rate generation mechanism is determined by using different refresh rate ranges. This provides a target refresh rate that meets the execution conditions for backlight black insertion dynamics throughout the entire VRR operating range, enabling BFI to operate stably across the entire refresh rate range from extremely low to high, avoiding flickering, failures, or brightness jumps caused by excessively low refresh rates or refresh rate variations. This not only significantly improves the clarity of dynamic images and effectively reduces motion blur, but also suppresses screen tearing while maintaining VRR mode input-output synchronization, thereby comprehensively improving the processor's display stability, consistency, and overall image quality performance under variable refresh rate conditions.

[0066] In some embodiments, in order to implement differentiated backlight compensation for different pixel zones and thereby improve the overall display quality, the processor can illuminate the target zone backlight through the following steps: Step C1: The processor acquires the partition image data of the target partition backlight in the current frame.

[0067] The processor acquires the partition image data corresponding to the target partition backlight in the current frame. The partition image data reflects the brightness distribution of pixels within the partition. In SDR mode, it mainly reflects the average brightness and contrast relationship, while in HDR mode, it further includes information such as peak brightness, brightness range, and the ratio of bright to dark areas, providing basic data for subsequent partition backlight adjustment.

[0068] Step C2: The processor performs brightness feature analysis based on the partitioned image data to obtain the corresponding brightness feature parameters.

[0069] The processor performs luminance feature analysis on the acquired partitioned image data and extracts luminance feature parameters to characterize the luminance properties of the partition. In SDR mode, the luminance feature parameters can focus on the average luminance or grayscale range of the partition; in HDR mode, the luminance feature parameters can further reflect the proportion of bright pixels, peak luminance level, or luminance dynamic range to distinguish between the needs of highlight enhancement and dark area suppression.

[0070] Step C3: The processor searches for the backlight control parameters corresponding to the brightness characteristic parameters from a preset mapping table.

[0071] Based on the brightness characteristic parameters, the processor looks up the corresponding backlight control parameters from the preset mapping table (LUT). The mapping table can be configured for SDR display mode and HDR display mode respectively. In SDR mode, the backlight control parameters prioritize ensuring the uniformity of brightness in each area and the stability of the image display. In HDR mode, the backlight control parameters are used to enhance the backlight output in bright areas and suppress backlight overflow in dark areas, thereby balancing the performance of bright details and the improvement of dark contrast.

[0072] Step C4: The processor illuminates the target zone backlight based on the backlight control parameters.

[0073] Based on the found backlight control parameters, the processor controls the illumination of the target zone backlight. By independently adjusting the brightness output of each zone's backlight, the backlight brightness is matched to the pixel content of the corresponding zone, thereby achieving fine-grained zone backlight compensation.

[0074] In this embodiment, the solution can perform targeted backlight compensation control on the pixel content of each zone in different display modes of SDR and HDR, so that bright areas receive sufficient brightness output and dark areas are prevented from being over-lit. This method not only improves the contrast, sense of layering and brightness consistency of the picture, but also fully leverages the advantages of high dynamic range in HDR scenes and maintains stable and natural display in SDR scenes, thereby significantly improving the overall display quality and visual experience.

[0075] In some embodiments, when the dimming current of the display backlight is changed from DC dimming to high-frequency PWM dimming, if the difference between the first current value of DC dimming and the second current value of high-frequency PWM dimming is greater than a preset current threshold, then a variable drive current for each frame is generated based on the time information corresponding to a specified number of frames to be processed, and the brightness of each frame to be processed is adjusted based on the corresponding variable drive current.

[0076] In the backlight system of Mini LED displays, DC dimming and high-frequency PWM dimming are two different dimming methods. DC dimming changes brightness by adjusting the steady-state current of the backlight, while high-frequency PWM dimming controls brightness by adjusting the duty cycle of the backlight. Due to the significant differences in their current waveform characteristics and brightness generation mechanisms, when switching from DC dimming to high-frequency PWM dimming, there is usually a large current difference between the first current value used by DC dimming and the second current value used by PWM dimming.

[0077] If the difference between these two current values ​​exceeds a preset current threshold, it indicates that a significant brightness jump will occur during the dimming mode switch, potentially causing visible flicker or drastic brightness changes. Therefore, upon detecting that the difference exceeds the threshold, the processor does not directly switch between the two current values. Instead, it generates a series of frame-by-frame varying drive currents based on the temporal distribution of a specified number of frames to be processed. In short, the current difference between the first and second current values ​​is distributed across several consecutive frames, allowing the drive current used in each frame to be gradually adjusted based on the previous frame. Subsequently, the backlight brightness in each frame is adjusted according to the corresponding varying drive current.

[0078] This frame-by-frame current transition strategy enables smooth switching between DC dimming and high-frequency PWM dimming, avoiding brightness jumps or flickering caused by sudden current changes, thereby effectively improving image stability and user viewing comfort when switching dimming modes.

[0079] In some embodiments, the control method further includes: if the difference between the first current value of DC dimming and the second current value of high-frequency PWM dimming is greater than a preset current threshold, then the on-time of the display backlight is increased and the peak current of the display backlight is increased.

[0080] In addition to performing frame-by-frame current transitions, the processor can also enhance the brightness during the backlight activation phase to further reduce brightness jumps. Specifically, by increasing the backlight's on-time (i.e., extending the BFI activation window or increasing the PWM duty cycle) and increasing the backlight's peak current, the processor can compensate for the brightness loss caused by dimming mode switching at the moment of activation. These two compensation measures work together to enable the backlight to achieve brightness output close to or continuous with DC dimming mode even in high-frequency PWM dimming mode.

[0081] By increasing the on-time and peak current when the difference exceeds the threshold, the brightness compression caused by black insertion can be effectively balanced, and the brightness drop or flicker caused by dimming mode switching can be reduced, thereby ensuring the stability of brightness output and maintaining a consistent visual effect in dynamic scenes and VRR mode.

[0082] In some embodiments, after the processor enables VRR mode, to address the issue that motion clarity (based on BFI) cannot function properly at refresh rates below 100Hz, the following operations can be performed: It is known that BFI is enabled when the refresh rate is higher than 100Hz, and when enabled, the backlight dimming method will switch from DC dimming to high-frequency PWM dimming. When the input refresh rate in VRR mode fluctuates randomly to below 100Hz, BFI is prone to being forced to shut down because the enable condition is not met, resulting in a significant jump in backlight brightness and display effect. The following strategies can be used to achieve stable operation of BFI and smooth brightness transition: First, for the extremely low refresh rate range of 48Hz to 50Hz, the monitor directly fixes the target refresh rate at 100Hz and generates the Vsync signal for Backlight Black Insertion (BFI) accordingly. This avoids frequency jitter caused by frequency multiplication and ensures that BFI can be stably triggered even in the lowest refresh rate range. Second, for the mid-to-low refresh rate range of 50Hz to 100Hz, the monitor multiplies the input refresh rate and uses the multiplied refresh rate as the target refresh rate for backlight driving. This ensures that BFI meets the refresh rate requirements even in the mid-to-low refresh rate range and is less prone to frequent on / off switching due to input refresh rate fluctuations. This avoids brightness jumps caused by repeated switching between DC and PWM dimming modes for the backlight.

[0083] Furthermore, to mitigate the brightness loss caused by BFI black insertion and maintain consistent brightness between motion-clear and non-motion-clear states, the windowing period of the backlight BFI can be appropriately increased in VRR mode. This increases the overall effective brightness from approximately 300 nits to approximately 400 nits, achieving a relatively balanced brightness output within the 100Hz–500Hz range. Additionally, the windowing period corresponding to motion clarity is preferably set at the midpoint between 360Hz and 400Hz to achieve the optimal balance between brightness and dynamic clarity.

[0084] Through the above control methods, the processor can maintain stable operation of backlight black insertion in different refresh rate ranges while maintaining the VRR anti-tearing effect, avoiding brightness jumps caused by mode switching, and continuously achieving excellent motion clarity performance across the entire refresh range, thereby significantly improving the overall image quality and display stability of Mini LED displays in VRR scenarios.

[0085] In some embodiments, when SDR / HDR is started with VRR and backlight black insertion (BFI) based on high-frequency PWM dimming enabled simultaneously, the processor parses the SDR / HDR image data of the current frame, decodes the luminance encoding information and metadata, and generates a base luminance reference that can be used by the display system. Unlike the traditional SDR / HDR processing method that relies on DC dimming and a fixed refresh cycle, this embodiment reconstructs the SDR / HDR processing architecture and introduces an SDR / HDR Base mode to decouple color processing and luminance generation. This allows SDR / HDR decoding to only complete color space conversion and color intent restoration, while the luminance is dynamically calculated by an independent luminance generation link based on the VRR refresh timing and the BFI black insertion mechanism, thereby avoiding dimming conflicts between high-frequency PWM modulation and SDR / HDR luminance control. Subsequently, the Mini LED display performs statistical analysis on the basic brightness to generate brightness distribution characteristics that reflect the current image's brightness and darkness structure. Combining the panel's peak brightness capability, backlight adjustable range, and brightness compensation requirements under black frame insertion timing, it calculates the target brightness for the current frame. Finally, within the backlight insertion black frame insertion allowed lighting window, the target brightness is output by adjusting the backlight current or duty cycle. This ensures that the backlight brightness remains consistent with the black frame insertion timing in the time dimension and meets the SDR / HDR display requirements in the brightness dimension. Thus, while achieving anti-tearing and improved motion clarity, it also ensures brightness stability, layering, and contrast performance in SDR / HDR scenes.

[0086] In this embodiment, the processor can achieve simultaneous activation of SDR / HDR, BFI and brightness based on the structured design of color and brightness decoupling. The dimming methods of SDR / HDR and BFI no longer conflict, and the brightness control is completely handled by the backlight and black bar system that can adapt to the characteristics of VRR and BFI.

[0087] In some embodiments, although the processor can perform black-insertion scanning after each partition pixel completes normal scanning through the display driver, so that the pixel grayscale returns to its initial state as much as possible, in actual display, due to the influence of refresh rate and frame time changes on the liquid crystal response speed, the pixel grayscale often cannot completely return to zero within the limited black-insertion window, easily causing ghosting between consecutive frames; in some refresh rate ranges, it may even lead to image quality degradation due to response lag. To solve this problem, before the control module generates scanning instructions according to the determined display timing, the processor also performs the following steps: Step D1: The processor obtains the input refresh rate of the current frame.

[0088] The processor first obtains the input refresh rate corresponding to the current frame, which can be dynamically determined by the upstream signal source or the VRR protocol. Since there may be significant differences in refresh rates between different frames in variable refresh rate scenarios, the effective driving time of pixels and the liquid crystal response window also change accordingly. Therefore, accurately obtaining the refresh rate of the current frame is the basis for subsequent pixel response control and timing adjustment.

[0089] Step D2: The processor determines the frame time corresponding to the current frame based on the input refresh rate.

[0090] After obtaining the refresh rate, the processor further calculates the corresponding frame time, which is the length of time occupied by a single frame display. The frame time directly determines the physical time window that a liquid crystal pixel has to switch from the target grayscale and return to its initial state. Especially when the panel has a high black insertion ratio or a low refresh rate, the time available for pixel response and recovery is significantly limited. Therefore, the frame time needs to be used as an important constraint parameter for the pixel driving strategy.

[0091] The duration of the overdrive voltage for pixel response acceleration (OD) and the length of time that can be allocated during the black insertion phase of the panel.

[0092] Step D3: The processor determines the matching pixel response acceleration parameters based on the input refresh rate or frame time.

[0093] Based on the refresh rate or frame time of the current frame, the processor determines the matching pixel response acceleration parameters from the preset pixel response acceleration strategies. The pixel response acceleration parameters are used to apply pixel response acceleration (Overdrive, OD) to the liquid crystal pixels. That is, during the pixel grayscale flipping stage, by increasing or correcting the initial driving voltage, the pixels approach the target grayscale faster and have more sufficient fallback conditions in the subsequent panel black insertion stage.

[0094] Specifically, in scenarios with short frame times or limited black insertion windows on the panel, a stronger OD parameter can be selected to compensate for LCD response lag; while in scenarios with long frame times, the OD intensity can be reduced to avoid overshoot, thereby maintaining stable pixel response characteristics in different refresh rate ranges.

[0095] Step D4: The processor generates the corresponding pixel driving signal based on the pixel response acceleration parameters.

[0096] After determining the pixel response acceleration parameters, the processor generates the corresponding pixel drive signal and outputs it to the display drive circuit. This pixel drive signal applies a driving voltage containing an OD acceleration component to the pixel during the normal display scanning phase, enabling the liquid crystal pixel to complete grayscale flipping as quickly as possible within the limited display time. It also reserves sufficient margin for grayscale fallback during the subsequent panel black-insertion scanning phase, thereby mitigating the problem of frame remnants caused by response lag.

[0097] Step D5: The processor determines the display timing of the current frame based on the frame time and the preset black-and-white interpolation ratio.

[0098] The processor further combines the frame time of the current frame with the preset panel black insertion ratio to determine the overall display timing of the frame, including the allocation relationship between the display scanning phase and the panel black insertion scanning phase on the time axis. Based on the determined display timing, the control module generates corresponding scanning instructions, so that after the pixels complete the display scan using the OD driver, the panel black insertion phase will promptly perform a shutdown or resumption operation.

[0099] By unifying the scheduling of pixel drive signals (including OD acceleration) with display timing, it is possible to ensure that the pixel response process is precisely matched with the black insertion window on the panel, avoiding insufficient response or visual artifacts caused by timing mismatch.

[0100] In this embodiment, an OD pixel response acceleration mechanism based on adaptive adjustment of refresh rate and frame time is introduced. This enables liquid crystal pixels to complete grayscale flipping and return to their initial state more quickly within the limited display and panel black insertion window, thereby effectively alleviating the problems of ghosting, image ghosting, and image quality degradation caused by refresh rate changes and response lag. If this method is executed in VRR and backlight black insertion scenarios, it will realize the coordinated control between pixel driving, black insertion timing, and refresh rate, maintaining a stable dynamic display effect in different refresh rate ranges, and significantly improving motion clarity and overall image consistency.

[0101] Furthermore, the Local Dimming module adjusts the target backlight brightness regionally based on image content and zone brightness weights, ensuring that the brightness within the illuminated window meets both SDR / HDR brightness requirements and the physical capabilities and light control strategies of zone backlighting. Through the coordinated execution of VRR mode, SDR / HDR, BFI, and Local Dimming, the monitor can simultaneously achieve accurate high dynamic range brightness presentation, effective local light control, stable black bar insertion, and tear-free image synchronization in a dynamic refresh environment, thereby obtaining a comprehensive display effect of high brightness, high contrast, high dynamic clarity, and high stability.

[0102] In some embodiments, to ensure that the brightness of the backlight LEDs does not jump / flicker, the target zone backlight is illuminated based on the target brightness, including: Step E1: The processor obtains the historical brightness corresponding to the previous frame of the target partition backlight.

[0103] Before activating the target zone backlight, the processor first reads the backlight brightness used in the previous frame of the target zone's backlight display, i.e., the historical brightness. Since backlight brightness changes continuously between frames, the historical brightness, as the starting point for the current brightness adjustment, plays a decisive role in the subsequent brightness transition method. By accurately obtaining the historical brightness, sudden brightness changes caused by missing information from the previous moment can be avoided, laying the foundation for achieving smooth dimming.

[0104] Step E2: The processor determines the brightness adjustment speed of the target zone backlight based on the historical brightness and the target brightness.

[0105] When adjusting the backlight brightness from the historical brightness to the target brightness, the processor should consider whether the brightness change is too large to avoid jumps or flickering caused by sudden brightness changes. Therefore, the appropriate brightness adjustment speed can be determined based on the brightness range between the historical and target brightness. A large brightness range indicates a more drastic backlight change requirement, in which case a faster adjustment speed should be used to quickly approach the target brightness; conversely, a smaller brightness range allows for a slower adjustment speed, resulting in a smoother and more natural brightness change and avoiding visual abruptness.

[0106] Preferably, the determination of the brightness adjustment speed can take into account factors such as the preset brightness range, the brightness change range, the display mode (such as SDR / HDR), and the requirements for screen stability, so that the backlight adjustment can respond to screen changes in a timely manner and maintain good visual continuity, avoiding discomfort caused by flickering or sudden changes.

[0107] Step E3: The processor adjusts the brightness of the target partition backlight from the historical brightness to the target brightness based on the brightness adjustment speed.

[0108] After obtaining the brightness adjustment speed, the processor gradually adjusts the target zone backlight from its historical brightness to the target brightness based on this speed, rather than jumping to the target value immediately. The adjustment method is usually achieved through timer cycles, small step increments or decrements, etc., so that the brightness transitions step by step in several tiny steps until the target brightness is reached, thereby ensuring a smooth and continuous brightness change and effectively avoiding visual interference such as flickering and jumps.

[0109] In this embodiment, the processor acquires the historical brightness of the previous frame before activating the target partition backlight, determines the brightness adjustment speed based on the difference between the historical brightness and the target brightness, and gradually transitions the brightness from the historical value to the target value according to the adjustment speed. This transforms the abrupt change in backlight brightness into a continuous, gradual change, effectively avoiding visual problems such as brightness jumps, flickering, and instability. This method enables the backlight to maintain a smooth brightness transition while meeting the requirements of rapid image response. It not only ensures natural and soft changes in brightness and a more stable and consistent brightness presentation but also avoids visual fatigue caused by sudden changes in brightness. Furthermore, by intelligently adjusting the dimming speed based on the brightness span, the backlight brightness can quickly keep up with the image requirements when there are large changes and maintain a delicate and smooth performance when there are small changes, significantly improving the stability of local dimming, image contrast performance, and the overall viewing experience.

[0110] In some embodiments, in order to smoothly adjust brightness, Local Dimming can determine the brightness adjustment speed of the target zone backlight based on historical brightness and target brightness, including: Step E31: The processor determines the historical brightness range to which the historical brightness belongs and the target brightness range to which the target brightness belongs from the pre-divided brightness ranges.

[0111] Before determining the backlight brightness adjustment speed, the processor first needs to determine the position of the historical brightness and the target brightness within the overall brightness range. To this end, each brightness range is divided based on a preset brightness range. For example, an 8-bit backlight range of 0 to 255 can be divided into four brightness ranges: 0 to 63, 64 to 127, 128 to 191, and 192 to 255.

[0112] Based on each brightness range, the processor can determine which of the aforementioned brightness ranges the historical brightness and the target brightness belong to, and thus measure the size of the adjustment range. For example, when the historical brightness is 45, it will be determined to be in the first brightness range (0-63); while when the target brightness is 150, it will be determined to be in the third brightness range (128-191). In this way, the display can clearly identify how many brightness ranges the brightness of a zone spans between the current frame and the previous frame, and provide a basis for determining the subsequent dimming speed.

[0113] Step E32: The processor determines the brightness adjustment speed based on the range between the historical brightness range and the target brightness range.

[0114] After determining the brightness ranges to which the historical brightness and the target brightness belong, the processor determines the backlight brightness adjustment speed based on the range between the two. The larger the brightness range, the more drastic the brightness change, and a faster adjustment speed should be used to quickly approach the target brightness; conversely, when the brightness change is small and the two are within the same range, a slower adjustment speed can be used to make the brightness transition smoother.

[0115] For example, when the historical brightness is in the first range (e.g., 45) and the target brightness is in the third range (e.g., 150), the range span is two ranges, and the monitor will use a faster dimming speed to quickly increase the brightness; while when the historical brightness and the target brightness are both in the second range (e.g., 140 and 155), the range span is zero, and the brightness change only needs to be increased slowly to avoid amplifying slight brightness changes and causing screen jumps.

[0116] Furthermore, different adjustment rates can be set for different brightness ranges, such as using different gradient speeds for low-brightness, medium-brightness, and high-brightness areas. When the brightness spans multiple ranges, the adjustment rates across the ranges can be averaged or weighted to obtain a comprehensive adjustment speed suitable for the brightness change process. Through this adaptive brightness adjustment method based on range span, the backlight can respond quickly to large brightness changes and remain natural and smooth during small changes, effectively avoiding flicker and abrupt changes, and significantly improving the stability and visual comfort of dynamic images.

[0117] In this embodiment, by first determining the brightness ranges to which the historical brightness and the target brightness belong, and then intelligently selecting the brightness adjustment speed based on the range span, the processor can quickly increase or decrease brightness when there are large changes, and smoothly transition when there are small changes. This ensures that the backlight brightness can keep up with the screen requirements without abrupt jumps or noticeable flickering. This method avoids the obvious jumps in brightness caused by large brightness changes and the brightness instability caused by reference frame errors in traditional backlights. At the same time, it improves the oversensitivity phenomenon when there are small brightness changes, making the backlight adjustment more natural and stable overall. This effectively improves the consistency and visual comfort of Local Dimming in fast screen switching scenarios, providing Mini LED displays with smooth, high-quality dynamic brightness transition capabilities.

[0118] In some embodiments, since the pixel response and light transmission changes of the liquid crystal panel are strictly time-related to the gate scanning direction, if the black insertion or shutdown control is not consistent with the line scanning process of the liquid crystal, it is easy to cause inconsistent display duration or non-display duration of different line areas, thereby causing visual problems such as uneven brightness, flickering or enhanced dynamic afterimages.

[0119] While there are various ways to implement pixel partitioning, such as treating each pixel as an independent partition or combining multiple pixels into a single partition to achieve different granularities of black pixel insertion scanning, the inherent top-down row scanning characteristic of LCD panels must still be considered in practical designs. Therefore, on the LCD panel side, the entire screen is first divided into multiple row partitions along the vertical direction according to the gate driving characteristics of the liquid crystal itself. Each partition corresponds to at least one row of liquid crystal pixels. The scanning drive does not refresh all the pixels simultaneously, but rather scans each row partition pixel sequentially along the inherent scanning direction of the LCD panel (e.g., top-down) based on a preset timing sequence. This ensures that the pixel refresh process is consistent with the physical scanning law of the liquid crystal, providing a clear time reference for subsequent black pixel insertion control and brightness management.

[0120] Building upon this, it's important to clarify that local dimming backlighting is not set independently of the local dimming pixels, but rather configured and adjusted relative to them. While theoretically, local dimming backlighting can be implemented in various ways—for example, by treating each LED as an independent local dimming zone, or by combining multiple LEDs to form local dimming zones of different granularities for finer local light control—in actual system design, the unchangeable top-to-bottom scanning characteristic of the LCD panel must be considered. If the spatial structure or lighting sequence of the local dimming zones does not match the LCD's horizontal scanning, situations may arise where the backlight is on while the LCD is still in the grayscale inversion stage, leading to problems such as dynamic display asynchrony and increased ghosting.

[0121] Therefore, when determining the partitioning scheme, it is usually necessary to comprehensively weigh the LED arrangement, backlight emission characteristics, and LCD horizontal scanning rules to ensure that the partitioned backlight corresponds to the partitioned pixels both spatially and temporally. Specifically, in this scheme, the partitioned backlight is set as a horizontal partitioned backlight, that is, the backlight is integrated and divided by line based on the LCD horizontal partitioned pixels, and each horizontal partitioned backlight is scanned zone by zone according to a preset timing, with the scanning direction consistent with the LCD scanning direction.

[0122] For example, a Mini LED backlight array originally composed of a large number of LEDs can be integrated row by row, so that at least one entire row of LEDs forms an independent backlight zone. Taking a 48-column × 24-row array with a total of 1152 LEDs as an example, it can be integrated from the original 1152 fine-grained zones into 24 row-level backlight zones. In this way, the number of zoned backlights corresponds one-to-one with the number of pixels in the LCD row-level zones, which not only significantly reduces the amount of data and transmission bandwidth required for backlight control, but also makes the backlight drive delay negligible.

[0123] In the above structure, when the scan driver scans the row partition pixels line by line according to a preset timing sequence, the corresponding row partition backlight is also scanned and controlled in the same order: when a row partition pixel enters the stable display stage, the corresponding row partition backlight is synchronously lit; while when the liquid crystal is in the grayscale flip or recovery stage, the corresponding row partition backlight remains off. By making the lighting order of the partition backlight strictly consistent with the scanning order of the partition pixels, the backlight can achieve row-level black insertion (BFI) relative to the partition pixels, thereby avoiding the liquid crystal being illuminated during the flip stage, significantly suppressing ghosting and afterimage phenomena, and ultimately improving the overall dynamic display clarity.

[0124] In some embodiments, to further reduce latency in the dynamic backlight control process, the target brightness can be set to a fixed value, thereby temporarily disabling the Local Dimming dynamic backlight mapping algorithm. In normal mode, Local Dimming requires performing complex processing steps such as APL calculation, weighted averaging, brightness mapping, and dynamic partition brightness adjustment for each frame of image. It also requires storing the entire frame or multiple frames of image data in the Scaler's DDR for calculation. These operations result in a large amount of computation and significant processing latency.

[0125] Once the target brightness is set to a fixed value, the backlight no longer changes in real time with the screen, effectively skipping all dynamic mapping-related calculations and storage processes. This allows the backlight driver to quickly and directly output the brightness value. This not only eliminates the computation time associated with image analysis and brightness mapping but also avoids the additional latency caused by data storage and retrieval in DDR, enabling the backlight to respond to timing control with near-zero latency. By simplifying the backlight calculation chain, the synchronization between backlight scanning and LCD scanning is further improved, effectively reducing the trailing effect caused by timing misalignments and making dynamic displays more stable and smooth.

[0126] In some embodiments, in order to achieve accurate timing matching of the backlight BFI at high refresh rates, it is necessary to calculate the backlight illumination time within one Vsync cycle and verify the matching relationship between the PWM frequency and the partitioned row scan.

[0127]

[0128] When the refresh rate vf is 320Hz, the single frame time is approximately 1000 / vf ≈ 3.125ms. If the desired effective backlight illumination time T_brightness per frame is approximately 0.5ms, then with a PWM dimming frequency P_cycle of 15360Hz, a single frame can contain 15360 / 320 = 48 PWM sub-cycles.

[0129] By reversing Equation 1, we can see that the software needs to configure approximately 8 PWM cycles for the High-cycle FW to be on. That is, in each frame of 48 sub-cycles, about 8 cycles are on and 40 cycles are off, thus forming a short pulse backlight window of about 0.5ms.

[0130] Further verification using Formula 2 shows that the duty cycle Hoc ≈ 0.5 / 3.125 ≈ 16%, indicating that the backlight duty cycle must not exceed 16% under 320Hz conditions; otherwise, it will compress the black insertion time and affect the BFI effect.

[0131] Subsequently, Formula 3 was used to verify the feasibility of PWM frequency and partitioned line scanning: at 320Hz, each frame has 48 PWM sub-cycles. When the backlight uses 18-line partitions, each line can be allocated approximately 2 PWM cycles; even if the partitions are increased to 36 lines, each line can still obtain approximately 1 PWM cycle, and progressive scanning can still be achieved in terms of timing. Through the above calculations, the backlight illumination window, duty cycle limit, and progressive scanning capability can be determined simultaneously at a given refresh rate, enabling stable coordination between the backlight BFI and partitioned scanning under high refresh rate conditions, ensuring hardware timing feasibility while guaranteeing improved dynamic clarity.

[0132] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0133] Figure 3 This is a partial structural schematic diagram of a micro-light-emitting unit array display provided in an embodiment of this application. (See attached diagram.) Figure 3 As shown, the miniature light-emitting unit array display of this embodiment includes a processor, a memory, a driver board for the display's liquid crystal panel, a control module, and a scan driver. The processor is connected to the driver board, and the driver board is connected to the control module and the scan driver. When the processor runs the computer program stored in the memory, it can implement the steps in the control method embodiment of the miniature light-emitting unit array display described above, for example... Figure 2 Steps 210-230 are shown.

[0134] In some embodiments, the micro-light-emitting unit array further includes a backlight control system controlled by a processor. Based on the new structure, the processor can implement the steps in the control method embodiments of any of the micro-light-emitting unit array displays described above when running a computer program stored in the memory.

[0135] See Figure 4 The backlight control system includes: Main control board used to generate backlight zone brightness data; Mini LED backlight driver board that communicates with the main control board; Multiple driver ICs are cascaded together via the OWC bus, and these driver ICs are used to drive the corresponding Mini-LED beads to output backlight brightness.

[0136] During operation, the backlight control system first generates brightness data for each backlight zone and transmits this data to the Mini LED backlight driver board via the SPI data protocol. The driver board then uses the OWC (One-Wire Communication) protocol to send the corresponding data to the first driver IC. Upon receiving the data, this driver IC forwards some or all of it to the next driver IC, cascading the data along the OWC bus until all driver ICs have received the data. During this process, each driver IC extracts the corresponding brightness data from the received data to drive its connected Mini LED chips to output the corresponding backlight brightness, thus completing the zoned brightness control of the entire backlight array.

[0137] In some embodiments, in order to further reduce the data transmission latency in the backlight control link, the main control board will divide the backlight partition brightness data to be sent via the SPI data protocol into two parts, left and right, and transmit them to the Mini LED backlight driver board respectively, so as to reduce the amount of data transmitted in a single transmission and improve the overall transmission efficiency.

[0138] Taking the basic partition control method with 1152-zone backlight and a display refresh rate of 320Hz as an example, the brightness data of a single black frame is as follows: The left side of the screen data consists of a header (11 bytes), 1152 / 2 partition brightness (576 bytes), and a check byte, totaling 588 bytes; the right side of the screen data is composed in the same way, also 588 bytes, so the two parts together total 1176 bytes. Calculated at the SPI transmission rate of 10.8 Mbit / s, the transmission time of data on one side is 588×8÷10.8×10^6≈0.435 ms, and the total transmission time for 320 frames is approximately 0.139s, consistent with theoretical and actual measurements.

[0139] Taking a 24-row backlight with a 320Hz refresh rate as an example, the number of backlight zones is reduced from 1152 to 24, significantly decreasing the data volume per frame. The left side of the screen consists of only an 11-byte header, 12 bytes of row brightness data, and a checksum, totaling 24 bytes. The right side also consists of 24 bytes, for a total of only 48 bytes. Calculated at the same SPI rate, the single transmission time is shortened to 24 × 8 ÷ 10.8 × 10^6 ≈ 17 μs, and the cumulative transmission time for 320 frames is only about 5.4 ms, significantly lower than the data transmission consumption of the original 1152-zone mode.

[0140] It should be noted that although the above calculation includes the total transmission time of multiple frames, what the end user can actually perceive is only the transmission delay of a single frame of data. Because the content of each frame is updated in real time and the single-frame delay is reduced to the microsecond level, the almost imperceptible timing lag of the backlight response enables the backlight scanning and LCD scanning to work together with higher synchronization accuracy, providing a fundamental support for achieving high dynamic clarity and ultra-low latency backlight control.

[0141] In some embodiments, the main control board may include a processor, memory, and interface circuitry for data transmission. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, or may be implemented using discrete gate circuits, transistor logic devices, or discrete hardware components. The processor may be a microprocessor or any conventional processor capable of executing program instructions. The processor is used to execute the logic for generating backlight zone brightness data, as well as data packetization, timing control, and protocol processing for SPI communication.

[0142] In some embodiments, the main control board may further include a memory for storing the operating system, applications, backlight processing program, brightness mapping algorithm, timing control program, bootloader, and other content. The memory can be an internal storage unit of the main control board, such as onboard Flash, DDR, or NVRAM, or an external storage device, such as a pluggable flash card, Secure Digital (SD) card, Smart Media Card (SMC), or Flash Card. The memory can also be used to temporarily cache backlight data to be output or image data being processed.

[0143] In some embodiments, the Mini LED backlight driver board may include a backlight control MCU, an SPI receiving module, an OWC (One-Wire Communication) transmitting module, a partitioned brightness buffer unit, a current-driven modulation unit, and a power management unit. The MCU on the backlight driver board may be any type of processor, such as a dedicated backlight control microcontroller, DSP, low-power ARM core MCU, ASIC, or FPGA for high-density driving, used to parse SPI data from the main control board and generate corresponding OWC driving instructions.

[0144] The driver board may also include a constant current driving unit, a voltage conversion module, and a PWM modulation circuit for driving Mini LED chips, providing stable power and dimming control for each driver IC. Furthermore, the memory on the driver board can be used to cache one or more frames of backlight zone brightness data, calibration parameters, or temperature compensation data; the memory can be onboard Flash, EEPROM, SRAM, or external memory.

[0145] In some embodiments, the driver IC may be an LED driver chip that supports OWC single-wire cascaded communication, such as a dedicated MiniLED driver IC that supports serial relay transmission, automatic address allocation, CRC verification, reverse communication, and constant current accuracy adjustment. The driver IC may include an OWC receiving module, an OWC forwarding module, a current drive output module, a PWM dimming module, a temperature protection circuit, a voltage protection circuit, etc.

[0146] In some embodiments, the driver IC may be an XP7208, SM16xx, or other LED constant current driver chip with similar functions, capable of driving multiple Mini LED beads simultaneously (e.g., 8, 16, or more channels). Each driver IC can automatically extract its corresponding brightness data channel from the received OWC data stream and drive its respective Mini LED bead group according to the extracted brightness value to achieve zoned, sub-zoned, or fine-grained backlight control.

[0147] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the above device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0148] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0149] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0150] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographic device / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, such as a USB flash drive, a portable hard drive, a magnetic disk, or an optical disk.

[0151] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0152] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0153] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0154] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A control method for a micro-light-emitting unit array display, characterized in that, A processor for use in a display, wherein the display is provided with a control module and a scanning driver connected to a driver board of the display's liquid crystal panel; During the display of the current frame, the control module generates a scanning command according to the determined display timing and sends the scanning command to the scanning driver; The scanning driver scans each zone pixel of the display's liquid crystal panel according to a preset timing sequence. For each target partition pixel being scanned, the scanning driver sequentially performs a regular scan and a black-insertion scan on the partition pixel based on the scan command.

2. The control method as described in claim 1, characterized in that, The control method further includes dividing the display backlight into zones based on the pixels of each zone: When the scanning driver scans each zone pixel of the display liquid crystal panel according to a preset timing sequence, the backlight of each zone is scanned synchronously according to the preset timing sequence. For the target partition backlight corresponding to the target partition pixel, perform regular scanning and black insertion scanning on the partition pixel in sequence based on the scanning driver, and turn the target partition backlight on or off.

3. The control method as described in claim 2, characterized in that, Before turning the target zone backlight on or off, the method further includes: Obtain the input refresh rate of the current frame; If the input refresh rate falls within the first refresh rate range, the preset refresh rate is determined as the target refresh rate. If the input refresh rate falls within the second refresh rate range, the input refresh rate is multiplied to obtain the target refresh rate; the minimum value of the second refresh rate range is greater than the maximum value of the first refresh rate range. If the input refresh rate is greater than the preset refresh rate, the input refresh rate is determined as the target refresh rate. Accordingly, turning the target partition backlight on or off includes: The target partition backlight is turned on or off based on the target refresh rate.

4. The control method as described in claim 2, characterized in that, Lighting up the target zone backlight includes: Obtain the partition image data of the target partition backlight in the current frame; Brightness feature analysis is performed on the partitioned image data to obtain the corresponding brightness feature parameters; Find the backlight control parameter corresponding to the brightness characteristic parameter from the preset mapping table; The target zone backlight is illuminated based on the backlight control parameters.

5. The control method as described in claim 2, characterized in that, When the dimming current of the display backlight is changed from DC dimming to high-frequency PWM dimming, if the difference between the first current value of DC dimming and the second current value of high-frequency PWM dimming is greater than a preset current threshold, then a variable drive current for each frame is generated based on the time information corresponding to a specified number of frames to be processed, and the brightness of each frame to be processed is adjusted based on the corresponding variable drive current.

6. The control method according to any one of claims 1 to 5, characterized in that, Before the control module generates the scan command according to the determined display timing, the following is also included: Obtain the input refresh rate of the current frame; The frame time corresponding to the current frame is determined based on the input refresh rate; Based on the input refresh rate or the frame time, determine the matching pixel response acceleration parameters; Generate corresponding pixel driving signals based on the pixel response acceleration parameters; The display timing of the current frame is determined based on the frame time and the preset black-and-white interpolation ratio. Accordingly, the control module generates scanning instructions based on the determined display timing, including: The scanning command is generated based on the display timing and the pixel driving signal.

7. The control method according to any one of claims 1 to 5, characterized in that, The partitioned pixels are row partitioned pixels, and the scan driver scans each partitioned pixel of the display liquid crystal panel sequentially based on a preset timing sequence, including: Based on the preset timing and the liquid crystal scanning direction of the micro light-emitting unit array display, each row of partition pixels is scanned.

8. A miniature light-emitting unit array display, characterized in that, The display includes a processor, a memory, a driver board for the LCD panel, a control module, and a scan driver. The processor is connected to the driver board, and the driver board is connected to the control module and the scan driver. When the processor runs the computer program stored in the memory, it can implement the control method of the micro light-emitting unit array display as described in any one of claims 1, 6, and 7.

9. The display as claimed in claim 8, characterized in that, It also includes a backlight control system controlled by the processor, which, when running the computer program stored in the memory, can implement the control method of the micro light-emitting unit array display as described in any one of claims 2 to 5; The backlight control system includes: Main control board used to generate backlight zone brightness data; The micro-light-emitting unit array backlight driver board is communicatively connected to the main control board; Multiple driver ICs are cascaded through an OWC bus, and these driver ICs are used to drive the corresponding micro light-emitting units to output backlight brightness.

10. The micro light-emitting unit array display as described in claim 9, characterized in that, The main control board establishes a communication connection with the micro light-emitting unit array backlight driver board through the SPI data protocol; The main control board divides the SPI data to be transmitted into left-side image data and right-side image data and transmits them to the micro-light-emitting unit array backlight driver board.

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