Driving method, driving circuit and display device of display panel

Abstract

The application provides a display panel driving method, a driving circuit and a display device, wherein in the display panel driving method, in a first display frame, the charging time of pixel units in odd rows and even rows is controlled to be a first charging time length and a second charging time length respectively, in a second display frame, the charging time of pixel units in odd rows and even rows is controlled to be a third charging time length and a fourth charging time length respectively, the fourth charging time length is controlled to make the data signal end output in advance before the corresponding row scanning signal is turned off, the third charging time length is greater than the first charging time length, the second charging time length is greater than the first charging time length, and the fourth charging time length is greater than the third charging time length, so that the brightness of the odd rows is weaker than that of the even rows in the first display frame, the brightness of the odd rows is stronger than that of the even rows in the second display frame, the odd rows and the even rows present an alternating dim effect, the brightness is completely balanced after being superimposed by the human eye visual lag effect, and the row stripes and the display roughness are eliminated.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a driving method, driving circuit and display device for a display panel. Background Technology

[0002] With the rapid upgrading of the consumer electronics and display industries, LCD display panels are developing towards higher resolution, higher refresh rates, lower power consumption, narrower bezels, and lower costs. To achieve both high resolution and high refresh rates under limited drive bandwidth and hardware costs, the industry widely adopts the HSR (Hardware Super Resolution) display mode.

[0003] HSR mode uses a frequency doubling output method to ensure that adjacent odd-numbered and even-numbered row pixel units receive the same data signal. This effectively doubles the screen refresh rate without increasing the number of source channels or significantly increasing the clock frequency. Therefore, it is widely used in terminal products such as high refresh rate mobile phones, gaming monitors, laptops, and in-vehicle central control instruments.

[0004] However, the traditional HSR driving method has inherent display defects, specifically: The charging times for odd-numbered rows and even-numbered rows are inconsistent. Due to the frequency doubling scanning timing structure, the gate opening time for odd-numbered rows in the first display frame is short and the charging time is insufficient, while the gate opening time for even-numbered rows is long and the charging is relatively sufficient.

[0005] Differences in pixel potential lead to differences in brightness. A pixel unit consists of a TFT switch, a storage capacitor Cst, and a liquid crystal capacitor Clc. When the horizontal scanning signal is turned off, the charged energy will experience a voltage drop due to TFT leakage and charge redistribution between capacitors, ultimately maintaining a holding potential. Because odd-numbered rows have shorter charging times and lower peak potentials, their holding potentials are even lower after leakage; even-numbered rows have longer charging times and higher peak potentials, resulting in even higher holding potentials after leakage. This directly causes odd-numbered rows to appear darker and even-numbered rows to appear brighter. Macroscopically, this results in a rougher image and line patterns. Under human observation, the screen displays a regular pattern of alternating bright and dark lines, especially noticeable in solid color images, low grayscale images, and high-brightness images. This results in a rough display texture and poor uniformity, severely impacting the user's visual experience. Summary of the Invention

[0006] The purpose of this invention is to provide a driving method for a display panel, which aims to solve the problem of poor display effect and alternating bright and dark lines when the traditional display panel uses frequency multiplication output.

[0007] A first aspect of this invention provides a method for driving a display panel, comprising: In the alternating first and second display frames, line scan signals are output to the display panel line by line, and multiple data signals are output to the display panel, wherein the data signals received by the two pixel units of each adjacent odd and even rows are the same; In the first display frame, the charging time of the pixel units in the odd-numbered rows is the first charging duration, and the charging time of the pixel units in the even-numbered rows is the second charging duration, wherein the second charging duration is longer than the first charging duration. In the second display frame, the charging time of the pixel units in odd-numbered rows is controlled to be a third charging duration, and the charging time of the pixel units in even-numbered rows is controlled to be a fourth charging duration. The third charging duration is longer than the first charging duration, the fourth charging duration is longer than the third charging duration, and the fourth charging duration is controlled to cause the data signal to end the output before the corresponding row scan signal is turned off.

[0008] Optionally, the rising edges of the multiple rows of the row scanning signals are spaced apart by a unit time interval, the falling edges of the multiple rows of the row scanning signals are spaced apart by a unit time interval, and the high-level periods of adjacent rows of the row scanning signals partially overlap.

[0009] Optionally, in the first display frame, controlling the charging time of pixel units in odd-numbered rows to be a first charging duration and the charging time of pixel units in even-numbered rows to be a second charging duration, wherein the second charging duration is longer than the first charging duration, includes: In the first display frame, a data signal is output before the falling edge of the row scan signal of each two adjacent rows and the output of the data signal is stopped after the falling edge of the row scan signal of each two adjacent rows. Wherein, the first time interval between the rising edge of the data signal of the pixel unit in the odd-numbered rows and the falling edge of the corresponding row scan signal is less than the second time interval between the rising edge of the data signal of the pixel unit in the even-numbered rows and the falling edge of the corresponding row scan signal, so that the first charging time is less than the second charging time.

[0010] Optionally, in the first display frame, the rising edge of the data signal of the pixel unit in the odd-numbered rows leads the rising edge of the data signal of the pixel unit in the even-numbered rows, or the rising edge of the data signal of the pixel unit in the odd-numbered rows and the rising edge of the data signal of the pixel unit in the even-numbered rows are at the same time point.

[0011] Optionally, in the second display frame, controlling the charging time of pixel units in odd-numbered rows to be a third charging duration and the charging time of pixel units in even-numbered rows to be a fourth charging duration, wherein the third charging duration is longer than the first charging duration and the fourth charging duration is longer than the third charging duration, and controlling the fourth charging duration to cause the data signal to end its output prematurely before the corresponding row scan signal is turned off, includes: In the second display frame, a data signal is output before the falling edge of the row scan signal between every two adjacent rows; In the second display frame, the data signal is cut off after the falling edge of the row scan signal for odd-numbered rows, and the data signal is cut off before the falling edge of the row scan signal for even-numbered rows. Wherein, the third time interval between the rising edge of the data signal of the pixel unit in the odd-numbered rows and the falling edge of the corresponding row scan signal is greater than the first time interval, and the fourth time interval between the rising edge of the data signal of the pixel unit in the even-numbered rows and the falling edge of the corresponding row scan signal is greater than the third time interval.

[0012] Optionally, in the second display frame, the rising edge of the data signal of the pixel unit in the odd-numbered rows is at the same time point as the rising edge of the data signal of the pixel unit in the even-numbered rows.

[0013] Optionally, the output duration of each of the data signals is equal.

[0014] Optionally, in the second display frame, before controlling the charging time of the pixel units in odd-numbered rows to be the third charging duration and the charging time of the pixel units in even-numbered rows to be the fourth charging duration, the method further includes: Obtain the display brightness difference between the odd-numbered rows and even-numbered rows in the first display frame; Calculate the charging time compensation amount based on the brightness difference; Based on the base charging time and the compensation amount, the parameter values ​​of the third charging duration and the fourth charging duration are determined.

[0015] A second aspect of this invention provides a driving circuit for a display panel, comprising: The source drive circuit is connected to the data line of the display panel. The source drive circuit is used to output multiple data signals under controlled conditions. A gate driving circuit is connected to the scan lines of the display panel, and the gate driving circuit is used to output line scan signals in a controlled manner. A timing controller is connected to the source driving circuit and the gate driving circuit respectively. The timing controller is used to control the source driving circuit and the gate driving circuit to implement the display panel driving method described above.

[0016] A third aspect of the present invention provides a display device, including a display panel and a driving circuit for the display panel as described above, wherein the display panel is connected to the driving circuit for the display panel.

[0017] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the above-mentioned display panel driving method, in the first display frame, the charging time of the pixel units in the odd-numbered rows is controlled as a first charging duration and the charging time of the pixel units in the even-numbered rows is controlled as a second charging duration. In the second display frame, the charging time of the pixel units in the odd-numbered rows is controlled as a third charging duration and the charging time of the pixel units in the even-numbered rows is controlled as a fourth charging duration. The fourth charging duration is controlled so that the data signal ends the output before the corresponding row scanning signal is turned off. The third charging duration is longer than the first charging duration, the second charging duration is longer than the first charging duration, and the fourth charging duration is longer than the third charging duration. As a result, the brightness of the odd-numbered rows is weaker than that of the even-numbered rows in the first display frame and stronger than that of the even-numbered rows in the second display frame. In different frames, the odd-numbered rows and even-numbered rows present an alternating darkening effect. After being superimposed by the visual lag effect of the human eye, the brightness is completely balanced, eliminating the row lines and the roughness of the display. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the display panel provided in Embodiment 1 of the present invention; Figure 2 This is a circuit diagram of a pixel unit provided in Embodiment 1 of the present invention; Figure 3 This is a schematic flowchart of a display panel driving method provided in Embodiment 1 of the present invention; Figure 4 This is a waveform diagram of the first display frame in the display panel driving method provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the brightness of the display panel in the first display frame according to Embodiment 1 of the present invention; Figure 6 This is a waveform diagram of the second display frame in the display panel driving method provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the brightness of the display panel provided in Embodiment 1 of the present invention in the second display frame; Figure 8 This is a flowchart illustrating step S30 in the display panel driving method provided in Embodiment 1 of the present invention. Figure 9 This is a schematic flowchart of a display panel driving method provided in Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the driving circuit and display device of the display panel provided in Embodiments 3 and 4 of the present invention.

[0019] The figures in the diagram are labeled as follows: 1. Display panel driving circuit; 2. Display panel; 100. Source driving circuit; 200. Gate driving circuit; 300. Timing controller; 11. Pixel unit; G1, First scan line; G2, Second scan line; G3, Third scan line; G4, Fourth scan line; D1, First data line; D2, Second data line; D3, Third data line; K1, Thin-film transistor; Cst, Storage capacitor; Clc, Liquid crystal capacitor; Vcom, Common electrode voltage; V1, Potential change curve of pixel units in odd-numbered rows of the first display frame; V2, Potential change curve of pixel units in even-numbered rows of the first display frame; V3, Potential change curve of pixel units in odd-numbered rows of the second display frame; V4, Potential change curve of pixel units in even-numbered rows of the second display frame; F1, Decreasing curve of the line scan signal; Vp1, First peak potential; Vp2, Second peak potential; Vp3, Third peak potential; Vp4, Fourth peak potential; Vh1, First holding potential; Vh2, Second holding potential; Vh3, Third holding potential; Vh4, Fourth holding potential; T1, first charging time; T2, second charging time; T3, third charging time; T4, fourth charging time; t0, unit duration; t1, output duration of data signal. Detailed Implementation

[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] Example 1 A first aspect of the present invention provides a driving method for a display panel 2.

[0023] Among them, such as Figure 1As shown, the display panel 2 includes pixel units 11 arranged in an array, as well as multiple rows of scan lines and multiple columns of data lines. For example, the scan lines include a first scan line G1, a second scan line G2, a third scan line G3, a fourth scan line G4, etc., and the data lines include a first data line D1, a second data line D2, a third data line D3, etc. Each pixel unit 11 is connected to a corresponding data line and a scan line. The scan lines are used to input row scan signals, and the data lines are used to input data signals. The pixel unit 11 is charged according to the received data signals and row scan signals, and displays the corresponding image information.

[0024] like Figure 2 As shown, pixel unit 11 includes thin-film transistor K1, storage capacitor Cst, and liquid crystal capacitor Clc. The input terminal of thin-film transistor K1 is connected to the data line, and the output terminal of thin-film transistor K1 is connected to the first electrode of storage capacitor Cst and the first electrode of liquid crystal capacitor Clc. The second electrode of storage capacitor Cst and the second electrode of liquid crystal capacitor Clc are used to input the common electrode voltage Vcom. The first electrode of storage capacitor Cst and the first electrode of liquid crystal capacitor Clc are pixel electrodes, the second electrode of storage capacitor Cst is the first common electrode layer, and the second electrode of liquid crystal capacitor Clc is the second common electrode layer. When thin-film transistor K1 receives the horizontal scanning signal and is turned on, the pixel electrode receives the data signal on the data line and is charged. The charging voltage and the common electrode voltage Vcom on the second common electrode layer form a driving voltage, which drives the liquid crystal to deflect, thereby displaying the corresponding image information.

[0025] The horizontal scanning signal consists of a horizontal enable signal and a horizontal disable signal. The voltage of the horizontal enable signal is greater than that of the horizontal disable signal. The thin-film transistor K1 turns on when it receives the horizontal enable signal and turns off when it receives the horizontal disable signal. The horizontal enable signal is converted to the horizontal disable signal, which generates the falling edge of the horizontal scanning signal. The horizontal disable signal is converted to the horizontal enable signal, which generates the rising edge of the horizontal scanning signal.

[0026] When the gate of the thin-film transistor K1 receives the row enable signal and is turned on, the data signal charges the liquid crystal capacitor Clc and the storage capacitor Cst to the peak potential.

[0027] When the gate of thin-film transistor K1 is turned off by the row turn-off signal, due to the capacitance difference between the storage capacitor Cst and the liquid crystal capacitor Clc, thin-film transistor K1 leaks current, and the potential of the pixel electrode drops to the holding potential.

[0028] like Figure 5 As shown, in traditional HSR driving, odd-numbered rows have short charging times and low holding potentials, resulting in darker brightness of pixel units 11 in odd-numbered rows. Even-numbered rows have long charging times and high holding potentials, resulting in brighter brightness of pixel units 11 in even-numbered rows, leading to bright and dark stripes and a rough display image.

[0029] To solve the above problems, such as Figure 3 As shown, in this embodiment, the driving method for the display panel 2 includes: S10. In the alternating first and second display frames, line scan signals are output to the display panel 2 line by line and multiple data signals are output to the display panel 2, wherein the data signals received by the two pixel units 11 of each adjacent odd and even rows are the same.

[0030] In this embodiment, in HSR display mode, the driving system outputs the screen in an alternating cycle of the first display frame and the second display frame.

[0031] Within each frame cycle, the control gate driving circuit 200 outputs line scan signals to the scan lines of the display panel 2 line by line, while the source driving circuit 100 synchronously outputs multiple data signals to the data lines of the display panel 2. The waveforms, amplitudes, and timings of the data signals received by the two pixel units 11 in each adjacent odd-numbered and even-numbered rows are completely identical to achieve frequency multiplication output and meet the HSR frequency multiplication driving requirements.

[0032] S20. In the first display frame, the charging time of the pixel unit 11 in the odd-numbered rows is controlled to be the first charging time T1, and the charging time of the pixel unit 11 in the even-numbered rows is controlled to be the second charging time T2, wherein the second charging time T2 is greater than the first charging time T1.

[0033] In this embodiment, the charging time refers to the time interval between the rising edge of the data signal and the falling edge of the corresponding row scan signal, which directly determines the peak potential that a pixel can be charged to.

[0034] The first display frame and the second display frame refer to two adjacent frames that are alternately output under the HSR frequency multiplication drive, which together constitute a composite image observed by the human eye.

[0035] The hold potential refers to the final hold potential of the pixel electrode after the line scan signal switches to a low level and the thin-film transistor K1 is turned off, which directly determines the display brightness of that line.

[0036] In the first display frame, such as Figure 4 As shown, the following timing control is performed: The charging time of the odd-numbered row pixel unit 11 is controlled to be the first charging time T1; The charging time of even-numbered row pixel units 11 is controlled to be the second charging time T2; The timing relationship is satisfied: the second charging time T2 > the first charging time T1.

[0037] Where V1 represents the potential change curve of pixel unit 11 in odd-numbered rows in the first display frame, and F1 represents the decreasing curve of the row scan signal. Since the charging time directly determines the pixel peak potential, in the first display frame, as shown... Figure 5 As shown, the charging time of the odd-numbered rows is short, the first peak potential Vp1 of the pixel unit 11 in the odd-numbered rows is low, the first holding potential Vh1 after leakage is low, and the brightness of the pixel unit 11 in the odd-numbered rows is dark.

[0038] V2 represents the potential change curve of pixel unit 11 in even-numbered rows in the first display frame. The charging time of pixel unit 11 in even-numbered rows is longer, the second peak potential Vp2 of pixel unit 11 in even-numbered rows is higher, the second holding potential Vh2 after leakage is higher, and the brightness of pixel unit 11 in even-numbered rows is normal.

[0039] In the first display frame, the multi-row pixel units 11 present a display effect where odd-numbered rows are darker and even-numbered rows are normal.

[0040] S30. In the second display frame, the charging time of the pixel unit 11 in the odd-numbered rows is controlled to be the third charging time T3, and the charging time of the pixel unit 11 in the even-numbered rows is controlled to be the fourth charging time T4. The third charging time T3 is greater than the first charging time T1, and the fourth charging time T4 is greater than the third charging time T3. The fourth charging time T4 is controlled to make the data signal end the output in advance before the corresponding row scan signal is turned off.

[0041] In the second display frame, as Figure 6 As shown, the following timing control is performed: The charging time of the odd-numbered row pixel unit 11 is controlled to be the third charging time T3; The charging time of even-numbered row pixel units 11 is controlled to be the fourth charging time T4; The timing relationship is satisfied: the third charging time T3 > the first charging time T1; the fourth charging time T4 > the third charging time T3.

[0042] At the same time, the fourth charging duration T4 is controlled so that the data signal ends output before the corresponding row scan signal is turned off, thereby creating a complementary effect in the second display frame.

[0043] Wherein, V3 represents the potential change curve of pixel unit 11 in odd-numbered rows of the second display frame, and V4 represents the potential change curve of pixel unit 11 in even-numbered rows of the second display frame. In the second display frame, as shown... Figure 7 As shown, the charging time of the pixel unit 11 in the odd-numbered rows is extended, the third peak potential Vp3 of the pixel unit 11 in the odd-numbered rows is increased, the third holding potential Vh3 is increased, and the brightness of the pixel unit 11 in the odd-numbered rows returns to normal.

[0044] Although the charging time of the even-numbered row pixel unit 11 is further extended, the data signal is turned off in advance, the fourth peak potential Vp4 of the data signal of the pixel unit 11 drops in advance, the fourth holding potential Vh4 of the pixel unit 11 is low, and the brightness of the even-numbered row pixel unit 11 is dark.

[0045] That is, in the second display frame, each row of pixel units 11 presents a complementary display effect where odd-numbered rows are normal and even-numbered rows are darker.

[0046] Because the first and second display frames are output alternately at a high frequency, the human eye cannot distinguish between the two independent frames due to the visual lag effect, and can only receive the superposition effect of the brightness of the two frames.

[0047] In the first display frame, odd-numbered rows are darker and even-numbered rows are brighter. In the second display frame, odd-numbered rows are brighter and even-numbered rows are darker. The brightness of odd-numbered rows and even-numbered rows compensate for each other and averages out. After final visual synthesis, a uniform display image with consistent brightness across all rows, no line lines, and no roughness is presented.

[0048] like Figure 4 As shown, in an optional embodiment, the rising edges of the multi-line scanning signals are sequentially spaced at unit time intervals t0, the falling edges of the multi-line scanning signals are sequentially spaced at unit time intervals t0, and the high-level periods of adjacent line scanning signals partially overlap.

[0049] The above timing sequence is a typical gate timing sequence for HSR frequency multiplier drive, in which rising edges and falling edges are output at equal intervals to ensure the uniformity and stability of line-by-line scanning.

[0050] The overlapping of adjacent row scan signals can shorten the row switching time and improve the frame refresh rate, providing a stable and accurate timing reference for the synchronous output of data signals and the control of charging time.

[0051] Based on this timing, by shifting the rising edge of the data signal forward or backward, or by turning off the data signal in advance, the charging time of odd-numbered rows and even-numbered rows can be configured to achieve complementary brightness control between the two frames.

[0052] In an optional embodiment, S20 includes: S21. In the first display frame, a data signal is output before the falling edge of the line scan signal of each two adjacent lines and the output data signal is stopped after the falling edge of the line scan signal of each two adjacent lines. In this case, the first time interval between the rising edge of the data signal of the pixel unit 11 in the odd-numbered rows and the falling edge of the corresponding row scan signal is less than the second time interval between the rising edge of the data signal of the pixel unit 11 in the even-numbered rows and the falling edge of the corresponding row scan signal, so that the first charging time T1 is less than the second charging time T2.

[0053] In the first display frame, charging time control is performed as follows: The output data signal is started before the falling edge of the row scan signal between each two adjacent rows; The output data signal is cut off after the falling edge of the row scan signal between every two adjacent rows; Correspondingly, for odd-numbered rows, the time interval between the rising edge of the data signal and the falling edge of the row scan signal is the first time interval, i.e., the first charging duration T1; For even-numbered rows, the time interval between the rising edge of the data signal and the falling edge of the row scan signal is the second time interval, i.e., the second charging duration T2.

[0054] The first time interval is less than the second time interval, thus achieving a first charging duration T1 less than a second charging duration T2.

[0055] Since the longer the charging time, the higher the peak potential that the pixel unit 11 can be charged to, the charging time of the pixel unit 11 in the odd-numbered rows is short, the first peak potential Vp1 of the pixel unit 11 is low, the first holding potential Vh1 after leakage is low, and the brightness of the pixel unit 11 in the odd-numbered rows is darker. The even-numbered row pixel unit 11 has a longer charging time, a higher second peak potential Vp2, a higher second holding potential Vh2 after leakage, and normal brightness.

[0056] By using the above-mentioned limiting settings, the inherent differences of traditional HSR driving are matched, and by retaining these differences in the first display frame, they are used to form complementary compensation with the second display frame.

[0057] In an optional embodiment, in the first display frame, the rising edge of the data signal of the pixel unit 11 in the odd-numbered rows leads the rising edge of the data signal of the pixel unit 11 in the even-numbered rows, or the rising edge of the data signal of the pixel unit 11 in the odd-numbered rows and the rising edge of the data signal of the pixel unit 11 in the even-numbered rows are at the same time point.

[0058] In the first display frame, the rising edge of the data signal can be configured in one of the following two ways: Method 1, where the rising edge of the odd-numbered row data signal leads the rising edge of the even-numbered row data signal, offers the advantage of more flexible timing control and the ability to finely adjust the charging time difference between the two rows.

[0059] Method 2: The rising edges of the odd-numbered and even-numbered rows of data signals are at the same time point. This method has the advantages of having the same data for both rows under the HSR frequency multiplication mode, and the rising edge alignment can simplify the source drive timing, reduce EMI interference, and improve drive stability.

[0060] Both methods can achieve the goal of the first charging time T1 being less than the second charging time T2, and can be freely selected according to the panel size, refresh rate, and IC driving capability. In the high refresh rate HSR display panel 2, the rising edge alignment method is preferred to simplify timing design.

[0061] In an alternative embodiment, such as Figure 8 As shown, S30 includes: S31. In the second display frame, output a data signal before the falling edge of the row scan signal of each two adjacent rows; S32. In the second display frame, the output data signal is cut off after the falling edge of the line scan signal of the odd-numbered rows, and the output data signal is cut off before the falling edge of the line scan signal of the even-numbered rows. In this case, the third time interval between the rising edge of the data signal of the pixel unit 11 in the odd-numbered rows and the falling edge of the corresponding row scan signal is greater than the first time interval, and the fourth time interval between the rising edge of the data signal of the pixel unit 11 in the even-numbered rows and the falling edge of the corresponding row scan signal is greater than the third time interval.

[0062] In this embodiment, the second display frame is executed according to the following timing sequence: The output data signal is started before the falling edge of the row scan signal between each two adjacent rows; For odd-numbered rows: the data signal is cut off after the falling edge of the row scan signal; Even-numbered rows: The data signal is cut off before the falling edge of the row scan signal.

[0063] For odd-numbered rows, the time interval between the rising edge of the data signal and the falling edge of the row scan signal is the third time interval, i.e., the third charging duration T3. For even-numbered rows, the time interval between the rising edge of the data signal and the falling edge of the row scan signal is the fourth time interval, i.e., the fourth charging duration T4.

[0064] The timing relationship is satisfied: the third time interval > the first time interval, and the fourth time interval > the third time interval.

[0065] The above control extends the charging time of the odd-numbered pixel units 11, increases the third peak potential Vp3 of the odd-numbered pixel units 11, increases the third holding potential Vh3 of the odd-numbered pixel units 11, and ensures normal brightness of the odd-numbered pixel units 11. Although the even-numbered row pixel unit 11 has a longer charging time, the data signal is turned off in advance. The fourth peak potential Vp4 of the even-numbered row pixel unit 11 has already started to decrease before the gate is turned off. In the end, the fourth holding potential Vh4 of the even-numbered row pixel unit 11 is low, and the brightness of the even-numbered row pixel unit 11 is dark.

[0066] Thus, the second display frame forms a brightness distribution that is completely complementary to the first display frame, providing a basis for visually synthesizing a uniform image.

[0067] In an optional embodiment, in the second display frame, the rising edge of the data signal of the pixel unit 11 in the odd-numbered rows is at the same time point as the rising edge of the data signal of the pixel unit 11 in the even-numbered rows.

[0068] By aligning the rising edges of the two data signals, the consistency of the two data lines in HSR mode can be maintained, which conforms to the frequency multiplication drive architecture. The source driver only needs to output one set of data to drive the two lines at the same time, simplifying the circuit structure. The rising edge alignment can avoid brightness jitter and line stripe interference caused by phase deviation.

[0069] Meanwhile, complementary brightness is achieved simply by switching off timing differences, and the timing control logic is simple and easy to implement with a controller.

[0070] In one optional embodiment, the output duration t1 of each data signal is equal, wherein the output duration t1 of the data signal refers to the total time from the rising edge to the falling edge.

[0071] In the first display frame, the output duration t1 of all data signals is the same. In the second display frame, the output duration t1 of all data signals is the same. The output duration t1 of the data signals in the first and second display frames can be the same or different. This ensures a constant source drive output load, avoids voltage drops and uneven driving caused by different durations, guarantees grayscale output linearity, does not disrupt the Gamma curve, and the charging time difference is determined only by the phase position, not the output width, resulting in higher control precision.

[0072] The beneficial effects of this invention embodiment compared with the prior art are as follows: In the above-described driving method for the display panel 2, in the first display frame, the charging time of the pixel units 11 in the odd-numbered rows is controlled to be a first charging duration T1 and the charging time of the pixel units 11 in the even-numbered rows is controlled to be a second charging duration T2. ​​In the second display frame, the charging duration of the pixel units 11 in the odd-numbered rows is controlled to be a third charging duration T3 and the charging duration of the pixel units 11 in the even-numbered rows is controlled to be a fourth charging duration T4, and the fourth charging duration T4 is controlled to make the number of rows of pixels 11 increase by 100%. According to the signal, the output ends before the corresponding line scanning signal is turned off. The third charging time T3 is greater than the first charging time T1, the second charging time T2 is greater than the first charging time T1, and the fourth charging time T4 is greater than the third charging time T3. As a result, the brightness of odd-numbered lines is weaker than that of even-numbered lines in the first display frame, and the brightness of odd-numbered lines is stronger than that of even-numbered lines in the second display frame. In different frames, odd-numbered lines and even-numbered lines present an alternating darkening effect. After being superimposed by the visual lag effect of the human eye, the brightness is completely balanced, eliminating line lines and display roughness.

[0073] Example 2 In an optional embodiment, in order to obtain accurate values ​​for the third charging duration T3 and the fourth charging duration T4, and to improve the brightness compensation effect, such as... Figure 9 As shown, S30 also includes: S41. Obtain the display brightness difference between odd-numbered rows and even-numbered rows in the first display frame; S42. Calculate the charging time compensation amount based on the brightness difference; S43. Based on the basic charging time and compensation amount, determine the parameter values ​​of the third charging time T3 and the fourth charging time T4.

[0074] In this embodiment, the actual brightness difference ΔL between odd-numbered rows and even-numbered rows in HSR mode can be collected by a brightness sensor or a detection module built into the panel.

[0075] The sources of brightness differences may include inherent charging time differences, TFT mobility differences, differences between storage capacitor Cst and liquid crystal capacitor Clc, and leakage rate differences.

[0076] Based on the preset mapping relationship between brightness and charging time, calculate the compensation time for the required third charging time T3 and fourth charging time T4: If the brightness of the pixel units 11 in the odd-numbered rows is too dim in the first display frame, the charging time of the pixel units 11 in the odd-numbered rows in the second display frame needs to be increased. If the brightness of the pixel units 11 in the even-numbered rows is too dim, the charging time of the pixel units 11 in the even-numbered rows in the first display frame needs to be increased. Based on the system's preset basic charging time and the calculated compensation amount, the first charging time T1, the second charging time T2, the third charging time T3, and the fourth charging time T4 are automatically determined, so that the brightness difference ΔL after the two frames are superimposed is 0.

[0077] The above methods can achieve automated timing calibration, which is suitable for automatic debugging of mass production lines, improving yield and display consistency.

[0078] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0079] Example 3 Corresponding to the driving method of the display panel 2 described above, such as Figure 10 As shown, a second aspect of the present invention provides a driving circuit 1 for a display panel, comprising: The source drive circuit 100 is connected to the data line of the display panel 2. The source drive circuit 100 is used for controlled output of multiple data signals. The gate driving circuit 200 is connected to the scan line of the display panel 2. The gate driving circuit 200 is used to output the line scan signal in a controlled manner. The timing controller 300 is connected to the source drive circuit 100 and the gate drive circuit 200 respectively. The timing controller 300 is used to control the source drive circuit 100 and the gate drive circuit 200 to implement the above-mentioned driving method of the display panel 2.

[0080] In this embodiment, the source drive circuit 100 is connected to multiple data lines of the display panel 2 and is used to output multiple data signals under the control of the timing controller 300. In HSR mode, adjacent rows output the same data signal.

[0081] The gate driving circuit 200 is connected to multiple scan lines of the display panel 2 and is used to output line scan signals line by line under the control of the timing controller 300. The line scan signals satisfy equal intervals of rising edges, equal intervals of falling edges, and partial overlap of adjacent lines.

[0082] The timing controller 300 is connected to the source driving circuit 100 and the gate driving circuit 200 respectively, and is used to output control timing, including controlling the alternating switching of the first display frame and the second display frame, controlling the charging time of the pixel units 11 in the odd row and even row, and controlling the data signal of the even row of the second display frame to be cut off in advance, thereby realizing complementary brightness output and visual uniformity.

[0083] Example 4 A third aspect of the present invention provides a display device, such as... Figure 10 As shown, the display device includes a display panel 2 and a driving circuit 1 for the display panel. The specific structure of the driving circuit 1 for the display panel is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The display panel 2 is connected to the driving circuit 1 for the display panel.

[0084] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving method for a display panel, characterized in that, include: In the alternating first and second display frames, line scan signals are output to the display panel line by line, and multiple data signals are output to the display panel, wherein the data signals received by the two pixel units of each adjacent odd and even rows are the same; In the first display frame, the charging time of the pixel units in the odd-numbered rows is the first charging duration, and the charging time of the pixel units in the even-numbered rows is the second charging duration, wherein the second charging duration is longer than the first charging duration. In the second display frame, the charging time of the pixel units in odd-numbered rows is controlled to be a third charging duration, and the charging time of the pixel units in even-numbered rows is controlled to be a fourth charging duration. The third charging duration is longer than the first charging duration, the fourth charging duration is longer than the third charging duration, and the fourth charging duration is controlled to cause the data signal to end the output before the corresponding row scan signal is turned off.

2. The driving method for the display panel as described in claim 1, characterized in that, The rising edges of the multiple row scan signals are sequentially spaced at unit time intervals, the falling edges of the multiple row scan signals are sequentially spaced at unit time intervals, and the high-level periods of adjacent row scan signals partially overlap.

3. The driving method for the display panel as described in claim 2, characterized in that, In the first display frame, the charging time for pixel units in odd-numbered rows is a first charging duration, and the charging time for pixel units in even-numbered rows is a second charging duration, wherein the second charging duration is longer than the first charging duration, including: In the first display frame, a data signal is output before the falling edge of the row scan signal of each two adjacent rows and the output of the data signal is stopped after the falling edge of the row scan signal of each two adjacent rows. Wherein, the first time interval between the rising edge of the data signal of the pixel unit in the odd-numbered rows and the falling edge of the corresponding row scan signal is less than the second time interval between the rising edge of the data signal of the pixel unit in the even-numbered rows and the falling edge of the corresponding row scan signal, so that the first charging time is less than the second charging time.

4. The driving method for the display panel as described in claim 3, characterized in that, In the first display frame, the rising edge of the data signal of the pixel unit in the odd-numbered rows leads the rising edge of the data signal of the pixel unit in the even-numbered rows, or the rising edge of the data signal of the pixel unit in the odd-numbered rows and the rising edge of the data signal of the pixel unit in the even-numbered rows are at the same time point.

5. The driving method for the display panel as described in claim 3, characterized in that, In the second display frame, the charging time for pixel units in odd-numbered rows is controlled to be a third charging duration, and the charging time for pixel units in even-numbered rows is controlled to be a fourth charging duration. The third charging duration is longer than the first charging duration, and the fourth charging duration is longer than the third charging duration. Furthermore, the fourth charging duration is controlled to cause the data signal to terminate output prematurely before the corresponding row scan signal is turned off. This includes: In the second display frame, a data signal is output before the falling edge of the row scan signal between every two adjacent rows; In the second display frame, the data signal is cut off after the falling edge of the line scan signal for odd-numbered rows, and the data signal is cut off before the falling edge of the line scan signal for even-numbered rows. Wherein, the third time interval between the rising edge of the data signal of the pixel unit in the odd-numbered rows and the falling edge of the corresponding row scan signal is greater than the first time interval, and the fourth time interval between the rising edge of the data signal of the pixel unit in the even-numbered rows and the falling edge of the corresponding row scan signal is greater than the third time interval.

6. The driving method for a display panel as described in claim 5, characterized in that, In the second display frame, the rising edge of the data signal of the pixel unit in the odd-numbered rows is at the same time point as the rising edge of the data signal of the pixel unit in the even-numbered rows.

7. The driving method for the display panel as described in any one of claims 2 to 6, characterized in that, The output duration of each of the data signals is equal.

8. The driving method for a display panel as described in claim 1, characterized in that, In the second display frame, before controlling the charging time of the pixel units in odd-numbered rows to be the third charging duration and the charging time of the pixel units in even-numbered rows to be the fourth charging duration, the following is also included: Obtain the display brightness difference between the odd-numbered rows and even-numbered rows in the first display frame; Calculate the charging time compensation amount based on the brightness difference; Based on the base charging time and the compensation amount, the parameter values ​​of the third charging duration and the fourth charging duration are determined.

9. A driving circuit for a display panel, characterized in that, include: The source drive circuit is connected to the data line of the display panel. The source drive circuit is used to output multiple data signals under controlled conditions. A gate driving circuit is connected to the scan lines of the display panel, and the gate driving circuit is used to output line scan signals in a controlled manner. A timing controller is connected to the source driving circuit and the gate driving circuit respectively. The timing controller is used to control the source driving circuit and the gate driving circuit to implement the driving method of the display panel as described in any one of claims 1 to 8.

10. A display device, characterized in that, It includes a display panel and a driving circuit for the display panel as described in claim 9, wherein the display panel is connected to the driving circuit for the display panel.

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