A content-aware based display module dynamic refresh rate adjustment method

Abstract

The application relates to the technical field of display module dynamic refresh rate adjustment, and particularly discloses a display module dynamic refresh rate adjustment method based on content sensing, which extracts pixel update features and visual saliency weights of a to-be-rendered layer in a graphics rendering pipeline, generates content dynamic characteristic values to represent content dynamic attributes, dynamically modulates a physical clock frequency of a transmission interface according to the content dynamic characteristic values, establishes a variable-frequency data transmission link, matches a data transmission bandwidth with content load, generates elastic scanning control instructions according to a real-time data transmission rate, adjusts a row scanning period and a gate driving voltage, forms a dynamic load row scanning timing, and when a high-priority touch event is detected, forcibly resets an association state of data transmission and scanning control, and ensures instant responsiveness of user interaction. Through fine content analysis and dynamic refresh rate adjustment, the application effectively reduces display module power consumption.

Description

Technical Field

[0001] This invention relates to the field of dynamic refresh rate adjustment technology for display modules, and more specifically, to a content-aware dynamic refresh rate adjustment method for display modules. Background Technology

[0002] In mobile devices, wearable devices, and other portable electronic products, the display module is one of the main sources of power consumption. To reduce overall system power consumption and extend battery life, the industry continues to explore technologies for dynamically adjusting display refresh rates. The core of display refresh rate adaptation lies in matching the screen's refresh rate with the update frequency of the content in front of it, avoiding unnecessary high-frequency refresh operations when displaying static or low-dynamic content, thereby saving energy consumed by frequently driving thin-film transistor arrays and performing high-speed data transmission.

[0003] Patent CN119964490A discloses a low-power display module system based on dynamic refresh rate switching, including a driver integrated circuit, a storage module, and a frame rate control module. When switching between high and low frame rate modes, the driver integrated circuit does not need to re-program the driver code. Frame rate switching is achieved by real-time switching of the parameter table and synchronous updating of the MIPI clock frequency, with a switching latency ≤20ms and a Gamma voltage curve deviation ≤0.1V between high and low frame rates.

[0004] Patent CN119920217B discloses a high refresh rate LCD screen driving method and system, including: a motion detection module that calculates the motion intensity of dynamic areas through inter-frame comparison; a voltage excitation adjustment module that applies voltage according to the differences between dynamic and static areas, with asymmetric voltage used in dynamic areas to improve response speed; a grayscale adjustment module that dynamically optimizes voltage amplitude based on local contrast to smooth grayscale; an adaptive refresh rate module that integrates motion intensity and image type to switch refresh rate levels; and a charge balance management module that intelligently triggers regional reverse voltage pulses in static scenes to eliminate ghosting.

[0005] Existing technologies have significant shortcomings in refresh rate adjustment mechanisms: First, their perception of displayed content is too coarse. Adjustment strategies either rely on preset macro-mode switching or are based solely on simple pixel physical changes, lacking the ability to deeply analyze the complexity and visual importance of content structure, and thus failing to effectively handle complex display scenarios involving a mix of dynamic and static content. Second, their optimization schemes fail to extend throughout the entire link from the data source to the display panel, ignoring the possibility of dynamically adjusting the data transmission interface bandwidth based on the actual content load, resulting in inherent power redundancy in the transmission link. Finally, at the lowest physical drive level, their panel scanning control method is relatively rigid, failing to achieve adaptive adjustment of line scanning timing and voltage parameters based on real-time data flow, thereby limiting the potential for further energy reduction in the physical drive stage. Summary of the Invention

[0006] In view of this, in order to solve the problems mentioned in the background technology, a content-aware dynamic refresh rate adjustment method for display modules is proposed.

[0007] The objective of this invention can be achieved through the following technical solution: This invention provides a content-aware dynamic refresh rate adjustment method for display modules, comprising the following steps: S1, obtaining the data of the layer to be rendered in the graphics rendering pipeline, extracting the pixel update features and visual saliency weights of the layer, generating content dynamic feature values ​​that characterize the dynamic attributes of the content, writing the content dynamic feature values ​​into the header field, and encapsulating the data of the layer to be rendered into a smart data packet.

[0008] S2. Parse the header fields of the smart data packet, dynamically modulate the physical clock frequency of the transmission interface based on the dynamic feature values ​​of the content, and establish a variable frequency data transmission link.

[0009] S3. Receive pixel data transmitted via the frequency conversion data transmission link, detect the real-time data transmission rate, and generate a flexible scan control command containing the target row period and target voltage value based on the real-time data transmission rate.

[0010] S4. In response to the flexible scan control command, perform voltage boost or period extension operation on the gate drive circuit of the display module to form a dynamic load line scan timing.

[0011] S5. By using dynamic load line scan timing to control the on / off state of the thin-film transistor array, and in conjunction with source drive data writing, content-aware pixel charging is completed.

[0012] S6. Monitor the touch interrupt signal of the user interface. When a high-priority touch event is detected, forcibly reset the association state of data transmission and scanning control, lock the frequency conversion data transmission link to the highest physical bandwidth, and output fixed parameters of maximum voltage and minimum line period.

[0013] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects: (1) By using content dynamic feature values ​​to characterize the content dynamic attributes at the layer level, the present invention can achieve a more refined analysis of the displayed content. The system not only judges whether there are changes between frames, but also further quantifies the density of the area where the change occurs and the visual importance of the area. This mechanism enables the system to distinguish between global small-scale, non-focus animation and local large-scale, focus video playback, thereby avoiding triggering the entire display link to enter a high-power working mode due to unimportant local changes. As a result, the matching degree of the refresh strategy to the actual display content complexity is improved, and the ineffective power consumption in mixed dynamic content scenarios is reduced.

[0014] (2) This invention establishes a variable frequency data transmission link between the application processor and the display driver chip, and couples its physical clock frequency with the dynamic characteristic value of the content in real time, enabling the bandwidth consumption of data transmission to match the actual content load. When the dynamic characteristic value of the content indicates that the content is low dynamic, the transmission interface can actively reduce the clock frequency or enter a gated suspension state, which directly reduces the static and dynamic power consumption generated by the high-speed serial interface in maintaining a high-speed link during idle or low-load periods. This mechanism of adjusting the transmission bandwidth from the data source avoids the practice of maintaining a high-bandwidth link regardless of the amount of content, and achieves energy saving at the transmission layer.

[0015] (3) By generating flexible scan control commands for controlling the row scanning behavior and forming a dynamic load row scanning timing sequence, this invention extends power consumption optimization measures from the data transmission link to the physical driving level of the display panel. The system dynamically adjusts the row scanning cycle length and gate drive voltage according to the real-time data transmission rate. By shortening the row cycle and increasing the voltage, charging efficiency is ensured, or by extending the row cycle or inserting sleep time slots, the operating frequency and voltage stress of the drive circuit are reduced. This mechanism makes the physical scanning action of the panel completely synchronized with the rhythm of upstream data arrival, eliminating the idle power consumption generated when waiting for low-speed data in the traditional fixed scan timing sequence, and enhancing the power consumption control flexibility of the entire display subsystem.

[0016] (4) This invention, by setting a mechanism to forcibly reset the associated state of data transmission and scanning control when a high-priority touch event is detected, can ensure the instantaneous responsiveness of user interaction while pursuing power consumption optimization. This mechanism bypasses complex content analysis and frequency calculation logic through parallel hardware detection channels, enabling the system to switch data transmission and physical scanning to the highest performance mode without delay the moment it senses a user's touch operation. This design ensures that users will not experience stuttering or lag that may be caused by dynamic refresh rate adjustment during latency-sensitive operations such as sliding and zooming, maintaining a smooth interactive experience, and automatically reverting to the energy-saving variable scanning mode after the touch ends, achieving a dynamic balance between power consumption and performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the method steps of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1 The present invention provides a content-aware dynamic refresh rate adjustment method for display modules, comprising: S1, acquiring the data of the layer to be rendered in the graphics rendering pipeline, extracting the pixel update features and visual saliency weights of the layer, generating content dynamic feature values ​​that characterize the dynamic attributes of the content, writing the content dynamic feature values ​​into the header field and encapsulating the data of the layer to be rendered into a smart data packet.

[0021] In a specific embodiment of the present invention, the specific process of extracting the pixel update features of the layer includes: comparing the data of the layer to be rendered in the current frame with the data of the historical frames pixel by pixel, and calculating the color channel difference.

[0022] If the color channel difference exceeds the preset noise suppression threshold, the corresponding pixel will be marked as an updated pixel.

[0023] The pixel update characteristics are obtained by calculating the ratio of the number of updated pixels to the total number of pixels in the layer.

[0024] Specifically, this step is implemented by a graphics processing unit integrated within the application processor or a dedicated coprocessor. The process begins at the end of the graphics rendering pipeline—before the hardware compositor synthesizes all the independent layers to be rendered into the final display frame—by setting a hardware interrupt or software hook to intercept the rendering instructions for each layer. This interception logic is triggered when the data buffer for the layer to be rendered is ready. The system first loads the layer data to be rendered for the current frame into the cache and retrieves historical pixel data from the same layer stored in the previous frame period. By comparing the color values ​​of the current frame with those of historical frames pixel by pixel, for example, calculating the sum of the absolute values ​​of the RGB channel differences at each pixel location, if the RGB channel difference exceeds a preset noise suppression threshold, the pixel is marked as updated. After completing a full layer traversal, the number of all updated pixels is counted, and the ratio of this count to the total number of pixels in the layer is used to calculate the pixel update characteristics.

[0025] In a specific embodiment of the present invention, the specific process of generating content dynamic feature values ​​that represent the dynamic attributes of content includes: querying a preset mapping table based on the layer type identifier of the layer data to be rendered, and extracting the corresponding visual saliency weights.

[0026] The pixel update features and visual saliency weights are weighted and calculated to quantify and generate dynamic feature values ​​for the content.

[0027] Specifically, simultaneously, the system parses the metadata transmitted along with the data of the layer to be rendered. This metadata includes layer type identifiers, such as video layer, UI control layer, or background layer. The system queries a pre-defined mapping table based on this identifier to extract the corresponding visual saliency weight. Subsequently, the system multiplies the extracted pixel update features with the visual saliency weights to generate a scalar value quantifying the content's dynamism and importance; this scalar value is the content dynamic feature value. Finally, the system constructs a data structure for subsequent transmission, namely the smart data packet, which includes a header field and a data payload area. The system writes the generated content dynamic feature value into the header field of the smart data packet and encapsulates the complete data of the layer to be rendered in the data payload area, ready for subsequent transmission to the display driver chip.

[0028] This step involves calculating the dynamic feature values ​​used to generate the content, and the specific formula is shown below: First, calculate the pixel update feature, i.e., the pixel change rate parameter. : Secondly, generate dynamic feature values ​​for the content. : ,in, Represents the dynamic feature value of the content. This represents the pixel update feature, i.e., the pixel change rate parameter. Represents visual saliency weight. This represents the number of pixels that have changed in the current frame relative to the previous frame. This represents the total number of pixels in the layer to be rendered. In this embodiment, For dimensionless parameters, Since they are dimensionless weighting coefficients, It is also a dimensionless scalar value, but its dimensions are consistent.

[0029] The layer data to be rendered refers to a two-dimensional pixel matrix in an independent buffer before being composited into a single frame image by the graphics processor, such as a pixel data block in RGBA8888 format with a resolution of 1920x1080. The pixel update feature is a normalized value ranging from 0 to 1, used to characterize the dynamic range of the image content. Visual saliency weight. This is a preset dimensionless coefficient value, typically set between 0.1 and 1.5. This value is based on the ergonomic visual focus model, assuming that layers located in the center of the screen or identified as video content are more likely to attract user attention, and therefore are given a higher weight value, such as 1.2; while layers that are static backgrounds or decorative elements located at the screen edges are given a lower weight value, such as 0.3. Content dynamic characteristic value It is a scalar value used to quantify the dynamic attributes of layer content, and its magnitude is positively correlated with the dynamic complexity and visual importance of the content. Smart data packets are a custom data structure designed to add metadata—i.e., dynamic content feature values—to the standard pixel data stream for controlling downstream hardware behavior. The preset noise suppression threshold used to determine whether a pixel has been updated is experimentally calibrated based on the inherent noise level of the display panel. It is assumed that at 8-bit color depth, if the sum of the absolute values ​​of the differences between the RGB channels is less than 10, it is considered a change caused by circuit noise and is not counted as a valid update.

[0030] For example, suppose the data to be processed for rendering a layer is a video playback window with a resolution of 1280x720, then its total number of pixels is... The value is 921600. First, the system parses the metadata of this layer to determine its type as "main video" and queries the internal mapping table to obtain its corresponding visual saliency weight. The threshold is set to 1.2. Next, the system compares the current frame's layer pixel data with the cached data from the previous frame, setting the noise suppression threshold to 10. Calculations show that 230,400 pixels have color value changes exceeding this threshold; therefore, the number of updated pixels is adjusted. The value is 230400. Subsequently, the system calculates the pixel update features. Its value is 230400 divided by 921600, resulting in It equals 0.25. Ultimately, the system updates the features by pixel. With visual saliency weight Multiplication generates dynamic feature values ​​of the content. The value is 0.25 multiplied by 1.2, resulting in 0.3. The system creates a smart data packet, writes the value 0.3 into its header field, and fills the data payload with the 1280x720 resolution pixel data to complete the encapsulation.

[0031] S2. Parse the header fields of the smart data packet, dynamically modulate the physical clock frequency of the transmission interface based on the dynamic feature values ​​of the content, and establish a variable frequency data transmission link.

[0032] In a specific embodiment of the present invention, the specific process of establishing a variable frequency data transmission link by dynamically modulating the physical clock frequency of the transmission interface based on the dynamic feature value of the content includes: mapping the value of the dynamic feature value of the content to the target bandwidth value of the transmission channel.

[0033] The clock signal frequency of the physical interface is adjusted according to the target bandwidth value using a phase-locked loop circuit.

[0034] When the dynamic characteristic value of the content is greater than the preset high dynamic threshold, the clock signal frequency is increased to activate the high-speed transmission channel.

[0035] When the dynamic characteristic value of the content is less than the preset low dynamic threshold, the gating logic is triggered to reduce the clock signal frequency or suspend the transmission.

[0036] Specifically, this step is implemented by a physical transmission interface controller integrated between the application processor and the display driver chip. When the smart data packet generated in step S1 arrives at the interface controller, its internal parsing logic circuit first performs hard-line parsing on the header field of the data packet, extracting the content dynamic feature value with a nanosecond-level delay. This content dynamic feature value is immediately sent to a digital lookup table or a digital signal processing unit. The digital lookup table pre-stores a nonlinear or piecewise linear mapping relationship between the content dynamic feature value and the target bandwidth value. Based on the input content dynamic feature value, the processing unit obtains a corresponding target clock frequency control word from the digital lookup table or by calculation. This target clock frequency control word is then transmitted to the frequency control input of a phase-locked loop (PLL) circuit. Based on the received control word, the PLL circuit adjusts the output of its internal voltage-controlled oscillator, adjusting the data transmission clock signal of the physical interface to the target frequency within microseconds. Specifically, when the content dynamic feature value is greater than a preset high dynamic threshold, it indicates that the content is a high-speed motion scene. The PLL circuit locks the clock frequency to the highest level supported by the physical interface, such as 1.5GHz, thereby activating the high-speed transmission channel. Conversely, when the value of the content's dynamic characteristic is less than the preset low dynamic threshold, it indicates that the content is static or nearly static. The controller not only reduces the clock frequency to the lowest operating level, such as 100MHz, but also triggers gating logic when the scalar value approaches zero, completely shutting down the clock signal output and putting the data transmission link into a suspended state. Through this frequency modulation mechanism that is coupled in real time with the content load, a variable frequency data transmission link is finally established.

[0037] This step involves dynamic feature values ​​of the content. Mapped to target clock frequency The specific mapping relationship for the calculation can be represented by the following piecewise function:

[0038]

[0039] in, It is the target physical clock frequency for establishing a variable frequency data transmission link. These are the dynamic feature values ​​of the content generated in step S1. It is the highest clock frequency supported by the transmission interface. It is the base clock frequency used to process low to medium dynamic content. It is the lowest active clock frequency used for transmitting nearly static content. and These are the information entropy thresholds used to distinguish between high, medium, and low dynamic content. It is a linear scaling factor used in... and The frequency is adjusted smoothly within the range. A value of 0 indicates that the clock is suspended via gating logic. Dimensional check: In the formula... , , and The unit for all values ​​is Hz. , as well as All are dimensionless values. Therefore, the coefficients... The dimension must be Hz to ensure The dimension of the value is Hz, thus ensuring that the entire formula remains consistent in terms of dimensions.

[0040] In this context, a variable frequency data transmission link refers to a data communication channel whose physical layer clock frequency can be dynamically adjusted in real time based on the dynamic characteristics carried in the header of the transmitted data packet, such as a MIPI D-PHY interface supporting multiple rate modes. A phase-locked loop (PLL) circuit is a feedback control circuit; in this scheme, its function is to receive a digital control signal and generate a stable clock signal proportional to its frequency. Gating logic is a digital circuit design technique that uses logic gates to cut off the clock signal supply to a circuit module under specific conditions, thereby reducing power consumption. It is usually determined by the hardware specifications of the physical interface. For example, for the next generation of mobile display interfaces, the value can be set from 1.5GHz to 2.5GHz. The setting should be as low as possible while ensuring smoothness, and is usually based on a large number of user experience tests, such as 300MHz. This is then set to a frequency that only meets the minimum data synchronization requirements, such as 50MHz. High dynamic threshold. Set to 0.6, this value is determined based on the typical range of content dynamic characteristics during statistical analysis of videos exceeding 60fps or fast scrolling operations. Low dynamic threshold. Set to 0.05 to filter out low-amplitude content changes caused by cursor blinking or minor animations, avoiding unnecessary frequency fluctuations. Linear scaling factor. According to the formula The calculations were performed to ensure the continuity of the frequency within the range of variation.

[0041] For example, the system receives the smart data packet generated in step S1 and parses the dynamic feature value of the content from its header field. The value is 0.3. The preset parameters for the transmission interface controller are: maximum clock frequency. The base clock frequency is 1.5GHz. 300MHz, high dynamic threshold The value is 0.6, indicating a low dynamic threshold. The value is 0.05. First, the system calculates the linear scaling factor. Its value is That is, (1500MHz-300MHz) / (0.6-0.05), to obtain Approximately 2182 MHz. Next, the system will... The value 0.3 is compared with the threshold to determine if it meets the requirement. The condition is 0.05 ≤ 0.3 < 0.6. Therefore, the system uses a linear interpolation formula to calculate the target clock frequency. Substitute the values, The calculation process is as follows: ,get The final result is 845.5MHz. Therefore, the frequency control input of the phase-locked loop circuit is configured with a control word corresponding to 845.5MHz, so that the frequency conversion data transmission link operates at a physical clock frequency of 845.5MHz during this data packet transmission.

[0042] S3. Receive pixel data transmitted via the frequency conversion data transmission link, detect the real-time data transmission rate, and generate a flexible scan control command containing the target row period and target voltage value based on the real-time data transmission rate.

[0043] In a specific embodiment of the present invention, the specific process of generating an elastic scan control command containing a target row period and a target voltage value based on the real-time data transmission rate includes: the receiving module at the display driver chip synchronously monitors the current physical data arrival rate to obtain the real-time data transmission rate.

[0044] The system searches a preset mapping table based on the real-time data transmission rate. The preset mapping table defines the row scan cycle duration and gate turn-on voltage value corresponding to different transmission rate ranges.

[0045] The specific physical drive parameters corresponding to the current scan line are calculated, and elastic scan control instructions are generated.

[0046] Specifically, this step is implemented by the receiving module and scanning control logic unit inside the display driver chip. When the smart data packet arrives through the frequency conversion data transmission link established in step S2, the physical receiver of the display driver chip first performs clock and data recovery with the incoming data stream. A frequency monitor or data throughput counter working in parallel with the physical receiver begins to measure the physical data arrival rate of the frequency conversion data transmission link in real time. This monitoring is achieved by counting effective data bits or clock cycles within a preset microsecond time window and converting the measurement result into a numerical real-time data transmission rate in Mbps or Gbps. Subsequently, the real-time data transmission rate value is used as an address index to query a mapping table stored in a read-only memory or programmable register inside the display driver chip. This mapping table structurally stores the real-time data transmission rate of different intervals and the corresponding display line scan parameters. After the query operation hits a unique entry that matches the current rate, the system reads two key parameters from it: the line scan cycle duration and the gate turn-on voltage value. The two calculated physical drive parameters are encapsulated into a digital instruction package, namely the elastic scan control instruction, and output by the scan control logic unit to directly control the downstream gate drive circuit.

[0047] The flexible scan control instruction is an internal data structure generated by the control core of the display driver chip. It is used to issue specific scan timing and voltage commands to the downstream row drive physical circuitry. It includes at least a target row cycle parameter for setting the row scan duration and a target voltage value parameter for setting the thin-film transistor (TFT) turn-on voltage. The real-time data transmission rate is the actual data flow speed measured at the physical layer by the display driver chip receiver. The real-time data transmission rate directly reflects the transmission bandwidth adjusted by the upstream application processor based on the dynamic characteristics of the content. The mapping table is a key component of this invention. Its content is pre-calibrated and set based on the physical characteristics of the display panel, aiming to establish an optimal matching relationship between data load and physical drive capability. For example, the calibration is based on the charging characteristic formula of the TFT, meaning that to make the pixel capacitance reach the target voltage in a shorter charging time, the gate turn-on voltage must be increased to reduce the transistor's on-resistance. Therefore, high-rate entries in the table correspond to shorter row scan cycles and higher gate turn-on voltages, while low-rate entries correspond to longer row scan cycles and standard or lower gate turn-on voltages.

[0048] For example, continuing from step S2, the display driver chip's receiving module receives serial data through the frequency conversion data transmission link, and its internal monitoring circuit determines the current real-time data transmission rate to be 845.5 Mbps. The system then uses this rate value to query a pre-loaded mapping table. Assume the table is as follows: when the rate is greater than 1.2 Gbps, the row scan period is 8.0 microseconds, and the gate turn-on voltage is 18V; when the rate is between 600 Mbps and 1.2 Gbps, the row scan period is 11.0 microseconds, and the gate turn-on voltage is 15V; when the rate is less than 600 Mbps, the row scan period is 16.7 microseconds, and the gate turn-on voltage is 12V. Since the measured rate of 845.5 Mbps falls within the range of 600 Mbps to 1.2 Gbps, the query operation hits the second rule. Therefore, the system calculates the specific physical drive parameters corresponding to the current scan row from this entry, namely, a target row period of 11.0 microseconds and a target voltage value of 15V. Finally, the system packages these two values ​​to generate a flexible scan control command containing a target row period of 11.0 microseconds and a target voltage value of 15V, and sends it to the gate drive circuit to guide the scanning operation of the next row of pixels.

[0049] S4. In response to the flexible scan control command, perform voltage boost or period extension operation on the gate drive circuit of the display module to form a dynamic load line scan timing.

[0050] In a specific embodiment of the present invention, the specific process of performing voltage boosting or period extension operations on the gate driving circuit of the display module to form a dynamic load row scanning timing includes: inputting the elastic scanning control command to the row period modulator and voltage level converter of the gate driving circuit.

[0051] Upon receiving a flexible scan control command indicating a high transmission rate, the line period modulator shortens the line gating time, while the voltage level converter increases the gate turn-on voltage of the thin-film transistor to compensate for charging efficiency, thus performing an overdrive scan.

[0052] In a specific embodiment of the present invention, the specific process of forming a dynamic load row scan timing further includes: when receiving an elastic scan control command indicating a low transmission rate, the row period modulator extends the row gating time and reduces the gate turn-on voltage, or inserts a sleep time slot of variable duration between rows to form a dynamic load row scan timing that breaks the fixed grating period.

[0053] Specifically, the main implementer of this step is the gate drive circuit integrated on the edge of the glass substrate of the display module or on the flexible circuit board. Upon receiving the flexible scan control command generated in step S3, this circuit immediately parses the flexible scan control command. The target row period parameter contained in the flexible scan control command is sent to a row period modulator, while the target voltage value parameter is routed to a voltage level converter. The row period modulator is a programmable digital pulse generator that sets the width of its output row strobe pulse and the interval between pulses according to the input target row period parameter. The voltage level converter is an adjustable output DC-DC boost circuit that boosts the logic level row strobe pulse to the actual high voltage required to drive the thin-film transistor array according to the input target voltage value parameter. When a command indicating a high transmission rate is received, i.e., the command contains a shorter target row period and a higher target voltage value, the row period modulator generates a narrow pulse with a shortened duration, while the voltage level converter boosts its output voltage to perform an overdrive scan. Conversely, when a command indicating a low transmission rate is received, the line period modulator correspondingly extends the duration of the line strobe pulse, and the voltage level converter outputs a standard or lower gate turn-on voltage. In extremely low dynamic conditions, the line period modulator can also insert a variable-length sleep slot after completing one line scan, based on an excessively long period parameter in the command, before starting the next line scan. By independently and in real-time configuring the scan period, voltage, and inter-line spacing for each line, a dynamic load line scan timing that breaks the fixed raster period is ultimately formed.

[0054] Dynamic load line scan timing refers to a sequence of gated signals used to control the on / off state of thin-film transistors (TFTs) in each row of the display panel. Its core characteristic is that the pulse width, voltage amplitude, and relative time interval between each signal are no longer fixed but dynamically change according to the data load transmitted upstream, achieving optimized driving for different content. A line cycle modulator replaces the traditional fixed-cycle pulse generator in this solution. It is digitally programmable, allowing control of the output pulse width and repetition rate at microsecond or finer granularity. A voltage level converter is a critical analog circuit whose output voltage range needs to cover from low voltages in power-saving mode to high peak voltages in overdrive mode; for example, its adjustable range is 10V to 22V. Overdrive scanning is a compensation technique. Assuming that during high-speed scanning, the line cycle is shortened from the standard 16 microseconds to 8 microseconds, to ensure that the pixel capacitors can still be fully charged in half the time, the gate turn-on voltage needs to be increased from the standard 15V to 18V to reduce the on-resistance of the thin-film transistors. A sleep time slot is an idle waiting time that is manually inserted after scanning one row of pixels and before scanning the next row of pixels. Its duration is variable and is used to stretch the row scanning action to a longer time dimension when displaying static content, thereby significantly reducing the average operating frequency and power consumption of the gate drive circuit.

[0055] For example, the gate drive circuit receives a flexible scan control command generated in step S3, containing a target row period of 11.0 microseconds and a target voltage value of 15V. First, the flexible scan control command is parsed by internal logic; the target row period parameter of 11.0 microseconds is sent to the row period modulator, and the target voltage value parameter of 15V is sent to the voltage level converter. Next, the row period modulator configures its internal timer based on the 11.0 microsecond parameter value to generate a row strobe pulse with a width of 11.0 microseconds. Simultaneously, the voltage level converter adjusts the feedback network of its boost circuit according to the 15V parameter value to ensure that the voltage amplitude of its output row strobe pulse signal is 15V. Finally, the output of the gate drive circuit generates a signal with a pulse width of 11.0 microseconds and a voltage of 15V; this signal is a specific pulse in the dynamic load row scan timing sequence used to drive the target row on the display panel. In contrast, if a high dynamic range video content causes the instruction generated by S3 to specify a target line period of 8.0 microseconds and a target voltage of 18V, this step will output an 8.0 microsecond wide, 18V high pulse to perform an overdrive scan. If the content is completely still, the target line period of the instruction may be set to 30.0 microseconds. In this case, after the modulator outputs an effective charging pulse of, for example, 12.0 microseconds, it will insert an 18.0 microsecond sleep time slot before processing the next line, thereby achieving dynamic extension of the scan timing.

[0056] S5. By using dynamic load line scan timing to control the on / off state of the thin-film transistor array, and in conjunction with source drive data writing, content-aware pixel charging is completed.

[0057] In a specific embodiment of the present invention, the specific process of completing content-aware pixel charging in conjunction with source-driven data writing includes: turning on the pixel switching transistor of the target row in the corresponding time slot according to the dynamic load row scanning timing.

[0058] Within the flexible time window when the pixel switching transistor is turned on, the source driver writes the pixel grayscale voltage parsed from the smart data packet into the pixel capacitor.

[0059] After completing the non-fixed-duration charging of the current row, the scanning action of the next row is triggered according to the arrival status of the next set of smart data packets, thereby achieving physical synchronization between display and content.

[0060] Specifically, this step involves the coordinated operation of the gate drive circuit, source drive circuit, and thin-film transistor array of the display module. First, the dynamic load row scan timing generated in step S4 is output by the gate drive circuit to the gate line of the target scan row in the thin-film transistor array. This timing signal is a level signal with a specific voltage amplitude and pulse width. Its application causes all pixel switching transistors in that row to switch from the off state to the on state, thus opening a flexible time window for data writing. Simultaneously, the source drive circuit has completed the parsing of the data load area of ​​the smart data packet received via the frequency conversion data transmission link, extracting the pixel grayscale data corresponding to the current scan row. The digital-to-analog converter inside the source drive circuit converts this digitized grayscale data into a series of analog voltage signals, i.e., grayscale voltages. These grayscale voltages are then applied to the output channels corresponding one-to-one with the source lines of the thin-film transistor array. Within the flexible time window during which the pixel switching transistors remain on, the grayscale voltage applied to the source lines charges the corresponding pixel capacitors through the conducting transistors. The duration of the charging process is strictly equal to the pulse width of the dynamic load row scan timing. When the pulse ends, the voltage on the gate line drops, the pixel switching transistor turns off, completing the non-fixed-duration charging of the current row and locking the brightness information represented by the grayscale voltage in the pixel capacitor. After this, the entire scanning system enters a waiting state until the display driver chip receives the next smart data packet and completes the processing flow from steps S3 to S4, thereby triggering the scanning action of the next row, thus achieving physical synchronization between the refresh behavior of the display panel and the generation of front-end content.

[0061] Content-aware pixel charging refers to a pixel charging method where the charging duration and driving voltage are not fixed, but indirectly determined by the specific content attributes to be displayed, i.e., the dynamic characteristic values ​​of the content. This optimizes charging efficiency and power consumption while ensuring display quality. Pixel switching transistors typically refer to thin-film transistors (TFTs), which act as an electronically controlled switch in each sub-pixel of the display panel. Pixel capacitors are key energy storage components that store charge to maintain liquid crystal deflection or drive OLED light emission. Grayscale voltage is an analog voltage generated by the source driver, and its amplitude is proportional to the brightness level of the target pixel. For example, in an 8-bit system, there are 256 different voltage levels corresponding to different grayscale levels from black to white. The flexible time window is the conduction time of the pixel switching transistor, and its length is determined by the pulse width of the dynamic load line scan timing, rather than a fixed period value.

[0062] For example, based on the dynamic load row scan timing generated in step S4, the gate drive circuit applies a pulse signal with a width of 11.0 microseconds and a voltage amplitude of 15V to the gate line of the Nth row of the display panel. This signal turns on all the pixel switching transistors in the Nth row. Simultaneously, the source drive circuit has parsed the data of the Nth row from the smart data packet. Assuming the target grayscale value of the Mth column pixel is 192, the digital-to-analog converter of the source drive circuit converts this value into the corresponding grayscale voltage, for example, 4.2V. This 4.2V voltage is applied to the source line of the Mth column. During the next 11.0 microsecond flexible time window, the pixel switching transistor in the Nth row and Mth column remains on, and the 4.2V voltage on the source line charges the pixel capacitor through the transistor. At the end of the 11.0 microseconds, the voltage on the gate line is removed, the transistor turns off, and the pixel capacitor successfully stores a charge of approximately 4.2V, completing the content-aware pixel charging for that pixel. The drive system then pauses until the next smart data packet arrives and triggers the generation of a scan instruction for line N+1, at which point the next charging cycle begins.

[0063] S6. Monitor the touch interrupt signal of the user interface. When a high-priority touch event is detected, forcibly reset the association state of data transmission and scanning control, lock the frequency conversion data transmission link to the highest physical bandwidth, and output fixed parameters of maximum voltage and minimum line period.

[0064] In a specific embodiment of the present invention, the specific process of forcibly resetting the associated state of data transmission and scanning control includes: listening to the input signal of the touch screen through parallel hardware detection channels, and generating a global reset interrupt with the highest priority when a click or swipe event is captured.

[0065] By utilizing the calculation logic of steps S1 to S3, which are bypassed by the highest priority global reset interrupt, the frequency converter data transmission link is forcibly locked to the highest physical bandwidth.

[0066] In a specific embodiment of the present invention, locking the frequency conversion data transmission link to the highest physical bandwidth and outputting fixed parameters of maximum voltage and minimum line period also includes: synchronously forced elastic scan control command outputting fixed parameters of maximum voltage and minimum line period.

[0067] Until the touch interrupt signal ends, the global reset interrupt is cleared, and the system returns to the variable scanning mode based on dynamic content feature values.

[0068] Specifically, this step is implemented by a hardware interrupt management module tightly coupled to the application processor's interrupt controller and the display subsystem. This hardware interrupt management module continuously monitors the physical interrupt request line from the touchscreen controller via a parallel hardware detection channel independent of the main data processing path. When a user's finger touches the screen to perform interactive operations such as clicking or swiping, the touchscreen controller detects a change in capacitance exceeding a preset threshold and immediately generates a high-level signal on the interrupt request line, i.e., a touch interrupt signal. Upon capturing this signal, the hardware interrupt management module identifies it as a high-priority touch event and generates a global reset interrupt with the highest processing priority. This global reset interrupt signal is broadcast to the logic unit responsible for executing steps S1 to S3. This signal forces the information entropy calculation logic in step S1 to pause and bypasses the frequency modulation function based on content dynamic feature values ​​in step S2, directly instructing the phase-locked loop circuit to lock the physical clock of the frequency conversion data transmission link to the highest frequency supported by the hardware. Simultaneously, the interrupt signal also bypasses the function of querying the mapping table based on the real-time rate in step S3, forcing the scan control logic unit to output a set of fixed, preset flexible scan control instructions with maximum performance parameters. These flexible scan control instructions include the maximum voltage and the minimum line period. This forced lock state will continue until the touch interrupt signal is canceled by the touch screen controller, indicating that the touch event has ended. At this time, the global reset interrupt is cleared, and the system returns to the variable scan mode based on the dynamic feature values ​​of the content.

[0069] The touch interrupt signal is a level transition signal generated by the touch controller chip to report the occurrence of a physical touch to the main processor. It has a higher response priority than software interrupts to ensure low latency in interactive operations. High-priority touch events specifically refer to interactive behaviors that require the screen to respond immediately with the highest smoothness, such as the initial stage of rapid swiping, drag-and-drop operations, or multi-touch gestures. The data transmission and scan control association state refers to the closed-loop control relationship established in steps S1 to S5, which corresponds one-to-one between content information entropy and physical scan timing. Resetting this state means temporarily breaking this content-based adaptive adjustment and switching to a predefined, open-loop highest performance mode. The maximum voltage refers to the highest gate turn-on voltage that the gate drive circuit can output to achieve the fastest pixel charging speed. Its value is set according to the electrical safety limits of the panel TFT devices, such as 22V. The minimum row cycle refers to the shortest time required to complete the effective charging of one row of pixels at the highest gate voltage. It is determined by the switching speed of the drive circuit and the responsiveness of the pixel array, such as 7.5 microseconds.

[0070] For example, the system is currently displaying a static image. According to the process from steps S1 to S5, the variable frequency data transmission link operates in a low-frequency energy-saving state of 100MHz, and the row period of the dynamic load row scan timing is 33.3 microseconds. At this time, the user's finger performs a leftward swipe operation on the screen. First, the touch screen controller detects this operation and immediately generates a high-level touch interrupt signal. The parallel hardware detection channel captures this signal and triggers a global reset interrupt. Then, the interrupt signal is broadcast. After receiving the signal, the transmission interface controller responsible for step S2 immediately bypasses its frequency modulation logic, forcing its internal phase-locked loop circuit to instantly boost the clock frequency from 100MHz to the highest physical bandwidth supported by the hardware, such as 1.5GHz. At the same time, the scan control logic unit in the display driver chip responsible for step S3 also receives the interrupt signal. It also bypasses the process of looking up the mapping table and instead outputs a flexible scan control instruction stored in a register, containing a maximum voltage of 22V and a minimum row period of 7.5 microseconds. Afterward, as long as the user's finger continues to slide on the screen, the system maintains a global high-speed refresh at a transmission rate of 1.5GHz and scanning parameters of {22V, 7.5 microseconds}. Until the user's finger leaves the screen, the touch interrupt signal is canceled, the global reset interrupt is cleared, and the system automatically resumes the process in step S1, recalculates the dynamic feature values ​​of the current screen content, and adjusts back to a low-power scanning mode suitable for static display.

[0071] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined by the present invention, and all such modifications and additions should fall within the protection scope of the present invention.

Claims

1. A content-aware dynamic refresh rate adjustment method for display modules, characterized in that, Includes the following steps: S1. Obtain the data of the layer to be rendered in the graphics rendering pipeline, extract the pixel update features and visual saliency weights of the layer, generate content dynamic feature values ​​that represent the dynamic attributes of the content, write the content dynamic feature values ​​into the header field and encapsulate the data of the layer to be rendered into a smart data package. S2. Parse the header fields of the smart data packet, dynamically modulate the physical clock frequency of the transmission interface based on the dynamic feature values ​​of the content, and establish a variable frequency data transmission link. S3. Receive pixel data transmitted via the frequency conversion data transmission link, detect the real-time data transmission rate, and generate an elastic scan control command containing the target row period and target voltage value based on the real-time data transmission rate. S4. In response to the flexible scan control command, perform voltage boost or periodic extension operation on the gate drive circuit of the display module to form a dynamic load line scan timing. S5. By using dynamic load line scan timing to control the on / off state of the thin-film transistor array, and in conjunction with source drive data writing, content-aware pixel charging is completed. S6. Monitor the touch interrupt signal of the user interface. When a high-priority touch event is detected, forcibly reset the association state of data transmission and scanning control, lock the frequency conversion data transmission link to the highest physical bandwidth, and output fixed parameters of maximum voltage and minimum line period.

2. The content-aware dynamic refresh rate adjustment method for a display module according to claim 1, characterized in that, The specific process of extracting the pixel update features of the layer includes: Compare the data of the layer to be rendered in the current frame with the data of the historical frames pixel by pixel and calculate the color channel difference; If the color channel difference exceeds the preset noise suppression threshold, the corresponding pixel will be marked as an updated pixel. The pixel update characteristics are obtained by calculating the ratio of the number of updated pixels to the total number of pixels in the layer.

3. The content-aware dynamic refresh rate adjustment method for a display module according to claim 2, characterized in that, The specific process of generating content dynamic feature values ​​that represent the dynamic attributes of the content includes: Based on the layer type identifier of the layer data to be rendered, query the preset mapping table and extract the corresponding visual saliency weight; The pixel update features and visual saliency weights are weighted and calculated to quantize and generate dynamic feature values ​​for the content.

4. The content-aware dynamic refresh rate adjustment method for a display module according to claim 1, characterized in that, The specific process of establishing a frequency conversion data transmission link by dynamically modulating the physical clock frequency of the transmission interface based on the dynamic feature values ​​of the content includes: Map the numerical values ​​of the content's dynamic features to the target bandwidth value of the transmission channel; The clock signal frequency of the physical interface is adjusted according to the target bandwidth value using a phase-locked loop circuit. When the dynamic characteristic value of the content is greater than the preset high dynamic threshold, the clock signal frequency is increased to activate the high-speed transmission channel. When the dynamic characteristic value of the content is less than the preset low dynamic threshold, the gating logic is triggered to reduce the clock signal frequency or suspend the transmission.

5. The content-aware dynamic refresh rate adjustment method for a display module according to claim 1, characterized in that, The specific process of generating the flexible scan control command containing the target row period and target voltage value based on the real-time data transmission rate includes: The receiving module at the display driver chip synchronously monitors the current physical data arrival rate to obtain the real-time data transmission rate; The preset mapping table is searched based on the real-time data transmission rate. The preset mapping table defines the row scan cycle duration and gate turn-on voltage value corresponding to different transmission rate ranges. The specific physical drive parameters corresponding to the current scan line are calculated, and elastic scan control instructions are generated.

6. The content-aware dynamic refresh rate adjustment method for a display module according to claim 5, characterized in that, The specific process of performing voltage boosting or periodic extension operations on the gate drive circuit of the display module to form a dynamic load row scan timing includes: The elastic scan control command is input to the row cycle modulator and voltage level converter of the gate drive circuit; Upon receiving a flexible scan control command indicating a high transmission rate, the line period modulator shortens the line gating time, while the voltage level converter increases the gate turn-on voltage of the thin-film transistor to compensate for charging efficiency, thus performing an overdrive scan.

7. The content-aware dynamic refresh rate adjustment method for a display module according to claim 6, characterized in that, The specific process of forming the dynamic load row scan timing also includes: when receiving an elastic scan control command indicating a low transmission rate, the row period modulator extends the row gating time and reduces the gate turn-on voltage, or inserts a sleep time slot of variable duration between rows to form a dynamic load row scan timing that breaks the fixed grating period.

8. The content-aware dynamic refresh rate adjustment method for a display module according to claim 1, characterized in that, The specific process of coordinating source-driven data writing to complete content-aware pixel charging includes: Based on the dynamic load row scan timing, the pixel switching transistors of the target row are turned on in the corresponding time slot; Within the flexible time window when the pixel switching transistor is turned on, the source driver writes the pixel grayscale voltage parsed from the smart data packet into the pixel capacitor. After completing the non-fixed-duration charging of the current row, the scanning action of the next row is triggered according to the arrival status of the next set of smart data packets, thereby achieving physical synchronization between display and content.

9. The content-aware dynamic refresh rate adjustment method for a display module according to claim 1, characterized in that, The specific process of forcibly resetting the association status between data transmission and scan control includes: The system listens for touchscreen input signals through parallel hardware detection channels. When a click or swipe event is detected, a global reset interrupt with the highest priority is generated. By utilizing the calculation logic of steps S1 to S3, which are bypassed by the highest priority global reset interrupt, the frequency converter data transmission link is forcibly locked to the highest physical bandwidth.

10. A content-aware dynamic refresh rate adjustment method for a display module according to claim 9, characterized in that, The fixed parameters for locking the frequency converter data transmission link to the highest physical bandwidth and outputting the maximum voltage and minimum line period also include: The synchronous forced elastic scan control command outputs fixed parameters for maximum voltage and minimum line period; Until the touch interrupt signal ends, the global reset interrupt is cleared, and the system returns to the variable scanning mode based on dynamic content feature values.

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